More work on the GW20 layout. This will be a tight squeeze. #7 #19

This commit is contained in:
Travis Goodspeed 2017-10-02 22:40:48 -04:00
parent 456daad9ce
commit 61e1a694a4
3 changed files with 205 additions and 155 deletions

View File

@ -1,15 +1,15 @@
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)
(page A4)
@ -138,29 +138,24 @@
(net 44 VCC)
(net 45 "Net-(U1-Pad36)")
(net 46 "Net-(U1-Pad37)")
(net 47 "Net-(U1-Pad38)")
(net 48 "Net-(U1-Pad39)")
(net 49 "Net-(U1-Pad42)")
(net 50 "Net-(U1-Pad43)")
(net 51 "Net-(U1-Pad44)")
(net 52 "Net-(U1-Pad45)")
(net 53 "Net-(U1-Pad46)")
(net 54 "Net-(U1-Pad47)")
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(net 57 "Net-(U1-Pad54)")
(net 58 "Net-(U1-Pad55)")
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(net 62 /COM1)
(net 63 /COM2)
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(net 65 "Net-(LCD1-Pad35)")
(net 66 /LCDCAP)
(net 67 /RF_P)
(net 68 /RF_N)
(net 69 "Net-(U2-Pad1)")
(net 47 "Net-(U1-Pad46)")
(net 48 "Net-(U1-Pad47)")
(net 49 "Net-(U1-Pad48)")
(net 50 "Net-(U1-Pad49)")
(net 51 "Net-(U1-Pad54)")
(net 52 "Net-(U1-Pad55)")
(net 53 /TST)
(net 54 /!RST)
(net 55 /COM0)
(net 56 /COM1)
(net 57 /COM2)
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(net 60 /LCDCAP)
(net 61 /RF_P)
(net 62 /RF_N)
(net 63 "Net-(A1-Pad1)")
(net 64 "Net-(R2-Pad1)")
(net_class Default "This is the default net class."
(clearance 0.1778)
@ -179,6 +174,7 @@
(add_net /TST)
(add_net /VCORE)
(add_net GND)
(add_net "Net-(A1-Pad1)")
(add_net "Net-(BRD1-Pad3)")
(add_net "Net-(BRD1-Pad4)")
(add_net "Net-(KPD1-Pad1)")
@ -222,21 +218,15 @@
(add_net "Net-(LCD1-Pad7)")
(add_net "Net-(LCD1-Pad8)")
(add_net "Net-(LCD1-Pad9)")
(add_net "Net-(R2-Pad1)")
(add_net "Net-(U1-Pad36)")
(add_net "Net-(U1-Pad37)")
(add_net "Net-(U1-Pad38)")
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(add_net "Net-(U1-Pad42)")
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(add_net "Net-(U1-Pad47)")
(add_net "Net-(U1-Pad48)")
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(add_net "Net-(U1-Pad54)")
(add_net "Net-(U1-Pad55)")
(add_net "Net-(U2-Pad1)")
(add_net VCC)
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@ -267,19 +257,19 @@
(pad 3 smd oval (at -4.475 -2.75 270) (size 0.25 0.8) (layers F.Cu F.Paste F.Mask)
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@ -335,41 +325,41 @@
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@ -438,11 +428,11 @@
(pad 1 connect rect (at 0.2 0) (size 0.31 1.75) (layers F.Cu F.Mask)
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(pad 6 connect rect (at 3.2 0) (size 0.31 1.75) (layers F.Cu F.Mask)
@ -504,7 +494,7 @@
(pad 34 connect rect (at 20 0) (size 0.31 1.75) (layers F.Cu F.Mask)
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(net 59 "Net-(LCD1-Pad35)"))
)
(module Crystals:Crystal_SMD_3215-2pin_3.2x1.5mm (layer B.Cu) (tedit 58CD2E9C) (tstamp 58F2CD65)
@ -533,9 +523,9 @@
(fp_line (start -2 1.15) (end -2 -1.15) (layer B.CrtYd) (width 0.05))
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(net 51 "Net-(U1-Pad54)"))
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(scale (xyz 0.2 0.2 0.2))
@ -566,7 +556,7 @@
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@ -649,9 +639,9 @@
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(net 60 /!RST))
(net 54 /!RST))
)
(module Capacitors_SMD:C_0402 (layer F.Cu) (tedit 5415D599) (tstamp 59D2E652)
@ -743,7 +733,7 @@
(fp_line (start 0.25 -0.475) (end -0.25 -0.475) (layer F.SilkS) (width 0.15))
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(net 58 /VCORE))
(pad 2 smd rect (at 0.55 0) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask)
(net 43 GND))
(model Capacitors_SMD.3dshapes/C_0402.wrl
@ -763,19 +753,69 @@
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at 0.64 0) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask)
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(net 43 GND))
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(net 67 /RF_P))
(net 61 /RF_P))
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(net 43 GND))
(pad 6 smd rect (at 0.64 1.25) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask)
(net 43 GND))
)
(module GoodWatch20:YageoS432 (layer F.Cu) (tedit 59D2F747) (tstamp 59D2F875)
(at 85.297 72.049 90)
(path /59D2F54A)
(fp_text reference A1 (at 6 1 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value YageoS432 (at 6 -1 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at 0 0 90) (size 1 4) (layers F.Cu F.Paste F.Mask)
(net 63 "Net-(A1-Pad1)"))
(pad 2 smd rect (at 12.3 0 90) (size 1 4) (layers F.Cu F.Paste F.Mask))
)
(module Resistors_SMD:R_0201 (layer F.Cu) (tedit 58E0A804) (tstamp 59D2F87B)
(at 109.4016 96.475001)
(descr "Resistor SMD 0201, reflow soldering, Vishay (see crcw0201e3.pdf)")
(tags "resistor 0201")
(path /59D2FA2B)
(attr smd)
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(effects (font (size 1 1) (thickness 0.15)))
)
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(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 -1.25) (layer F.Fab)
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)
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(fp_line (start 0.3 -0.15) (end 0.3 0.15) (layer F.Fab) (width 0.1))
(fp_line (start -0.3 -0.15) (end 0.3 -0.15) (layer F.Fab) (width 0.1))
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(net 43 GND))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0201.wrl
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)
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(connect_pads (clearance 0.508))

View File

@ -0,0 +1,10 @@
(module YageoS432 (layer F.Cu) (tedit 59D2F747)
(fp_text reference REF** (at 6 1) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value YageoS432 (at 6 -1) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at 0 0) (size 1 4) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 12.3 0) (size 1 4) (layers F.Cu F.Paste F.Mask))
)

View File

@ -614,12 +614,12 @@ Wire Wire Line
Text Label 9150 6000 0 60 ~ 0
GND
$Comp
L YageoS432 A?
L YageoS432 A1
U 1 1 59D2F54A
P 9150 5250
F 0 "A?" H 9150 5650 60 0000 C CNN
F 0 "A1" H 9150 5650 60 0000 C CNN
F 1 "YageoS432" V 9000 5350 60 0000 C CNN
F 2 "" H 9150 5250 60 0001 C CNN
F 2 "GoodWatch20:YageoS432" H 9150 5250 60 0001 C CNN
F 3 "" H 9150 5250 60 0001 C CNN
1 9150 5250
1 0 0 -1
@ -630,16 +630,16 @@ U 1 1 59D2FA2B
P 4700 5600
F 0 "R2" V 4600 5600 50 0000 C CNN
F 1 "56k" V 4700 5600 50 0000 C CNN
F 2 "" V 4630 5600 50 0000 C CNN
F 2 "Resistors_SMD:R_0201" V 4630 5600 50 0001 C CNN
F 3 "" H 4700 5600 50 0000 C CNN
1 4700 5600
1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR012
U 1 1 59D2FD8F
P 4700 5800
F 0 "#PWR?" H 4700 5550 50 0001 C CNN
F 0 "#PWR012" H 4700 5550 50 0001 C CNN
F 1 "GND" H 4700 5650 50 0000 C CNN
F 2 "" H 4700 5800 50 0000 C CNN
F 3 "" H 4700 5800 50 0000 C CNN
@ -655,7 +655,7 @@ Wire Wire Line
Wire Wire Line
4100 5200 4100 5250
Wire Wire Line
5500 5250 4100 5250
4100 5250 5500 5250
Wire Wire Line
4200 5200 4200 5250
Connection ~ 4200 5250
@ -669,12 +669,12 @@ Wire Wire Line
4800 5200 4800 5250
Connection ~ 4800 5250
Wire Wire Line
5500 5050 5500 5250
5500 5250 5500 5050
$Comp
L VCC #PWR?
L VCC #PWR013
U 1 1 59D30A8B
P 5500 5050
F 0 "#PWR?" H 5500 4900 50 0001 C CNN
F 0 "#PWR013" H 5500 4900 50 0001 C CNN
F 1 "VCC" H 5500 5200 50 0000 C CNN
F 2 "" H 5500 5050 50 0000 C CNN
F 3 "" H 5500 5050 50 0000 C CNN