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Reduces 32kHz load capacitance. I believe it is now at the appropriate level.
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@ -25,7 +25,7 @@ void ucs_slow(){
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//! Initialize the XT1 crystal, and stabilize it.
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void ucs_init(){
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P5SEL |= BIT0 + BIT1; // Select XT1
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UCSCTL6 |= XCAP_3; // Internal load cap
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UCSCTL6 |= XCAP_1; // Internal load cap
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// Loop until XT1 & DCO stabilizes
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do{
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