mirror of
https://github.com/travisgoodspeed/goodwatch
synced 2024-11-23 01:08:35 +00:00
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/* RTC driver for the GoodWatch.
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*/
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#include <msp430.h>
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#include <string.h>
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#include "rtc.h"
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#include "lcd.h"
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#include "lcdtext.h"
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static unsigned long magicword __attribute__ ((section (".noinit")));
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static unsigned char ramsavetime[8] __attribute__ ((section (".noinit")));
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static unsigned char *romsavetime=(unsigned char*) 0xFF00;
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//! Save the times to RAM. Must be fast.
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static void rtc_savetime(){
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ramsavetime[0]=RTCHOUR;
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ramsavetime[1]=RTCMIN;
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ramsavetime[2]=RTCSEC;
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*((int*) &(ramsavetime[4]))=RTCYEAR;
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ramsavetime[6]=RTCMON;
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ramsavetime[7]=RTCDAY;
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//Set the magic word, so we'll know the time is good.
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magicword=0xdeadbeef;
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}
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//! Load the time from RAM or ROM
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static void rtc_loadtime(){
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//Use the RAM copy if it is reasonable.
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if(magicword!=0xdeadbeef){
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memcpy(ramsavetime,romsavetime,8);
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}
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//Default clock comes from flash.
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//RTC will fix any corruption.
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RTCHOUR = ramsavetime[0] %24;
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RTCMIN = ramsavetime[1] %60;
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RTCSEC = ramsavetime[2] %60;
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RTCYEAR = (ramsavetime[4]+(ramsavetime[5]<<8)) % 4096;
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RTCMON = ramsavetime[6];
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RTCDAY = ramsavetime[7]; //Not sure why, but we have to set
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RTCDAY = ramsavetime[7]; //the day twice. RTC Errata?
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}
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//! Initializes the clock with the timestamp from memory.
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void rtc_init(){
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// Setup RTC Timer
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// Calendar Mode, RTC1PS, 8-bit ovf
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// overflow interrupt enable
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RTCCTL01 = RTCTEVIE + RTCSSEL_2 + RTCTEV_0 + RTCMODE;
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RTCPS0CTL = RT0PSDIV_2; // ACLK, /8, start timer
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RTCPS1CTL = RT1SSEL_2 + RT1PSDIV_3; // out from RT0PS, /16, start timer
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rtc_loadtime();
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}
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void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void){
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//Save the time once a minute, so that when we reboot, we loose just
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//a few seconds. We might later decide to call this in the
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//rendering loop.
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rtc_savetime();
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//We don't really handly these, but might want to in the future.
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switch(RTCIV&~1){
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case 0: break; // No interrupts
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case 2: break; // RTCRDYIFG
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case 4: break; // RTCTEVIFG
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case 6: break; // RTCAIFG Alarm
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case 8: break; // RT0PSIFG
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case 10: break; // RT1PSIFG
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case 12: break; // Reserved
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case 14: break; // Reserved
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case 16: break; // Reserved
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default: break;
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}
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}
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