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https://github.com/travisgoodspeed/goodwatch
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423 lines
13 KiB
C
423 lines
13 KiB
C
/*! \file radio.c
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\brief RF1A Radio Module Driver
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This is our neighborly little driver for the RF1A radio module.
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While we try really hard to avoid lasagna-code by over-abstracting
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drivers, the radio needs to be abstracted for good reasons, with
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exceptions to that rule in applications as appropriate.
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In general:
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1) Not all watches have a radio, so your application ought to
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gracefully fail if XT2 is not present.
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2) The CR2016 battery lasts forever when telling the time, but
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you'll quickly run out of juice if you leave the radio on. For this
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reason, your app should probably time out after three minutes and
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you should never expect to be receiving in the background.
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3) Remember that transmitting is cheaper than receiving, because a
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transmitter can shut down afterward.
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4) The CPU runs at 32kHz by default. You can speed it up, but at
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the cost of power consumption.
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*/
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#include<stdio.h>
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#include<stdint.h>
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#include<msp430.h>
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#include "power.h"
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#include "radio.h"
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#include "configdefault.h"
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//! Cleared to zero at the first radio failure.
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int has_radio=1;
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//! Sets the radio frequency.
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void radio_setfreq(float freq){
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float freqMult = (0x10000 / 1000000.0) / 26;
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uint32_t num = freq * freqMult;
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//Store the frequency.
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radio_writereg(FREQ2, (num >> 16) & 0xFF);
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radio_writereg(FREQ1, (num >> 8) & 0xFF);
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radio_writereg(FREQ0, num & 0xFF);
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//Strobe a calibration to make it count.
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radio_strobe(RF_SCAL);
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//Wait for it to take effect.
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while(radio_getstate()!=1);
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}
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//! Sets the raw radio frequency registers.
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void radio_setrawfreq(uint8_t freq2, uint8_t freq1, uint8_t freq0){
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//Store the frequency.
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radio_writereg(FREQ2, freq2);
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radio_writereg(FREQ1, freq1);
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radio_writereg(FREQ0, freq0);
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//Strobe a calibration to make it count.
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radio_strobe(RF_SCAL);
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//Wait for it to take effect.
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while(radio_getstate()!=1);
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}
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//! Gets the radio frequency.
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uint32_t radio_getfreq(){
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static uint32_t oldhex=0, oldnum=0;
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uint32_t hex=
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0xFF0000l & (((uint32_t) radio_readreg(FREQ2))<<16);
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hex|= (0xFF00l & (radio_readreg(FREQ1)<<8));
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hex|= (0xFFl & (radio_readreg(FREQ0)));
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//Return the old value if it hasn't changed.
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if(oldhex==hex)
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return oldnum;
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//Otherwise calculate the new value and return it.
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oldhex=hex;
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oldnum=hex*396.728515625;
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return oldnum;
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}
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// Only called from here.
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extern void packet_init();
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//! Called at boot. Gracefully fails if no radio.
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void radio_init(){
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/* If the radio components are missing, the AVCC_RF lines will be
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unconnected and the radio will immediately have a low voltage error.
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*/
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radio_on();
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/* We can't check RF1AIFERR&1 to tell whether the radio circuit is
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powered, because Errata RF1A6 makes that bit useless. Instead,
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we run a radio strobe and look for its reply.
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*/
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radio_strobe(RF_SCAL);
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printf("This watch has %s radio.\n",
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has_radio?"a":"no");
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radio_off();
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}
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//! Turns the radio on. Returns zero on failure.
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void radio_on(){
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if(!has_radio){
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return;
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}
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//Be sure to reset the radio variables, in case the state machine is
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//out of whack. This should only be called from here, nowhere else.
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packet_init();
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//Enable high power mode so that LPM3 can be used with an active
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//radio.
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PMMCTL0_H = 0xA5;
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PMMCTL0_L |= PMMHPMRE_L;
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PMMCTL0_H = 0x00;
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//Step up the core voltage a bit.
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while(!power_setvcore(COREVOLTAGE)){
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printf("Failed to set vcore.\n");
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__delay_cycles(850);
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}
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__delay_cycles(850);
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//Strobe the radio to reset it.
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radio_resetcore();
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}
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//! Restarts the radio.
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void radio_resetcore(){
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//Reset the core.
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radio_strobe(RF_SRES);
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//Wait for readiness, or give up if there's no radio.
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while(has_radio && radio_strobe(RF_SIDLE)&0x70);
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}
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//! Turns the radio off.
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void radio_off(){
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//Cut the radio's oscillator.
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radio_strobe(RF_SRES);
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radio_strobe(RF_SXOFF);
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/* We really ought to lower the core voltage, but seems that it can
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never come back up.
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*/
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//Drop the voltage first.
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power_setvcore(0);
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__delay_cycles(850);
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//Then disable high-power mode.
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PMMCTL0_H = 0xA5;
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PMMCTL0_L &= ~PMMHPMRE_L;
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PMMCTL0_H = 0x00;
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}
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//! Read a register from the radio.
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uint8_t radio_readreg(uint8_t addr){
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// Check for valid configuration register address, 0x3E refers to PATABLE
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if ((addr <= 0x2E) || (addr == 0x3E))
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// Send address + Instruction + 1 dummy byte (auto-read)
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RF1AINSTR1B = (addr | RF_SNGLREGRD);
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else
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// Send address + Instruction + 1 dummy byte (auto-read)
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RF1AINSTR1B = (addr | RF_STATREGRD);
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while (!(RF1AIFCTL1 & RFDOUTIFG) );
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//Reading the data clears the interrupt flag.
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return RF1ADOUTB;
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}
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//! Read multiple bytes from a register.
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void radio_readburstreg(uint8_t addr,
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uint8_t *buffer, uint8_t count){
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unsigned int i;
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if(count > 0){
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while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for INSTRIFG
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RF1AINSTR1B = (addr | RF_REGRD); // Send addr of first conf. reg. to be read
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// ... and the burst-register read instruction
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for (i = 0; i < (count-1); i++) {
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while (!(RFDOUTIFG&RF1AIFCTL1)); // Wait for the Radio Core to update the RF1ADOUTB reg
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buffer[i] = RF1ADOUT1B; // Read DOUT from Radio Core + clears RFDOUTIFG
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// Also initiates auo-read for next DOUT byte
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}
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buffer[count-1] = RF1ADOUT0B; // Store the last DOUT from Radio Core
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}
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}
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//! Write multiple bytes to a register.
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void radio_writeburstreg(uint8_t addr,
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uint8_t *buffer, uint8_t count){
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unsigned char i;
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if(count > 0){
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while (!(RF1AIFCTL1 & RFINSTRIFG)); // Wait for the Radio to be ready for next instruction
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RF1AINSTRW = ((addr | RF_REGWR)<<8 ) + buffer[0]; // Send address + Instruction
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for (i = 1; i < count; i++) {
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RF1ADINB = buffer[i]; // Send data
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while (!(RFDINIFG & RF1AIFCTL1)); // Wait for TX to finish
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}
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i = RF1ADOUTB; // Reset RFDOUTIFG flag which contains status byte
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}
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}
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//! Write to a register in the radio.
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void radio_writereg(uint8_t addr, uint8_t value){
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// Wait until the radio is ready.
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while (!(RF1AIFCTL1 & RFINSTRIFG));
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// Send the address and instruction.
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RF1AINSTRB = (addr | RF_SNGLREGWR);
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// And the value.
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RF1ADINB = value;
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}
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// Chipcon
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// Product = CC430Fx13x
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// Chip version = C (PG 0.7)
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// Crystal accuracy = 10 ppm
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// X-tal frequency = 26 MHz
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// RF output power = 0 dBm
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// RX filterbandwidth = 101.562500 kHz
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// Deviation = 19 kHz
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// Datarate = 38.383484 kBaud
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// Modulation = (1) GFSK
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// Manchester enable = (0) Manchester disabled
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// RF Frequency = 914.999969 MHz
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// Channel spacing = 199.951172 kHz
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// Channel number = 0
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// Optimization = -
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// Sync mode = (3) 30/32 sync word bits detected
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// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
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// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
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// Forward Error Correction =
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// Length configuration = (0) Fixed packet length, packet length configured by PKTLEN
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// Packetlength = 61
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// Preamble count = (2) 4 bytes
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// Append status = 1
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// Address check = (0) No address check
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// FIFO autoflush = 0
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// Device address = 0
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// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
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// GDO2 signal selection = (41) RF_RDY
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const uint8_t morsesettings[]={
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FSCTRL1, 0x08, // FSCTRL1 Frequency synthesizer control.
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FSCTRL0, 0x00, // FSCTRL0 Frequency synthesizer control.
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FREQ2, 0x23, // FREQ2 Frequency control word, high byte.
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FREQ1, 0x31, // FREQ1 Frequency control word, middle byte.
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FREQ0, 0x3B, // FREQ0 Frequency control word, low byte.
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MDMCFG4, 0xCA, // MDMCFG4 Modem configuration.
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MDMCFG3, 0x83, // MDMCFG3 Modem configuration.
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MDMCFG2, 0x93, // MDMCFG2 Modem configuration.
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MDMCFG1, 0x22, // MDMCFG1 Modem configuration.
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MDMCFG0, 0xF8, // MDMCFG0 Modem configuration.
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CHANNR, 0x00, // CHANNR Channel number.
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DEVIATN, 0x34, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
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FREND1, 0x56, // FREND1 Front end RX configuration.
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FREND0, 0x11, // FREND0 Front end TX configuration.
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MCSM0, 0x18, // MCSM0 Main Radio Control State Machine configuration.
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FOCCFG, 0x16, // FOCCFG Frequency Offset Compensation Configuration.
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BSCFG, 0x6C, // BSCFG Bit synchronization Configuration.
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AGCCTRL2, 0x43, // AGCCTRL2 AGC control.
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AGCCTRL1, 0x40, // AGCCTRL1 AGC control.
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AGCCTRL0, 0x91, // AGCCTRL0 AGC control.
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FSCAL3, 0xE9, // FSCAL3 Frequency synthesizer calibration.
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FSCAL2, 0x2A, // FSCAL2 Frequency synthesizer calibration.
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FSCAL1, 0x00, // FSCAL1 Frequency synthesizer calibration.
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FSCAL0, 0x1F, // FSCAL0 Frequency synthesizer calibration.
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FSTEST, 0x59, // FSTEST Frequency synthesizer calibration.
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TEST2, 0x81, // TEST2 Various test settings.
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TEST1, 0x35, // TEST1 Various test settings.
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TEST0, 0x09, // TEST0 Various test settings.
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FIFOTHR, 0x47, // FIFOTHR RXFIFO and TXFIFO thresholds.
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IOCFG2, 0x29, // IOCFG2 GDO2 output pin configuration.
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IOCFG0, 0x06, // IOCFG0 GDO0 output pin configuration. Refer to SmartRF? Studio User Manual for detailed pseudo register explanation.
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PKTCTRL1, 0x04, // PKTCTRL1 Packet automation control.
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PKTCTRL0, 0x04, // PKTCTRL0 Packet automation control.
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ADDR, 0x00, // ADDR Device address.
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PKTLEN, 0x64, // PKTLEN Packet length.
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0, 0
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};
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//! Writes a table of radio settings until the first null pair.
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void radio_writesettings(const uint8_t *settings){
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int i=0;
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/* If there are no settings, we default to sending Morse code.
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*/
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if(!settings)
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settings=morsesettings;
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/* This is ugly as sin, and it deserves a bit of an explanation. We
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are terminating on a null *pair* in the settings, so that every
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pair can be set except setting IOCFG2 to 0, as that would be a
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null pair.
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*/
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while(settings[i]!=0 || settings[i+1]!=0){
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radio_writereg(settings[i],settings[i+1]);
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//printf("%02x,%02x\n",settings[i],settings[i+1]);
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i+=2;
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}
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}
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//! Strobe a radio register.
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uint8_t radio_strobe(uint8_t strobe){
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uint8_t statusByte = 0;
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uint16_t count=0;
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uint16_t gdo_state;
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/*
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if(!has_radio)
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return 0xFF;
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*/
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// Check for valid strobe command
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if((strobe == 0xBD) || ((strobe >= RF_SRES) && (strobe <= RF_SNOP))){
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// Clear the Status read flag
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RF1AIFCTL1 &= ~(RFSTATIFG);
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// Wait for radio to be ready for next instruction
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while( !(RF1AIFCTL1 & RFINSTRIFG));
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// Write the strobe instruction
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if ((strobe > RF_SRES) && (strobe < RF_SNOP)){
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gdo_state = radio_readreg(IOCFG2); // buffer IOCFG2 state
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radio_writereg(IOCFG2, 0x29); // chip-ready to GDO2
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RF1AINSTRB = strobe;
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if ( (RF1AIN&0x04)== 0x04 ) { // chip at sleep mode
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if ( (strobe == RF_SXOFF) || (strobe == RF_SPWD) || (strobe == RF_SWOR) ) {
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}else{
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/* We'll get stuck in an infinite loop here if the radio
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crystal isn't available.
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*/
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while ((RF1AIN&0x04)== 0x04){
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if(count++>1000){
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//printf("Timeout in radio_strobe. Broken XT2?\n");
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has_radio=0;
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return 0xFF;
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}
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}
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// Delay for ~810usec at 1.05MHz CPU clock, see erratum RF1A7
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__delay_cycles(850);
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}
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}
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radio_writereg(IOCFG2, gdo_state); // restore IOCFG2 setting
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while( !(RF1AIFCTL1 & RFSTATIFG) );
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}else{ //Active mode
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RF1AINSTRB = strobe;
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}
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statusByte = RF1ASTATB;
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}
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return statusByte;
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}
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//! Writes one value to the power table.
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void radio_writepower(uint8_t value) {
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uint8_t powertable[2];
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/* To make AFSK and OOK play nice with eachother, powertable[0] is
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always zero and powertable[1] is the selected power setting.
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Use radio_writepowertable() if you need to control the entire table.
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*/
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powertable[0]=0;
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powertable[1]=value;
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radio_writepatable(powertable, 2);
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while( !(RF1AIFCTL1 & RFINSTRIFG));
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RF1AINSTRB = RF_SNOP; // reset PA_Table pointer
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}
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//! Writes a set of values ot the power table.
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void radio_writepatable(uint8_t *table, uint8_t count) {
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radio_writeburstreg(PATABLE, table, count);
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}
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//! Read the RSSI.
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int radio_getrssi(){
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int rssi;
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//Enter RX mode to get the value if we aren't already there.
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radio_strobe(RF_SRX);
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//Need a delay before the value becomes valid.
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__delay_cycles(400);
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//Idle when we're done.
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radio_strobe(RF_SIDLE);
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//Grab the new value.
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rssi=radio_readreg(RSSI)^0x80;
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return rssi;
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}
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//! Read the radio MARC state.
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int radio_getstate(){
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int state;
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state=radio_readreg(MARCSTATE);
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return state;
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}
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