2024-02-04 12:32:49 +00:00
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/* Original work Copyright 2023 Dual Tachyon
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2023-09-09 07:03:56 +00:00
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* https://github.com/DualTachyon
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*
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2024-02-04 12:32:49 +00:00
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* Modified work Copyright 2024 kamilsss655
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* https://github.com/kamilsss655
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*
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2023-09-09 07:03:56 +00:00
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef HARDWARE_DP32G030_AES_H
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#define HARDWARE_DP32G030_AES_H
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#if !defined(__ASSEMBLY__)
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#include <stdint.h>
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#endif
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/* -------- AES -------- */
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#define AES_BASE_ADDR 0x400BD000U
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#define AES_BASE_SIZE 0x00000800U
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#define AES_CR_ADDR (AES_BASE_ADDR + 0x0000U)
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#define AES_CR (*(volatile uint32_t *)AES_CR_ADDR)
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#define AES_CR_EN_SHIFT 0
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#define AES_CR_EN_WIDTH 1
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#define AES_CR_EN_MASK (((1U << AES_CR_EN_WIDTH) - 1U) << AES_CR_EN_SHIFT)
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#define AES_CR_EN_VALUE_DISABLE 0U
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#define AES_CR_EN_BITS_DISABLE (AES_CR_EN_VALUE_DISABLE << AES_CR_EN_SHIFT)
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#define AES_CR_EN_VALUE_ENABLE 1U
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#define AES_CR_EN_BITS_ENABLE (AES_CR_EN_VALUE_ENABLE << AES_CR_EN_SHIFT)
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#define AES_CR_CHMOD_SHIFT 5
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#define AES_CR_CHMOD_WIDTH 2
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#define AES_CR_CHMOD_MASK (((1U << AES_CR_CHMOD_WIDTH) - 1U) << AES_CR_CHMOD_SHIFT)
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#define AES_CR_CHMOD_VALUE_ECB 0U
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#define AES_CR_CHMOD_BITS_ECB (AES_CR_CHMOD_VALUE_ECB << AES_CR_CHMOD_SHIFT)
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#define AES_CR_CHMOD_VALUE_CBC 1U
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#define AES_CR_CHMOD_BITS_CBC (AES_CR_CHMOD_VALUE_CBC << AES_CR_CHMOD_SHIFT)
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#define AES_CR_CHMOD_VALUE_CTR 2U
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#define AES_CR_CHMOD_BITS_CTR (AES_CR_CHMOD_VALUE_CTR << AES_CR_CHMOD_SHIFT)
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#define AES_CR_CCFC_SHIFT 7
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#define AES_CR_CCFC_WIDTH 1
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#define AES_CR_CCFC_MASK (((1U << AES_CR_CCFC_WIDTH) - 1U) << AES_CR_CCFC_SHIFT)
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#define AES_CR_CCFC_VALUE_SET 1U
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#define AES_CR_CCFC_BITS_SET (AES_CR_CCFC_VALUE_SET << AES_CR_CCFC_SHIFT)
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#define AES_SR_ADDR (AES_BASE_ADDR + 0x0004U)
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#define AES_SR (*(volatile uint32_t *)AES_SR_ADDR)
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#define AES_SR_CCF_SHIFT 0
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#define AES_SR_CCF_WIDTH 1
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#define AES_SR_CCF_MASK (((1U << AES_SR_CCF_WIDTH) - 1U) << AES_SR_CCF_SHIFT)
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#define AES_SR_CCF_VALUE_NOT_COMPLETE 0U
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#define AES_SR_CCF_BITS_NOT_COMPLETE (AES_SR_CCF_VALUE_NOT_COMPLETE << AES_SR_CCF_SHIFT)
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#define AES_SR_CCF_VALUE_COMPLETE 1U
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#define AES_SR_CCF_BITS_COMPLETE (AES_SR_CCF_VALUE_COMPLETE << AES_SR_CCF_SHIFT)
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#define AES_DINR_ADDR (AES_BASE_ADDR + 0x0008U)
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#define AES_DINR (*(volatile uint32_t *)AES_DINR_ADDR)
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#define AES_DOUTR_ADDR (AES_BASE_ADDR + 0x000CU)
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#define AES_DOUTR (*(volatile uint32_t *)AES_DOUTR_ADDR)
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#define AES_KEYR0_ADDR (AES_BASE_ADDR + 0x0010U)
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#define AES_KEYR0 (*(volatile uint32_t *)AES_KEYR0_ADDR)
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#define AES_KEYR1_ADDR (AES_BASE_ADDR + 0x0014U)
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#define AES_KEYR1 (*(volatile uint32_t *)AES_KEYR1_ADDR)
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#define AES_KEYR2_ADDR (AES_BASE_ADDR + 0x0018U)
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#define AES_KEYR2 (*(volatile uint32_t *)AES_KEYR2_ADDR)
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#define AES_KEYR3_ADDR (AES_BASE_ADDR + 0x001CU)
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#define AES_KEYR3 (*(volatile uint32_t *)AES_KEYR3_ADDR)
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#define AES_IVR0_ADDR (AES_BASE_ADDR + 0x0020U)
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#define AES_IVR0 (*(volatile uint32_t *)AES_IVR0_ADDR)
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#define AES_IVR1_ADDR (AES_BASE_ADDR + 0x0024U)
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#define AES_IVR1 (*(volatile uint32_t *)AES_IVR1_ADDR)
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#define AES_IVR2_ADDR (AES_BASE_ADDR + 0x0028U)
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#define AES_IVR2 (*(volatile uint32_t *)AES_IVR2_ADDR)
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#define AES_IVR3_ADDR (AES_BASE_ADDR + 0x002CU)
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#define AES_IVR3 (*(volatile uint32_t *)AES_IVR3_ADDR)
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#endif
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