#ifndef DP32G030_IRQ_H
#define DP32G030_IRQ_H

enum {
	DP32_WWDT_IRQn = 0,
	DP32_IWDT_IRQn,
	DP32_RTC_IRQn,
	DP32_DMA_IRQn,
	DP32_SARADC_IRQn,
	DP32_TIMER_BASE0_IRQn,
	DP32_TIMER_BASE1_IRQn,
	DP32_TIMER_PLUS0_IRQn,
	DP32_TIMER_PLUS1_IRQn,
	DP32_PWM_BASE0_IRQn,
	DP32_PWM_BASE1_IRQn,
	DP32_PWM_PLUS0_IRQn,
	DP32_PWM_PLUS1_IRQn,
	DP32_UART0_IRQn,
	DP32_UART1_IRQn,
	DP32_UART2_IRQn,
	DP32_SPI0_IRQn,
	DP32_SPI1_IRQn,
	DP32_IIC0_IRQn,
	DP32_IIC1_IRQn,
	DP32_CMP_IRQn,
	DP32_TIMER_BASE2_IRQn,
	DP32_GPIOA5_IRQn,
	DP32_GPIOA6_IRQn,
	DP32_GPIOA7_IRQn,
	DP32_GPIOB0_IRQn,
	DP32_GPIOB1_IRQn,
	DP32_GPIOC0_IRQn,
	DP32_GPIOC1_IRQn,
	DP32_GPIOA_IRQn,
	DP32_GPIOB_IRQn,
	DP32_GPIOC_IRQn,
};

#endif