mirror of
https://github.com/kamilsss655/uv-k5-firmware-custom
synced 2024-11-21 17:57:59 +00:00
69 lines
3.3 KiB
C
69 lines
3.3 KiB
C
/* Original work Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Modified work Copyright 2024 kamilsss655
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* https://github.com/kamilsss655
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef HARDWARE_DP32G030_PMU_H
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#define HARDWARE_DP32G030_PMU_H
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#if !defined(__ASSEMBLY__)
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#include <stdint.h>
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#endif
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/* -------- PMU -------- */
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#define PMU_BASE_ADDR 0x40000800U
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#define PMU_BASE_SIZE 0x00000800U
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#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U)
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#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR)
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#define PMU_SRC_CFG_RCHF_EN_SHIFT 0
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#define PMU_SRC_CFG_RCHF_EN_WIDTH 1
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#define PMU_SRC_CFG_RCHF_EN_MASK (((1U << PMU_SRC_CFG_RCHF_EN_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_EN_SHIFT)
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#define PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE 0U
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#define PMU_SRC_CFG_RCHF_EN_BITS_DISABLE (PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)
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#define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U
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#define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)
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#define PMU_SRC_CFG_RCHF_SEL_SHIFT 1
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#define PMU_SRC_CFG_RCHF_SEL_WIDTH 1
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#define PMU_SRC_CFG_RCHF_SEL_MASK (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT)
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#define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ 0U
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#define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)
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#define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ 1U
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#define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)
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#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U)
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#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)
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#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U)
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#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR)
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#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U)
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#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR)
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#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU)
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#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR)
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#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U)
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#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR)
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#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U)
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#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR)
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#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U)
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#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR)
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#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU)
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#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR)
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#endif
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