mirror of
https://github.com/kamilsss655/uv-k5-firmware-custom
synced 2024-11-22 10:18:15 +00:00
146 lines
6.0 KiB
C
146 lines
6.0 KiB
C
#ifndef HARDWARE_DP32G030_PWMPLUS_H
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#define HARDWARE_DP32G030_PWMPLUS_H
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#define PWM_PLUS0_BASE_ADDR 0x400B4000U
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//---------------
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#define PWMPLUS_CFG 0x00U
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#define PWMPLUS_CFG_COUNTER_EN_SHIFT 0U
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#define PWMPLUS_CFG_COUNTER_EN_WIDTH 1U
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#define PWMPLUS_CFG_COUNTER_EN_MASK (((1U << PWMPLUS_CFG_COUNTER_EN_WIDTH) - 1U) << PWMPLUS_CFG_COUNTER_EN_SHIFT)
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#define PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE 1U
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#define PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE (PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE << PWMPLUS_CFG_COUNTER_EN_SHIFT)
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#define PWMPLUS_CFG_CNT_TYPE_SHIFT 1U
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#define PWMPLUS_CFG_CNT_REP_SHIFT 2U
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#define PWMPLUS_CFG_CNT_REP_WIDTH 1U
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#define PWMPLUS_CFG_CNT_REP_VALUE_ENABLE 1U
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#define PWMPLUS_CFG_CNT_REP_BITS_ENABLE (PWMPLUS_CFG_CNT_REP_VALUE_ENABLE << PWMPLUS_CFG_CNT_REP_SHIFT)
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#define PWMPLUS_CFG_OUT_MODE_SHIFT 3U
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#define PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE 1U
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#define PWMPLUS_CFG_OUT_MODE_BITS_ENABLE (PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE << PWMPLUS_CFG_OUT_MODE_SHIFT)
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#define PWMPLUS_CFG_AUTO_RELOAD_SHIFT 8U
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//---------------
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#define PWMPLUS_GEN 0x04U
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#define PWMPLUS_GEN_CH0_OE_SHIFT 24U
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#define PWMPLUS_GEN_CH0_OE_WIDTH 1U
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#define PWMPLUS_GEN_CH0_OE_VALUE_ENABLE 1U
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#define PWMPLUS_GEN_CH0_OE_BITS_ENABLE (PWMPLUS_GEN_CH0_OE_VALUE_ENABLE << PWMPLUS_GEN_CH0_OE_SHIFT)
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#define PWMPLUS_GEN_CH0_OUTINV_SHIFT 16U
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#define PWMPLUS_GEN_CH0_OUTINV_WIDTH 1U
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#define PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE 1U
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#define PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE (PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE << PWMPLUS_GEN_CH0_OUTINV_SHIFT)
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#define PWMPLUS_GEN_CH0_START_SHIFT 8U
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#define PWMPLUS_GEN_CH0_START_WIDTH 1U
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#define PWMPLUS_GEN_CH0_START_VALUE_ENABLE 1U
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#define PWMPLUS_GEN_CH0_START_BITS_ENABLE (PWMPLUS_GEN_CH0_START_VALUE_ENABLE << PWMPLUS_GEN_CH0_START_SHIFT)
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#define PWMPLUS_GEN_CH0_IDLE_SHIFT 0U
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#define PWMPLUS_GEN_CH0_IDLE_WIDTH 1U
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#define PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE 1U
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#define PWMPLUS_GEN_CH0_IDLE_BITS_ENABLE (PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE << PWMPLUS_GEN_CH0_IDLE_SHIFT)
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//---------------
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#define PWMPLUS_CLKSRC 0x08U
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#define PWMPLUS_BRAKE_CFG 0x0CU
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#define PWMPLUS_MASK_LEV 0x10U
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#define PWMPLUS_PERIOD 0x1CU
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#define PWMPLUS_CH0_COMP 0x20U
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#define PWMPLUS_CH1_COMP 0x24U
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#define PWMPLUS_CH2_COMP 0x28U
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#define PWMPLUS_CH0_DT 0x30U
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#define PWMPLUS_CH1_DT 0x34U
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#define PWMPLUS_CH2_DT 0x38U
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#define PWMPLUS_TRIG_COMP 0x40U
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#define PWMPLUS_TRIG_CFG 0x44U
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#define PWMPLUS_IE 0x60U
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#define PWMPLUS_IF 0x64U
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#define PWMPLUS_SWLOAD 0x84U
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#define PWMPLUS_MASK_EN 0x88
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#define PWMPLUS_CNT_ST 0xE0
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#define PWMPLUS_BRAKE_ST 0xE4
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#define PWM_PLUS0_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CFG)
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#define PWM_PLUS0_CFG (*(volatile uint32_t *)PWM_PLUS0_CFG_ADDR)
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#define PWM_PLUS0_GEN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_GEN)
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#define PWM_PLUS0_GEN (*(volatile uint32_t *)PWM_PLUS0_GEN_ADDR)
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#define PWM_PLUS0_CLKSRC_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CLKSRC)
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#define PWM_PLUS0_CLKSRC (*(volatile uint32_t *)PWM_PLUS0_CLKSRC_ADDR)
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#define PWM_PLUS0_BRAKE_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_CFG)
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#define PWM_PLUS0_BRAKE_CFG (*(volatile uint32_t *)PWM_PLUS0_BRAKE_CFG_ADDR)
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#define PWM_PLUS0_MASK_LEV_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_LEV)
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#define PWM_PLUS0_MASK_LEV (*(volatile uint32_t *)PWM_PLUS0_MASK_LEV_ADDR)
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#define PWM_PLUS0_PERIOD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_PERIOD)
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#define PWM_PLUS0_PERIOD (*(volatile uint32_t *)PWM_PLUS0_PERIOD_ADDR)
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#define PWM_PLUS0_CH0_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_COMP)
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#define PWM_PLUS0_CH0_COMP (*(volatile uint32_t *)PWM_PLUS0_CH0_COMP_ADDR)
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#define PWM_PLUS0_CH1_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_COMP)
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#define PWM_PLUS0_CH1_COMP (*(volatile uint32_t *)PWM_PLUS0_CH1_COMP_ADDR)
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#define PWM_PLUS0_CH2_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_COMP)
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#define PWM_PLUS0_CH2_COMP (*(volatile uint32_t *)PWM_PLUS0_CH2_COMP_ADDR)
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#define PWM_PLUS0_CH0_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_DT)
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#define PWM_PLUS0_CH0_DT (*(volatile uint32_t *)PWM_PLUS0_CH0_DT_ADDR)
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#define PWM_PLUS0_CH1_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_DT)
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#define PWM_PLUS0_CH1_DT (*(volatile uint32_t *)PWM_PLUS0_CH1_DT_ADDR)
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#define PWM_PLUS0_CH2_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_DT)
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#define PWM_PLUS0_CH2_DT (*(volatile uint32_t *)PWM_PLUS0_CH2_DT_ADDR)
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#define PWM_PLUS0_TRIG_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_COMP)
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#define PWM_PLUS0_TRIG_COMP (*(volatile uint32_t *)PWM_PLUS0_TRIG_COMP_ADDR)
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#define PWM_PLUS0_TRIG_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_CFG)
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#define PWM_PLUS0_TRIG_CFG (*(volatile uint32_t *)PWM_PLUS0_TRIG_CFG_ADDR)
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#define PWM_PLUS0_IE_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IE)
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#define PWM_PLUS0_IE (*(volatile uint32_t *)PWM_PLUS0_IE_ADDR)
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#define PWM_PLUS0_IF_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IF)
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#define PWM_PLUS0_IF (*(volatile uint32_t *)PWM_PLUS0_IF_ADDR)
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#define PWM_PLUS0_SWLOAD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_SWLOAD)
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#define PWM_PLUS0_SWLOAD (*(volatile uint32_t *)PWM_PLUS0_SWLOAD_ADDR)
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#define PWM_PLUS0_MASK_EN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_EN)
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#define PWM_PLUS0_MASK_EN (*(volatile uint32_t *)PWM_PLUS0_MASK_EN_ADDR)
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#define PWM_PLUS0_CNT_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CNT_ST)
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#define PWM_PLUS0_CNT_ST (*(volatile uint32_t *)PWM_PLUS0_CNT_ST_ADDR)
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#define PWM_PLUS0_BRAKE_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_ST)
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#define PWM_PLUS0_BRAKE_ST (*(volatile uint32_t *)PWM_PLUS0_BRAKE_ST_ADDR)
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#endif |