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lavc/aacpsdsp: unroll RISC-V V hybrid_analysis_ileave
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@ -168,10 +168,10 @@ func ff_ps_hybrid_analysis_ileave_rvv, zve32x /* no needs for zve32f here */
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mv t4, a4
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mv t4, a4
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addi a2, a2, 1
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addi a2, a2, 1
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2:
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2:
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vsetvli t5, t3, e32, m1, ta, ma
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vsetvli t5, t3, e32, m4, ta, ma
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vlse32.v v16, (t1), t6
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vlse32.v v16, (t1), t6
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sub t3, t3, t5
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sub t3, t3, t5
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vlse32.v v17, (t4), t6
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vlse32.v v20, (t4), t6
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mul t2, t5, t6
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mul t2, t5, t6
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vsseg2e32.v v16, (t0)
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vsseg2e32.v v16, (t0)
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sh3add t0, t5, t0
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sh3add t0, t5, t0
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