From 96a59cf37b080080b7e45dd57828b40a7a2bbfe7 Mon Sep 17 00:00:00 2001 From: Jason Garrett-Glaser Date: Mon, 26 Sep 2011 14:44:47 -0700 Subject: [PATCH] x86: XOP/FMA4 CPU detection support --- libavutil/avutil.h | 4 ++-- libavutil/cpu.c | 2 ++ libavutil/cpu.h | 2 ++ libavutil/x86/cpu.c | 9 +++++++++ 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/libavutil/avutil.h b/libavutil/avutil.h index 5d378ce3a9..d89b23cf40 100644 --- a/libavutil/avutil.h +++ b/libavutil/avutil.h @@ -40,8 +40,8 @@ #define AV_VERSION(a, b, c) AV_VERSION_DOT(a, b, c) #define LIBAVUTIL_VERSION_MAJOR 51 -#define LIBAVUTIL_VERSION_MINOR 10 -#define LIBAVUTIL_VERSION_MICRO 2 +#define LIBAVUTIL_VERSION_MINOR 11 +#define LIBAVUTIL_VERSION_MICRO 0 #define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \ LIBAVUTIL_VERSION_MINOR, \ diff --git a/libavutil/cpu.c b/libavutil/cpu.c index baa7922daa..25895d6d5d 100644 --- a/libavutil/cpu.c +++ b/libavutil/cpu.c @@ -60,6 +60,8 @@ static const struct { { AV_CPU_FLAG_SSE4, "sse4.1" }, { AV_CPU_FLAG_SSE42, "sse4.2" }, { AV_CPU_FLAG_AVX, "avx" }, + { AV_CPU_FLAG_XOP, "xop" }, + { AV_CPU_FLAG_FMA4, "fma4" }, { AV_CPU_FLAG_3DNOW, "3dnow" }, { AV_CPU_FLAG_3DNOWEXT, "3dnowext" }, #endif diff --git a/libavutil/cpu.h b/libavutil/cpu.h index 777cdc01d1..df7bf4421a 100644 --- a/libavutil/cpu.h +++ b/libavutil/cpu.h @@ -38,6 +38,8 @@ #define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions #define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions #define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used +#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions +#define AV_CPU_FLAG_FMA4 0x0800 ///< Bulldozer FMA4 functions #define AV_CPU_FLAG_IWMMXT 0x0100 ///< XScale IWMMXT #define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard diff --git a/libavutil/x86/cpu.c b/libavutil/x86/cpu.c index f747e4dba8..3975e68533 100644 --- a/libavutil/x86/cpu.c +++ b/libavutil/x86/cpu.c @@ -133,6 +133,15 @@ int ff_get_cpu_flags_x86(void) rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) { rval |= AV_CPU_FLAG_SSE2SLOW; } + + /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be + * used unless the OS has AVX support. */ + if (rval & AV_CPU_FLAG_AVX) { + if (ecx & 0x00000800) + rval |= AV_CPU_FLAG_XOP; + if (ecx & 0x00010000) + rval |= AV_CPU_FLAG_FMA4; + } } if (!strncmp(vendor.c, "GenuineIntel", 12)) {