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riscv: test for assembler support

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This should fix the build on LLVM 16 and earlier, at the cost of turning
all non-RVV optimisations off.

Signed-off-by: Paul B Mahol <onemda@gmail.com>
This commit is contained in:
Rémi Denis-Courmont 2023-12-05 17:54:26 +02:00 committed by Paul B Mahol
parent 74b95c412a
commit eb60a406e4
13 changed files with 33 additions and 16 deletions
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6
Makefile
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@ -93,10 +93,10 @@ ffbuild/.config: $(CONFIGURABLE_COMPONENTS)
SUBDIR_VARS := CLEANFILES FFLIBS HOSTPROGS TESTPROGS TOOLS \
HEADERS ARCH_HEADERS BUILT_HEADERS SKIPHEADERS \
ARMV5TE-OBJS ARMV6-OBJS ARMV8-OBJS VFP-OBJS NEON-OBJS \
ALTIVEC-OBJS VSX-OBJS RVV-OBJS MMX-OBJS X86ASM-OBJS \
ALTIVEC-OBJS VSX-OBJS MMX-OBJS X86ASM-OBJS \
MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSP-OBJS MSA-OBJS \
MMI-OBJS LSX-OBJS LASX-OBJS OBJS SLIBOBJS SHLIBOBJS \
STLIBOBJS HOSTOBJS TESTOBJS
MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS \
OBJS SLIBOBJS SHLIBOBJS STLIBOBJS HOSTOBJS TESTOBJS
define RESET
$(1) :=

5
configure vendored
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@ -2152,6 +2152,7 @@ ARCH_EXT_LIST_PPC="
"
ARCH_EXT_LIST_RISCV="
rv
rvv
"
@ -2677,7 +2678,8 @@ ppc4xx_deps="ppc"
vsx_deps="altivec"
power8_deps="vsx"
rvv_deps="riscv"
rv_deps="riscv"
rvv_deps="rv"
loongson2_deps="mips"
loongson3_deps="mips"
@ -6238,6 +6240,7 @@ elif enabled ppc; then
elif enabled riscv; then
enabled rv && check_inline_asm rv '".option arch, +zbb\nrev8 t0, t1"'
enabled rvv && check_inline_asm rvv '".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"'
elif enabled x86; then

1
ffbuild/arch.mak
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@ -15,6 +15,7 @@ OBJS-$(HAVE_LASX) += $(LASX-OBJS) $(LASX-OBJS-yes)
OBJS-$(HAVE_ALTIVEC) += $(ALTIVEC-OBJS) $(ALTIVEC-OBJS-yes)
OBJS-$(HAVE_VSX) += $(VSX-OBJS) $(VSX-OBJS-yes)
OBJS-$(HAVE_RV) += $(RV-OBJS) $(RV-OBJS-yes)
OBJS-$(HAVE_RVV) += $(RVV-OBJS) $(RVV-OBJS-yes)
OBJS-$(HAVE_MMX) += $(MMX-OBJS) $(MMX-OBJS-yes)

16
libavcodec/riscv/Makefile
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@ -1,15 +1,15 @@
OBJS-$(CONFIG_AAC_DECODER) += riscv/aacpsdsp_init.o riscv/sbrdsp_init.o
RVV-OBJS-$(CONFIG_AAC_DECODER) += riscv/aacpsdsp_rvv.o riscv/sbrdsp_rvv.o
OBJS-$(CONFIG_AC3DSP) += riscv/ac3dsp_init.o \
riscv/ac3dsp_rvb.o
OBJS-$(CONFIG_AC3DSP) += riscv/ac3dsp_init.o
RV-OBJS-$(CONFIG_AC3DSP) += riscv/ac3dsp_rvb.o
RVV-OBJS-$(CONFIG_AC3DSP) += riscv/ac3dsp_rvv.o
OBJS-$(CONFIG_ALAC_DECODER) += riscv/alacdsp_init.o
RVV-OBJS-$(CONFIG_ALAC_DECODER) += riscv/alacdsp_rvv.o
OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_init.o \
riscv/audiodsp_rvf.o
OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_init.o
RV-OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_rvf.o
RVV-OBJS-$(CONFIG_AUDIODSP) += riscv/audiodsp_rvv.o
OBJS-$(CONFIG_BSWAPDSP) += riscv/bswapdsp_init.o \
riscv/bswapdsp_rvb.o
OBJS-$(CONFIG_BSWAPDSP) += riscv/bswapdsp_init.o
RV-OBJS-$(CONFIG_BSWAPDSP) += riscv/bswapdsp_rvb.o
RVV-OBJS-$(CONFIG_BSWAPDSP) += riscv/bswapdsp_rvv.o
OBJS-$(CONFIG_EXR_DECODER) += riscv/exrdsp_init.o
RVV-OBJS-$(CONFIG_EXR_DECODER) += riscv/exrdsp_rvv.o
@ -35,8 +35,8 @@ OBJS-$(CONFIG_LLVIDENCDSP) += riscv/llvidencdsp_init.o
RVV-OBJS-$(CONFIG_LLVIDENCDSP) += riscv/llvidencdsp_rvv.o
OBJS-$(CONFIG_OPUS_DECODER) += riscv/opusdsp_init.o
RVV-OBJS-$(CONFIG_OPUS_DECODER) += riscv/opusdsp_rvv.o
OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o \
riscv/pixblockdsp_rvi.o
OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_init.o
RV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvi.o
RVV-OBJS-$(CONFIG_PIXBLOCKDSP) += riscv/pixblockdsp_rvv.o
OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_init.o
RVV-OBJS-$(CONFIG_UTVIDEO_DECODER) += riscv/utvideodsp_rvv.o

2
libavcodec/riscv/ac3dsp_init.c
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@ -31,6 +31,7 @@ void ff_float_to_fixed24_rvv(int32_t *dst, const float *src, size_t len);
av_cold void ff_ac3dsp_init_riscv(AC3DSPContext *c)
{
#if HAVE_RV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVB_ADDR) {
@ -39,4 +40,5 @@ av_cold void ff_ac3dsp_init_riscv(AC3DSPContext *c)
if (flags & AV_CPU_FLAG_RVV_F32)
c->float_to_fixed24 = ff_float_to_fixed24_rvv;
}
#endif
}

2
libavcodec/riscv/audiodsp_init.c
View File

@ -33,6 +33,7 @@ void ff_vector_clipf_rvv(float *dst, const float *src, int len, float min, float
av_cold void ff_audiodsp_init_riscv(AudioDSPContext *c)
{
#if HAVE_RV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVF)
@ -47,4 +48,5 @@ av_cold void ff_audiodsp_init_riscv(AudioDSPContext *c)
c->vector_clipf = ff_vector_clipf_rvv;
}
#endif
#endif
}

2
libavcodec/riscv/bswapdsp_init.c
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@ -30,6 +30,7 @@ void ff_bswap16_buf_rvv(uint16_t *dst, const uint16_t *src, int len);
av_cold void ff_bswapdsp_init_riscv(BswapDSPContext *c)
{
#if HAVE_RV
int flags = av_get_cpu_flags();
if (flags & AV_CPU_FLAG_RVB_ADDR) {
@ -42,4 +43,5 @@ av_cold void ff_bswapdsp_init_riscv(BswapDSPContext *c)
c->bswap16_buf = ff_bswap16_buf_rvv;
#endif
}
#endif
}

2
libavcodec/riscv/pixblockdsp_init.c
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@ -45,6 +45,7 @@ av_cold void ff_pixblockdsp_init_riscv(PixblockDSPContext *c,
AVCodecContext *avctx,
unsigned high_bit_depth)
{
#if HAVE_RV
int cpu_flags = av_get_cpu_flags();
if (cpu_flags & AV_CPU_FLAG_RVI) {
@ -69,4 +70,5 @@ av_cold void ff_pixblockdsp_init_riscv(PixblockDSPContext *c,
c->diff_pixels = ff_diff_pixels_rvv;
}
#endif
#endif
}

2
libswscale/riscv/Makefile
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@ -1,3 +1,3 @@
OBJS += riscv/rgb2rgb.o
OBJS += riscv/rgb2rgb_rvb.o
RV-OBJS += riscv/rgb2rgb_rvb.o
RVV-OBJS += riscv/rgb2rgb_rvv.o

2
libswscale/riscv/rgb2rgb.c
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@ -42,6 +42,7 @@ void ff_yuyvtoyuv422_rvv(uint8_t *ydst, uint8_t *udst, uint8_t *vdst,
av_cold void rgb2rgb_init_riscv(void)
{
#if HAVE_RV
int flags = av_get_cpu_flags();
#if (__riscv_xlen == 64)
@ -61,4 +62,5 @@ av_cold void rgb2rgb_init_riscv(void)
}
}
#endif
#endif
}

2
tests/checkasm/Makefile
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@ -68,7 +68,7 @@ CHECKASMOBJS-$(CONFIG_AVUTIL) += $(AVUTILOBJS)
CHECKASMOBJS-$(ARCH_AARCH64) += aarch64/checkasm.o
CHECKASMOBJS-$(HAVE_ARMV5TE_EXTERNAL) += arm/checkasm.o
CHECKASMOBJS-$(ARCH_RISCV) += riscv/checkasm.o
CHECKASMOBJS-$(HAVE_RV) += riscv/checkasm.o
CHECKASMOBJS-$(HAVE_X86ASM) += x86/checkasm.o
CHECKASMOBJS += $(CHECKASMOBJS-yes) checkasm.o

2
tests/checkasm/checkasm.c
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@ -738,7 +738,7 @@ int main(int argc, char *argv[])
if (have_vfp(av_get_cpu_flags()) || have_neon(av_get_cpu_flags()))
checkasm_checked_call = checkasm_checked_call_vfp;
#endif
#if ARCH_RISCV
#if ARCH_RISCV && HAVE_RV
struct sigaction act = {
.sa_handler = checkasm_handle_signal,
.sa_flags = 0,

5
tests/checkasm/checkasm.h
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@ -217,7 +217,7 @@ void checkasm_set_function(void *, sigjmp_buf);
void *checkasm_get_wrapper(void);
void checkasm_handle_signal(int signum);
#if (__riscv_xlen == 64) && defined (__riscv_d)
#if HAVE_RV && (__riscv_xlen == 64) && defined (__riscv_d)
#define declare_new(ret, ...) \
int checked_call_signum = 0; \
sigjmp_buf checked_call_jb; \
@ -227,6 +227,9 @@ void checkasm_handle_signal(int signum);
(checked_call_signum = sigsetjmp(checked_call_jb, 1)) == 0 \
? checked_call(__VA_ARGS__) \
: (checkasm_fail_signal(checked_call_signum), 0))
#else
#define declare_new(ret, ...)
#define call_new(...) ((func_type *)func_new)(__VA_ARGS__)
#endif
#else
#define declare_new(ret, ...)