mirror of
https://github.com/egzumer/uv-k5-firmware-custom
synced 2024-11-22 18:44:58 +00:00
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
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/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "bsp/dp32g030/pmu.h"
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#include "bsp/dp32g030/syscon.h"
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#include "driver/system.h"
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#include "driver/systick.h"
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void SYSTEM_DelayMs(uint32_t Delay)
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{
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SYSTICK_DelayUs(Delay * 1000);
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}
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void SYSTEM_ConfigureClocks(void)
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{
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// Set source clock from external crystal
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PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK))
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| PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ
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| PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;
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// Divide by 2
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SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2;
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// Disable division clock gate
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SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE;
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}
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