mirror of
https://github.com/phdlee/uvk5cec
synced 2024-11-21 23:51:47 +00:00
254 lines
16 KiB
C
254 lines
16 KiB
C
/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef HARDWARE_DP32G030_SARADC_H
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#define HARDWARE_DP32G030_SARADC_H
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#if !defined(__ASSEMBLY__)
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#include <stdint.h>
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#endif
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/* -------- SARADC -------- */
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#define SARADC_BASE_ADDR 0x400BA000U
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#define SARADC_BASE_SIZE 0x00000800U
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#define SARADC_CFG_ADDR (SARADC_BASE_ADDR + 0x0000U)
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#define SARADC_CFG (*(volatile uint32_t *)SARADC_CFG_ADDR)
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#define SARADC_CFG_CH_SEL_SHIFT 0
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#define SARADC_CFG_CH_SEL_WIDTH 15
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#define SARADC_CFG_CH_SEL_MASK (((1U << SARADC_CFG_CH_SEL_WIDTH) - 1U) << SARADC_CFG_CH_SEL_SHIFT)
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#define SARADC_CFG_AVG_SHIFT 16
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#define SARADC_CFG_AVG_WIDTH 2
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#define SARADC_CFG_AVG_MASK (((1U << SARADC_CFG_AVG_WIDTH) - 1U) << SARADC_CFG_AVG_SHIFT)
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#define SARADC_CFG_AVG_VALUE_1_SAMPLE 0U
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#define SARADC_CFG_AVG_BITS_1_SAMPLE (SARADC_CFG_AVG_VALUE_1_SAMPLE << SARADC_CFG_AVG_SHIFT)
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#define SARADC_CFG_AVG_VALUE_2_SAMPLE 1U
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#define SARADC_CFG_AVG_BITS_2_SAMPLE (SARADC_CFG_AVG_VALUE_2_SAMPLE << SARADC_CFG_AVG_SHIFT)
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#define SARADC_CFG_AVG_VALUE_4_SAMPLE 2U
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#define SARADC_CFG_AVG_BITS_4_SAMPLE (SARADC_CFG_AVG_VALUE_4_SAMPLE << SARADC_CFG_AVG_SHIFT)
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#define SARADC_CFG_AVG_VALUE_8_SAMPLE 3U
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#define SARADC_CFG_AVG_BITS_8_SAMPLE (SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT)
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#define SARADC_CFG_CONT_SHIFT 18
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#define SARADC_CFG_CONT_WIDTH 1
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#define SARADC_CFG_CONT_MASK (((1U << SARADC_CFG_CONT_WIDTH) - 1U) << SARADC_CFG_CONT_SHIFT)
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#define SARADC_CFG_CONT_VALUE_SINGLE 0U
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#define SARADC_CFG_CONT_BITS_SINGLE (SARADC_CFG_CONT_VALUE_SINGLE << SARADC_CFG_CONT_SHIFT)
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#define SARADC_CFG_CONT_VALUE_CONTINUOUS 1U
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#define SARADC_CFG_CONT_BITS_CONTINUOUS (SARADC_CFG_CONT_VALUE_CONTINUOUS << SARADC_CFG_CONT_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_SHIFT 19
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#define SARADC_CFG_SMPL_SETUP_WIDTH 3
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#define SARADC_CFG_SMPL_SETUP_MASK (((1U << SARADC_CFG_SMPL_SETUP_WIDTH) - 1U) << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE 0U
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#define SARADC_CFG_SMPL_SETUP_BITS_1_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE 1U
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#define SARADC_CFG_SMPL_SETUP_BITS_2_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE 2U
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#define SARADC_CFG_SMPL_SETUP_BITS_4_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE 3U
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#define SARADC_CFG_SMPL_SETUP_BITS_8_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE 4U
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#define SARADC_CFG_SMPL_SETUP_BITS_16_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE 5U
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#define SARADC_CFG_SMPL_SETUP_BITS_32_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE 6U
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#define SARADC_CFG_SMPL_SETUP_BITS_64_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE 7U
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#define SARADC_CFG_SMPL_SETUP_BITS_128_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)
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#define SARADC_CFG_MEM_MODE_SHIFT 22
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#define SARADC_CFG_MEM_MODE_WIDTH 1
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#define SARADC_CFG_MEM_MODE_MASK (((1U << SARADC_CFG_MEM_MODE_WIDTH) - 1U) << SARADC_CFG_MEM_MODE_SHIFT)
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#define SARADC_CFG_MEM_MODE_VALUE_FIFO 0U
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#define SARADC_CFG_MEM_MODE_BITS_FIFO (SARADC_CFG_MEM_MODE_VALUE_FIFO << SARADC_CFG_MEM_MODE_SHIFT)
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#define SARADC_CFG_MEM_MODE_VALUE_CHANNEL 1U
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#define SARADC_CFG_MEM_MODE_BITS_CHANNEL (SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT)
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#define SARADC_CFG_SMPL_CLK_SHIFT 23
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#define SARADC_CFG_SMPL_CLK_WIDTH 1
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#define SARADC_CFG_SMPL_CLK_MASK (((1U << SARADC_CFG_SMPL_CLK_WIDTH) - 1U) << SARADC_CFG_SMPL_CLK_SHIFT)
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#define SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL 0U
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#define SARADC_CFG_SMPL_CLK_BITS_EXTERNAL (SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL << SARADC_CFG_SMPL_CLK_SHIFT)
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#define SARADC_CFG_SMPL_CLK_VALUE_INTERNAL 1U
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#define SARADC_CFG_SMPL_CLK_BITS_INTERNAL (SARADC_CFG_SMPL_CLK_VALUE_INTERNAL << SARADC_CFG_SMPL_CLK_SHIFT)
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#define SARADC_CFG_SMPL_WIN_SHIFT 24
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#define SARADC_CFG_SMPL_WIN_WIDTH 3
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#define SARADC_CFG_SMPL_WIN_MASK (((1U << SARADC_CFG_SMPL_WIN_WIDTH) - 1U) << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE 0U
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#define SARADC_CFG_SMPL_WIN_BITS_1_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE 1U
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#define SARADC_CFG_SMPL_WIN_BITS_3_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE 2U
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#define SARADC_CFG_SMPL_WIN_BITS_5_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE 3U
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#define SARADC_CFG_SMPL_WIN_BITS_7_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE 4U
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#define SARADC_CFG_SMPL_WIN_BITS_9_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE 5U
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#define SARADC_CFG_SMPL_WIN_BITS_11_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE 6U
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#define SARADC_CFG_SMPL_WIN_BITS_13_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE 7U
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#define SARADC_CFG_SMPL_WIN_BITS_15_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)
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#define SARADC_CFG_ADC_EN_SHIFT 27
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#define SARADC_CFG_ADC_EN_WIDTH 1
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#define SARADC_CFG_ADC_EN_MASK (((1U << SARADC_CFG_ADC_EN_WIDTH) - 1U) << SARADC_CFG_ADC_EN_SHIFT)
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#define SARADC_CFG_ADC_EN_VALUE_DISABLE 0U
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#define SARADC_CFG_ADC_EN_BITS_DISABLE (SARADC_CFG_ADC_EN_VALUE_DISABLE << SARADC_CFG_ADC_EN_SHIFT)
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#define SARADC_CFG_ADC_EN_VALUE_ENABLE 1U
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#define SARADC_CFG_ADC_EN_BITS_ENABLE (SARADC_CFG_ADC_EN_VALUE_ENABLE << SARADC_CFG_ADC_EN_SHIFT)
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#define SARADC_CFG_ADC_TRIG_SHIFT 28
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#define SARADC_CFG_ADC_TRIG_WIDTH 1
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#define SARADC_CFG_ADC_TRIG_MASK (((1U << SARADC_CFG_ADC_TRIG_WIDTH) - 1U) << SARADC_CFG_ADC_TRIG_SHIFT)
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#define SARADC_CFG_ADC_TRIG_VALUE_CPU 0U
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#define SARADC_CFG_ADC_TRIG_BITS_CPU (SARADC_CFG_ADC_TRIG_VALUE_CPU << SARADC_CFG_ADC_TRIG_SHIFT)
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#define SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL 1U
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#define SARADC_CFG_ADC_TRIG_BITS_EXTERNAL (SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL << SARADC_CFG_ADC_TRIG_SHIFT)
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#define SARADC_CFG_DMA_EN_SHIFT 29
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#define SARADC_CFG_DMA_EN_WIDTH 1
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#define SARADC_CFG_DMA_EN_MASK (((1U << SARADC_CFG_DMA_EN_WIDTH) - 1U) << SARADC_CFG_DMA_EN_SHIFT)
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#define SARADC_CFG_DMA_EN_VALUE_DISABLE 0U
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#define SARADC_CFG_DMA_EN_BITS_DISABLE (SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT)
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#define SARADC_CFG_DMA_EN_VALUE_ENABLE 1U
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#define SARADC_CFG_DMA_EN_BITS_ENABLE (SARADC_CFG_DMA_EN_VALUE_ENABLE << SARADC_CFG_DMA_EN_SHIFT)
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#define SARADC_START_ADDR (SARADC_BASE_ADDR + 0x0004U)
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#define SARADC_START (*(volatile uint32_t *)SARADC_START_ADDR)
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#define SARADC_START_START_SHIFT 0
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#define SARADC_START_START_WIDTH 1
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#define SARADC_START_START_MASK (((1U << SARADC_START_START_WIDTH) - 1U) << SARADC_START_START_SHIFT)
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#define SARADC_START_START_VALUE_DISABLE 0U
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#define SARADC_START_START_BITS_DISABLE (SARADC_START_START_VALUE_DISABLE << SARADC_START_START_SHIFT)
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#define SARADC_START_START_VALUE_ENABLE 1U
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#define SARADC_START_START_BITS_ENABLE (SARADC_START_START_VALUE_ENABLE << SARADC_START_START_SHIFT)
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#define SARADC_START_SOFT_RESET_SHIFT 2
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#define SARADC_START_SOFT_RESET_WIDTH 1
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#define SARADC_START_SOFT_RESET_MASK (((1U << SARADC_START_SOFT_RESET_WIDTH) - 1U) << SARADC_START_SOFT_RESET_SHIFT)
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#define SARADC_START_SOFT_RESET_VALUE_ASSERT 0U
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#define SARADC_START_SOFT_RESET_BITS_ASSERT (SARADC_START_SOFT_RESET_VALUE_ASSERT << SARADC_START_SOFT_RESET_SHIFT)
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#define SARADC_START_SOFT_RESET_VALUE_DEASSERT 1U
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#define SARADC_START_SOFT_RESET_BITS_DEASSERT (SARADC_START_SOFT_RESET_VALUE_DEASSERT << SARADC_START_SOFT_RESET_SHIFT)
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#define SARADC_IE_ADDR (SARADC_BASE_ADDR + 0x0008U)
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#define SARADC_IE (*(volatile uint32_t *)SARADC_IE_ADDR)
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#define SARADC_IE_CHx_EOC_SHIFT 0
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#define SARADC_IE_CHx_EOC_WIDTH 16
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#define SARADC_IE_CHx_EOC_MASK (((1U << SARADC_IE_CHx_EOC_WIDTH) - 1U) << SARADC_IE_CHx_EOC_SHIFT)
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#define SARADC_IE_CHx_EOC_VALUE_NONE 0U
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#define SARADC_IE_CHx_EOC_BITS_NONE (SARADC_IE_CHx_EOC_VALUE_NONE << SARADC_IE_CHx_EOC_SHIFT)
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#define SARADC_IE_CHx_EOC_VALUE_ALL 65535U
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#define SARADC_IE_CHx_EOC_BITS_ALL (SARADC_IE_CHx_EOC_VALUE_ALL << SARADC_IE_CHx_EOC_SHIFT)
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#define SARADC_IE_FIFO_FULL_SHIFT 16
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#define SARADC_IE_FIFO_FULL_WIDTH 1
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#define SARADC_IE_FIFO_FULL_MASK (((1U << SARADC_IE_FIFO_FULL_WIDTH) - 1U) << SARADC_IE_FIFO_FULL_SHIFT)
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#define SARADC_IE_FIFO_FULL_VALUE_DISABLE 0U
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#define SARADC_IE_FIFO_FULL_BITS_DISABLE (SARADC_IE_FIFO_FULL_VALUE_DISABLE << SARADC_IE_FIFO_FULL_SHIFT)
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#define SARADC_IE_FIFO_FULL_VALUE_ENABLE 1U
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#define SARADC_IE_FIFO_FULL_BITS_ENABLE (SARADC_IE_FIFO_FULL_VALUE_ENABLE << SARADC_IE_FIFO_FULL_SHIFT)
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#define SARADC_IE_FIFO_HFULL_SHIFT 17
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#define SARADC_IE_FIFO_HFULL_WIDTH 1
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#define SARADC_IE_FIFO_HFULL_MASK (((1U << SARADC_IE_FIFO_HFULL_WIDTH) - 1U) << SARADC_IE_FIFO_HFULL_SHIFT)
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#define SARADC_IE_FIFO_HFULL_VALUE_DISABLE 0U
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#define SARADC_IE_FIFO_HFULL_BITS_DISABLE (SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT)
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#define SARADC_IE_FIFO_HFULL_VALUE_ENABLE 1U
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#define SARADC_IE_FIFO_HFULL_BITS_ENABLE (SARADC_IE_FIFO_HFULL_VALUE_ENABLE << SARADC_IE_FIFO_HFULL_SHIFT)
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#define SARADC_IF_ADDR (SARADC_BASE_ADDR + 0x000CU)
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#define SARADC_IF (*(volatile uint32_t *)SARADC_IF_ADDR)
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#define SARADC_IF_CHx_EOC_SHIFT 0
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#define SARADC_IF_CHx_EOC_WIDTH 16
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#define SARADC_IF_CHx_EOC_MASK (((1U << SARADC_IF_CHx_EOC_WIDTH) - 1U) << SARADC_IF_CHx_EOC_SHIFT)
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#define SARADC_IF_FIFO_FULL_SHIFT 16
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#define SARADC_IF_FIFO_FULL_WIDTH 1
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#define SARADC_IF_FIFO_FULL_MASK (((1U << SARADC_IF_FIFO_FULL_WIDTH) - 1U) << SARADC_IF_FIFO_FULL_SHIFT)
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#define SARADC_IF_FIFO_FULL_VALUE_NOT_SET 0U
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#define SARADC_IF_FIFO_FULL_BITS_NOT_SET (SARADC_IF_FIFO_FULL_VALUE_NOT_SET << SARADC_IF_FIFO_FULL_SHIFT)
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#define SARADC_IF_FIFO_FULL_VALUE_SET 1U
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#define SARADC_IF_FIFO_FULL_BITS_SET (SARADC_IF_FIFO_FULL_VALUE_SET << SARADC_IF_FIFO_FULL_SHIFT)
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#define SARADC_IF_FIFO_HFULL_SHIFT 17
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#define SARADC_IF_FIFO_HFULL_WIDTH 1
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#define SARADC_IF_FIFO_HFULL_MASK (((1U << SARADC_IF_FIFO_HFULL_WIDTH) - 1U) << SARADC_IF_FIFO_HFULL_SHIFT)
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#define SARADC_IF_FIFO_HFULL_VALUE_NOT_SET 0U
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#define SARADC_IF_FIFO_HFULL_BITS_NOT_SET (SARADC_IF_FIFO_HFULL_VALUE_NOT_SET << SARADC_IF_FIFO_HFULL_SHIFT)
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#define SARADC_IF_FIFO_HFULL_VALUE_SET 1U
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#define SARADC_IF_FIFO_HFULL_BITS_SET (SARADC_IF_FIFO_HFULL_VALUE_SET << SARADC_IF_FIFO_HFULL_SHIFT)
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#define SARADC_CH0_ADDR (SARADC_BASE_ADDR + 0x0010U)
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#define SARADC_CH0 (*(volatile uint32_t *)SARADC_CH0_ADDR)
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#define SARADC_EXTTRIG_SEL_ADDR (SARADC_BASE_ADDR + 0x00B0U)
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#define SARADC_EXTTRIG_SEL (*(volatile uint32_t *)SARADC_EXTTRIG_SEL_ADDR)
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#define SARADC_CALIB_OFFSET_ADDR (SARADC_BASE_ADDR + 0x00F0U)
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#define SARADC_CALIB_OFFSET (*(volatile uint32_t *)SARADC_CALIB_OFFSET_ADDR)
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#define SARADC_CALIB_OFFSET_OFFSET_SHIFT 0
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#define SARADC_CALIB_OFFSET_OFFSET_WIDTH 8
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#define SARADC_CALIB_OFFSET_OFFSET_MASK (((1U << SARADC_CALIB_OFFSET_OFFSET_WIDTH) - 1U) << SARADC_CALIB_OFFSET_OFFSET_SHIFT)
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#define SARADC_CALIB_OFFSET_VALID_SHIFT 16
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#define SARADC_CALIB_OFFSET_VALID_WIDTH 1
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#define SARADC_CALIB_OFFSET_VALID_MASK (((1U << SARADC_CALIB_OFFSET_VALID_WIDTH) - 1U) << SARADC_CALIB_OFFSET_VALID_SHIFT)
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#define SARADC_CALIB_OFFSET_VALID_VALUE_NO 0U
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#define SARADC_CALIB_OFFSET_VALID_BITS_NO (SARADC_CALIB_OFFSET_VALID_VALUE_NO << SARADC_CALIB_OFFSET_VALID_SHIFT)
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#define SARADC_CALIB_OFFSET_VALID_VALUE_YES 1U
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#define SARADC_CALIB_OFFSET_VALID_BITS_YES (SARADC_CALIB_OFFSET_VALID_VALUE_YES << SARADC_CALIB_OFFSET_VALID_SHIFT)
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#define SARADC_CALIB_KD_ADDR (SARADC_BASE_ADDR + 0x00F4U)
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#define SARADC_CALIB_KD (*(volatile uint32_t *)SARADC_CALIB_KD_ADDR)
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#define SARADC_CALIB_KD_KD_SHIFT 0
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#define SARADC_CALIB_KD_KD_WIDTH 8
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#define SARADC_CALIB_KD_KD_MASK (((1U << SARADC_CALIB_KD_KD_WIDTH) - 1U) << SARADC_CALIB_KD_KD_SHIFT)
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#define SARADC_CALIB_KD_VALID_SHIFT 16
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#define SARADC_CALIB_KD_VALID_WIDTH 1
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#define SARADC_CALIB_KD_VALID_MASK (((1U << SARADC_CALIB_KD_VALID_WIDTH) - 1U) << SARADC_CALIB_KD_VALID_SHIFT)
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#define SARADC_CALIB_KD_VALID_VALUE_NO 0U
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#define SARADC_CALIB_KD_VALID_BITS_NO (SARADC_CALIB_KD_VALID_VALUE_NO << SARADC_CALIB_KD_VALID_SHIFT)
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#define SARADC_CALIB_KD_VALID_VALUE_YES 1U
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#define SARADC_CALIB_KD_VALID_BITS_YES (SARADC_CALIB_KD_VALID_VALUE_YES << SARADC_CALIB_KD_VALID_SHIFT)
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/* -------- ADC_CHx -------- */
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typedef struct {
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uint32_t STAT;
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uint32_t DATA;
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} ADC_Channel_t;
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#define ADC_CHx_STAT_EOC_SHIFT 0
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#define ADC_CHx_STAT_EOC_WIDTH 1
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#define ADC_CHx_STAT_EOC_MASK (((1U << ADC_CHx_STAT_EOC_WIDTH) - 1U) << ADC_CHx_STAT_EOC_SHIFT)
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#define ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE 0U
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#define ADC_CHx_STAT_EOC_BITS_NOT_COMPLETE (ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE << ADC_CHx_STAT_EOC_SHIFT)
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#define ADC_CHx_STAT_EOC_VALUE_COMPLETE 1U
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#define ADC_CHx_STAT_EOC_BITS_COMPLETE (ADC_CHx_STAT_EOC_VALUE_COMPLETE << ADC_CHx_STAT_EOC_SHIFT)
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#define ADC_CHx_DATA_DATA_SHIFT 0
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#define ADC_CHx_DATA_DATA_WIDTH 12
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#define ADC_CHx_DATA_DATA_MASK (((1U << ADC_CHx_DATA_DATA_WIDTH) - 1U) << ADC_CHx_DATA_DATA_SHIFT)
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#define ADC_CHx_DATA_NUM_SHIFT 12
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#define ADC_CHx_DATA_NUM_WIDTH 4
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#define ADC_CHx_DATA_NUM_MASK (((1U << ADC_CHx_DATA_NUM_WIDTH) - 1U) << ADC_CHx_DATA_NUM_SHIFT)
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#endif
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