diff --git a/.idea/workspace.xml b/.idea/workspace.xml index 573f093..e8398f5 100644 --- a/.idea/workspace.xml +++ b/.idea/workspace.xml @@ -20,8 +20,1083 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - { - "keyToString": { - "ASKED_ADD_EXTERNAL_FILES": "true", - "RunOnceActivity.OpenProjectViewOnStart": "true", - "RunOnceActivity.ShowReadmeOnStart": "true", - "RunOnceActivity.cidr.known.project.marker": "true", - "SHARE_PROJECT_CONFIGURATION_FILES": "true", - "WebServerToolWindowFactoryState": "false", - "cf.first.check.clang-format": "false", - "cidr.known.project.marker": "true", - "last_opened_file_path": "C:/Qt/Qt5.14.2/Tools/mingw730_64/bin/mingw32-make.exe", - "node.js.detected.package.eslint": "true", - "node.js.detected.package.tslint": "true", - "node.js.selected.package.eslint": "(autodetect)", - "node.js.selected.package.tslint": "(autodetect)", - "nodejs_package_manager_path": "npm", - "settings.editor.selected.configurable": "File.Encoding", - "structure.view.defaults.are.configured": "true", - "vue.rearranger.settings.migration": "true" + +}]]> + - - + @@ -188,11 +1263,11 @@ + + - - @@ -260,14 +1335,7 @@ - - - - 1701738213205 - 1701738485690 @@ -605,7 +1673,14 @@ - @@ -632,7 +1707,6 @@ - @@ -657,7 +1731,8 @@ - diff --git a/Makefile b/Makefile index 4dae2fc..d437f39 100644 --- a/Makefile +++ b/Makefile @@ -56,7 +56,7 @@ ENABLE_AM_FIX_SHOW_DATA ?= 0 ENABLE_AGC_SHOW_DATA ?= 0 ############################################################# -OPENOCD = C:/openocd-win/bin/openocd.exe +OPENOCD = openocd-win/bin/openocd.exe TARGET = firmware ifeq ($(ENABLE_CLANG),1) @@ -429,7 +429,7 @@ ifdef MY_PYTHON endif -build: $(TARGET) +build:clean $(TARGET) $(OBJCOPY) -O binary $(TARGET) $(TARGET).bin ifndef MY_PYTHON $(info ) @@ -469,17 +469,6 @@ bsp/dp32g030/%.h: hardware/dp32g030/%.def -include $(DEPS) -ifdef OS - ifeq ($(OS),Windows_NT) - clean: - .\clean.bat - else - clean: - $(RM) $(call FixPath, $(TARGET).bin $(TARGET).packed.bin $(TARGET) $(OBJS) $(DEPS)) - doxygen: - doxygen - endif -else - clean: - @echo "Unsupported OS. Please use this Makefile on Windows or Linux." -endif +clean: + $(RM) $(call FixPath, $(TARGET).bin $(TARGET).packed.bin $(TARGET) $(OBJS) $(DEPS)) + diff --git a/dp32g030.cfg b/dp32g030.cfg index c41a4f4..c38fc6d 100644 --- a/dp32g030.cfg +++ b/dp32g030.cfg @@ -21,7 +21,7 @@ swd newdap $_CHIP_NAME cpu -enable -expected-id $CPUTAPID dap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu -# Set up the GDB target for the CPU, cortex_m is the CPU type, +# Set up the GDB target for the CPU, cortex_m is the CPU type, target create $_CHIP_NAME.cpu cortex_m -dap $_CHIP_NAME.dap @@ -88,7 +88,7 @@ proc uv_wait_busy {} { } proc write_image {filename address} { - global _SECTOR_SIZE + global _SECTOR_SIZE set fs [file size $filename] set fd [open $filename "rb"] @@ -110,7 +110,7 @@ proc write_image {filename address} { } uv_clear_sectors [expr {(($fs+$_SECTOR_SIZE-1)&(0x10000000-$_SECTOR_SIZE))/($_SECTOR_SIZE/2)}] uv_flash_unlock - + set addr $address while {![eof $fd]} { set data [read $fd 4] @@ -127,7 +127,7 @@ proc write_image {filename address} { } } uv_flash_lock - + close $fd } diff --git a/firmware b/firmware deleted file mode 100644 index 4e08499..0000000 Binary files a/firmware and /dev/null differ diff --git a/openocd-win/README.md b/openocd-win/README.md new file mode 100644 index 0000000..4e7bbf2 --- /dev/null +++ b/openocd-win/README.md @@ -0,0 +1,14 @@ +# The xPack OpenOCD + +The **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD) +is the **xPack** version of **OpenOCD**, +an open-source project. + +For more details, please read the corresponding release pages: + +- +- + +Thank you for using open source software, + +Liviu Ionescu diff --git a/openocd-win/bin/libftdi1.dll b/openocd-win/bin/libftdi1.dll new file mode 100644 index 0000000..ae775e8 Binary files /dev/null and b/openocd-win/bin/libftdi1.dll differ diff --git a/openocd-win/bin/libusb-1.0.dll b/openocd-win/bin/libusb-1.0.dll new file mode 100644 index 0000000..f57958f Binary files /dev/null and b/openocd-win/bin/libusb-1.0.dll differ diff --git a/openocd-win/bin/openocd b/openocd-win/bin/openocd new file mode 100644 index 0000000..f57eb3f Binary files /dev/null and b/openocd-win/bin/openocd differ diff --git a/openocd-win/bin/openocd.exe b/openocd-win/bin/openocd.exe new file mode 100644 index 0000000..17e70e7 Binary files /dev/null and b/openocd-win/bin/openocd.exe differ diff --git a/openocd-win/openocd/OpenULINK/ulink_firmware.hex b/openocd-win/openocd/OpenULINK/ulink_firmware.hex new file mode 100644 index 0000000..efaea58 --- /dev/null +++ b/openocd-win/openocd/OpenULINK/ulink_firmware.hex @@ -0,0 +1,347 @@ +:040000000200713257 +:01000B0032C2 +:0100130032BA +:01001B0032B2 +:0100230032AA +:01002B0032A2 +:01003300329A +:01003B003292 +:01004300328A +:01004B003282 +:01005300327A +:01005B003272 +:01006300326A +:03006B000201107F +:0300CA0002006EC3 +:03006E000201018B +:1000CD00907F937404F0907F9C7495F0907F96745C +:1000DD0090F0907F94E4F0907F9D747FF0907F97E7 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+:0F13970004D005D006D0070CBC00E20D80DF2289 +:03004300021B009D +:101B0000020110000201630002016400020165008D +:101B1000020166000201670002016800020169001B +:101B200002016A0002016B0002016C0002019300D5 +:101B30000201BA000201BB000201BC000201BD00AB +:101B40000201BE000201BF000201C0000201C1008B +:081B50000201C2000201C30002 +:1013A6007A10E4FBFCE58225E0F582E58333F583DC +:1013B600EB33FBEC33FCEB950AF5F0EC950B4006B2 +:0913C600FCABF0438201DADD22E8 +:0600A000E478FFF6D8FD34 +:10007E007900E94400601B7A009014617800759253 +:10008E0020E493F2A308B800020592D9F4DAF275CF +:02009E0092FFCF +:1000A6007800E84400600A7900759220E4F309D8E4 +:1000B600FC7800E84400600C7900902000E4F0A38E +:0400C600D8FCD9FA8F +:0D00710075814A1213CFE582600302006E14 +:0413CF007582002201 +:00000001FF diff --git a/openocd-win/openocd/README.md b/openocd-win/openocd/README.md new file mode 100644 index 0000000..4e7bbf2 --- /dev/null +++ b/openocd-win/openocd/README.md @@ -0,0 +1,14 @@ +# The xPack OpenOCD + +The **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD) +is the **xPack** version of **OpenOCD**, +an open-source project. + +For more details, please read the corresponding release pages: + +- +- + +Thank you for using open source software, + +Liviu Ionescu diff --git a/openocd-win/openocd/angie/angie_bitstream.bit b/openocd-win/openocd/angie/angie_bitstream.bit new file mode 100644 index 0000000..aebd370 Binary files /dev/null and b/openocd-win/openocd/angie/angie_bitstream.bit differ diff --git a/openocd-win/openocd/angie/angie_firmware.bin b/openocd-win/openocd/angie/angie_firmware.bin new file mode 100644 index 0000000..da69631 Binary files /dev/null and b/openocd-win/openocd/angie/angie_firmware.bin differ diff --git a/openocd-win/openocd/bin/libftdi1.dll b/openocd-win/openocd/bin/libftdi1.dll new file mode 100644 index 0000000..ae775e8 Binary files /dev/null and b/openocd-win/openocd/bin/libftdi1.dll differ diff --git a/openocd-win/openocd/bin/libusb-1.0.dll b/openocd-win/openocd/bin/libusb-1.0.dll new file mode 100644 index 0000000..f57958f Binary files /dev/null and b/openocd-win/openocd/bin/libusb-1.0.dll differ diff --git a/openocd-win/openocd/bin/openocd b/openocd-win/openocd/bin/openocd new file mode 100644 index 0000000..f57eb3f Binary files /dev/null and b/openocd-win/openocd/bin/openocd differ diff --git a/openocd-win/openocd/bin/openocd.exe b/openocd-win/openocd/bin/openocd.exe new file mode 100644 index 0000000..17e70e7 Binary files /dev/null and b/openocd-win/openocd/bin/openocd.exe differ diff --git a/openocd-win/openocd/contrib/60-openocd.rules b/openocd-win/openocd/contrib/60-openocd.rules new file mode 100644 index 0000000..42b43f0 --- /dev/null +++ b/openocd-win/openocd/contrib/60-openocd.rules @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copy this file to /etc/udev/rules.d/ +# If rules fail to reload automatically, you can refresh udev rules +# with the command "udevadm control --reload" + +ACTION!="add|change", GOTO="openocd_rules_end" + +SUBSYSTEM=="gpio", MODE="0660", GROUP="plugdev", TAG+="uaccess" + +SUBSYSTEM!="usb|tty|hidraw", GOTO="openocd_rules_end" + +# Please keep this list sorted by VID:PID + +# opendous and estick +ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="204f", MODE="666" + +# Original FT232/FT245 VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="666" + +# Original FT2232 VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="666" + +# Original FT4232 VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="666" + +# Original FT232H VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="666" +# Original FT231XQ VID:PID +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", MODE="666" + +# DISTORTEC JTAG-lock-pick Tiny 2 +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="666" + +# TUMPA, TUMPA Lite +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a98", MODE="666" +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a99", MODE="666" + +# Marvell OpenRD JTAGKey FT2232D B +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="9e90", MODE="666" + +# XDS100v2 +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d0", MODE="666" +# XDS100v3 +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d1", MODE="666" + +# OOCDLink +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="baf8", MODE="666" + +# Kristech KT-Link +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bbe2", MODE="666" + +# Xverve Signalyzer Tool (DT-USB-ST), Signalyzer LITE (DT-USB-SLITE) +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca0", MODE="666" +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca1", MODE="666" + +# TI/Luminary Stellaris Evaluation Board FTDI (several) +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcd9", MODE="666" + +# TI/Luminary Stellaris In-Circuit Debug Interface FTDI (ICDI) Board +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcda", MODE="666" + +# egnite Turtelizer 2 +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bdc8", MODE="666" + +# Section5 ICEbear +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c140", MODE="666" +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="666" + +# Amontec JTAGkey and JTAGkey-tiny +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="666" + +# ASIX Presto programmer +ATTRS{idVendor}=="0403", ATTRS{idProduct}=="f1a0", MODE="666" + +# Nuvoton NuLink +ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511b", MODE="666" +ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511c", MODE="666" +ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511d", MODE="666" +ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5200", MODE="666" +ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5201", MODE="666" + +# TI ICDI +ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="666" + +# STMicroelectronics ST-LINK V1 +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", MODE="666" + +# STMicroelectronics ST-LINK/V2 +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", MODE="666" + +# STMicroelectronics ST-LINK/V2.1 +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", MODE="666" + +# STMicroelectronics STLINK-V3 +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3755", MODE="666" +ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3757", MODE="666" + +# Cypress SuperSpeed Explorer Kit +ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="0007", MODE="666" + +# Cypress KitProg in KitProg mode +ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="f139", MODE="666" + +# Cypress KitProg in CMSIS-DAP mode +ATTRS{idVendor}=="04b4", ATTRS{idProduct}=="f138", MODE="666" + +# Infineon DAP miniWiggler v3 +ATTRS{idVendor}=="058b", ATTRS{idProduct}=="0043", MODE="666" + +# Hitex LPC1768-Stick +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0026", MODE="666" + +# Hilscher NXHX Boards +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0028", MODE="666" + +# Hitex STR9-comStick +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002c", MODE="666" + +# Hitex STM32-PerformanceStick +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002d", MODE="666" + +# Hitex Cortino +ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0032", MODE="666" + +# Altera USB Blaster +ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="666" +# Altera USB Blaster2 +ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="666" +ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="666" + +# Ashling Opella-LD +ATTRS{idVendor}=="0B6B", ATTRS{idProduct}=="0040", MODE="666" + +# Amontec JTAGkey-HiSpeed +ATTRS{idVendor}=="0fbb", ATTRS{idProduct}=="1000", MODE="666" + +# SEGGER J-Link +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0101", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0102", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0103", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0104", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0107", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0108", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1010", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1011", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1012", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1013", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1014", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1015", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1016", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1017", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1018", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1020", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1051", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1055", MODE="666" +ATTRS{idVendor}=="1366", ATTRS{idProduct}=="1061", MODE="666" + +# Raisonance RLink +ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="666" + +# Debug Board for Neo1973 +ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="666" + +# OSBDM +ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0042", MODE="666" +ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0058", MODE="666" +ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="005e", MODE="666" + +# Olimex ARM-USB-OCD +ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0003", MODE="666" + +# Olimex ARM-USB-OCD-TINY +ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0004", MODE="666" + +# Olimex ARM-JTAG-EW +ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="001e", MODE="666" + +# Olimex ARM-USB-OCD-TINY-H +ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002a", MODE="666" + +# Olimex ARM-USB-OCD-H +ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002b", MODE="666" + +# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC +ATTRS{idVendor}=="16c0", ATTRS{idProduct}=="06ad", MODE="666" + +# USBprog with OpenOCD firmware +ATTRS{idVendor}=="1781", ATTRS{idProduct}=="0c63", MODE="666" + +# TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board +ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="666" + +# TI XDS110 Debug Probe (Launchpads and Standalone) +ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef3", MODE="666" +ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef4", MODE="666" +ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="02a5", MODE="666" + +# TI Tiva-based ICDI and XDS110 probes in DFU mode +ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00ff", MODE="666" + +# isodebug v1 +ATTRS{idVendor}=="22b7", ATTRS{idProduct}=="150d", MODE="666" + +# PLS USB/JTAG Adapter for SPC5xxx +ATTRS{idVendor}=="263d", ATTRS{idProduct}=="4001", MODE="666" + +# Numato Mimas A7 - Artix 7 FPGA Board +ATTRS{idVendor}=="2a19", ATTRS{idProduct}=="1009", MODE="666" + +# Ambiq Micro EVK and Debug boards. +ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="6010", MODE="666" +ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="6011", MODE="666" +ATTRS{idVendor}=="2aec", ATTRS{idProduct}=="1106", MODE="666" + +# Espressif USB JTAG/serial debug units +ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1001", MODE="666" +ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1002", MODE="666" + +# ANGIE USB-JTAG Adapter +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="424e", MODE="666" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4255", MODE="666" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4355", MODE="666" +ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4a55", MODE="666" + +# Marvell Sheevaplug +ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="666" + +# Keil Software, Inc. ULink +ATTRS{idVendor}=="c251", ATTRS{idProduct}=="2710", MODE="666" +ATTRS{idVendor}=="c251", ATTRS{idProduct}=="2750", MODE="666" + +# CMSIS-DAP compatible adapters +ATTRS{product}=="*CMSIS-DAP*", MODE="666" + +LABEL="openocd_rules_end" diff --git a/openocd-win/openocd/contrib/libdcc/README b/openocd-win/openocd/contrib/libdcc/README new file mode 100644 index 0000000..1135b24 --- /dev/null +++ b/openocd-win/openocd/contrib/libdcc/README @@ -0,0 +1,18 @@ +This code is an example of using the openocd debug message system. + +Before the message output is seen in the debug window, the functionality +will need enabling: + +From the gdb prompt: +monitor target_request debugmsgs enable +monitor trace point 1 + +From the Telnet prompt: +target_request debugmsgs enable +trace point 1 + +To see how many times the trace point was hit: +(monitor) trace point 1 + +Spen +spen@spen-soft.co.uk diff --git a/openocd-win/openocd/contrib/libdcc/dcc_stdio.c b/openocd-win/openocd/contrib/libdcc/dcc_stdio.c new file mode 100644 index 0000000..9ad633b --- /dev/null +++ b/openocd-win/openocd/contrib/libdcc/dcc_stdio.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2008 by Dominic Rath * + * Dominic.Rath@gmx.de * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * Copyright (C) 2008 by Frederik Kriewtz * + * frederik@kriewitz.eu * + ***************************************************************************/ + +#include "dcc_stdio.h" + +#define TARGET_REQ_TRACEMSG 0x00 +#define TARGET_REQ_DEBUGMSG_ASCII 0x01 +#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8)) +#define TARGET_REQ_DEBUGCHAR 0x02 + +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__) + +/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel + * DCRDR[7:0] is used by target for status + * DCRDR[15:8] is used by target for write buffer + * DCRDR[23:16] is used for by host for status + * DCRDR[31:24] is used for by host for write buffer */ + +#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8)) + +#define BUSY 1 + +void dbg_write(unsigned long dcc_data) +{ + int len = 4; + + while (len--) + { + /* wait for data ready */ + while (NVIC_DBG_DATA_R & BUSY); + + /* write our data and set write flag - tell host there is data*/ + NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY); + dcc_data >>= 8; + } +} + +#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__) + +void dbg_write(unsigned long dcc_data) +{ + unsigned long dcc_status; + + do { + asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status)); + } while (dcc_status & 0x2); + + asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data)); +} + +#else + #error unsupported target +#endif + +void dbg_trace_point(unsigned long number) +{ + dbg_write(TARGET_REQ_TRACEMSG | (number << 8)); +} + +void dbg_write_u32(const unsigned long *val, long len) +{ + dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16)); + + while (len > 0) + { + dbg_write(*val); + + val++; + len--; + } +} + +void dbg_write_u16(const unsigned short *val, long len) +{ + unsigned long dcc_data; + + dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16)); + + while (len > 0) + { + dcc_data = val[0] + | ((len > 1) ? val[1] << 16: 0x0000); + + dbg_write(dcc_data); + + val += 2; + len -= 2; + } +} + +void dbg_write_u8(const unsigned char *val, long len) +{ + unsigned long dcc_data; + + dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16)); + + while (len > 0) + { + dcc_data = val[0] + | ((len > 1) ? val[1] << 8 : 0x00) + | ((len > 2) ? val[2] << 16 : 0x00) + | ((len > 3) ? val[3] << 24 : 0x00); + + dbg_write(dcc_data); + + val += 4; + len -= 4; + } +} + +void dbg_write_str(const char *msg) +{ + long len; + unsigned long dcc_data; + + for (len = 0; msg[len] && (len < 65536); len++); + + dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16)); + + while (len > 0) + { + dcc_data = msg[0] + | ((len > 1) ? msg[1] << 8 : 0x00) + | ((len > 2) ? msg[2] << 16 : 0x00) + | ((len > 3) ? msg[3] << 24 : 0x00); + dbg_write(dcc_data); + + msg += 4; + len -= 4; + } +} + +void dbg_write_char(char msg) +{ + dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16)); +} diff --git a/openocd-win/openocd/contrib/libdcc/dcc_stdio.h b/openocd-win/openocd/contrib/libdcc/dcc_stdio.h new file mode 100644 index 0000000..3447b8c --- /dev/null +++ b/openocd-win/openocd/contrib/libdcc/dcc_stdio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * Copyright (C) 2008 by Dominic Rath * + * Dominic.Rath@gmx.de * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + ***************************************************************************/ + +#ifndef DCC_STDIO_H +#define DCC_STDIO_H + +void dbg_trace_point(unsigned long number); + +void dbg_write_u32(const unsigned long *val, long len); +void dbg_write_u16(const unsigned short *val, long len); +void dbg_write_u8(const unsigned char *val, long len); + +void dbg_write_str(const char *msg); +void dbg_write_char(char msg); + +#endif /* DCC_STDIO_H */ diff --git a/openocd-win/openocd/contrib/libdcc/example.c b/openocd-win/openocd/contrib/libdcc/example.c new file mode 100644 index 0000000..7c7d936 --- /dev/null +++ b/openocd-win/openocd/contrib/libdcc/example.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * Copyright (C) 2008 by Frederik Kriewtz * + * frederik@kriewitz.eu * + ***************************************************************************/ + +#include "dcc_stdio.h" + +/* enable openocd debugmsg at the gdb prompt: + * monitor target_request debugmsgs enable + * + * create a trace point: + * monitor trace point 1 + * + * to show how often the trace point was hit: + * monitor trace point +*/ + +int main(void) +{ + dbg_write_str("hello world"); + + dbg_write_char('t'); + dbg_write_char('e'); + dbg_write_char('s'); + dbg_write_char('t'); + dbg_write_char('\n'); + + unsigned long test_u32 = 0x01234567; + dbg_write_u32(&test_u32, 1); + + static const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF}; + dbg_write_u16(test_u16, 8); + + static const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF}; + dbg_write_u8(test_u8, 16); + + while(1) + { + dbg_trace_point(0); + } +} diff --git a/openocd-win/openocd/distro-info/CHANGELOG.md b/openocd-win/openocd/distro-info/CHANGELOG.md new file mode 100644 index 0000000..fdbf8ca --- /dev/null +++ b/openocd-win/openocd/distro-info/CHANGELOG.md @@ -0,0 +1,628 @@ +# Change & release log + +Entries in this file are in reverse chronological order. + +## 2023-09-04 + +* 8186554 package-lock.json update +* bdd0375 package.json: use github: helper +* 43fb8ee package.json: remove pkg-config from deps +* 99526e9 versioning.sh: bump deps +* 6743160 versioning.sh: update for latest commit +* f8e0808 openocd.sh: run_verbose diff +* c8379f3 CHANGELOG update +* 5a3f058 README updates +* 88994ee package.json: bump deps +* 012f130 dot.*ignore update +* d3d94dd re-generate workflows + +## 2023-09-03 + +* 70caa99 package.json: bump deps + +## 2023-08-28 + +* b3de5ce READMEs update + +## 2023-08-25 + +* e0e3c8e package.json: rm xpack-dev-tools-build/* +* e4c5804 package.json: bump deps + +## 2023-08-21 + +* e13385a READMEs update +* 82b20e2 package.json: bump deps + +## 2023-08-19 + +* c1aa321 READMEs update +* f2f7239 package.json: bump deps + +## 2023-08-15 + +* 8dd0d21 re-generate workflows +* f959671 README-MAINTAINER rename xbbla +* 60ff8ef package.json: rename xbbla +* a20733a package.json: bump deps +* 27277ab READMEs update +* ddcc6a0 package.json: bump deps + +## 2023-08-05 + +* 378cbda READMEs update + +## 2023-08-04 + +* 3c3e82e READMEs update +* 835a8d2 READMEs update +* 1188627 READMEs update + +## 2023-08-03 + +* 92f9c49 package.json: reorder build actions +* 7a5f3eb READMEs update +* 5be3464 package.json: bump deps + +## 2023-07-28 + +* 0f34460 READMEs update +* 3e3bceb READMEs update +* f743191 package.json: bump deps +* bbd6eb2 package.json: liquidjs --context --template +* 65ea0a9 scripts cosmetics +* cb1d34c re-generate workflows +* 629a380 READMEs update +* 9cdb678 package.json: minXpm 0.16.3 & @xpack-dev-tools/xbb-helper +* 40dfb2a READMEs update +* 77b1b4b package.json: bump deps + +## 2023-07-26 + +* 60a3907 package.json: move scripts to actions +* c26109e package.json: update xpack-dev-tools path +* 193f4d5 READMEs update xpack-dev-tools path +* ef9e796 .vscode/launch.json update +* fc6ac8c body-jekyll update +* 2774d4e READMEs update + +## 2023-07-17 + +* 03631fd package.json: bump deps +* 05f05aa package.json: add -develop-debug actions + +## 2023-07-08 + +* 08fe285 versioning.sh: add 0.12.0-2 commit id +* 592885b ~/Work/xpack-dev-tools/ +* 5423546 prepare v0.12.0-2 + +## 2023-04-19 + +* a6ed8e5 Merge pull request #26 from zqb-all/fix_typo +* 2aab171 README: fix typo + +## 2023-03-31 + +* 574ff3c README-DEVELOP.md: update +* 3909232 README-DEVELOP.md: update +* 63a1335 README-DEVELOP.md: update deep-clean +* 8e35423 openocd.sh: --enable-internal-libjaylink + +## 2023-03-28 + +* 068dc2d README-DEVELOPER update + +## 2023-03-27 + +* d531f0b README-DEVELOPER update +* 180d15d README-DEVELOPER update + +## 2023-03-25 + +* 7f7d1db README update +* c1891fb add README-DEVELOPER.md +* 29c93c1 READMEs update +* 26ecf82 READMEs update prerequisites + +## 2023-03-24 + +* 85dfffc package.json: mkdir -pv cache +* b5081e9 README update +* c312703 .vscode/settings.json: ignoreWords +* 07cb567 README-MAINTAINER.md update +* e320656 README-MAINTAINER: update prerequisites + +## 2023-02-22 + +* 33e43d0 READMEs update + +## 2023-02-14 + +* 32fbd24 body-jekyll update + +* ebf9368 package.json: update Work/xpacks +* 73b0ea7 READMEs update + +## 2023-02-07 + +* 65251a2 READMEs update +* 813a0e2 package.json: bump deps & reorder git-log +* 68ba49c versioning.sh: update for https +* 1ed35c9 body-jekyll update + +## 2023-01-30 + +* 65cdee4 0.12.0-1.1 +* 85ad2d2 CHANGELOG: publish npm v0.12.0-1.1 +* f82dae3 package.json: update urls for 0.12.0-1.1 release +* e79ff4c READMEs updates +* af00549 body-jekyll update +* 8022518 CHANGELOG update +* b6da41e .vscode/settings.json: ignoreWords +* v0.12.0-1 released +* f37a409 README update +* 3b8d65d remove unused XBB_BRANDING +* bd6d610 openocd.sh: move docs to LIBRARIES +* 381fa84 versioning.sh: move GIT_URL defs +* e0f02bf add .vscode/launch.json +* 61987a9 package.json: bump deps +* 73ca561 README updates +* 8bb511b openocd.sh: re-enable parallel build +* 65aee84 openocd.sh: use only -ludev on linux +* 2d369c1 openocd.sh: apply patches locally +* 427c081 .vscode/settings.json: ignoreWords +* e619b4d prepare v0.12.0-1 + +## 2023-01-29 + +* v0.12.0-1 prepared +* 02486b4 re-generate workflows +* 53c05f2 package.json: bump deps + +## 2023-01-28 + +* bcce8c3 versioning.sh: use versioning functions +* 949bed6 README-MAINTAINER remove caffeinate xpm + +## 2023-01-27 + +* 3b80250 package.json: reorder scripts + +## 2023-01-24 + +* b16e64a README updates + +## 2023-01-22 + +* ac30acd README update + +## 2023-01-11 + +* 4b20bb2 cosmetize xbb_adjust_ldflags_rpath + +## 2023-01-09 + +* ceef268 package.json: bump deps +* 777c73c package.json: loglevel info +* 201a58c versioning.sh: add comment before *_installed_bin + +## 2023-01-02 + +* ae9ffd4 package.json: add gcc to windows deps + +## 2023-01-01 + +* 528e1f2 package.json: pass xpm version & loglevel +* 099a8d5 README update + +## 2022-12-30 + +* fef7655 README-MAINTAINER: xpm run install +* 3556cba package.json: bump deps +* f8576b0 versioning.sh: regexp + +## 2022-12-27 + +* d8e72c0 README update +* 30753c6 echo FUNCNAME[0] +* 62b1cd0 use autotools_build +* d588a1f move *_installed_bin to versions.sh +* c7a592c re-generate from templates +* 927f3a9 cosmetics: move versions to the top + +## 2022-12-26 + +* 0258972 README updates + +## 2022-12-25 + +* fce7aa2 README update +* 12952ed versioning.sh: remove explicit xbb_set_executables_install_path +* 8e83ec7 package.json: add m4 dep +* 975d1d4 versioning.sh: add comment M4 + +## 2022-12-24 + +* 5452b76 README updates +* 241998a openocd.sh: pass path to test +* 719eb0a updates for xbb v 5.x +* 54da172 test.sh: update +* 3c40213 package.json: update +* 23269b2 package.json: bump deps +* 0e195e4 re-generate from templates +* d93b8ef rename functions + +## 2022-12-12 + +* d41e004 package.json: add caffeinate builds for macOS +* cca6fcc versioning.sh: use XBB_REQUESTED_* + +## 2022-11-18 + +* e92dd4c .vscode/settings.json: watcherExclude + +## 2022-10-28 + +* 1e9b995 cleanups +* 6b1c896 tests/run.sh: cosmetics +* 6237479 README updates +* 4b65463 README update +* d713f53 openocd.sh: fix test +* 33eebca .gitignore xpacks + +## 2022-10-27 + +* 9757baa package.json: bump deps +* 08b7b90 package.json: bump deps +* a5e069e package.json: bump deps +* b2ef4b3 package.json: bump deps +* b5a9472 versioning.sh: adjust LD_LIBRARY_PATH for libusb1 +* 89e5a13 openocd.sh: set -rpath +* f40f094 bring build_pkg_config back for macOS +* af34c4f package.json: add ninja to deps +* 15f9671 package.json: add cmake to deps +* ac46aa1 run.sh: cleanups +* 14be2a2 application.sh: remove pkg-config coreutils +* 582c24f versioning.sh: remove build_pkg_config +* 0f5a08d versioning.sh: build_application_versioned_components +* cc1087a README updates +* 1183e66 package.json: cp build.sh & test.sh +* ba1fd0b package.json: bump deps & cleanups +* cf2b53f .vscode/settings.json: ignoreWords +* 14504f4 re-generate workflows & scripts + +## 2022-10-23 + +* 821a513 package.json: bump deps +* f332865 package.json: bump deps +* c4b9381 READMEs update +* fb51384 package.json: add devDep realpath +* 0a13362 package.json: reorder actions +* c9f1e2e versioning.sh: remove build_coreutils +* 4a05989 cosmetics +* d19ddee test.sh: update +* 19956f9 build.sh: update +* d328879 rename application.sh + +## 2022-10-19 + +* b853e1c READMEs updates +* 8b816e4 versioning.sh: add XBB_COREUTILS_INSTALL_REALPATH_ONLY +* cd61164 updates for xbb v4.0 +* 88d94dc remove patches & pkgconfig (moved to helper) +* 1a676ae re-generate workflows + +## 2022-10-18 + +* d15ec21 remove submodule + +## 2022-10-04 + +* 101682e README-RELEASE update for bullet lists in CHANGELOG + +## 2022-09-25 + +* 30cf7d8 README-RELEASE update + +## 2022-09-17 + +* d2d81ea package.json: remove -ia32 +* 049765b README update +* 34d14ba README-BUILD update + +## 2022-09-03 + +* 72e5bc5 READMEs updates + +## 2022-09-01 + +* v0.11.0-5 published on npmjs.com +* v0.11.0-5 released + +## 2022-03-25 + +* v0.11.0-4 published on npmjs.com +* v0.11.0-4 published + +## 2021-12-07 + +* v0.11.0-3 published on npmjs.com +* v0.11.0-3 released + +## 2021-11-21 + +* v0.11.0-3 prepared +* update for Apple Silicon + +## 2021-10-16 + +* v0.11.0-2 published on npmjs.com +* v0.11.0-2 released + +## 2021-08-27 + +* v0.11.0-2 prepared +* [#10] - fix copying license sub-folders + +## 2021-03-15 + +* v0.11.0-1 prepared +* update to upstream 0.11 +* [#3] - remove deprecated --enable-oocd_trace +* v0.11.0-1 published +* v0.11.0-1.1 published on npmjs.com + +## 2020-10-13 + +* v0.10.0-15 published +* v0.10.0-15.1 published on npmjs.com + +## 2020-06-27 + +* v0.10.0-13.2 published on npmjs.com + +## 2020-06-26 + +* v0.10.0-14.2 published on npmjs.com (wrong skip:3) +* v0.10.0-14.1 published on npmjs.com (wrong .tgz extension) +* v0.10.0-14 released +* add binaries for Arm 32/64-bit +* update for XBB v3.2 +* based on openocd.git 8833c889da07eae750bcbc11215cc84323de9b74 from June 23rd, 2020 + +## 2020-03-26 + +* update for XBB v3.1 +* based on openocd.git d9ffe75e257aa4005dd34603860e45c57b1765b6 + +## 2019-07-27 + +* bump v0.10.0-14 +* add support for Arm binaries +* based on openocd.git e1e63ef30cea39aceda40daf194377c89c570101 + +## 2019-07-20 + +* v0.10.0-13.1 published on npmjs.com + +## 2019-07-17 + +* v0.10.0-13 released + +## 2019-07-08 + +* update to 263deb380 from 7 Jul 2019 + +___ + +# Historical GNU MCU Eclipse change log + +## 2019-04-23 + +* v0.10.0-12-20190423 released + +## 2019-04-09 + +* prepare - v0.10.0-12 +* update to latest master from Apr 7th, 2019 +* update LIBUSB1_VERSION="1.0.22" +* update LIBFTDI_VERSION="1.4" + +## 2019-01-18 + +* v0.10.0-11-20190118 released +* update to latest master from Jan 16, 2019 +* RISC-V specific patches were removed, only upstreamed functionality retained. + +## 2018-10-20 + +* v0.10.0-10-20181020 released +* rerun, to fix the macOS file dates +* update the -bit to singular + +## 2018-10-16 + +* v0.10.0-9-20181016 released +* update to latest master +* update to latest RISC-V +* revert some of the RISC-V patches in the common files + +## 2018-06-19 + +* update to latest RISC-V commits, including semihosting + +## 2018-06-12 + +* use separate README-*.md files +* update to latest commits, which include new semihosting (OpenOCD June 6th, RISC-V June 12th) + +## 2018-05-12 + +* v0.10.0-8-20180512 released +* use new build scripts based on XBB +* update to latest commits (OpenOCD April 27th, RISC-V May 8th) + +## 2018-01-23 + +* v0.10.0-7-20180123 released +* move semihosting code to separate files +* use them in RISC-V and ARM +* add 'arm semihosting_resexit enable' to allow exit() to return + +## 2018-01-12 + +* v0.10.0-6-20180112 released +* update to master from Dec 20 +* update to riscv from Dec 29 +* remove the patch to hide the CSRs, the new version displays only a limited number of them. +* remove the `remote_bitbang.c` patch, since it compiles ok on mingw-w64 +* the SiFive board scripts were upstreamed to the RISC-V fork + +## 2017-11-10 + +* v0.10.0-5-20171110-dev released +* update to master from Oct 2 +* update to riscv from Nov 4 +* target.c & riscv/riscv-0[13].c: hide the 4096 CSRs from `monitor reg` +* update the SiFive board script files +* revert the risc-v changes in `remote_bitbang.c`, since they break the build on mingw-w64 + +## 2017-10-04 + +* v0.10.0-4-20171004-*-dev released +* update to master from Aug 10 +* update to riscv fom Oct 2 +* gdb_server.c: workaround to gdb errors; disable passing errors back to gdb since this risc-v change breaks other targets. + +## 2017-08-25 + +* v0.10.0-3-20170826-*-dev released +* merge RISC-V tag v20170818 +* server.c: fix clang warning in getsockname() + +## 2017-07-03 + +* update build script to use Debian 9 Docker containers + +## 2017-06-22 + +* v0.10.0-2-20170622-1535-dev released +* merge RISC-V tag v20170621 + +## 2017-06-15 + +* move the build specific gnu-mcu-eclipse folder to a separate openocd-build project + +## 2017-06-12 + +* add --enable-riscv and #if BUILD_RISCV +* add --enable-branding + +## 2017-06-07 + +* v0.10.0-1-20170607-2132-dev released +* add sifive-* configuration files to the board folder +* 60-openocd.rules: simplify access rights +* merge RISC-V commit '11008ba' into gnu-mcu-eclipse-dev + +## 2017-06-06 + +* rename gnu-mcu-eclipse & content + +## 2017-06-04 + +* merge original branch 'master' from 2017-06-02 into gnuarmeclipse-dev. +* merge RISC-V commit '51ab5a0' from 2017-05-26 into gnuarmeclipse-dev + +## 2017-01-24 + +* v0.10.0-20170124* released (stable) +* merge original 0.10.0, override local relative path processing + +## 2016-10-28 + +* v0.10.0-20161028*-dev released + +## 2016-10-20 + +* nsi file: add InstallDir; silent install should honour /D + +## 2016-01-10 + +* v0.10.0-20160110*-dev released + +## 2015-10-28 + +* v0.10.0-20151028*-dev released + +## 2015-05-19 + +* v0.9.0-20150519*-dev released +* remove @raggedright from openocd.texi + +## 2015-05-11 + +* the three separate build scripts were deprecated, and a single script, +using Docker, was added to the main gnuarmeclipse-se.git/scripts. + +* the greeting shows 32-bits or 64-bits (plural for bits). (wrong!) + +## 2015-03-24 + +* v0.9.0-20150324*-dev released +* v0.8.0-20150324* released + +## 2015-03-22 + +* the NSIS script was fixed to prevent removing the keys when +uninstalling an older version. + +## 2015-03-20 + +* v0.9.0-20150320*-dev released +* v0.8.0-20150320* released + +## 2015-03-18 + +* the build scripts were extended to generate both the stable and the +development version. + +* multiple versions of the package can be installed in separate folders, +named using the version. + +* for Windows, more accurate keys were stored, so remember separate locations +for 32/64-bit versions. + +## 2015-01-31 + +* v0.8.0-20150131* released + +## 2015-01-30 + +* gnuarmeclipse + +All GNU ARM Eclipse OpenOCD build related files were grouped under this folder. + +* README.md + +Markdown files were added in all new folders, to improve the look when browsed +in the SourceForge Git web browser. + +## 2015-01-19 + +* v0.8.0-20150119* released + +## 2015-01-12 + +* src/openocd.c + +Add branding 'GNU ARM Eclipse' to the greeting message, to +more easily identify this custom version. + +* helper/options.c + +Update the logic used to locate the 'scripts' folder, by +using the argv[0], as on Windows. The logic is a bit more +complicated, to accommodate 3 cases (no path, relative path +and absolute path). diff --git a/openocd-win/openocd/distro-info/licenses/autoconf-2.71/AUTHORS b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/AUTHORS new file mode 100644 index 0000000..b6a63f2 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/AUTHORS @@ -0,0 +1,128 @@ +Authors of GNU Autoconf. + +Autoconf was originally written by David MacKenzie, with help from +François Pinard, Karl Berry, Richard Pixley, Ian Lance Taylor, Roland +McGrath, Noah Friedman, david d zuhn, and many others. + +Ben Elliston next took over the maintenance, facing a huge Autoconf +backlog that had been piling up since the departure of David. Other +maintainers have included Akim Demaille, Jim Meyering, Alexandre +Oliva, and Tom Tromey, with plenty of contributions from Lars J. Aas, +Mo DeJong, Steven G. Johnson, Matthew D. Langston, Pavel Roskin. + +Today, the primary maintainers are Paul Eggert and Eric Blake, with +help from Ralf Wildenhues, Stepan Kasal, and Benoit Sigoure. Many +other people have contributed, as listed in the THANKS file. + +The following contributors have warranted legal paper exchanges with +the Free Software Foundation for their contributions to GNU Autoconf. +This list results from searching for AUTOCONF in the file +/gd/gnuorg/copyright.list on the fencepost.gnu.org machine. + +David J. MacKenzie djm@gnu.org 1991-07-09 +James L. Avera ? 1993-10-04 +Roland McGrath roland@gnu.org 1994-06-24 +Noah Friedman friedman@gnu.org 1994-07-15 +Francois Pinard pinard@iro.umontreal.ca 1997-02-02 +Thomas E. Dickey dickey@clark.net 1998-01-11 +Matthew D. Langston langston@slac.stanford.edu 1998-09-29 +Mark Elbrecht snowball3@usa.net 1999-01-11 +Akim Demaille akim@gnu.org 1999-02-02 +Pavel Roskin pavel_roskin@geocities.com 1999-02-24 +Alexandre Oliva oliva@dcc.unicamp.br 1999-03-26 +Thomas Tanner tanner@ffii.org 1999-06-23 +Gary V. Vaughan gary@gnu.org 2000-01-10 +Joseph Samuel Myers jsm28@cam.ac.uk 2000-03-13 +Lars J. Aas larsa@sim.no 2000-07-07 +Morten Eriksen mortene@sim.no 2000-07-07 +Martin Wilck martin@tropos.de 2000-07-12 +Paul Eggert eggert@twinsun.com 2000-10-13 +Alexandre Duret-Lutz duret_g@epita.fr 2001-02-12 +Tim Van Holder tim.van.holder@pandora.be 2001-02-13 +Christian Marquardt marq@gfz-potsdam.de 2001-02-19 +Derek R. Price dprice@collab.net 2001-03-12 +Markus Kuhn Markus.Kuhn@cl.cam.ac.uk 2001-07-07 +Erik Lindahl erik@theophys.kth.se 2001-08-22 +Hans-Peter Nilsson hp@bitrange.com 2001-10-24 +Paul Wagland paul@wagland.net 2001-10-30 +Paolo Bonzini bonzini@gnu.org 2001-11-08 +Nishio Futoshi fut_nis@d3.dion.ne.jp 2002-01-23 +Federico G. Schwindt fgsch@openbsd.org 2002-05-21 +Mark D. Roth roth@feep.net 2002-05-28 +Greg McGary greg@mcgary.org 2002-06-05 +Charles Stephen Wilson cwilson@ece.gatech.edu 2002-07-25 +Robert Bernstein rocky@panix.com 2002-08-20 +Assar Westerlund assar@kth.se 2002-09-13 +Scott Bambrough sbambrough@storm.ca 2002-09-24 +Richard Dawe rich@phekda.freeserve.co.uk 2003-01-23 +Andreas Buening andreas.buening@nexgo.de 2003-02-18 +Raja R. Harinath harinath@acm.org 2003-02-25 +Ilya Zakharevich ilya@Math.Berkeley.EDU 2003-03-11 +Kaveh Ghazi ghazi@caip.rutgers.edu 2003-03-15 +Felix Lee felix.1@canids.net 2003-03-31 +Nathanael Nerode neroden@twcny.rr.com 2003-04-04 +Gavin Puche user42@zip.com.au 2003-04-10 +Steven Glenn Johnson stevenj@alum.mit.edu 2003-07-26 +Bernardo Innocenti bernie@codewiz.org 2003-07-31 +Albert Marsden Chin-A-Young china@thewrittenword.com 2003-08-02 +Ralf Corsepius corsepiu@faw.uni-ulm.de 2003-09-03 +Scott Remnant scott@netsplit.com 2003-10-04 +Daniel Jacobowitz dan@debian.org 2003-10-17 +Kevin Fleming kpfleming@backtobasicsmgmt.com 2003-11-17 +John David Anglin dave.anglin@nrc-cnrc.gc.ca 2004-01-21 +Eric Sunshine sunshine@sunshineco.com 2004-01-25 +Ralf Wildenhues Ralf.Wildenhues@gmx.de 2004-02-12 +Noah Jeffrey Misch noah@cs.caltech.edu 2004-07-05 +Thorsten Glaser tg@66h.42h.de 2004-10-11 +Peter O'Gorman peter@pogma.com 2004-11-14 +Toshio Ernie Kuratomi toshio@tiki-lounge.com 2004-11-17 +Roger Leigh rleigh@whinlatter.ukfsn.org 2004-12-09 +Ian Lance Taylor ian@airs.com 2004-12-22 +Daniel Manthey dan_manthey@partech.com 2005-02-14 +Gregorio Guidi greg_g@gentoo.org 2005-03-03 +Bruno Haible bruno@clisp.org 2005-06-12 +Toby Oliver Hilary White tow21@cam.ac.uk 2005-10-18 +Eric Benjamin Blake ebb9@byu.net 2006-01-18 +Romain Lenglet romain.lenglet@laposte.net 2006-02-10 +Markus Duft markus.duft@salomon.at 2006-08-03 +Robert Schiele rschiele@gmail.com 2006-09-12 +Joel Edward Denny jdenny@clemson.edu 2006-09-15 +Helge Deller deller@gmx.de 2007-02-01 +Benoit Sigoure tsuna@lrde.epita.fr 2007-04-20 +Bob Proulx bob@proulx.com 2007-06-25 +Bruce Korb bkorb@gnu.org 2008-05-06 +Benjamin Pfaff blp@gnu.org 2008-09-29 +Peter Breitenlohner peb@mppmu.mpg.de 2009-08-18 +Stefano Lattarini stefano.lattarini@gmail.com 2009-10-01 +Reuben Thomas rrt@sc3d.org 2010-03-10 +Peter Rosin peda@lysator.liu.se 2010-07-21 +John W. Eaton jwe@gnu.org 2010-11-05 +Christopher Hulbert cchgroupmail@gmail.com 2010-11-09 +Tim Rice tim@multitalents.net 2011-01-24 +KO Myun-Hun komh78@gmail.com 2011-04-05 +Christian Roessel christian.roessel@gmx.de 2011-08-26 +Nicolai Stange nicolai.stange@zmaw.de 2011-10-13 +Zachary Weinberg zackw@panix.com 2013-06-11 + +======================================================================== + +Local Variables: +mode: text +coding: utf-8 +End: + +Copyright (C) 1996, 2000-2001, 2005, 2007-2017, 2020-2021 Free Software +Foundation, Inc. + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING new file mode 100644 index 0000000..7b63d8e --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING @@ -0,0 +1,338 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. 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If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING.EXCEPTION b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING.EXCEPTION new file mode 100644 index 0000000..7d5c24e --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING.EXCEPTION @@ -0,0 +1,43 @@ + AUTOCONF CONFIGURE SCRIPT EXCEPTION + Version 3.0, 18 August 2009 + + Copyright (C) 2009 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +This Exception is an additional permission under section 7 of the GNU +General Public License, version 3 ("GPLv3"). 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But first, please read +. diff --git a/openocd-win/openocd/distro-info/licenses/autoconf-2.71/NEWS b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/NEWS new file mode 100644 index 0000000..f035e65 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/autoconf-2.71/NEWS @@ -0,0 +1,2608 @@ +GNU Autoconf NEWS - User visible changes. + +* Noteworthy changes in release 2.71 (2021-01-28) [stable] + +** Bug fixes, including: + +*** Compilers that support C99 but not C2011 are detected correctly. + +*** Compatibility improved with clang and Oracle C++. + +*** Compatibility restored with automake's rules for regenerating configure. + +*** Compatibility restored with old versions of std-gnu11.m4. + + Packages that wish to maintain compatibility with Autoconf 2.69 or + older, should update their copy of std-gnu11.m4 from Gnulib as soon + as practical, as the compatibility code bulks up the configure script. + + Packages that require Autoconf 2.70 can drop this file entirely. + +* Noteworthy changes in release 2.70 (2020-12-08) [stable] + +** Backward incompatibilities: + +*** Warnings about obsolete constructs are now on by default. + + These warnings can be turned off with ‘-Wno-obsolete’. + + Many of these warnings advise maintainers to run autoupdate. + Be aware that autoupdate cannot solve all backward compatibility + problems, and cannot completely solve all of the problems it does + address. A configure script edited by autoupdate is likely to + need further manual fix-ups. + +*** Many macros have become pickier about argument quotation. + + If you get a shell syntax error from your generated configure + script, or seemingly impossible misbehavior (e.g. entire blocks of + the configure script not getting executed), check first that all + macro arguments are properly quoted. The “M4 Quotation” section of + the manual explains how to quote macro arguments properly. + + It is unfortunately not possible for autoupdate to correct + quotation errors. + +*** Many macros no longer AC_REQUIRE as many other macros as they used to. + + This can expose several classes of latent bugs. These are the ones + we know about: + + - Make sure to explicitly invoke all of the macros that set result + variables used later in the configure script, or in generated + Makefiles. + + - Autoconf macros that use AC_REQUIRE are not safe to use in shell + control-flow constructs that appear outside of macros defined by + AC_DEFUN. Use AS_IF, AS_CASE, etc. instead. (See the + “Prerequisite Macros” section of the manual for details.) + + The set of macros that use AC_REQUIRE internally may change from + release to release. The only macros that are guaranteed *not* to + use AC_REQUIRE are the macros for acting on the results of a + test: AC_DEFINE, AC_SUBST, AC_MSG_*, AC_CACHE_CHECK, etc. + + - AC_REQUIRE cannot be applied to macros that need to be used with + arguments. Instead, invoke the macro normally, with its arguments. + +*** More macros use config.sub and config.guess internally. + + As a consequence of improved support for cross compilation (see below), + more macros now use the auxiliary scripts ‘config.sub’ and ‘config.guess’. + If you use any of the affected macros, these scripts must be available + when your configure script is run, even if you have no intention of + ever cross-compiling your program. + + autoreconf will issue an error if any auxiliary scripts are needed but + cannot be found. (It is not currently possible to make autoconf + itself issue this error.) + + ‘autoreconf --install’ will add ‘config.sub’, ‘config.guess’, and + ‘install-sh’ to your source tree if they are needed. If you are + using Automake, scripts added to your tree by ‘autoreconf --install’ + will automatically be included in the tarball produced by ‘make dist’; + otherwise, you will need to arrange for them to be distributed + yourself. + + See the “Input” section of the manual for more detail, including + where to get the auxiliary scripts that may be needed by autoconf macros. + +*** Setting CC to a C++ compiler is no longer supported. + + The C and C++ languages have diverged enough that we can no longer + guarantee that test C programs will be processed as intended by a + C++ compiler. In this release, configure will proceed anyway, but + many test results will be incorrect. In a future release, we may + make AC_PROG_CC error out if it detects that CC is a C++ compiler. + + See the “Language Choice” section of the manual for instructions on + how to write configure scripts for C++ programs, and for programs + with code in more than one language. + +*** Running configure tests with warnings promoted to errors is not supported. + + For instance, setting ‘CC="gcc -Werror"’ on the configure command + line, or adding -Werror to CFLAGS early in the configure script when + the compiler recognizes this option, is very likely to cause + subsequent tests to fail. + + This has never been guaranteed to work; the code generated by + AC_CHECK_FUNC, for instance, is incorrect by a strict reading of the + original 1989 C standard, and has been ever since that macro was + introduced. Problems are more likely with newer, pickier compilers. + + To enable compiler warnings and/or warnings-as-errors mode for your + own code, we currently recommend a dedicated Makefile variable + (e.g. ‘WARN_CFLAGS’) that is set by AC_SUBST when appropriate. + The Gnulib ‘warnings’ and ‘manywarnings’ modules can help with this. + We plan to add core support for probing for useful sets of compiler + warnings in a future release. + +*** Including confdefs.h manually may cause test failures. + + This has never been necessary; confdefs.h is automatically included + at the beginning of all test programs (by AC_LANG_SOURCE). Because + of the way confdefs.h is generated and used, it is not practical to + give it a multiple inclusion guard. Therefore, if you include it + yourself, all of its definitions will be scanned twice. + + Historically this has not been a problem, because confdefs.h only + makes macro definitions, and the C standard allows redefinitions + of macros as long as they’re exactly the same, but newer, pickier + compilers may complain anyway (see for instance GCC bug 97998). + +*** Older versions of automake and aclocal (< 1.8) are no longer supported. + +*** AC_CONFIG_SUBDIRS no longer directly supports Cygnus configure. + + If you are still using an Autoconf script to drive configuration of + a multi-package build tree where some subdirectories use Cygnus + configure, copy or link $ac_aux_dir/configure into each subdirectory + where it is needed. Please also contact us; we were under the + impression nobody used this very old tool anymore. + +*** AC_CHECK_HEADER and AC_CHECK_HEADERS only do a compilation test. + + This completes the transition from preprocessor-based header tests + begun in Autoconf 2.56. + + The double test that was the default since Autoconf 2.64 is no + longer available. You can still request a preprocessor-only test + by specifying [-] as the fourth argument to either macro, but this + is now deprecated. If you really need that behavior use + AC_PREPROC_IFELSE. + +*** AC_INCLUDES_DEFAULT assumes an ISO C90 compliant C implementation. + + Specifically, it assumes that the ISO C90 header + is available, without checking for it, and it does not include + the pre-standard header at all. If the POSIX header + exists, it will be included, without first testing + whether both and can be included in the + same source file. + + AC_INCLUDES_DEFAULT still checks for the existence of , + , and , because these headers may not exist + in a “freestanding environment” (a compilation mode intended for OS + kernels and similar, where most of the features of the C library are + optional). Most programs need not use ‘#ifdef HAVE_STDLIB_H’ etc in + their own code. + + For compatibility’s sake, the C preprocessor macro STDC_HEADERS + will be defined when both and are available; + however, and are no longer checked for + (these, like , are required to exist in a freestanding + environment). New code should not refer to this macro. + + Future releases of Autoconf may reduce the set of headers checked + for by AC_INCLUDES_DEFAULT. + +*** AS_ECHO and AS_ECHO_N unconditionally use ‘printf’. + + This is substantially simpler, more reliable, and, in most cases, + faster than attempting to use ‘echo’ at all. However, if ‘printf’ + is not a shell builtin, configure scripts will run noticeably + slower, and if ‘printf’ is not available at all, they will crash. + The only systems where this is known to be a problem are extremely + old, and unlikely to be able to handle modern C programs for other + reasons (e.g. not having a C90-compliant compiler at all). + +*** Configure scripts require support for $( ... ) command substitution. + + This POSIX shell feature is approximately the same age as + user-defined functions, but there do exist shells that support + functions and not $( ... ), such as Solaris 10 /bin/sh. + + Configure scripts will automatically locate a shell that supports + this feature and re-execute themselves with it, if necessary, so + the new requirement should be transparent to most users. + + In this release, most of Autoconf’s code still uses the older `...` + notation for command substitution. + +*** AC_INIT now trims extra white space from its arguments. + + For instance, AC_INIT([ GNU Hello ], [1.0]) will set PACKAGE_NAME + to “GNU Hello”. + +*** Macros that take whitespace-separated lists as arguments + now always expand macros within those arguments. + + Formerly, these macros would *usually* expand those arguments, but + the behavior was not reliable nor was it consistent between autoconf + and autoheader. + + Macro expansion within these arguments is deprecated; if expansion + changes the list, a warning in the “obsolete” category will be + emitted. Note that ‘dnl’ is a macro. Putting ‘dnl’ comments inside + any argument to an Autoconf macro is, in general, only supported + when that argument takes more Autoconf code (e.g. the ACTION-IF-TRUE + argument to AC_COMPILE_IFELSE). + + The affected macros are AC_CHECK_FILES, AC_CHECK_FUNCS, + AC_CHECK_FUNCS_ONCE, AC_CHECK_HEADERS, AC_CHECK_HEADERS_ONCE, + AC_CONFIG_MACRO_DIRS, AC_CONFIG_SUBDIRS, and AC_REPLACE_FUNCS. + +*** AC_FUNC_VFORK no longer ignores a signal-handling bug in Solaris 2.4. + + This bug was being ignored because Emacs wanted to use ‘vfork’ on + Solaris 2.4 anyway, but current versions of Emacs have dropped + support for Solaris 2.4. Most programs will want to avoid ‘vfork’ + on this OS because of this bug. + +*** AC_FUNC_STRERROR_R assumes strerror_r is unavailable if it’s not declared. + + The fallback technique it used to probe strerror_r’s return type + when the function was present in the C library, but not declared by + , was fragile and did not work at all when cross-compiling. + The systems where this fallback was necessary were all obsolete. + + Programs that use AC_FUNC_STRERROR_R should make sure to test the + preprocessor macro HAVE_DECL_STRERROR_R before using strerror_r at all. + +*** AC_OPENMP can’t be used if you have files named ‘mp’ or ‘penmp’. + + Autoconf will now issue an error if AC_OPENMP is used in a configure + script that’s in the same directory as a file named ‘mp’ or ‘penmp’. + Configure scripts that use AC_OPENMP will now error out upon + encountering files with these names in their working directory + (e.g. when the build directory is separate from the source directory). + + If you have files with these names at the top level of your source + tree, we recommend either renaming them or moving them into a + subdirectory. See the documentation of AC_OPENMP for further + explanation. + +** New features + +*** Configure scripts now support a ‘--runstatedir’ option. + + This defaults to ‘${localstatedir}/run’. It can be used, for + instance, to place per-process temporary runtime files (such as pid + files) into ‘/run’ instead of ‘/var/run’. + +*** autoreconf will now run gtkdocize and intltoolize when appropriate. + +*** autoreconf now recognizes AM_GNU_GETTEXT_REQUIRE_VERSION. + + This macro can be used with gettext 0.19.6 or later to specify + a *minimum* version requirement for gettext, instead of the *fixed* + version requirement specified by AM_GNU_GETTEXT_VERSION. + +*** autoheader handles secondary config headers better. + + It is no longer necessary to duplicate AC_DEFINE templates in the + main configuration header for autoheader to notice them. + +*** AC_PROG_CC now enables C2011 mode if the compiler supports it. + + If not, it will fall back to C99 and C89, as before. Similarly, + AC_PROG_CXX now enables C++2011 if available, falling back on C++98. + +*** New macro AC_C__GENERIC tests for C2011 _Generic support. + +*** AC_C_VARARRAYS has been aligned with C2011. + + It now defines __STDC_NO_VLA__ if variable-length arrays are not + supported but the compiler does not define __STDC_NO_VLA__. + + For backward compatibility with Autoconf 2.61-2.69 AC_C_VARARRAYS + still defines HAVE_C_VARARRAYS, but this result macro is obsolescent. + +*** New macro AC_CONFIG_MACRO_DIRS. + + This macro can be used more than once and accepts a list of + directories to search for local M4 macros. With Automake 1.13 and + later, use of this macro eliminates a reason to use ACLOCAL_AMFLAGS + in Makefile.am. + + The older AC_CONFIG_MACRO_DIR, which could only be used once, is + still supported but considered deprecated. + +*** AC_USE_SYSTEM_EXTENSIONS knows about more extensions to enable. + + System extensions will now be enabled on HP-UX, macOS, and MINIX. + Optional ISO C library components (e.g. decimal floating point) will + also be enabled. + +*** New compatibility macro AC_CHECK_INCLUDES_DEFAULT. + + This macro runs the checks normally performed as a side-effect by + AC_INCLUDES_DEFAULT, if they haven’t already been done. Autoupdate + will replace certain obsolete constructs, whose only remaining + useful effect is to trigger those checks, with this macro. It is + unlikely to be useful otherwise. + +*** AC_REQUIRE_AUX_FILE has been improved. + + Configure scripts now check, on startup, for the availability of all + the aux files that were mentioned in an AC_REQUIRE_AUX_FILE + invocation. This should help prevent certain classes of packaging + errors. + + Also, it is no longer necessary for third-party macros that use + AC_REQUIRE_AUX_FILE to mention AC_CONFIG_AUX_DIR_DEFAULT. However, + if you are using AC_CONFIG_AUX_DIR_DEFAULT *without* also using + AC_REQUIRE_AUX_FILE, please start using AC_REQUIRE_AUX_FILE to + specify the aux files you actually need, so that the check can be + effective. + +*** AC_PROG_LEX has an option to not look for yywrap. + + AC_PROG_LEX now takes one argument, which may be either ‘yywrap’ or + ‘noyywrap’. If it is ‘noyywrap’, AC_PROG_LEX will only set LEXLIB + to ‘-lfl’ or ‘-ll’ if a scanner that defines both main and yywrap + itself still needs something else from that library. On the other + hand, if it is ‘yywrap’, AC_PROG_LEX will fail (setting LEX to ‘:’ + and LEXLIB to nothing) if it can’t find a library that defines yywrap. + + In the absence of arguments, AC_PROG_LEX’s behavior is bug-compatible + with 2.69, which did neither of the above things (see the manual for + details). This mode is deprecated. + + We encourage all programs that use AC_PROG_LEX to use the new + ‘noyywrap’ mode, and to define yywrap themselves, or use %noyywrap. + The yywrap function in lib(f)l is trivial, and self-contained + scanners are easier to work with. + +** Obsolete features and new warnings + +*** Use of the long-deprecated name ‘configure.in’ for the autoconf + input file now elicits a warning in the “obsolete” category. + +*** Use of the undocumented internal shell variables $as_echo and + $as_echo_n now elicits a warning in the “obsolete” category. + The macros AS_ECHO and AS_ECHO_N should be used instead. + +*** autoconf will now issue warnings (in the “syntax” category) + if the input file is missing a call to AC_INIT and/or AC_OUTPUT. + +*** autoconf will now issue warnings (in the “syntax” category) + for a non-literal URL argument to AC_INIT, and for a TARNAME + argument to AC_INIT which is either non-literal or contains + characters that should not be used in file names (e.g. ‘*’). + +*** AC_PROG_CC_STDC, AC_PROG_CC_C89, AC_PROG_CC_C99 are now obsolete. + + Applications should use AC_PROG_CC. + +*** AC_HEADER_STDC and AC_HEADER_TIME are now stubs. + + They still define the C preprocessor macros STDC_HEADERS and + TIME_WITH_SYS_TIME, respectively, but they no longer check for the + ancient, non-ISO-C90 compliant systems where formerly those macros + would not be defined. Autoupdate will remove them. + + These macros were already labeled obsolete in the manual. + +*** AC_DIAGNOSE, AC_FATAL, AC_WARNING, and _AC_COMPUTE_INT are now + replaced with modern equivalents by autoupdate. + + These macros were already labeled obsolete in the manual. + +*** AC_CONFIG_HEADER is now diagnosed as obsolete, and replaced with + AC_CONFIG_HEADERS by autoupdate. + + This macro has been considered obsolete for many years and was not + documented at all. + +*** The macro AC_OBSOLETE is obsolete. + + Autoupdate will replace it with m4_warn([obsolete], [explanation]). + If possible, macros using AC_OBSOLETE should be converted to use + AU_DEFUN or AU_ALIAS instead, which enables autoupdate to replace + them, but this has to be done by hand and is not always possible. + + This macro has been considered obsolete for many years, but was not + officially declared as such. + +*** Man pages for config.guess and config.sub are no longer provided. + + They were moved to the master source tree for config.guess and + config.sub. + +** Notable bug fixes + +*** Compatible with current Automake, Libtool, Perl, Texinfo, and shells. + + All of autoconf’s tools and generated scripts, and the build process + and testsuite for autoconf itself, have been tested to work + correctly with current versions of Automake, Libtool, Perl, Texinfo, + bash, ksh93, zsh, and FreeBSD and NetBSD /bin/sh. + + Generated configure scripts are expected to work reliably with an + even wider variety of shells, including BusyBox sh and various + proprietary Unixes’ /bin/sh, as long as they are minimally compliant + with the Unix95 shell specification. Notably, support for + shell-script functions and the ‘printf’ builtin are required. + +*** Checks compatible with current language standards and compilers. + + Many individual macros have been improved to accommodate changes in + recent versions of the C and C++ language standards, and new + features and quirks of commonly used compilers (both free and + proprietary). + +*** Improved support for cross compilation. + + Many individual macros have been improved to produce more accurate + results when cross-compiling. + +*** Improved robustness against unusual build environments. + + Many bugs have been fixed where generated configure scripts would + fail catastrophically under unusual conditions, such as stdout being + closed, or $TMPDIR not being an absolute path, or the root directory + being mentioned in $PATH. + +*** AC_CHECK_FUNCS_ONCE and AC_CHECK_HEADERS_ONCE now support multiple + programming languages. They no longer perform all checks in the + language active upon the first use of the macro. + +*** AC_CHECK_DECL and AC_CHECK_DECLS will now detect missing declarations for + library functions that are also Clang compiler builtins. + +*** AC_PATH_X and AC_PATH_XTRA don’t search for X11 when cross-compiling. + + Libraries and headers found by running xmkmf or searching /usr/X11, + /usr/X11R7, etc. are likely to belong to a native X11 installation + for the build machine and to be inappropriate for cross compilation. + + To cross-compile programs that require X11, we recommend putting the + headers and libraries for the host system in your cross-compiler’s + default search paths. Alternatively, use configure’s --x-includes + and --x-libraries command line options to tell it where they are. + +*** AS_IF’s if-false argument may be empty after macro expansion. + + This long-standing limitation broke configure scripts that used + macros in this position that emitted shell code in 2.69 but no + longer do, so we have lifted it. + +*** AC_HEADER_MAJOR detects the location of the major, minor, and + makedev macros correctly under glibc 2.25 and later. + +*** AC_FC_LINE_LENGTH now documents the maximum portable length of + “unlimited” Fortran source code lines to be 250 columns, not 254. + +*** AC_INIT and AS_INIT no longer embed (part of) the path to the + source directory in generated files. + + We believe this was the only case where generated file contents + could change depending on the environment outside the source tree + itself. If you find any other cases please report them as bugs. + +*** config.log properly escapes arguments in the header comment. + +*** config.status --config output is now quoted in a more readable fashion. + +** Autotest enhancements + +*** Autotest provides a new macro AT_DATA_UNQUOTED, similar to AT_DATA + but processing variable substitutions, command substitutions and + backslashes in the contents argument. + +*** AC_CONFIG_TESTDIR will automatically pass EXEEXT to a testsuite (via + the atconfig file). + +*** AT_TESTED arguments can use variable or command substitutions, including + in particular $EXEEXT + +*** New macros AT_PREPARE_TESTS, AT_PREPARE_EACH_TEST, and AT_TEST_HELPER_FN. + + These provide an official way to define testsuite-specific + initialization code and shell functions. + +* Noteworthy changes in release 2.69 (2012-04-24) [stable] + +** Autoconf now requires perl 5.6 or better (but generated configure + scripts continue to run without perl). + +* Noteworthy changes in release 2.68b (2012-03-01) [beta] + Released by Eric Blake, based on git versions 2.68.*. + +** Autoconf-generated configure scripts now unconditionally re-execute + themselves with $CONFIG_SHELL, if that's set in the environment. + +** The texinfo documentation no longer specifies "front-cover" or + "back-cover" texts, so that it may now be included in Debian's + "main" section. + +** Support for the Go programming language has been added. The new macro + AC_LANG_GO sets variables GOC and GOFLAGS. + +** AS_LITERAL_IF again treats '=' as a literal. Regression introduced in + 2.66. + +** The macro AS_EXECUTABLE_P, present since 2.50, is now documented. + +** Macros + +- AC_PROG_LN_S and AS_LN_S now fall back on 'cp -pR' (not 'cp -p') if 'ln -s' + does not work. This works better for symlinks to directories. + +- New macro AC_HEADER_CHECK_STDBOOL. + +- New and updated macros for Fortran support: + + AC_FC_CHECK_BOUNDS to enable array bounds checking + AC_F77_IMPLICIT_NONE and AC_FC_IMPLICIT_NONE to disable implicit integer + AC_FC_MODULE_EXTENSION to compute the Fortran 90 module name extension + AC_FC_MODULE_FLAG for the Fortran 90 module search path flag + AC_FC_MODULE_OUTPUT_FLAG for the Fortran 90 module output directory flag + AC_FC_PP_SRCEXT for preprocessed Fortran source files extensions + AC_FC_PP_DEFINE for the Fortran preprocessor define flag + +* Noteworthy changes in release 2.68 (2010-09-22) [stable] + Released by Eric Blake, based on git versions 2.67.*. + +** AC_MSG_ERROR (and AS_ERROR) can once again be followed immediately by + `dnl'. Regression introduced in 2.66. + +** AC_INIT again allows URLs with '?' for its BUG-REPORT argument. + Regression introduced in 2.66. + +** AC_REPLACE_FUNCS again allows a non-literal argument, such as a shell + variable that expands to a list of functions to check. Regression + introduced in 2.66. + +** AT_BANNER() with empty argument will cause visual separation from previous + test category. + +** The macros AC_PREPROC_IFELSE, AC_COMPILE_IFELSE, AC_LINK_IFELSE, and + AC_RUN_IFELSE now warn if the first argument failed to use + AC_LANG_SOURCE or AC_LANG_PROGRAM to generate the conftest file + contents. A new macro AC_LANG_DEFINES_PROVIDED exists if you have + a compelling reason why you cannot use AC_LANG_SOURCE but must + avoid the warning. + +** The macro m4_define_default is now documented. + +** Symlinked config.cache files are supported; configure now tries to + update non-symlinked cache files atomically, so that concurrent configure + runs do not leave behind broken cache files. It is still unspecified + which subset or union of results is cached though. + +** Autotest testsuites should not contain long text lines any more, and be + portable even when very many test groups are used. + +** AT_CHECK semantics with respect to the Autotest variable $at_status and + shell execution environment of the arguments are documented now. + +** AC_FC_LIBRARY_LDFLAGS now tolerates output from newer gfortran. + +** Newly obsolete macros + The following macros have been marked obsolete. New programs + should use the corresponding Gnulib modules. Gnulib not only + detects a larger set of portability problems with these functions, + but also provides complete workarounds. + + AC_FUNC_ERROR_AT_LINE AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK + AC_FUNC_MKTIME AC_FUNC_STRTOD + + +* Major changes in Autoconf 2.67 (2010-07-21) [stable] + Released by Eric Blake, based on git versions 2.66.*. + +** AC_CONFIG_SUBDIRS with more than one subdirectory at a time works again. + Regression introduced in 2.66. + +** AC_CHECK_SIZEOF of a pointer type works again. Regression introduced in + 2.66. + +** New macro AC_FC_LINE_LENGTH to accept long Fortran source code lines. + +** AC_PREPROC_IFELSE now keeps the preprocessed output in the conftest.i + file for inspection by the commands in the ACTION-IF-TRUE argument. + +** AC_INIT again allows parentheses and other characters that are literal + in single- or double-quoted strings, and in quoted and unquoted + here-documents, for its PACKAGE and VERSION arguments. Regression + introduced in 2.66. + +** autoreconf passes warning flags to new enough versions of aclocal. + +** Running an Autotest testsuite in parallel mode no longer triggers a + race condition that could cause the testsuite run to end early, + fixing a sporadic failure in autoconf's own testsuite. Bug present + since introduction of parallel tests in 2.63b. + + +* Major changes in Autoconf 2.66 (2010-07-02) [stable] + Released by Eric Blake, based on git versions 2.65.*. + +** AC_FUNC_MMAP works in C++ mode again. Regression introduced in 2.65. + +** Use of m4_divert without a named diversion now issues a syntax warning, + since it is seldom right to change diversions behind autoconf's back. + +** The macros AC_TYPE_INT8_T, AC_TYPE_INT16_T, AC_TYPE_INT32_T, and + AC_TYPE_INT64_T work again. Regression introduced in 2.65. + +** AC_PROG_INSTALL correctly uses `shtool' again. Regression introduced + in 2.64. + +** Autoconf should work on EBCDIC hosts. + +** AC_CHECK_DECL and AC_CHECK_DECLS accept optional function argument types + for overloaded C++ functions. + +** AS_SET_CATFILE accepts nonliterals in its variable name argument now. + +** Autotest testsuites accept an option --recheck to rerun tests that + failed or passed unexpectedly during the last non-debug testsuite run. + +** AC_ARG_ENABLE and AC_ARG_WITH now also accept `+' signs in `--enable-*' + and `--with-*' arguments, converting them to underscores for the variable + names. + +** In configure scripts, loading CONFIG_SITE no longer searches PATH, + and problems in loading the configuration site files are diagnosed. + +** Autotest testsuites may optionally provide colored test results. + +** The previously undocumented Autotest macros AT_ARG_OPTION and + AT_ARG_OPTION_ARG have seen bug fixes and are documented now. + AT_ARG_OPTION has been changed in that the negative of a long option + --OPTION is now --no-OPTION rather than --noOPTION. + +** The macro AS_LITERAL_IF is slightly more conservative; text + containing shell quotes are no longer treated as literals. + Furthermore, a new macro, AS_LITERAL_WORD_IF, adds an additional + level of checking that no whitespace occurs in literals. + +** The macros AS_TR_SH and AS_TR_CPP no longer expand their results. + +** The following macros are now documented: + AS_BOX + +** New macro AC_FC_FIXEDFORM to accept fixed-form Fortran. + + +* Major changes in Autoconf 2.65 (2009-11-21) [stable] + Released by Eric Blake, based on git versions 2.64.*. + +** Autoconf is now licensed under the General Public License version 3 + or later (GPLv3+). As with earlier versions, the license includes + an exception clause so that you may release a configure script + generated by autoconf under the license of your own program. + +** New macros to support Objective C++. + AC_PROG_OBJCXX AC_PROG_OBJCXXCPP + +** The following undocumented autoconf macros, removed in Autoconf 2.64, + have been reinstated: + AH_CHECK_HEADERS + + These macros are present only for backwards compatibility purposes. + +** The macro AC_LANG_COMPILER no longer fails on embedded systems that + lack fopen in the C library, such as AVR or RTEMS (regression + introduced in 2.64). + +** The AC_FC_FREEFORM macro no longer suffers from a whitespace bug that + made it fail with some Fortran compilers (regression introduced in + 2.64). + +** The AC_TYPE_UINT64_T and AC_TYPE_INT64_T macros have been fixed to no + longer mistakenly select a 32-bit type on some compilers (bug present + since macros were introduced in 2.59c). + +** The AC_FUNC_MMAP macro has been fixed to be portable to systems like + Cygwin (bug present since macro was introduced in 2.0). + +** The following documented autotest macros are new: + AT_CHECK_EUNIT + +** The following m4sugar macros now quote their expansion: + m4_toupper m4_tolower + +** The following m4sugar macros are new: + m4_escape + +** The m4sugar macro m4_text_wrap now copes with embedded quoting without + requiring quadrigraphs. For uses like AC_ARG_VAR([a], [[b c]]), + this gives the intuitive behavior of "[b c]" in the output (2.63 + gave the output of "[b], [c]", and 2.64 encountered a failure). + +** The `$tmp' temporary directory used in config.status is documented for + public use now. + +** config.status now provides a --config option to produce the configuration. + +** Many cache variables used by Autoconf's macros are now documented. + +** Configure scripts work better on DJGPP by avoiding a bug present in + the DJGPP port of bash 2.04 in handling 'return' in a shell + function (regression introduced in 2.64). + +* Major changes in Autoconf 2.64 (2009-07-26) [stable] + Released by Eric Blake, based on git versions 2.63b.*. + +** Autoconf now requires GNU M4 1.4.6 or later. Earlier versions of M4 + have a bug in regular expression handling that interferes with some + of the speedups provided since Autoconf 2.63. GNU M4 1.4.13 or + later is recommended. + +** AS_IF and AS_CASE have been taught to avoid syntax errors even when + given arguments that expand to just whitespace. + +** The following documented autoconf macros are new: + AC_ERLANG_SUBST_ERTS_VER + +** The autoheader tool now understands m4 macro arguments passed to + AC_DEFINE and AC_DEFINE_UNQUOTED. + +** Ensure AT_CHECK can support commands that include a # given with + proper m4 quoting. For shell comments, this is a new feature; for + non-shell comments, this fixes a regression introduced in 2.63b. + Additionally, AT_CHECK correctly supplies shell escapes for + metacharacters occurring in m4 macro expansions within the expected + stdout and stderr parameters. + +** The macro AT_CHECK now understands the concept of hard failure. If + a test exits with an unexpected status 99, cleanup actions for the + test are inhibited and the test is treated as a failure regardless + of AT_XFAIL_IF. It also understands the new directives + ignore-nolog, stdout-nolog, and stderr-nolog. + +** The following documented autotest macros are new: + AT_CHECK_UNQUOTED AT_FAIL_IF AT_SKIP_IF + +** The following documented m4sugar macros are new: + m4_argn m4_copy_force m4_default_nblank m4_default_nblank_quoted + m4_ifblank m4_ifnblank m4_rename_force + +** The autoconf testsuite now exercises all Erlang macros. + +* Major changes in Autoconf 2.63b (2009-03-31) [beta] + Released by Eric Blake, based on git versions 2.63.*. + +** The manual is now shipped under the terms of the GNU FDL 1.3. + +** AC_REQUIRE now detects the case of an outer macro which first expands + then later indirectly requires the same inner macro. Previously, + this case led to silent out-of-order expansion (bug present since + 2.50); it now issues a syntax warning, and duplicates the expansion + of the inner macro to guarantee dependencies have been met. See + the manual for advice on how to refactor macros in order to avoid + the bug in earlier autoconf versions and avoid increased script + size in the current version. + +** AC_DEFUN_ONCE has improved semantics. Previously, a macro declared + with AC_DEFUN_ONCE warned on a second invocation; and out-of-order + expansion was still possible. Now, dependencies are guaranteed, + and subsequent invocations are a silent no-op. This makes + AC_DEFUN_ONCE an ideal macro for silencing AC_REQUIRE warnings. + +** The following macros are now defined with AC_DEFUN_ONCE. This means + a subtle change in semantics; previously, an AC_DEFUN macro could + expand one of these macros multiple times or surround the macro + inside shell conditional text to bypass the effects of these + macros, but now the macro will expand exactly once, and prior to + the start of any enclosing AC_DEFUN macro: + AC_CANONICAL_BUILD AC_CANONICAL_HOST AC_CANONICAL_TARGET + AC_HEADER_ASSERT AC_PROG_INSTALL AC_PROG_MKDIR_P + AC_USE_SYSTEM_EXTENSIONS + +** AC_LANG_ERLANG works once again (regression introduced in 2.61a). + +** AC_HEADER_ASSERT is fixed so that './configure --enable-assert' no + longer mistakenly disables assertions. + +** AC_INIT now takes an optional fifth parameter that can be used to + set AC_PACKAGE_URL, a URL for the package's home page; the URL is + used in `configure --help' and is also available via AC_DEFINE. + +** Autotest testsuites accept an option --jobs[=N] for parallel testing. + This feature is still in testing, and may not work on every + platform, help in improving it would be appreciated. + +** Autotest testsuites do not attempt to write startup error messages + to the log file before that is opened (regression introduced in 2.63). + +** Configure scripts now use shell functions. This feature leads to + smaller configure files and faster execution. + +** Present But Cannot Be Compiled: Autoconf will now proceed with + the compiler's result if a header is present but cannot be compiled. + The warning is still printed, and you should really fix it by + providing a fourth parameter to AC_CHECK_HEADER/AC_CHECK_HEADERS. + +** Autoreconf added aclocal to the set of programs affected by the + `autoreconf -I dir' option. + +** The following documented m4sugar macros are new: + m4_chomp m4_chomp_all m4_cleardivert m4_curry m4_default_quoted + m4_esyscmd_s m4_map_args m4_map_args_pair m4_map_args_sep + m4_map_args_w m4_set_map m4_set_map_sep m4_stack_foreach + m4_stack_foreach_lifo m4_stack_foreach_sep + m4_stack_foreach_sep_lifo + +** The following m4sugar macros are documented now, but in some cases + with slightly different semantics than what the previous + undocumented version had: + m4_copy m4_dumpdefs m4_rename m4_version_prereq + +** The m4sugar macro m4_expand has been taught to handle unterminated + comments and shell case statements. As a result, it is used + internally in more places, such as AC_DEFINE and AT_CHECK. Most + uses of AC_DEFINE and AT_CHECK should not behave any differently; + however, it may be necessary to add double-quoting around + unbalanced `(' where single-quoting used to be sufficient. + +** The following documented m4sh macros are new: + AS_INIT_GENERATED AS_LINENO_PREPARE AS_ME_PREPARE AS_SET_STATUS + AS_VAR_APPEND AS_VAR_ARITH AS_VAR_COPY + +** The following m4sh macros are documented now, but in some cases + with slightly different semantics than what the previous + undocumented version had: + AS_ECHO AS_ECHO_N AS_ESCAPE AS_EXIT AS_LITERAL_IF AS_UNSET + AS_VAR_IF AS_VAR_POPDEF AS_VAR_PUSHDEF AS_VAR_SET AS_VAR_SET_IF + AS_VAR_TEST_SET AS_VERSION_COMPARE + +** The m4sh macros AS_IF and AS_CASE can now be used in shell lists. + The responsibility for supplying a trailing newline now belongs to + the call site, but since most users did not add dnl, this generally + results in fewer empty lines in configure. + + +* Major changes in Autoconf 2.63 (2008-09-09) [stable] + Released by Eric Blake, based on git versions 2.62.*. + +** AC_C_BIGENDIAN does not mistakenly report "universal" for some + bigendian hosts, a regression introduced with universal binary + support in 2.62. + +** AC_PATH_X now includes /lib64 and /usr/lib64 in its list of default + library directories. + +** AC_USE_SYSTEM_EXTENSIONS no longer conflicts with an external + AC_DEFINE([__EXTENSIONS__]). This fixes a regression introduced in + 2.62 when using macros such as AC_AIX that were made obsolete in + favor of the more portable AC_USE_SYSTEM_EXTENSIONS. + +** AC_CHECK_TARGET_TOOLS is usable in the non-cross-compile case. + +** Newly obsolete macros + The following macro has been marked obsolete, since current porting + targets can safely assume C89 semantics that signal handlers return + void. We have no current plans to remove the macro. + + AC_TYPE_SIGNAL + +** The macros m4_map and m4_map_sep now ignore any list elements + consisting of just empty quotes, and m4_map_sep now expands its + separator. This fixes a regression in 2.62 when these macros were + first documented, for the sake of clients expecting the semantics + that these macros had prior to that time. The new macros m4_mapall + and m4_mapall_sep, along with extra quoting of the separator, can + be used to get the semantics that m4_map_sep had in 2.62. + +** Clients of m4_expand, such as AS_HELP_STRING and AT_SETUP, can now + handle properly quoted but otherwise unbalanced parentheses (for + some macros, this fixes a regression in 2.62). + +** Two new quadrigraphs have been introduced: @{:@ for (, and @:}@ for ), + allowing the output of unbalanced parentheses in more contexts. + +** The following m4sugar macros are new: + m4_cleardivert m4_joinall m4_mapall m4_mapall_sep m4_reverse + m4_set_add m4_set_add_all m4_set_contains m4_set_contents + m4_set_delete m4_set_difference m4_set_dump m4_set_empty + m4_set_foreach m4_set_intersection m4_set_list m4_set_listc + m4_set_remove m4_set_size m4_set_union + +** The following m4sugar macros now accept multiple arguments, as is the + case with underlying m4: + m4_defn m4_popdef m4_undefine + +** The following m4sugar macros now guarantee linear scaling; they + previously had linear scaling with m4 1.6 but quadratic scaling + when using m4 1.4.x. All macros built on top of these also gain + the scaling improvements. + m4_bmatch m4_bpatsubsts m4_case m4_cond m4_do m4_dquote_elt + m4_foreach m4_join m4_list_cmp m4_map m4_map_sep m4_max + m4_min m4_shiftn + +** AT_KEYWORDS once again performs expansion on its argument, such that + AT_KEYWORDS([m4_if([$1], [], [default])]) no longer complains about + the possibly unexpanded m4_if [regression introduced in 2.62]. + +** Config header templates `#undef UNDEFINED /* comment */' do not lead to + nested comments any more; regression introduced in 2.62. + + +* Major changes in Autoconf 2.62 (2008-04-05) [stable] + Released by Eric Blake, based on git versions 2.61a.*. + +** Many optimizations have been applied to make overall execution faster. + +** Autotest now makes use of shell functions. + +** config.status now uses awk instead of sed also for config headers. + + - As a side effect, AC_DEFINE and AC_DEFINE_UNQUOTED now handle multi-line + values, i.e., backslash-newline combinations are handled correctly. + Further, for config headers, the total size of values is not limited by + the POSIX length limit of text lines any more, only each single line. + +** New config variable `top_build_prefix'. + +** New Autoconf macros: + AC_AUTOCONF_VERSION AC_OPENMP AC_PATH_PROGS_FEATURE_CHECK + +** AC_C_BIGENDIAN now supports universal binaries a la Mac OS X. + +** AC_C_RESTRICT now prefers to #define 'restrict' to a variant spelling + like '__restrict' if the variant spelling is available, as this is + more likely to work when mixing C and C++ code. + +** AC_CHECK_ALIGNOF's type argument T is now documented better: it must + be a string of tokens such that "T y;" is a valid member declaration + in a struct. + +** AC_CHECK_SIZEOF now accepts objects as well as types: the general rule + is that sizeof (X) works, then AC_CHECK_SIZEOF (X) should work. + +** AC_CHECK_TYPE and AC_CHECK_TYPES now work on any C type-name; formerly, + they did not work for function types. In C++, they now work on any + type-id that can be the operand of sizeof; this is similar to C, + except it excludes anonymous struct and union types. Formerly, + some (but not all) C++ types involving anonymous struct and union + were accepted, though this was not documented. + +** AC_CONFIG_LINKS now prefers to link against files in the build tree + if found, and it works to link against a file of the same name in + the source tree, even if both trees coincide. + +** AC_INIT no longer alters $@; regression introduced in 2.60. + +** AC_USE_SYSTEM_EXTENSIONS now defines _ALL_SOURCE for Interix platforms. + +** AS_HELP_STRING no longer underquotes its first argument; it also handles + the case where the first argument contains single-quoted commas. + For example, "AS_HELP_STRING([-a, [--arg[=foo]]], [bar])" produces: + " -a, --arg[=foo] bar" + Additionally, the macro now takes two additional arguments, + indent-column and wrap-column; these should not normally be needed, + but can be used to fine-tune how the output text is wrapped. + +** AC_PROG_INSTALL now requires an install program that can install multiple + files into a target directory. + +** The command 'autoconf -' now correctly processes a file from stdin. + +** 'autoreconf -m' now honors $MAKE. + +** For all of the directory arguments for 'configure', such as '--prefix' + or '--bindir', trailing slashes are stripped. As an example, if + tab completion in the user's shell appends trailing slashes, the + command './configure --prefix=/usr/' will still result in an + expanded libdir value of /usr/lib, not /usr//lib. + +** `configure --help=recursive' now works in read-only trees and from + unconfigured build trees. + +** If precious variables differ only in whitespace, then the cache consistency + check warns instead of fails, and reuses the old value. + +** AT_BANNER is now documented. + +** AT_SETUP now handles macro expansions properly when calculating line + length. + +** Autotest now determines $srcdir correctly. + +** Testsuites built by autotest now accept a -C/--directory=DIR option + to adjust the working directory prior to creating files. + +** Autoconf now requires GNU M4 1.4.5 or later. Earlier versions of M4 have + a bug in macro tracing that interferes with the interaction between + Autoconf and Automake. GNU M4 1.4.11 or later is recommended. The + configure search for a working M4 is improved. + +** For portability with the eventual M4 2.0, macros should no longer use + anything larger than $9 to refer to arguments. + +** Documentation for m4sugar is improved. + + - The following macros were previously available as undocumented + interfaces; the macros are now documented as stable interfaces. + + __oline__ m4_assert m4_bmatch m4_bpatsubsts m4_car m4_case + m4_cdr m4_default m4_divert_once m4_divert_pop m4_divert_push + m4_divert_text m4_do m4_errprintn m4_fatal m4_flatten + m4_ifndef m4_ifset m4_ifval m4_ifvaln m4_location + m4_n m4_shiftn m4_strip m4_warn + + - The following macros were previously available as undocumented + interfaces, but had bug fixes or semantic changes as part of this + release. Packages that relied on the undocumented behavior + should be analyzed to make sure they will still work with the + new documented behavior. + + m4_cmp m4_list_cmp m4_join m4_map m4_map_sep m4_sign + m4_text_box m4_text_wrap m4_version_compare + + - The m4_wrap macro used to have unspecified order, but now + guarantees FIFO order. m4_wrap_lifo was added to guarantee LIFO + order. + + - Packages using the undocumented m4sugar macro m4_PACKAGE_VERSION + should consider using the new AC_AUTOCONF_VERSION instead. + + - m4sugar macros that are not documented in the manual are still + deemed experimental, and should not be used outside of Autoconf. + +** The m4sugar macros m4_append and m4_append_uniq, first documented in + 2.60, have been fixed to treat both the string and the separator + arguments consistently with regards to quoting. Prior to this fix, + m4_append_uniq could mistakenly duplicate entries if the expansion + of the separator resulted in a different string (for example, if it + contained quotes, a comma, or a macro name). However, it means + that programs previously using + m4_append([name], [string], [[, ]]) + are now using a four-character separator instead of the intended + comma and space. If you need portability to earlier versions of + Autoconf, you can insert the following snippet after AC_INIT but + before any other macro expansions, to enforce the new semantics: + m4_pushdef([m4_append], [m4_define([$1], + m4_ifdef([$1], [m4_defn([$1])[$3]])[$2])]) + Additionally, m4_append_uniq now takes optional parameters that can + be used to take action depending on whether anything was appended, + and warns if a non-empty separator occurs within the string being + appended, since that can lead to duplicates. + +** The following m4sugar macros are new: + m4_append_uniq_w m4_apply m4_combine m4_cond m4_count + m4_dquote_elt m4_echo m4_expand m4_ignore m4_make_list m4_max + m4_min m4_newline m4_shift2 m4_shift3 m4_unquote m4_wrap_lifo + +** Warnings are now generated by default when an installer invokes + 'configure' with an unknown --enable-* or --with-* option. + These warnings can be disabled with the new AC_DISABLE_OPTION_CHECKING + macro, or by invoking 'configure' with --disable-option-checking. + +** Existing obsolete macros + The documentation for the following macros is adjusted to make it + more clear that they have previously been marked obsolete, as their + functionality can be accomplished by other macros. We have no + current plans to remove them from Autoconf. + + AC_ENABLE AC_STRUCT_ST_BLKSIZE AC_STRUCT_ST_RDEV AC_WITH + +** Newly obsolete macros + The following macros have been marked obsolete, as they only + perform a subset of AC_USE_SYSTEM_EXTENSIONS. We have no current + plans to remove them. + + AC_AIX AC_GNU_SOURCE AC_ISC_POSIX AC_MINIX + +** AC_C_LONG_DOUBLE is obsolescent. + The documentation now says that AC_C_LONG_DOUBLE is obsolescent: it + tests for problems that are so old that it is no longer of + practical importance on current systems. New programs need not use + AC_C_LONG_DOUBLE. We have no current plans to remove it. + +** AC_DIAGNOSE, AC_WARNING, and AC_FATAL are obsolescent. + The documentation now favors the use of M4sugar macros m4_warn and + m4_fatal, since the naming makes it more obvious that the + diagnostics are associated with M4 expansion (ie. when running + `autoconf'), and offers less confusion with the AC_MSG_ERROR, + AC_MSG_FAILURE, and AC_MSG_WARN macros which manage diagnostics + when running `configure'. We have no current plans to remove these + macros. + + +* Major changes in Autoconf 2.61a (2006-12-11) + +** AC_FUNC_FSEEKO was broken in 2.61; it didn't make fseeko and ftello visible + on many platforms. This has been fixed. + +** AC_FUNC_SETVBUF_REVERSED is now obsolete. It is still defined for backward + compatibility but it does nothing. The macro was already + obsolescent, as the last systems to have the problem were those + based on SVR2, which became obsolete in 1987. The macro had bugs + on some modern systems and could no longer be maintained reliably + due to lack of ancient systems to test it on. + +** config.status now uses awk instead of sed for most substitutions, for speed. + + - As a side effect multi-line values of substituted variables no + longer have a small limit in total size, though for portability + each line should not exceed the POSIX length limit for text lines. + + - It is now documented that Makefile.in should not contain + overlapping variable occurrences, e.g., @VAR1@VAR2@. + Autoconf's behavior was always iffy in such cases, and the + awk implementation has changed the behavior. + +** Many uses of 'echo' have been rewritten so that Autoconf-generated + scripts have fewer problems with strings or file names containing + embedded special characters such as backslash or leading "-". This + was implemented by using `printf '%s\n' "$foo"' instead of `echo + "$foo"' when printf works. Due to the implementation technique + used, Autoconf-generated scripts now run considerably more slowly + on ancient implementations lacking printf. However, this should + not be a problem, since Autoconf-generated scripts in practice + invariably find a more-modern shell these days. + + +* Major changes in Autoconf 2.61 (2006-11-17) + +** New macros AC_C_FLEXIBLE_ARRAY_MEMBER, AC_C_VARARRAYS. + +** AC_ARG_ENABLE and AC_ARG_WITH now allow '.' in feature and package names. + + +* Major changes in Autoconf 2.60b (2006-10-22) + +** BIN_SH + Autoconf-generated shell scripts no longer export BIN_SH, due to + configuration hassles with this. Installers who need BIN_SH in + their environment should set it before invoking 'configure' and + 'make'. As far as we know, this affects only Unixware installations. + +** Obsolescent macros + The documentation now says that the following macros are obsolescent, + as they are superseded by Gnulib: + + AC_FUNC_FNMATCH AC_FUNC_FNMATCH_GNU AC_FUNC_GETLOADVG AC_REPLACE_FNMATCH + + New programs should use the Gnulib counterparts of these macros. + We have no current plans to remove them from Autoconf. + +** AC_COMPUTE_INT no longer caches or reports results. + +** AC_CHECK_DECL now also works with aggregate objects. + +** AC_USE_SYSTEM_EXTENSIONS now defines _TANDEM_SOURCE for NonStop platforms. + +** GNU M4 1.4.7 or later is now recommended. + +** m4_mkstemp + New M4sugar macro, which is more secure than the POSIX M4 maketemp. + +** m4_maketemp + Now an alias for m4_mkstemp. + +* Major changes in Autoconf 2.60a (2006-08-25) + +** GNU M4 1.4.6 or later is now recommended. + +** The check for C99 now tests for varargs macros, as documented. + It also tests that the preprocessor supports 64-bit integers. + +** Autoconf now uses constructs like "#ifdef HAVE_STDLIB_H" rather than + "#if HAVE_STDLIB_H", so that it now works with "gcc -Wundef -Werror". + +** The functionality of the undocumented _AC_COMPUTE_INT is now provided + by a public and documented macro, AC_COMPUTE_INT. The parameters to the + two macros are different, so autoupdate will not change the old private name + to the new one. _AC_COMPUTE_INT may be removed in a future release. + +** AC_TYPE_LONG_LONG_INT and AC_TYPE_UNSIGNED_LONG_LONG_INT now require + that long long types be at least 64 bits wide, as C99 and tradition + requires. Formerly, they accepted implementations of any width. + + +* Major changes in Autoconf 2.60 + + Released 2006-06-23, by Ralf Wildenhues. + +** Autoconf no longer depends on whether m4wrap is FIFO (as Posix requires) + or LIFO (as in GNU M4 1.4.x). GNU M4 2.0 is expected to conform to Posix + here, so m4wrap/m4_wrap users should no longer depend on LIFO behavior. + +** Provide a way to turn off warnings about the changed directory variables. + +* Major changes in Autoconf 2.59d + + Released 2006-06-05, by Ralf Wildenhues. + +** GNU make now recommended for VPATH builds + INSTALL now suggests VPATH builds (e.g., "sh ../srcdir/configure") + only if you use GNU make. In practice, other 'make' implementations + have too many subtle incompatibilities in their support for VPATH. + Many packages (including Autoconf itself) are portable to other + 'make' implementations, but some packages are not, and recommending + GNU make keeps the installation instructions simpler. + +** Even more safety checks for the new Directory variables: + Warn about suspicious `${datarootdir}' found in config files output. + +** AC_TRY_COMMAND, AC_TRY_EVAL, ac_config_guess, ac_config_sub, ac_configure + These never-documented macros and variables have been marked with + comments saying that they may be removed in a future release, + because their use can lead to unintended code being executed. + If you need functionality that only these macros or variables + currently supply, please write bug-autoconf@gnu.org. + +** AC_SUBST, AC_DEFINE + Literal arguments to these are passed to m4_pattern_allow now. + +** AC_PROG_CC_STDC + Passing 'ac_cv_prog_cc_stdc=no' to 'configure' now sets ac_cv_prog_cc_c99 + and ac_cv_prog_cc_c89 to 'no' as well, for backward compatibility with + obsolete K&R tests in the Automake test suite. + +** AC_PROG_CXX_C_O + New macro. + +** AC_PROG_MKDIR_P + New macro. + +** AS_MKDIR_P + Now more robust with special characters in file names, or when + multiple processes create the same directory at the same time. + +** Obsolescent macros + The documentation now says that the following macros are obsolescent: + they test for problems that are so old that they are no longer of + practical importance on current systems. + + AC_C_BACKSLASH_A AC_FUNC_MEMCMP AC_HEADER_DIRENT + AC_C_CONST AC_FUNC_SELECT_ARGTYPES AC_HEADER_STAT + AC_C_PROTOTYPES AC_FUNC_SETPGRP AC_HEADER_STDC + AC_C_STRINGIZE AC_FUNC_SETVBUF_REVERSED AC_HEADER_SYS_WAIT + AC_C_VOLATILE AC_FUNC_STAT AC_HEADER_TIME + AC_FUNC_CLOSEDIR_VOID AC_FUNC_STRFTIME AC_ISC_POSIX + AC_FUNC_GETPGRP AC_FUNC_UTIME_NULL AC_PROG_GCC_TRADITIONAL + AC_FUNC_LSTAT AC_FUNC_VPRINTF AC_STRUCT_TM + + New programs need not use these macros. We have no current plans to + remove them. + +** autoreconf + For compatibility with future Libtool 2.0, autoreconf will invoke + libtoolize with the option `--ltdl' now, if LT_CONFIG_LTDL_DIR is + used. + +* Major changes in Autoconf 2.59c + + Released 2006-04-12, by Ralf Wildenhues. + +** The configure command now redirects standard input from /dev/null, + to help avoid problems with subsidiary commands that might mistakenly + read standard input. AS_ORIGINAL_STDIN_FD points to the original + standard input before this redirection, if you really want configure to + read from standard input. + +** Directory variables adjusted to recent changes in the GNU Coding Standards. + The following directory variables are new: + + datarootdir read-only architecture-independent data root [PREFIX/share] + localedir locale-specific message catalogs [DATAROOTDIR/locale] + docdir documentation root [DATAROOTDIR/doc/PACKAGE] + htmldir html documentation [DOCDIR] + dvidir dvi documentation [DOCDIR] + pdfdir pdf documentation [DOCDIR] + psdir ps documentation [DOCDIR] + + The following variables have new default values: + + datadir read-only architecture-independent data [DATAROOTDIR] + infodir info documentation [DATAROOTDIR/info] + mandir man documentation [DATAROOTDIR/man] + + This means that if you use any of `@datadir@', `@infodir@', or + `@mandir@' in a file, you will have to ensure `${datarootdir}' is + defined in this file. As a temporary measure, if any of those are + found but no mention of `datarootdir', the substitutions will be + replaced with values that do not contain `${datarootdir}', and a + warning will be issued. + +** @top_builddir@ is now a dir name: it is always nonempty and doesn't have + a trailing slash. Similar change will be made to ac_top_builddir in a + future release; the old style value, which matches (../)*, is (and will + continue to be) available as ac_top_build_prefix. + +** AC_C_TYPEOF + New macro to check for support of 'typeof' syntax a la GNU C. + +** AC_CHECK_DECLS_ONCE, AC_CHECK_FUNCS_ONCE, AC_CHECK_HEADERS_ONCE + New "once-only" variants of commonly-used macros, to make 'configure' + smaller and faster in common cases. + +** AC_FUNC_STRTOLD + New macro to check for strtold with C99 semantics. + +** AC_HEADER_ASSERT + New macro that lets builder disable assertions at 'configure'-time. + +** AC_PATH_X + Now checks for X11/Xlib.h and XrmInitialize (X proper) rather than + X11/Intrinsic.h and XtMalloc (Xt). + +** AC_PRESERVE_HELP_ORDER + New macro that causes `configure' to display help strings for AC_ARG_ENABLE + and AC_ARG_WITH arguments in one region, in the order defined. The default + behavior is to group options of each classes separately. + +** AC_PROG_CC, AC_PROG_CXX + No longer automatically arrange to declare the 'exit' function of C, + when a C++ compiler is used. Standard Autoconf macros no longer use + 'exit', so this is no longer an issue for them. If you use C++, and + want to call 'exit', you'll have to arrange for its declaration + yourself. But we now suggest you return from 'main' instead. + +** AC_PROG_CC_C89, AC_PROG_CC_C99 + New macros for ISO C99 support. AC_PROG_CC_C89 and AC_PROG_CC_C99 + check for ANSI C89 and ISO C99 support respectively. + +** AC_PROG_CC_STDC + Has been unobsoleted, and will check if the compiler supports ISO + C99, falling back to ANSI C89 if not. ac_cv_prog_cc_stdc is + retained for backwards compatibility, assuming the value of + ac_cv_prog_cc_c99 or ac_cv_prog_cc_c89 (whichever is valid, in + that order). + +** AC_STRUCT_DIRENT_D_INO, AC_STRUCT_DIRENT_D_TYPE + New macros for checking commonly-used members of struct dirent. + +** AC_SUBST + The substituted value can now contain newlines. + +** AC_SUBST_FILE + The substitution now occurs only when @variable@ is on a line by itself, + optionally surrounded by spaces and tabs. The whole line is replaced. + +** AC_TYPE_LONG_DOUBLE, AC_TYPE_LONG_DOUBLE_WIDER + New macros to check for long double, and whether it is wider than double. + The old macro AC_C_TYPE_LONG_DOUBLE has been marked as obsolete; + applications should switch to the new macro. + +** AC_TYPE_INT8_T, AC_TYPE_INT16_T, AC_TYPE_INT32_T, AC_TYPE_INT64_T, + AC_TYPE_INTMAX_T, AC_TYPE_INTPTR_T, AC_TYPE_LONG_LONG_INT, AC_TYPE_SSIZE_T, + AC_TYPE_UINT8_T, AC_TYPE_UINT16_T, AC_TYPE_UINT32_T, AC_TYPE_UINT64_T, + AC_TYPE_UINTMAX_T, AC_TYPE_UINTPTR_T, AC_TYPE_UNSIGNED_LONG_LONG_INT + New macros to check for C99 and POSIX types. + +** AC_USE_SYSTEM_EXTENSIONS + New macro to enable extensions to Posix. + +** AH_HEADER + New macro which is defined to the name of the first declared config header + or undefined if no config headers have been declared yet. + +** AS_HELP_STRING + The macro correctly handles quadrigraphs now. + +** AS_BOURNE_COMPATIBLE, AS_SHELL_SANITIZE, AS_CASE + These macros are new or published now. + +** AT_COPYRIGHT + New macro for copyright notices in testsuite files. + +** ALLOCA, LIBOBJS, LTLIBOBJS + Object names added to these variables are now prefixed with `${LIBOBJDIR}', + as in `${LIBOBJDIR}alloca.o'. LIBOBJDIR is meant to be defined from + `Makefile.in' in case the object files lie in a different directory. + The LIBOBJDIR feature is experimental. + +** autoreconf + Supports --no-recursive now. + +** New macros to support Erlang/OTP. + New macros for configuring paths to Erlang tools and libraries: + AC_ERLANG_PATH_ERLC, AC_ERLANG_NEED_ERLC, AC_ERLANG_PATH_ERL, + AC_ERLANG_NEED_ERL, AC_ERLANG_CHECK_LIB, AC_ERLANG_SUBST_ROOT_DIR, + AC_ERLANG_SUBST_LIB_DIR. + + New macros for configuring installation of Erlang libraries: + AC_ERLANG_SUBST_INSTALL_LIB_DIR, AC_ERLANG_SUBST_INSTALL_LIB_SUBDIR. + +** The manual now mentions Gnulib more prominently. + +** New macros to support Objective C. + AC_PROG_OBJC, AC_PROG_OBJCPP. + +* Major changes in Autoconf 2.59b + + Released 2004-08-20, by Paul Eggert. + +** AC_CHECK_ALIGNOF + New macro that computes the default alignment of a type. + +** AC_CHECK_TOOL, AC_PATH_TOOL, AC_CHECK_TOOLS + When cross-compiling, these macros will give a warning if the tool + is not prefixed. In the future, unprefixed cross tools will not + be detected; please consult the info documentation for information + about the reason of this change. + +** AC_CHECK_TARGET_TOOL, AC_PATH_TARGET_TOOL, AC_CHECK_TARGET_TOOLS + New macros that detect programs whose name is prefixed with the + target type, if the build type and target type are different. + +** AC_REQUIRE_AUX_FILE + New trace macro that declares expected auxiliary files. + +** AC_PROG_GREP + New macro that tests for a grep program that accepts as a long a line + as possible. + +** AC_PROG_EGREP, AC_PROG_FGREP + These macros now require AC_PROG_GREP, and try EGREP="$GREP -E" and + FGREP="$GREP -F" respectively if possible, or else run a path search for + a program that accepts as long a line as possible. + +** AC_PROG_SED + New macro that tests for a sed program that truncates as few characters + as possible. + +* Major changes in Autoconf 2.59 + + Released 2003-11-04, by Akim Demaille + +** ac_abs_builddir etc. + Absolute file names were actually relative in 2.58. + +* Major changes in Autoconf 2.58 + + Released 2003-11-04, by Akim Demaille + +** core.* + core.* files are no longer removed, as they may be valid user files. + +** autoreconf and auxiliary directory + Autoreconf creates the auxiliary directory if needed. This is + especially useful for initial "bootstrapping" of fresh CVS checkouts. + +** AC_CONFIG_MACRO_DIR + Use this macro to declare the directory for local M4 macros for aclocal. + +** AC_LIBOBJS + No longer includes twice the same file in LIBOBJS if invoked + multiple times. + +** AC_CONFIG_COMMANDS + The directory for its first argument is automatically created. For + instance, with + + AC_CONFIG_COMMANDS([src/modules.hh], [...]) + + $top_builddir/src/ is created if needed. + +** Autotest and local.at + The optional file local.at is always included in Autotest test suites. + +** Warnings + The warnings are always issued, including with cached runs. + This became a significant problem since aclocal and automake can + run autoconf behind the scene. + +** autoheader warnings + The warnings of autoheader can be turned off, using --warning. + For instance, -Wno-obsolete disables the complaints about acconfig.h + and other deprecated constructs. + +** New macros + AC_C_RESTRICT, AC_INCLUDES_DEFAULT, AC_LANG_ASSERT, AC_LANG_WERROR, + AS_SET_CATFILE. + +** AC_DECL_SYS_SIGLIST + Works again. + +** AC_FUNC_MKTIME + Now checks that mktime is the inverse of localtime. + +** Improve DJGPP portability + The Autoconf tools and configure behave better under DJGPP. + +** Present But Cannot Be Compiled + New FAQ section dedicated to the mystic + + configure: WARNING: pi.h: present but cannot be compiled + configure: WARNING: pi.h: check for missing prerequisite headers? + configure: WARNING: pi.h: proceeding with the preprocessor's result + messages. + +** Concurrent executions of autom4te + autom4te now locks its internal files, which enables concurrent + executions of autom4te, likely to happen if automake, autoconf, + autoheader etc. are run simultaneously. + +** Libtool + Use of Libtool 1.5 and higher is encouraged. Compatibility with + Libtool pre-1.4 is not checked. + +** Autotest + Testsuites no longer rerun failed tests in verbose mode; instead, + failures are logged while the test is run. + + In addition, expected failures can be marked as such. + +* Major changes in Autoconf 2.57 + + Released 2002-12-03 by Paul Eggert. + +Bug fixes for problems with AIX linker, with freestanding C compilers, +with GNU M4 limitations, and with obsolete copies of GNU documents. + +The Free Documentation License has been upgraded from 1.1 to 1.2. + +* Major changes in Autoconf 2.56 + + Released 2002-11-15 by Akim Demaille. + +One packaging problem fixed (config/install-sh was not executable). + +* Major changes in Autoconf 2.55 + + Released 2002-11-14 by Akim Demaille. + +Release tips: + + Have your configure.ac checked by autoscan ("autoscan"). + Try the warning options ("autoreconf -fv -Wall"). + +** Documentation + +- AC_CHECK_HEADER, AC_CHECK_HEADERS + More information on proper use. + +- Writing Test Programs + + This sections explains how to write good test sources to use with + AC_COMPILE_IFELSE etc. It documents AC_LANG_PROGRAM and so forth. + +- AC_FOO_IFELSE vs. AC_TRY_FOO + + Explains why Autoconf moves from AC_TRY_COMPILE etc. to + AC_COMPILE_IFELSE and AC_LANG_PROGRAM etc. + +** autoreconf + +- Is more robust to different Gettext installations. + +- Produces messages (when --verbose) to be understood by Emacs' + compile mode. + +- Supports -W/--warnings. + +- -m/--make + Once the GNU Build System reinstalled, run `./config.status + --recheck && ./config.status && make' if possible. + +** autom4te + +- Supports --cache, and --no-cache. + +- ~/.autom4te.cfg makes it possible to disable the caching mechanism + (autom4te.cache). See `Customizing autom4te' in the documentation. + +** config.status + Supports --quiet. + +** Obsolete options + + Support for the obsoleted options -m, --macrodir, -l, --localdir is + dropped in favor of the safer --include/--prepend-include scheme. + +** Macros + +- New macros + AC_COMPILER_IFELSE, AC_FUNC_MBRTOWC, AC_HEADER_STDBOOL, + AC_LANG_CONFTEST, AC_LANG_SOURCE, AC_LANG_PROGRAM, AC_LANG_CALL, + AC_LANG_FUNC_TRY_LINK, AC_MSG_FAILURE, AC_PREPROC_IFELSE. + +- Obsoleted + Obsoleted macros are kept for Autoconf backward compatibility, but + should be avoided in configure.ac. Running autoupdate is advised. + AC_DECL_SYS_SIGLIST. + +- AC_DEFINE/AC_DEFINE_UNQUOTED + + We have to stop using the old compatibility scheme --that tried to + avoid useless backslashes-- because Libtool 1.4.3 contains a + + AC_DEFINE([error_t], [int], + [Define to a type to use for \`error_t' if it is not + otherwise available.]) + + We have to quote the single quotes and backslashes with \. The old + compatibility scheme saw that ` was backslashed, and therefore did + not quote the single quote... Failure. Hence, Autoconf 2.54 is not + compatible with Libtool. Autoconf 2.55 is, but in some cases might + produce more \ than wanted. + + Please, note that in the future the same problem will happen with + AC_MSG_*: use `autoreconf -f -Wall'. + +** Bug Fixes + +- Portability of the Autoconf package to Solaris. + +- Spurious warnings caused by config.status. + This bug is benign, but painful: on some systems (typically + FreeBSD), warnings such as: + + config.status: creating Makefile + mv: Makefile: set owner/group (was: 1357/0): Operation not permitted + + could be issued. This is fixed. + +- Parallel Builds + Simultaneous executions of config.status are possible again. + +- Precious variables accumulation + + config.status could stack several copies of the precious variables + assignments. + + +** Plans for later versions + +- ./configure + + The compatibility hooks with the old scheme will be completely + removed. Please, advice/use `--build', `--host', and `--target' + only. + +- AC_CHECK_HEADER, AC_CHECK_HEADERS + + The tests will be stricter, please make sure your invocations are + valid. + +- shell functions + + Shell functions will gradually be introduced, probably starting with + Autotest. If you know machines which are in use that you suspect + *not* to support shell functions, please run the test suite of + Autoconf 2.55 on it, and report the results to + bug-autoconf@gnu.org. + +- AC_MSG_* + + Special characters in AC_MSG_* need not be quoted. Currently, + Autoconf has heuristics to decide when a string is escaped, or has + to be escaped. This scheme is fragile, and will be removed; the + only risk is uglified messages. Please, run `autoreconf -f -Wall' + to find occurrences that will be affected. + +* Major changes in Autoconf 2.54 + + Released 2002-09-13 by Akim Demaille. + +** Executables + +- autoreconf no longer changes the version of the gettext/po/intl + support files. It now adds the files the correspond to the + AM_GNU_GETTEXT_VERSION declared in configure.ac. + + Warning: It now relies on the 'autopoint' program, which is part + of GNU gettext 0.11.4 and newer. + + Please note that you need to have a GNU gettext version that + corresponds at least to the AM_GNU_GETTEXT_VERSION declared + in configure.ac. You can upgrade to newer GNU gettext versions, + though, without needing to change configure.ac. + +- The -I DIR or --include=DIR option now appends DIR to the include path + instead of prepending; this is for consistency with other GNU tools. + The new -B DIR or --prepend-include=DIR option has the old behavior. + +** Macros + +- AC_OUTPUT + Now handles all the gory details about LIBOBJS and LTLIBOBJS. + Please, remove lines such as + + # This is necessary so that .o files in LIBOBJS are also + # built via the ANSI2KNR-filtering rules. + LIBOBJS=`echo $LIBOBJS|sed 's/\.o /\$U.o /g;s/\.o$/\$U.o/'` + + and read the `AC_LIBOBJ vs LIBOBJS' section. Do not define U in + your Makefiles either. + +- AC_CONFIG_LINKS now makes copies if it can't make links. + +- AC_FUNC_FNMATCH now tests only for POSIX compatibility, reverting to + Autoconf 2.13 behavior. The new macro AC_FUNC_FNMATCH_GNU also + tests for GNU extensions to fnmatch, and replaces fnmatch if needed. + +- AC_FUNC_SETVBUF_REVERSED no longer fails when cross-compiling. + +- AC_PROG_CC_STDC is integrated into AC_PROG_CC. + +- AC_PROG_F77 default search no longer includes cf77 and cfg77. + +- New macros + + AC_C_BACKSLASH_A, AC_CONFIG_LIBOBJ_DIR, AC_GNU_SOURCE, + AC_PROG_EGREP, AC_PROG_FGREP, AC_REPLACE_FNMATCH, + AC_FUNC_FNMATCH_GNU, AC_FUNC_REALLOC, AC_TYPE_MBSTATE_T. + +- AC_FUNC_GETLOADAVG + looks for getloadavg.c in the CONFIG_LIBOBJ_DIR. + +- AC_FUNC_MALLOC + Now defines HAVE_MALLOC to 0 if `malloc' does not work, and asks + for an AC_LIBOBJ replacement. + +** Bug fixes + +- Spurious complaints from `m4_bmatch' about invalid regular + expressions are suppressed. + +- Empty top_builddirs are properly handled. + +- AC_CHECK_MEMBER works correctly when the member is an aggregate. + +- AC_PATH_PROG + Now colon in the optional path arguments are properly handled. + +** Improved portability + +- Both Autoconf the package, and the scripts it produces, should run + more reliably with Zsh. Bear in mind it is the default Bourne shell + on Darwin. + +- Autoconf and the scripts it produces no longer assume the existence of + the obsolescent commands egrep and fgrep. + +** Documentation + +- Limitations of Make + More of them. + +- GNATS + The GNATS base moved to + https://bugs.gnu.org/cgi-bin/gnatsweb.pl?database=autoconf + (It is no longer available, though.) + +** Misc. + +- config.log + Now contains the list of output variables and files (AC_SUBST, + AC_SUBST_FILES). + +* Major changes in Autoconf 2.53 + + Released 2002-03-08 by Akim Demaille. + +** Requirements + + Perl 5.005_03 or later is required: autom4te is written in Perl and is + needed by autoconf. autoheader, autoreconf, ifnames, and autoscan are + rewritten in Perl. + +** Documentation + +- AC_INIT + Argument requirements, output variables, defined macros. +- M4sugar, M4sh, Autotest + First sketch. +- Double quoting macros + AC_TRY_CPP, AC_TRY_COMPILE, AC_TRY_LINK and AC_TRY_RUN. +- Licensing + The Autoconf manual is now distributed under the terms of the GNU FDL. +- Section `Hosts and Cross-Compilation' + Explains the rationale for the 2.5x changes in the cross-compilation + chain, and in the relationships between build, host, and target + types. + Emphasizes that `cross-compilation' == `--host is given'. + If you are working on compilers etc., be sure to read this section. +- Section `AC_LIBOBJ vs. LIBOBJS' + Explains why assigning LIBOBJS directly is now an error. + Details how to update the code. + +** configure + +- $LINENO + Now used instead of hard coded line numbers. + This eases the comparison of `configure's, and diminishes the + pressure over control version archives. + Automatic replacement for shells that don't support this feature. +- New output variables + @builddir@, @top_builddir@, @abs_srcdir@, @abs_top_srcdir@, @abs_builddir@, + @abs_top_builddir@. + +** Emacs + + Autoconf and Autotest modes are provided. + +** Executables + +- autom4te + New, used by the Autoconf suite to cache and speed up most processing. +- --force, -f + Supported by autom4te, autoconf and autoheader. +- --include, -I + Replaces --autoconf-dir and --localdir in autoconf, autoheader, + autoupdate, and autoreconf. +- autoreconf + No longer passes --cygnus, --foreign, --gnits, --gnu, --include-deps: + automake options are to be given via AUTOMAKE_OPTIONS. +- autoreconf + Runs gettextize and libtoolize when appropriate. +- autoreconf + --m4dir is no longer supported. +- autoreconf + Now runs only in the specified directories, defaulting to `.', + but understands AC_CONFIG_SUBDIRS for dependent directories. + Before, it used to run on all the `configure.ac' found in the + current tree. + Independent packages are properly updated. + +** Bug fixes + +- The top level $prefix is propagated to the AC_CONFIG_SUBDIRS configures. +- AC_TRY_RUN + Under the user pressure, $? is finally available. Probably a mistake. +- AC_F77_LIBRARY_LDFLAGS now supports the HP/UX f90 compiler. +- Precious variables accumulation + config.status could stack several copies of the precious variables + assignments. +- AC_PATH_PROG and family. + Works properly when given a literal path. +- AC_FUNC_SETPGRP + Somewhere since 2.13, the result had been reversed. + +** C Macros + +- AC_C_BIGENDIAN supports the cross-compiling case. +- AC_C_BIGENDIAN accepts ACTION-IF-TRUE, ACTION-IF-FALSE, and + ACTION-IF-UNKNOWN arguments. All are optional, and the default + for ACTION-IF-TRUE is to define WORDS_BIGENDIAN like AC_C_BIGENDIAN + always did. +- AC_C_LONG_DOUBLE now succeeds only if `long double' has more range or + precision than `double'. + +** Generic macros + +- AC_INIT + It now defines the preprocessor symbols PACKAGE_NAME, + PACKAGE_TARNAME, PACKAGE_VERSION, PACKAGE_STRING, and + PACKAGE_BUGREPORT. + +- AC_INIT + Admits a fourth optional parameter: the tar name. + +- AC_CONFIG_COMMANDS, HEADERS, FILES, LINKS. + Provide the user with srcdir, ac_srcdir, ac_top_srcdir, ac_builddir, + ac_top_builddir, ac_abs_srcdir, ac_abs_top_srcdir, ac_abs_builddir, + ac_abs_top_builddir. + +- AC_CONFIG_COMMANDS, HEADERS, FILES, LINKS and AC_OUTPUT. + Are much less expensive when using long lists of files. + +- AC_PREFIX_PROGRAM + Works with shell variables, and non alphanumeric names. + +** Library macros + +- AC_FUNC_STRERROR_R now sets STRERROR_R_CHAR_P, not HAVE_WORKING_STRERROR_R, + because POSIX 1003.1-200x draft 7 says strerror_r returns int, not char *. + +- AC_FUNC_STRTOD substitutes POW_LIB. + +- AC_FUNC_STRNLEN + New. + +* Major changes in Autoconf 2.52 + + Released 2001-07-18 by Akim Demaille. + +** Documentation +- AC_ARG_VAR +- Quadrigraphs + This feature was present in autoconf 2.50 but was not documented. + For example, `@<:@' is translated to `[' just before output. This + is useful when writing strings that contain unbalanced quotes, or + other hard-to-quote constructs. +- m4_pattern_forbid, m4_pattern_allow +- Tips for upgrading from 2.13. +- Using autoscan to maintain a configure.ac. + +** Default includes +- Now include stdint.h. +- sys/types.h and sys/stat.h are guarded. +- strings.h is included if available, and not conflicting with string.h. + +** Bug fixes +- The test suite is more robust and presents less false failures. +- Invocation of GNU M4 now robust to POSIXLY_CORRECT. +- configure accepts --prefix='' again. +- AC_CHECK_LIB works properly when its first argument is not a + literal. +- HAVE_INTTYPES_H is defined only if not conflicting with sys/types.h. +- build_, host_, and target_alias are AC_SUBST as in 2.13. +- AC_ARG_VAR properly propagates precious variables inherited from the + environment to ./config.status. +- Using --program-suffix/--program-prefix is portable. +- Failures to detect the default compiler's output extension are less + likely. +- `config.status foo' works properly when `foo' depends on variables + set in an AC_CONFIG_THING INIT-CMD. +- autoheader is more robust to broken input. +- Fixed Fortran name-mangling and link tests on a number of systems, + e.g. NetBSD; see AC_F77_DUMMY_MAIN, below. + +** Generic macros +- AC_CHECK_HEADER and AC_CHECK_HEADERS support a fourth argument to + specify pre-includes. In this case, the headers are compiled with + cc, not merely preprocessed by cpp. Therefore it is the _usability_ + of a header which is checked for, not just its availability. +- AC_ARG_VAR refuses to run configure when precious variables have + changed. +- Versions of compilers are dumped in the logs. +- AC_CHECK_TYPE recognizes use of `foo_t' as a replacement type. + +** Specific Macros +- AC_PATH_XTRA only adds -ldnet to $LIBS if it's needed to link. +- AC_FUNC_WAIT3 and AC_SYS_RESTARTABLE_SYSCALLS are obsoleted. +- AM_FUNC_ERROR_AT_LINE, AM_FUNC_FNMATCH, AM_FUNC_MKTIME, + AM_FUNC_OBSTACK, and AM_FUNC_STRTOD are now activated. + Be sure to read `Upgrading from Version 2.13' to understand why + running `autoupdate' is needed. +- AC_F77_DUMMY_MAIN, AC_F77_MAIN: new macros to detect whether + a main-like routine is required/possible when linking C/C++ with + Fortran. Users of e.g. AC_F77_WRAPPERS should be aware of these. +- AC_FUNC_GETPGRG behaves better when cross-compiling. + +* Major changes in Autoconf 2.51 +There was no release of Autoconf 2.51 since some packagers had used +this version number without permission to ship intermediary versions +of 2.50. The version was skipped to avoid confusion. + +* Major changes in Autoconf 2.50 + + Released 2001-05-21 by Akim Demaille. + +** Lots of bug fixes +There have been far too many to enumerate them here. Check out +ChangeLog if you really want to know more. + +** Improved documentation +In particular, portability issues are better covered. + +** Use of Automake +All the standard GNU Makefile targets are supported. The layout has +changed: m4/ holds the M4 extensions Autoconf needs for its +configuration, doc/ contains the documentation, and tests/ contains +the test suite. + +** Man pages are provided +For autoconf, autoreconf, autoupdate, autoheader, autoscan, ifnames, +config.guess, config.sub. + +** autoconf +- --trace + Provides a safe and powerful means to trace the macro uses. This + provide the parsing layer for tools which need to `study' + configure.in. + +- --warnings + Specify what category of warnings should be enabled. + +- When recursing into subdirectories, try for configure.gnu before + configure to adapt for packages not using autoconf on case-insensitive + file systems. + +- Diagnostics + More errors are now caught (circular AC_REQUIRE dependencies, + AC_DEFINE in the action part of an AC_CACHE_CHECK, too many pops + etc.). In addition, their location and call stack are given. + +** autoupdate +autoupdate is much more powerful, and is able to provide the glue code +which might be needed to move from an old macro to its newer +equivalent. + +You are strongly encouraged to use it to modernize both your +`configure.in' and your .m4 extension files. + +** autoheader +The internal machinery of autoheader has completely changed. As a +result, using `acconfig.h' should be considered to be obsoleted, and +you are encouraged to get rid of it using the AH macros. + +** autoreconf +Extensive overhaul. + +** Fortran 77 compilers +Globally, the support for Fortran 77 is considerably improved. + +Support for automatically determining a Fortran 77 compiler's +name-mangling scheme. New CPP macros F77_FUNC and F77_FUNC_ are +provided to wrap C/C++ identifiers, thus making it easier and more +transparent for C/C++ to call Fortran 77 routines, and Fortran 77 to +call C/C++ routines. See the Texinfo documentation for details. + +** Test suite +The test suite no longer uses DejaGNU. It should be easy to submit +test cases in this new framework. + +** configure +- --help, --help=long, -hl + no longer dumps useless items. +- --help=short, -hs + lists only specific options. +- --help=recursive, -hr + displays the help of all the embedded packages. +- Remembers environment variables when reconfiguring. + The previous scheme to set envvar before running configure was + ENV=VAL ./configure + what prevented configure from remembering the environment in which + it was run, therefore --recheck was run in an inconsistent + environment. Now, one should run + ./configure ENV=VAR + and then --recheck will work properly. Variables declared with + AC_ARG_VAR are also preserved. +- cross-compilation + $build defaults to `config.guess`, $host to $build, and then $target + to $host. + Cross-compilation is a global status of the package, it no longer + depends upon the current language. + Cross compilation is enabled iff the user specified `--host'. + `configure' now fails if it can't run the executables it compiles, + unless cross-compilation is enabled. +- Cache file + The cache file is disabled by default. The new options + `--config-cache', `-C' set the cache to `config.cache'. + +** config.status +- faster + Much faster on most architectures. +- concurrent executions + It is safe to use `make -j' with config.status. +- human interface improved + It is possible to invoke + ./config.status foobar + instead of the former form (still valid) + CONFIG_COMMANDS= CONFIG_HEADERS= CONFIG_LINKS= \ + CONFIG_FILES=foobar:foo.in:bar.in \ + ./config.status + The same holds for configuration headers and links. + You can instantiate unknown files and headers: + ./config.status --header foo.h:foo.h.in --file bar:baz +- has a useful --help +- accepts special file name "-" for stdin/stdout + + +** Identity Macros +- AC_COPYRIGHT + Specify additional copyright information. + +- AC_INIT + Now expects the identity of the package as argument. + +** General changes. +- Uniform quotation + Most macros, if not all, now strictly follow the `one quotation + level' rule. This results in a more predictable expansion. + +- AC_REQUIRE + A sly bug in the AC_REQUIRE machinery, which could produce incorrect + configure scripts, was fixed by Axel Thimm. + +** Setup Macros +- AC_ARG_VAR + Document and ask for the registration of an envvar. + +- AC_CONFIG_SRCDIR + Specifies the file which `configure' should look for when trying to + find the source tree (used to be handled by AC_INIT). + +- AC_CONFIG_COMMANDS + To add new actions to config.status. Should be used instead of + AC_OUTPUT_COMMANDS. + +- AC_CONFIG_LINKS + Replaces AC_LINK_FILES. + +- AC_CONFIG_HEADERS, AC_CONFIG_COMMANDS, AC_CONFIG_SUBDIRS, + AC_CONFIG_LINKS, and AC_CONFIG_FILES + They now obey sh: you should no longer use shell variables as + argument. Instead of + + test "$package_foo_enabled" = yes && $my_subdirs="$my_subdirs foo" + AC_CONFIG_SUBDIRS($my_subdirs) + + write + + if test "$package_foo_enabled" = yes; then + AC_CONFIG_SUBDIRS(foo) + fi + +- AC_HELP_STRING + To format an Autoconf macro's help string so that it looks pretty + when the user executes `configure --help'. + + +** Generic Test Macros +- AC_CHECK families + The interface of the AC_CHECK families of macros (decl, header, + type, member, func) is now uniform. They support the same set of + default includes. + +- AC_CHECK_DECL, AC_CHECK_DECLS + To check whether a symbol is declared. + +- AC_CHECK_SIZEOF, AC_C_CHAR_UNSIGNED. + No longer need a cross-compilation default. + +- AC_CHECK_TYPE + The test it performs is much more robust than previously, and makes + it possible to test builtin types in addition to typedefs. + It is now schizophrenic: + - AC_CHECK_TYPE(TYPE, REPLACEMENT) + remains for backward compatibility, but its use is discouraged. + - AC_CHECK_TYPE(TYPE, IF-FOUND, IF-NOT-FOUND, INCLUDES) + behaves exactly like the other AC_CHECK macros. + +- AC_CHECK_TYPES + Checks whether given types are supported by the system. + +- AC_CHECK_MEMBER, AC_CHECK_MEMBERS + Check for given members in aggregates (e.g., pw_gecos in struct + passwd). + +- AC_PROG_CC_STDC + Checks if the compiler supports ISO C, included when needs special + options. + +- AC_PROG_CPP + Checking whether the preprocessor indicates missing includes by the + error code. stderr is checked by AC_TRY_CPP only as a fallback. + +- AC_LANG + Takes a language as argument and replaces AC_LANG_C, + AC_LANG_CPLUSPLUS and AC_LANG_FORTRAN77. + +- AC_LANG_PUSH, AC_LANG_POP + Are preferred to AC_LANG_SAVE, AC_LANG_RESTORE. + +** Specific Macros +- AC_FUNC_CHOWN, AC_FUNC_MALLOC, AC_FUNC_STRERROR_R, + AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK, AC_FUNC_STAT, AC_FUNC_LSTAT, + AC_FUNC_ERROR_AT_LINE, AC_FUNC_OBSTACK, AC_FUNC_STRTOD, AC_FUNC_FSEEKO. + New. + +- AC_FUNC_GETGROUPS + Sets GETGROUPS_LIBS. + +- AC_FUNC_GETLOADAVG + Defines `HAVE_STRUCT_NLIST_N_UN_N_NAME' instead of `NLIST_NAME_UNION'. + +- AC_PROG_LEX + Now integrates `AC_DECL_YYTEXT' which is obsoleted. + +- AC_SYS_LARGEFILE + Arrange for large-file support. + +- AC_EXEEXT, AC_OBJEXT + You are no longer expected to use them: their computation is + performed by default. + +** C++ compatibility + Every macro has been revisited in order to support at best CC=c++. + +Major changes in Autoconf 2.14: + There was no release of GNU Autoconf 2.14. + +Major changes in Autoconf 2.13: + + Released 1999-05-01 by Ben Elliston. + +* Support for building on 32-bit Windows systems where the only available C or + C++ compiler is the Microsoft Visual C++ command line compiler + (`cl'). Additional support for building on 32-bit Windows systems which are + using the Cygwin or Mingw32 environments. +* Support for alternative object file and executable file extensions. + On 32-bit Windows, for example, these are .obj and .exe. These are discovered + using AC_OBJEXT and AC_EXEEXT, which substitute @OBJEXT@ and + @EXEEXT@ in the output, respectively. +* New macros: AC_CACHE_LOAD, AC_CACHE_SAVE, AC_FUNC_SELECT_ARGTYPES, + AC_VALIDATE_CACHED_SYSTEM_TUPLE, AC_SEARCH_LIBS, AC_TRY_LINK_FUNC, + AC_C_STRINGIZE, AC_CHECK_FILE(S), AC_PROG_F77 (and friends). +* AC_DEFINE now has an optional third argument for a description to be + placed in the config header input file (e.g. config.h.in). +* The C++ code fragment compiled for the C++ compiler test had to be + improved to include an explicit return type for main(). This was + causing failures on systems using recent versions of the EGCS C++ + compiler. +* Fixed an important bug in AC_CHECK_TYPE that would cause a configure + script to report that `sometype_t' was present when only `type_t' + was defined. +* Merge of the FSF version of config.guess and config.sub to modernize + these scripts. Add support for a few new hosts in config.guess. + Incorporate latest versions of install-sh, mkinstalldirs and + texinfo.tex from the FSF. +* autoreconf is capable of running automake if necessary (and + applicable). +* Support for Fortran 77. See the Texinfo documentation for details. +* Bug fixes and workarounds for quirky bugs in vendor utilities. + +Major changes in Autoconf 2.12: + + Released 1996-11-26 by David J. MacKenzie + +* AC_OUTPUT and AC_CONFIG_HEADERS can create output files by + concatenating multiple input files separated by colons, like so: + AC_CONFIG_HEADERS([config.h:conf.pre:config.h.in:conf.post]) + AC_OUTPUT([Makefile:Makefile.in:Makefile.rules]) + The arguments may be shell variables, to compute the lists on the fly. +* AC_LINK_FILES and AC_CONFIG_SUBDIRS may be called multiple times. +* New macro AC_OUTPUT_COMMANDS adds more commands to run in config.status. +* Bug fixes. + +Major changes in Autoconf 2.11: + + Released November 18th, 1996, by David J. MacKenzie + +* AC_PROG_CC and AC_PROG_CXX check whether the compiler works. + They also default CFLAGS/CXXFLAGS to "-g -O2" for gcc, instead of "-g -O". +* AC_REPLACE_FUNCS defines HAVE_foo if the system has the function `foo'. +* AC_CONFIG_HEADERS expands shell variables in its argument. +* New macros: AC_FUNC_FNMATCH, AC_FUNC_SETPGRP. +* The "checking..." messages and the source code for test programs that + fail are saved in config.log. +* Another workaround has been added for seds with small command length limits. +* config.sub and config.guess recognize more system types. +* Bug fixes. + +Major changes in Autoconf 2.10: + + Released May 7th, 1996, by Roland McGrath + +* Bug fixes. +* The cache variable names used by `AC_CHECK_LIB(LIB, FUNC, ...)' has + changed: now $ac_cv_lib_LIB_FUNC, previously $ac_cv_lib_LIB. + +Major changes in Autoconf 2.9: + + Released March 16th, 1996, by Roland McGrath + +* Bug fixes. + +Major changes in Autoconf 2.8: + + Released March 8th, 1996, by Roland McGrath + +* Bug fixes. + +Major changes in Autoconf 2.7: + + Released November 22nd, 1995, by David J. MacKenzie + +* Bug fixes. + +Major changes in Autoconf 2.6: + + Released November 20th, 1995, by David J. MacKenzie + +* Bug fixes. + +Major changes in Autoconf 2.5: + + Released November 17th, 1995, by Roland McGrath + +* New configure options --bindir, --libdir, --datadir, etc., with + corresponding output variables. +* New macro: AC_CACHE_CHECK, to make using the cache easier. +* config.log contains the command being run as well as any output from it. +* AC_CHECK_LIB can check for libraries with "." or "/" or "+" in their name. +* AC_PROG_INSTALL doesn't cache a name for install-sh, for sharing caches. +* AC_CHECK_PROG, AC_PATH_PROG, AC_CHECK_PROGS, AC_PATH_PROGS, and + AC_CHECK_TOOL can search a path other than $PATH. +* AC_CHECK_SIZEOF takes an optional size to use when cross-compiling. + +Major changes in Autoconf 2.4: + + Released June 14th, 1995, by David J. MacKenzie + +* Fix a few bugs found by Emacs testers. + +Major changes in Autoconf 2.3: + + Released March 27th, 1995, by David J. MacKenzie + +* Fix the cleanup trap in several ways. +* Handle C compilers that are picky about option placement. +* ifnames gets the version number from the right directory. + +Major changes in Autoconf 2.2: + + Released March 8th, 1995, by David J. MacKenzie + +* The ifnames utility is much faster but requires a "new awk" interpreter. +* AC_CHECK_LIB and AC_HAVE_LIBRARY check and add the new + library before existing libs, not after, in case it uses them. +* New macros: AC_FUNC_GETPGRP, AC_CHECK_TOOL. +* Lots of bug fixes. +* Many additions to the TODO file :-) + +Major changes in Autoconf 2.1: + + Released November 4th, 1994, by David J. MacKenzie + +* Fix C++ problems. +* More explanations in the manual. +* Fix a spurious failure in the testsuite. +* Clarify some warning messages. +* autoreconf by default only rebuilds configure and config.h.in files + that are older than any of their particular input files; there is a + --force option to use after installing a new version of Autoconf. + +Thanks to everybody who's submitted changes and additions to Autoconf! +I've incorporated many of them, and am still considering others for +future releases -- but I didn't want to postpone this release indefinitely. + +Caution: don't indiscriminately rebuild configure scripts with +Autoconf version 2. Some configure.in files need minor adjustments to +work with it; the documentation has a chapter on upgrading. A few +configure.in files, including those for GNU Emacs and the GNU C +Library, need major changes because they relied on undocumented +internals of version 1. Future releases of those packages will have +updated configure.in files. + +It's best to use GNU M4 1.3 (or later) with Autoconf version 2. +Autoconf now makes heavy use of M4 diversions, which were implemented +inefficiently in GNU M4 releases before 1.3. + +Major changes in Autoconf 2.0: + + Released October 26th, 1994, by David J. MacKenzie + +** New copyright terms: +* There are no restrictions on distribution or use of configure scripts. + +** Documentation: +* Autoconf manual is reorganized to make information easier to find + and has several new indexes. +* INSTALL is reorganized and clearer and is now made from Texinfo source. + +** New utilities: +* autoscan to generate a preliminary configure.in for a package by + scanning its source code for commonly used nonportable functions, + programs, and header files. +* ifnames to list the symbols used in #if and #ifdef directives in a + source tree. +* autoupdate to update a configure.in to use the version 2 macro names. +* autoreconf to recursively remake configure and configuration header + files in a source tree. + +** Changed utilities: +* autoheader can take pieces of acconfig.h to replace config.h.{top,bot}. +* autoconf and autoheader can look for package-local definition files + in an alternate directory. + +** New macros: +* AC_CACHE_VAL to share results of tests between configure runs. +* AC_DEFUN to define macros, automatically AC_PROVIDE them, and ensure + that macros invoked with AC_REQUIRE don't interrupt other macros. +* AC_CONFIG_AUX_DIR, AC_CANONICAL_SYSTEM, AC_CANONICAL_HOST, AC_LINK_FILES to + support deciding unguessable features based on the host and target types. +* AC_CONFIG_SUBDIRS to recursively configure a source tree. +* AC_ARG_PROGRAM to use the options --program-prefix, + --program-suffix, and --program-transform-name to change the names + of programs being installed. +* AC_PREFIX_DEFAULT to change the default installation prefix. +* AC_TRY_COMPILE to compile a test program without linking it. +* AC_CHECK_TYPE to check whether sys/types.h or stdlib.h defines a given type. +* AC_CHECK_LIB to check for a particular function and library. +* AC_MSG_CHECKING and AC_MSG_RESULT to print test results, on a single line, + whether or not the test succeeds. They obsolete AC_CHECKING and AC_VERBOSE. +* AC_SUBST_FILE to insert one file into another. +* AC_FUNC_MEMCMP to check whether memcmp is 8-bit clean. +* AC_FUNC_STRFTIME to find strftime even if it's in -lintl. +* AC_FUNC_GETMNTENT to find getmntent even if it's in -lsun or -lseq. +* AC_HEADER_SYS_WAIT to check whether sys/wait.h is POSIX.1 compatible. + +** Changed macros: +* Many macros renamed systematically, but old names are accepted for + backward compatibility. +* AC_OUTPUT adds the "automatically generated" comment to + non-Makefiles where it finds @configure_input@ in an input file, to + support files with various comment syntaxes. +* AC_OUTPUT does not replace "prefix" and "exec_prefix" in generated + files when they are not enclosed in @ signs. +* AC_OUTPUT allows the optional environment variable CONFIG_STATUS to + override the file name "config.status". +* AC_OUTPUT takes an optional argument for passing variables from + configure to config.status. +* AC_OUTPUT and AC_CONFIG_HEADERS allow you to override the input-file names. +* AC_OUTPUT automatically substitutes the values of CFLAGS, CXXFLAGS, + CPPFLAGS, and LDFLAGS from the environment. +* AC_PROG_CC and AC_PROG_CXX now set CFLAGS and CXXFLAGS, respectively. +* AC_PROG_INSTALL looks for install-sh or install.sh in the directory + specified by AC_CONFIG_AUXDIR, or srcdir or srcdir/.. or + srcdir/../.. by default. +* AC_DEFINE, AC_DEFINE_UNQUOTED, and AC_SUBST are more robust and smaller. +* AC_DEFINE no longer prints anything, because of the new result reporting + mechanism (AC_MSG_CHECKING and AC_MSG_RESULT). +* AC_VERBOSE pays attention to --quiet/--silent, not --verbose. +* AC_ARG_ENABLE and AC_ARG_WITH support whitespace in the arguments to + --enable- and --with- options. +* AC_CHECK_FUNCS and AC_CHECK_HEADERS take optional shell commands to + execute on success or failure. +* Checking for C functions in C++ works. + +** Removed macros: +* AC_REMOTE_TAPE and AC_RSH removed; too specific to tar and cpio, and + better maintained with them. +* AC_ARG_ARRAY removed because no one was likely using it. +* AC_HAVE_POUNDBANG replaced with AC_SYS_INTERPRETER, which doesn't + take arguments, for consistency with all of the other specific checks. + +** New files: +* Comes with config.sub and config.guess, and uses them optionally. +* Uses config.cache to cache test results. An alternate cache file + can be selected with the --cache-file=FILE option. +* Uses optional shell scripts $prefix/share/config.site and + $prefix/etc/config.site to perform site or system specific initializations. +* configure saves compiler output to ./config.log for debugging. +* New files autoconf.m4 and autoheader.m4 load the other Autoconf macros. +* acsite.m4 is the new name for the system-wide aclocal.m4. +* Has a DejaGnu test suite. + +Major changes in Autoconf 1.11: + +* AC_PROG_INSTALL calls install.sh with the -c option. +* AC_SET_MAKE cleans up after itself. +* AC_OUTPUT sets prefix and exec_prefix if they weren't set already. +* AC_OUTPUT prevents shells from looking in PATH for config.status. + +Plus a few other bug fixes. + +Major changes in Autoconf 1.10: + +* autoheader uses config.h.bot if present, analogous to config.h.top. +* AC_PROG_INSTALL looks for install.sh in srcdir or srcdir/.. and + never uses cp. +* AC_PROG_CXX looks for cxx as a C++ compiler. + +Plus several bugs fixed. + +Major changes in Autoconf 1.9: + +* AC_YYTEXT_POINTER replaces AC_DECLARE_YYTEXT. +* AC_SIZEOF_TYPE generates the cpp symbol name automatically, + and autoheader generates entries for those names automatically. +* AC_FIND_X gets the result from xmkmf correctly. +* AC_FIND_X assumes no X if --without-x was given. +* AC_FIND_XTRA adds libraries to the variable X_EXTRA_LIBS. +* AC_PROG_INSTALL finds OSF/1 installbsd. + +Major changes in Autoconf 1.8: + +** New macros: +* New macros AC_LANG_C, AC_LANG_CPLUSPLUS, AC_LANG_SAVE, AC_LANG_RESTORE, + AC_PROG_CXX, AC_PROG_CXXCPP, AC_REQUIRE_CPP + for checking both C++ and C features in one configure script. +* New macros AC_CHECKING, AC_VERBOSE, AC_WARN, AC_ERROR for printing messages. +* New macros AC_FIND_XTRA, AC_MMAP, AC_SIZEOF_TYPE, AC_PREREQ, + AC_SET_MAKE, AC_ENABLE. + +** Changed macros: +* AC_FIND_X looks for X in more places. +* AC_PROG_INSTALL defaults to install.sh instead of cp, if it's in srcdir. + install.sh is distributed with Autoconf. +* AC_DECLARE_YYTEXT has been removed because it can't work, pending + a rewrite of quoting in AC_DEFINE. +* AC_OUTPUT adds its comments in C format when substituting in C files. +* AC_COMPILE_CHECK protects its ECHO-TEXT argument with double quotes. + +** New or changed command line options: +* configure accepts --enable-FEATURE[=ARG] and --disable-FEATURE options. +* configure accepts --without-PACKAGE, which sets withval=no. +* configure accepts --x-includes=DIR and --x-libraries=DIR. +* Giving --with-PACKAGE no argument sets withval=yes instead of withval=1. +* configure accepts --help, --version, --silent/--quiet, --no-create options. +* configure accepts and ignores most other Cygnus configure options, and + warns about unknown options. +* config.status accepts --help, --version options. + +** File names and other changes: +* Relative srcdir values are not made absolute. +* The values of @prefix@ and @exec_prefix@ and @top_srcdir@ get substituted. +* Autoconf library files are installed in ${datadir}/autoconf, not ${datadir}. +* autoheader optionally copies config.h.top to the beginning of config.h.in. +* The example Makefile dependencies for configure et al. work better. +* Namespace cleanup: all shell variables used internally by Autoconf + have names beginning with `ac_'. + +More big improvements are in process for future releases, but have not +yet been (variously) finished, integrated, tested, or documented enough +to release yet. + +Major changes in Autoconf 1.7: + +* New macro AC_OBSOLETE. +* Bugs in Makefile.in fixed. +* AC_LONG_FILE_NAMES improved. + +Major changes in Autoconf 1.6: + +* New macro AC_LONG_64_BITS. +* Multiple .h files can be created. +* AC_FIND_X looks for X files directly if it doesn't find xmkmf. +* AC_ALLOCA defines C_ALLOCA if using alloca.c. +* --with-NAME can take a value, e.g., --with-targets=sun4,hp300bsd. +* Unused --no-create option to configure removed. +* autoheader doesn't change the timestamp of its output file if + the file didn't change. +* All macros that look for libraries now use AC_HAVE_LIBRARY. +* config.status checks three optional environment variables to + modify its behavior. +* The usual bug fixes. + +Major changes in Autoconf 1.5: + +* New macros AC_FIND_X, AC_OFF_T, AC_STAT_MACROS_BROKEN, AC_REVISION. +* autoconf and autoheader scripts have GNU standards conforming + --version and --help options (they print their message and exit). +* Many bug fixes. + +Major changes in Autoconf 1.4: + +* New macros AC_HAVE_POUNDBANG, AC_TIME_WITH_SYS_TIME, AC_LONG_DOUBLE, + AC_GETGROUPS_T, AC_DEFINE_UNQUOTED. +* autoconf and autoheader use the M4 environment variable to determine the + name of the M4 program to use. +* The --macrodir option to autoconf and autoheader specifies the directory + in which acspecific.m4, acgeneral.m4, etc. reside if not the default. +* autoconf and autoheader can take `-' as their file names, which means to + read stdin as input. +* Resulting configure scripts can take a --verbose option which causes them + to print the results of their tests. +* AC_DEFINE quotes its second argument in such a way that spaces, magic + shell characters, etc. will be preserved during various stages of + expansion done by the shell. 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Mitchell dustin@zmanda.com +Edouard Bechetoille ebecheto@ens-lyon.fr +Elbert Pol elbert.pol@gmail.com +Eli Zaretskii eliz@gnu.org +Elias Pipping pipping@macports.org +Enrique Robledo Arnuncio enrique.robledo@wanadoo.es +Erez Zadok ezk@cs.columbia.edu +Eric Backus ericb@lsid.hp.com +Eric Blake ebb9@byu.net +Eric Lemings lemings@roguewave.com +Eric Mumpower nocturne@mit.edu +Eric Paire ? +Eric Sunshine sunshine@sunshineco.com +Ezra Peisach epeisach@zif.mit.edu +Fedor Sergeev ? +Felix Lee flee@cygnus.com +Fernando Carrijo fcarrijo@freedesktop.org +Franceseco Romani fromani@gmail.com +Frank Denis j@jedi.claranet.fr +François Pinard pinard@iro.umontreal.ca +Fred Kreek Fred.Kreek@kadaster.nl +Frederik Fouvry fouvry@CoLi.Uni-SB.DE +Gareth McCaughan gareth.mccaughan@pobox.com +Gary V. Vaughan gvaughan@oranda.demon.co.uk +Geir Ove Myhr myhr@stud.fim.ntnu.no +Gerrit P. Haase gp@familiehaase.de +Gideon Go gideon.go@gmail.com +Giorgos Keramidas gkeramidas@gmail.com +Giuseppe Guerrini guisguerrini@racine.ra.it +Glenn P. Davis davis@unidata.ucar.edu +Godmar Back gback@cs.utah.edu +Gordon Matzigkeit gord@trick.fig.org +Graham Jenkins c714553@vus415.telstra.com.au +Greg A. Woods woods@weird.com +Greg Schafer gschafer@zip.com.au +Gregorio Guidi ? +Gregory Giannoni sand@narguile.org +Giulio Paci giuliopaci@interfree.it +Guido Draheim Guido.Draheim@gmx.de +Guido Flohr gufl0000@stud.uni-sb.de +Guido van Rossum ? +Guillermo Gomez gomez@mi.uni-erlangen.de +H. Merijn Brand h.m.brand@hccnet.nl +H. Peter Anvin ? +H.J. Lu hjl@gnu.org +Hallvard B Furuseth h.b.furuseth@usit.uio.no +Hans Aberg haberg@math.su.se +Hans Olsson Hans.Olsson@dna.lth.se +Hans Ulrich Niedermann hun@n-dimensional.de +Harlan Stenn stenn@whimsy.udel.edu +Heiko Schlichting inn-workers@fu-berlin.de +Henk Krus h.krus@cyclone.nl +Howard Chu hyc@highlandsun.com +Ian Lance Taylor ian@cygnus.com +Ian Macdonald iamacdo@telkomsa.net +Ian Redfern Ian.Redfern@logicacmg.com +Ilya Bobir ilya.bobir@gmail.com +Ilya Zakharevich ilya@Math.Berkeley.EDU +Ineiev ineiev@yahoo.co.uk +Iohannes m zmoelnig zmoelnig@iem.at +J C Fitzgerald v7022@wave.co.nz +Jaap Haitsma jaap@haitsma.org +James A. Lupo lupoja@feynman.ml.wpafb.af.mil +Jan Madzik jmadzik@gmail.com +Jason Molenda jsm@cygnus.com +Jeff Garzik jgarzik@pobox.com +Jeff Painter ? +Jeff Squyres jsquyres@cisco.com +Jeffrey A Law law@cygnus.com +Jeffrey J. Barteet ? +Jennis Pruett ? +Jens Petersen petersen@redhat.com +Jens Schmidt jens.schmidt35@arcor.de +Jeremy Yallop jeremy@yallop.org +Jerker Bäck jerker.back@home.se +Jim Blandy jimb@wookumz.gnu.ai.mit.edu +Jim Meyering meyering@ascend.com +Jim Warhol jrw@jwarhol.com +Jiro Takabatake jiro@din.or.jp +Jochen Friedrich jochen@scram.de +Joel E. Denny jdenny@ces.clemson.edu +Joel James Adamson joel@chondestes.bio.unc.edu +Joey Mingrone joey@mingrone.org +Johan Danielsson joda@pdc.kth.se +John Calcote john.calcote@gmail.com +John David Anglin dave@hiauly1.hia.nrc.ca +John Fortin fortinj@attglobal.net +John Interrante interran@uluru.stanford.edu +John R. Cary cary@txcorp.com +John W. Eaton jwe@bevo.che.wisc.edu +Jonathan Kamens jik@kamens.brookline.ma.us +Jonathan Lebon jlebon@redhat.com +Josef Tran josef@timetrackertechnology.com +Josef Vukovic josefvukovic@googlemail.com +Joseph S. Myers jsm28@cam.ac.uk +Joshua G. Hale jgh.emc@gmail.com +Juan Carlos Hurtado adso.lists@gmail.com +Jules Colding colding@42tools.com +Julian C. Cummings cummings@cacr.caltech.edu +Julian Onions j.onions@nexor.co.uk +Julien Danjou acid@debian.org +Julien Élie julien@trigofacile.com +Julio Garvia ? +Justace Clutter ? +Jörn Rennecke amylaar@cygnus.co.uk +Karl Berry karl@cs.umb.edu +Karl Heuer kwzh@gnu.org +Karsten Hopp karsten@redhat.com +Kate Hedstrom ? +Kathryn Hargreaves kathryn@deas.harvard.edu +Kaveh R. Ghazi ghazi@caip.rutgers.edu +Keith Bostic bostic@abyssinian.sleepycat.com +Keith Marshall keith.marshall@total.com +Kelly Anderson tgcorp@attglobal.net +Ken Pizzini ken@halcyon.com +Ken Raeburn raeburn@cygnus.com +Kevin Ryde user42@zip.com.au +Klee Dienes kdienes@apple.com +Koji Arai JCA02266@nifty.ne.jp +Kristian Kvilekval kris@cs.ucsb.edu +Křištof Želechovski giecrilj@stegny.2a.pl +Kurt D. Zeilenga kurt@openldap.org +Larry Jones larry.jones@sdrc.com +Larry Schmitt larry@mail.haleakalawebdesigns.com +Larry Schwimmer rosebud@cyclone.stanford.edu +Lars Hecking lhecking@nmrc.ucc.ie +Lars J. Aas larsa@sim.no +Laurence Darbe ldarby@tuffmail.com +Leo Moisio leo.moisio@gmail.com +Loulou Pouchet loulou@lrde.epita.fr +Luc Maisonobe luc@spaceroots.org +Ludovic Courtes ? +Luke Dalessandro luked@cs.rochester.edu +Magnus Therning therning@gforge.natlab.research.philips.com +Manu manubee@wanadoo.fr +Marc Espie Marc.Espie@liafa.jussieu.fr +Marcus Brinkmann ? +Marcus Daniels marcus@sysc.pdx.edu +Marcus Thiessel marcus@xemacs.org +Mark Cave-Ayland ? +Mark D. Baushke ? +Mark D. Roth ? +Mark Elbrecht snowball3@usa.net +Mark Hessling mark@rexx.org +Mark Kettenis kettenis@gnu.org +Markku Savela msa@msa.tte.vtt.fi +Markus Oberhumer markus.oberhumer@jk.uni-linz.ac.at +Markus Geimer m.geimer@fz-juelich.de +Martin Buchholz martin@xemacs.org +Martin Costabel costabel@wanadoo.fr +Martin Frydl martin@systinet.com +Martin Koeppe mkoeppe@gmx.de +Martin Mokrejs mmokrejs@natur.cuni.cz +Martin Wilck martin@tropos.de +Martyn Johnson Martyn.Johnson@cl.cam.ac.uk +Matěj Týč matej.tyc@gmail.com +Matt Kraai kraai@ftbfs.org +Matteo Frigo ? +Matthew D. Langston langston@SLAC.Stanford.EDU +Matthew Mueller donut@azstarnet.com +Matthew Woehlke mw_triad@users.sourceforge.net +Matthias Andree matthias.andree@gmx.de +Michal Čihař nijel@debian.org +Michael Elizabeth Chastain chastain@cygnus.com +Michael Jenning ? +Michael Matz matz@kde.org +Michael Schoene mrs@mlc.de +Michael Wardle ? +Mike Frysinger vapier@gentoo.org +Mike Hopkirk hops@sco.com +Mike Stump mrs@wrs.com +Mikulas Patocka ? +Miles Bader miles@gnu.ai.mit.edu +Mo DeJong mdejong@cygnus.com +Momchil Velkov velco@fadata.bg +Monty Taylor mordred@inaugust.com +Morten Eriksen mortene@sim.no +Mostafa mostafa_working_away@yahoo.com +Motoyuki Kasahara m-kasahr@sra.co.jp +Nathan Schulte reklipz@gmail.com +Nathanael Nerode neroden@gcc.gnu.org +Nelson H. F. Beebe beebe@math.utah.edu +Nicolas Joly njoly@pasteur.fr +Nicolás Lichtmaier jnl@synapsis-sa.com.ar +Nick Bowler nbowler@draconx.ca +NightStrike nightstrike@gmail.com +Nishio Futoshi fut_nis@d3.dion.ne.jp +Noah Elliott elliott@hera.llnl.gov +Noah Friedman friedman@gnu.ai.mit.edu +Noah Misch noah@cs.caltech.edu +Noel Grandin noel@peralex.com +Norman Gray ? +Olaf Lenz olenz@fias.uni-frankfurt.de +Ole Holm Nielsen Ole.H.Nielsen@fysik.dtu.dk +Oliver Kiddle opk@zsh.org +Olly Betts olly@survex.com +Ossama Othman ossama@debian.org +Pallav Gupta pallavgupta@gmail.com +Paolo Bonzini bonzini@gnu.org +Patrice Dumas pertusus@free.fr +Patrick Tullmann tullmann@cs.utah.edu +Patrick Welche prlw1@newn.cam.ac.uk +Paul Berrevoets paul@swi.com +Paul D. Smith psmith@gnu.org +Paul Eggert eggert@cs.ucla.edu +Paul Gampe paulg@apnic.net +Paul Jarc prj@po.cwru.edu +Paul Martinolich martinol@datasync.com +Paul Pogonyshev ? +Paul Townsend ? +Pavel Roskin pavel_roskin@geocities.com +Pádraig Brady P@draigbrady.com +Per Øyvind Karlsen peroyvind@mandriva.org +Peter Breitenlohner peb@mppmu.mpg.de +Peter Eisentraut peter_e@gmx.net +Peter Hendrickson pdh@wiredyne.com +Peter Johansson trojkan@gmail.com +Peter O'Gorman peter@pogma.com +Peter Palfrader weasel@debian.org +Peter Simons simons@cryp.to +Peter Stephenson pws@csr.com +Philipp Thomas kthomas@gwdg.de +Philippe De Muyter ? +Pierre pierre42d@9online.fr +Pierre Ynard linkfanel@yahoo.fr +Pontus Skoeld pont@soua.net +Rainer Orth ro@TechFak.Uni-Bielefeld.DE +Raja R Harinath harinath@cs.umn.edu +Ralf Corsepius corsepiu@faw.uni-ulm.de +Ralf Menzel menzel@ls6.cs.uni-dortmund.de +Ralf S. Engelschall rse@engelschall.com +Ralf Wildenhues Ralf.Wildenhues@gmx.de +Randall Cotton recotton@earthlink.net +Reuben Thomas rrt@sc3d.org +Richard Dawe rich@phekda.freeserve.co.uk +Richard Stallman rms@gnu.org +Robert Lipe robertlipe@usa.net +Robert S. Maier rsm@math.arizona.edu +Roberto Bagnara bagnara@cs.unipr.it +Rochan rochan@ices.utexas.edu +Roger Leigh rleigh@whinlatter.ukfsn.org +Roland McGrath roland@gnu.org +Rolf Ebert rolf.ebert.gcc@gmx.de +Rolf Vandevaart Rolf.Vandevaart@sun.com +Romain Lenglet romain.lenglet@laposte.net +Ruediger Kuhlmann info@ruediger-kuhlmann.de +Rugxulo rugxulo@gmail.com +Ruslan Babayev ruslan@babayev.com +Russ Allbery rra@stanford.edu +Russ Boylan ross@biostat.ucsf.edu +Ryuji Abe raeva@t3.rim.or.jp +Sam Sexton Sam.Sexton@reuters.com +Sam Sirlin sam@kalessin.jpl.nasa.gov +Sam Steingold sds@gnu.org +Sam Varshavchik mrsam@courier-mta.com +Sander Niemeijer niemeijer@science-and-technology.nl +santilín listas@gestiong.org +Scott Bambrough scottb@corelcomputer.com +Scott McCreary scottmc2@gmail.com +Scott Stanton stanton@scriptics.com +Sebastian Freundt hroptatyr@gna.org +Sergey Poznyakoff ? +Simon Josefsson jas@extundo.com +Simon Leinen simon@lia.di.epfl.ch +Slava Sysoltsev Viatcheslav.Sysoltsev@h-d-gmbh.de +Stefan Seefeld stefan@codesourcery.com +Stefan `Sec' Zehl ? +Stefano Lattarini stefano.lattarini@gmail.com +Stepan Kasal kasal@ucw.cz +Stéphane Chazelas Stephane_Chazelas@yahoo.fr +Stephen Gildea filtered@against.spam +Stephen Rasku srasku@mail.tantalus-systems.com +Stephen P. Schaefer sschaefer@acm.org +Steve Chamberlain sac@cygnus.com +Steve Goetze goetze@dovetail.com +Steve Huston shuston@riverace.com +Steve Robbins steve@nyongwa.montreal.qc.ca +Steven G. Johnson stevenj@alum.mit.edu +Steven R. Loomis srl@icu-project.org +Stu Grossman grossman@cygnus.com +Sumit Pandya sumit@elitecore.com +Syd Polk spolk@cygnus.com +T.E. Dickey dickey@clark.net +Ted Bullock tbullock@canada.com +Theodore Ts'o tytso@mit.edu +Thien-Thi Nguyen ttn@gnu.org +Thomas Jahns jahns@dkrz.de +Thomas Winder tom@vlsivie.tuwien.ac.at +Tim Freeman tim@fungible.com +Tim Mooney mooney@dogbert.cc.ndsu.NoDak.edu +Tim Rice tim@multitalents.net +Tim Van Holder tim.van.holder@pandora.be +Tobias Burnus burnus@net-b.de +Tom Browder tom.browder@gmail.com +Tom Epperly tepperly@llnl.gov +Tom Lane tgl@sss.pgh.pa.us +Tom Purcell Tom.Purcell@wang.com +Tom Tromey tromey@cygnus.com +Tom Yu tlyu@mit.edu +Tomohiro Suzuki ? +Tony Leneis tony@plaza.ds.adp.com +Toshio Kuratomi ? +Uwe Seimet us@orbacus.com +Václav Haisman v.haisman@sh.cvut.cz +Vance Shipley vances@motivity.ca +Viktor Dukhovni viktor@anaheim.esm.com +Ville Karaila karaila@iki.fi +Vincent Lefèvre vincent@vinc17.org +Vincent Torri vtorri at univ-evry.fr +Vladimir Volovich vvv@vsu.ru +Volker Borchert bt@teknon.de +Wayne Chapeskie waynec@spinnaker.com +Werner Lemberg wl@gnu.org +Wilfredo Sanchez wsanchez@apple.com +William Pursell bill.pursell@gmail.com +Wiseman Jun junwiseman@gmail.com +Wolfgang Mueller Wolfgang.Mueller@cui.unige.ch +Yaakov Selkowitz yselkowitz@users.sourceforge.net +Yavor Doganov yavor@gnu.org +Yury Puhalsky pooh@cryptopro.ru +Zack Weinberg zack@codesourcery.com +? Seanster@Seanster.com + +Many people are not named here because we lost track of them. We +thank them! Please, help us keep this list up to date. + +================ + +Local Variables: +mode: text +coding: utf-8 +End: + +Copyright (C) 1999-2017, 2020-2021 Free Software Foundation, Inc. + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/AUTHORS b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/AUTHORS new file mode 100644 index 0000000..a3c5c01 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/AUTHORS @@ -0,0 +1,27 @@ +Authors of GNU Automake. + +David Mackenzie + First version of most ".am" files. + Wrote sh version of automake.in. + +Tom Tromey + Touched all ".am" files. + Rewrote automake.in + +Alexandre Oliva + Some of the user-side dependency tracking system. + Some more random hacking. + +Alexandre Duret-Lutz + Major overhaul of everything. + Maintenance since 2002. + +Ralf Wildenhues + Random breakage. + Maintenance since 2006. + +Stefano Lattarini + Testsuite overhaul. + TAP support and custom testsuite drivers. + Random breakage. + De-facto maintenance since 2012. diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/COPYING b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/COPYING new file mode 100644 index 0000000..d511905 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS new file mode 100644 index 0000000..fb05ee2 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS @@ -0,0 +1,3118 @@ +For planned incompatibilities in a future Automake 2.0 release, +please see NEWS-2.0 and start following the advice there now. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16.5: + +* Bugs fixed + + - PYTHON_PREFIX and PYTHON_EXEC_PREFIX are now set according to + Python's sys.* values only if the new configure option + --with-python-sys-prefix is specified. Otherwise, GNU default values + are used, as in the past. (The change in 1.16.3 was too incompatible.) + + - consistently depend on install-libLTLIBRARIES. + +* Distribution + + - use const for yyerror declaration in bison/yacc tests. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16.4: + +* New features added + + - The PYTHON_PREFIX and PYTHON_EXEC_PREFIX variables are now set from + Python's sys.prefix and sys.exec_prefix; use the new configure options + --with-python_prefix and --with-python_exec_prefix to specify explicitly. + + - Common top-level files can be provided as .md; the non-md version is + used if both are present: + AUTHORS ChangeLog INSTALL NEWS README README-alpha THANKS + + - CTAGS, ETAGS, SCOPE variables can be set via configure. + + - Silent make output for custom link commands. + + - New option "no-dist-built-sources" skips generating $(BUILT_SOURCES) + before building the tarball as part of "make dist", that is, + omits the dependency of $(distdir): $(BUILT_SOURCES). + +* Bugs fixed + + - automake output more reproducible. + + - test-driver less likely to clash with tests writing to the same file. + + - DejaGnu tests always use the directory name, testsuite/, for + compatibility with the newer dejagnu-1.6.3 and with prior versions. + +* Distribution + + - config.sub and config.guess updates include restoration of `...` + for maximum portability. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16.3: + +* New features added + + - In the testsuite summary, the "for $(PACKAGE_STRING)" suffix + can be overridden with the AM_TESTSUITE_SUMMARY_HEADER variable. + +* Bugs fixed + + - Python version number 3.10 no longer considered to be 3.1. + + - Broken links in manual fixed or removed, and new script + contrib/checklinkx (a small modification of W3C checklink) added, + with accompany target checklinkx to recheck urls. + + - install-exec target depends on $(BUILT_SOURCES). + + - valac argument matching more precise, to avoid garbage in DIST_COMMON. + + - Support for Vala in VPATH builds fixed so that both freshly-generated and + distributed C files work, and operation is more reliable with or without + an installed valac. + + - Dejagnu doesn't break on directories containing spaces. + +* Distribution + + - new variable AM_DISTCHECK_DVI_TARGET, to allow overriding the + "make dvi" that is done as part of distcheck. + +* Miscellaneous changes + + - install-sh tweaks: + . new option -p to preserve mtime, i.e., invoke cp -p. + . new option -S SUFFIX to attempt backup files using SUFFIX. + . no longer unconditionally uses -f when rm is overridden by RMPROG. + . does not chown existing directories. + + - Removed function up_to_date_p in lib/Automake/FileUtils.pm. + We believe this function is completely unused. + + - Support for in-tree Vala libraries improved. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16.2: + +* New features added + + - add zstd support and the automake option, dist-zstd. + + - support for Python 3: py-compile now supports both Python 3 + and Python 2; tests do not require .pyo files, and uninstall + deletes __pycache__ correctly (automake bug #32088). + +* Miscellaneous changes + + - automake no longer requires a @setfilename in each .texi file + +* Bugs fixed + + - When cleaning the compiled python files, '\n' is not used anymore in the + substitution text of 'sed' transformations. This is done to preserve + compatibility with the 'sed' implementation provided by macOS which + considers '\n' as the 'n' character instead of a newline. + (automake bug#31222) + + - For make tags, lisp_LISP is followed by the necessary space when + used with CONFIG_HEADERS. + (automake bug#38139) + + - The automake test txinfo-vtexi4.sh no longer fails when localtime + and UTC cross a day boundary. + + - Emacsen older than version 25, which require use of + byte-compile-dest-file, are supported again. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16.1: + +* Bugs fixed: + + - 'install-sh' now ensures that nobody can cross privilege boundaries by + pre-creating symlink on the directory inside "/tmp". + + - 'automake' does not depend on the 'none' subroutine of the List::Util + module anymore to support older Perl version. (automake bug#30631) + + - A regression in AM_PYTHON_PATH causing the rejection of non literal + minimum version parameter hasn't been fixed. (automake bug#30616) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.16: + +* Miscellaneous changes + + - When subdir-objects is in effect, Automake will now construct + shorter object file names when no programs and libraries name + clashes are encountered. This should make the discouraged use of + 'foo_SHORTNAME' unnecessary in many cases. + +* Bugs fixed: + + - Automatic dependency tracking has been fixed to work also when the + 'subdir-object' option is used and some 'foo_SOURCES' definition + contains unexpanded references to make variables, as in, e.g.: + + a_src = sources/libs/aaa + b_src = sources/bbb + foo_SOURCES = $(a_src)/bar.c $(b_src)/baz.c + + With such a setup, the created makefile fragment containing dependency + tracking information will be correctly placed under the directories + named 'sources/libs/aaa/.deps' and 'sources/bbb/.deps', rather than + mistakenly under directories named (literally!) '$(src_a)/.deps' and + '$(src_b)/.deps' (this was the first part of automake bug#13928). + + Notice that in order to fix this bug we had to slightly change the + semantics of how config.status bootstraps the makefile fragments + required for the dependency tracking to work: rather than attempting + to parse the Makefiles via grep and sed trickeries only, we actually + invoke 'make' on a slightly preprocessed version of those Makefiles, + using a private target that is only meant to bootstrap the required + makefile fragments. + + - The 'subdir-object' option no longer causes object files corresponding + to source files specified with an explicit '$(srcdir)' component to be + placed in the source tree rather than in the build tree. + + For example, if Makefile.am contains: + + AUTOMAKE_OPTIONS = subdir-objects + foo_SOURCES = $(srcdir)/foo.c $(srcdir)/s/bar.c $(top_srcdir)/baz.c + + then "make all" will create 'foo.o' and 's/bar.o' in $(builddir) rather + than in $(srcdir), and will create 'baz.o' in $(top_builddir) rather + than in $(top_srcdir). + + This was the second part of automake bug#13928. + + - Installed 'aclocal' m4 macros can now accept installation directories + containing '@' characters (automake bug#20903) + + - "./configure && make dist" no longer fails when a distributed file depends + on one from BUILT_SOURCES. + + - When combining AC_LIBOBJ or AC_FUNC_ALLOCA with the + "--disable-dependency-tracking" configure option in an out of source + build, the build sub-directory defined by AC_CONFIG_LIBOBJ_DIR is now + properly created. (automake bug#27781) + + - The time printed by 'mdate-sh' is now using the UTC time zone to support + the reproducible build effort. (automake bug#20314) + + - The elisp byte-compilation rule now uses byte-compile-dest-file-function, + rather than byte-compile-dest-file, which was obsoleted in 2009. We expect + that Emacs-26 will continue to support the old function, but will complain + loudly, and that Emacs-27 will remove support for it altogether. + +* New features added + + - A custom testsuite driver for the Guile Scheme SRFI-64 API has been added + to the "contrib" section. This allows a more convenient way to test Guile + code without having to use low primitives such as exit status. See + SRFI-64 API specification for more details: + + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.15.1: + +* Bugs fixed: + + - The code has been adapted to remove a warning present since Perl + 5.22 stating that "Unescaped left brace in regex is deprecated". + This warning has become an hard error in Perl 5.26 (bug#22372). + + - The generated Makefiles do not rely on the obsolescent GZIP + environment variable which was used for passing arguments to + 'gzip'. Compatibility with old versions has been + preserved. (bug#20132) + +* Miscellaneous changes: + + - Support the Windows version of the Intel C Compiler (icl) in the + 'compile' script in the same way the (compatible) Microsoft C + Compiler is supported. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.15: + +* Improvements and refactorings in the install-sh script: + + - It has been modernized, and now makes the following assumptions + *unconditionally*: + (1) a working 'dirname' program is available; + (2) the ${var:-value} shell parameters substitution works; + (3) the "set -f" and "set +f" shell commands work, and, respectively, + disable and enable shell globbing. + + - The script implements stricter error checking, and now it complains + and bails out if any of the following expectations is not met: + (1) the options -d and -t are never used together; + (2) the argument passed to option -t is a directory; + (3) if there are two or more SOURCEFILE arguments, the + DESTINATION argument must be a directory. + +* Automake-generated testsuites: + + - The default test-driver used by the Automake-generated testsuites + now appends the result and exit status of each "plain" test to the + associated log file (automake bug#11814). + + - The perl implementation of the TAP testsuite driver is no longer + installed in the Automake's scripts directory, and is instead just + distributed as a "contrib" addition. There should be no reason to + use this implementation anyway in real packages, since the awk+shell + implementation of the TAP driver (which is documented in the manual) + is more portable and has feature parity with the perl implementation. + + - The rule generating 'test-suite.log' no longer risk incurring in an + extra useless "make all" recursive invocation in some corner cases + (automake bug#16302). + +* Distribution: + + - Automake bug#18286: "make distcheck" could sometimes fail to detect + files missing from the distribution tarball, especially in those cases + where both the generated files and their dependencies are explicitly + in $(srcdir). An important example of this are *generated* makefile + fragments included at Automake time in Makefile.am; e.g.: + + ... + $(srcdir)/fragment.am: $(srcdir)/data.txt $(srcdir)/preproc.sh + cd $(srcdir) && $(SHELL) preproc.sh fragment.am + include $(srcdir)/fragment.am + ... + + If the use forgot to add data.txt and/or preproc.sh in the distribution + tarball, "make distcheck" would have erroneously succeeded! This issue + is now fixed. + + - As a consequence of the previous change, "make distcheck" will run + using '$(distdir)/_build/sub' as the build directory, rather than + simply '$(distdir)/_build' (as it was the case for Automake 1.14 and + earlier). Consequently, the './configure' and 'make' invocations + issued by the distcheck recipe now have $(srcdir) equal to '../..', + rather than to just '..'. Dependent and similar variables (e.g., + '$(top_srcdir)') are also changed accordingly. + + Thus, Makefiles that made assumptions about the exact values of the + build and source directories used by "make distcheck" will have to + be adjusted. Notice that making such assumptions was a bad and + unsupported practice anyway, since the exact locations of those + directories should be considered implementation details, and we + reserve the right to change them at any time. + +* Miscellaneous bugs fixed: + + - The expansion of AM_INIT_AUTOMAKE ends once again with a trailing + newline (bug#16841). Regression introduced in Automake 1.14. + + - We no longer risk to use '$ac_aux_dir' before it's defined (see + automake bug#15981). Bug introduced in Automake 1.14. + + - The code used to detect whether the currently used make is GNU make + or not (relying on the private macro 'am__is_gnu_make') no longer + risks causing "Arg list too long" for projects using automatic + dependency tracking and having a ton of source files (bug#18744). + + - Automake tries to offer a more deterministic output for generated + Makefiles, in the face of the newly-introduced randomization for + hash keys order in Perl 5.18. + + - In older Automake versions, if a user defined one single Makefile + fragment (say 'foo.am') to be included via Automake includes in + his main Makefile.am, and defined a custom make rule to generate that + file from other data, Automake used to spuriously complain with some + message like "... overrides Automake target '$(srcdir)/foo.am". + This bug is now fixed. + + - The user can now extend the special .PRECIOUS target, the same way + he could already do with the .MAKE .and .PHONY targets. + + - Some confusing typos have been fixed in the manual and in few warning + messages (automake bug#16827 and bug#16997). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.14.1: + +* Bugs fixed: + + - The user is no longer allowed to override the --srcdir nor the --prefix + configure options used by "make distcheck" (bug#14991). + + - Fixed a gross inefficiency in the recipes for installing byte-compiled + python files, that was causing an O(N^2) performance on the number N of + files, instead of the expected O(N) performance. Note that this bug + was only relevant when the number of python files was high (which is + unusual in practice). + + - Automake try to offer a more deterministic output for warning messages, + in the face of the newly-introduced randomization for hash keys order + in Perl 5.18. + + - The 'test-driver' script now actually error out with a clear error + message on the most common invalid usages. + + - Several spurious failures/hangs in the testsuite (bugs #14706, #14707, + #14760, #14911, #15181, #15237). + +* Documentation fixes: + + - Fixed typos in the 'fix-timestamp.sh' example script that made it + nonsensical. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.14: + +* C compilation, and the AC_PROG_CC and AM_PROG_CC_C_O macros: + + - The 'compile' script is now unconditionally required for all packages + that perform C compilation (if you are using the '--add-missing' + option, automake will fetch that script for you, so you shouldn't + need any explicit adjustment). This new behaviour is needed to avoid + obscure errors when the 'subdir-objects' option is used, and the + compiler is an inferior one that doesn't grasp the combined use of + both the "-c -o" options; see discussion about automake bug#13378 for + more details: + + + + - The next major Automake version (2.0) will unconditionally activate + the 'subdir-objects' option. In order to smooth out the transition, + we now give a warning (in the category 'unsupported') whenever a + source file is present in a subdirectory but the 'subdir-object' is + not enabled. For example, the following usage will trigger such a + warning: + + bin_PROGRAMS = sub/foo + sub_foo_SOURCES = sub/main.c sub/bar.c + + - Automake will automatically enhance the autoconf-provided macro + AC_PROG_CC to force it to check, at configure time, that the + C compiler supports the combined use of both the '-c' and '-o' + options. The result of this check is saved in the cache variable + 'am_cv_prog_cc_c_o', and said result can be overridden by + pre-defining that variable. + + - The AM_PROG_CC_C_O macro can still be called, albeit that should no + longer be necessary. This macro is now just a thin wrapper around the + Automake-enhanced AC_PROG_CC. This means, among the other things, + that its behaviour is changed in three ways: + + 1. It no longer invokes the Autoconf-provided AC_PROG_CC_C_O + macro behind the scenes. + + 2. It caches the check result in the 'am_cv_prog_cc_c_o' variable, + and not in a 'ac_cv_prog_cc_*_c_o' variable whose exact name is + dynamically computed only at configure runtime (really!) from + the content of the '$CC' variable. + + 3. It no longer automatically AC_DEFINE the C preprocessor + symbol 'NO_MINUS_C_MINUS_O'. + +* Texinfo support: + + - Automake can now be instructed to place '.info' files generated from + Texinfo input in the builddir rather than in the srcdir; this is done + specifying the new automake option 'info-in-builddir'. This feature + was requested by the developers of GCC, GDB, GNU binutils and the GNU + bfd library. See the extensive discussion about automake bug#11034 + for more details. + + - For quite a long time, Automake has been implementing an undocumented + hack which ensured that '.info' files which appeared to be cleaned + (by being listed in the CLEANFILES or DISTCLEANFILES variables) were + built in the builddir rather than in the srcdir; this hack was + introduced to ensure better backward-compatibility with package + such as Texinfo, which do things like: + + info_TEXINFOS = texinfo.txi info-stnd.texi info.texi + DISTCLEANFILES = texinfo texinfo-* info*.info* + # Do not create info files for distribution. + dist-info: + @: + + in order not to distribute generated '.info' files. + + Now that we have the 'info-in-builddir' option that explicitly causes + generated '.info' files to be placed in the builddir, this hack should + be longer necessary, so we deprecate it with runtime warnings. + It will be removed altogether in Automake 2.0. + +* Relative directory in Makefile fragments: + + - The special Automake-time substitutions '%reldir%' and '%canon_reldir%' + (and their short versions, '%D%' and '%C%' respectively) can now be used + in an included Makefile fragment. The former is substituted with the + relative directory of the included fragment (compared to the top-level + including Makefile), and the latter with the canonicalized version of + the same relative directory. + + # in 'Makefile.am': + bin_PROGRAMS = # will be updated by included Makefile fragments + include src/Makefile.inc + + # in 'src/Makefile.inc': + bin_PROGRAMS += %reldir%/foo + %canon_reldir%_foo_SOURCES = %reldir%/bar.c + + This should be especially useful for packages using a non-recursive + build system. + +* Deprecated distribution formats: + + - The 'shar' and 'compress' distribution formats are deprecated, and + scheduled for removal in Automake 2.0. Accordingly, the use of the + 'dist-shar' and 'dist-tarZ' will cause warnings at automake runtime + (in the 'obsolete' category), and the recipes of the Automake-generated + targets 'dist-shar' and 'dist-tarZ' will unconditionally display + (non-fatal) warnings at make runtime. + +* New configure runtime warnings about "rm -f" support: + + - To simplify transition to Automake 2.0, the shell code expanded by + AM_INIT_AUTOMAKE now checks (at configure runtime) that the default + 'rm' program in PATH doesn't complain when called without any + non-option argument if the '-f' option is given (so that commands like + "rm -f" and "rm -rf" act as a no-op, instead of raising usage errors). + If this is not the case, the configure script is aborted, to call the + attention of the user on the issue, and invite him to fix his PATH. + The checked 'rm' behavior is very widespread in the wild, and will be + required by future POSIX versions: + + + + The user can still force the configure process to complete even in the + presence of a broken 'rm' by defining the ACCEPT_INFERIOR_RM_PROGRAM + environment variable to "yes". And the generated Makefiles should + still work correctly even when such broken 'rm' is used. But note + that this will no longer be the case with Automake 2.0 though, so, if + you encounter the warning, please report it to us ASAP (and try to fix + your environment as well). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.13.4: + +* Bugs fixed: + + - Fix a minor regression introduced in Automake 1.13.3: when two or more + user-defined suffix rules were present in a single Makefile.am, + automake would needlessly include definition of some make variables + related to C compilation in the generated Makefile.in (bug#14560). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.13.3: + +* Documentation fixes: + + - The documentation no longer mistakenly reports that the obsolete + 'AM_MKDIR_PROG_P' macro and '$(mkdir_p)' make variable are going + to be removed in Automake 2.0. + +* Bugs fixed: + + - Byte-compilation of Emacs lisp files could fail spuriously on + Solaris, when /bin/ksh or /usr/xpg4/bin/sh were used as shell. + + - If the same user-defined suffixes were transformed into different + Automake-known suffixes in different Makefile.am files in the same + project, automake could get confused and generate inconsistent + Makefiles (automake bug#14441). + For example, if 'Makefile.am' contained a ".ext.cc:" suffix rule, + and 'sub/Makefile.am' contained a ".ext.c:" suffix rule, automake + would have mistakenly placed into 'Makefile.in' rules to compile + "*.c" files into object files, and into 'sub/Makefile.in' rules to + compile "*.cc" files into object files --- rather than the other + way around. This is now fixed. + +* Testsuite work: + + - The test cases no longer have the executable bit set. This should + make it clear that they are not meant to be run directly; as + explained in t/README, they can only be run through the custom + 'runtest' script, or by a "make check" invocation. + + - The testsuite has seen the introduction of a new helper function + 'run_make', and several related changes. These serve a two-fold + purpose: + + 1. Remove brittleness due to the use of "make -e" in test cases. + + 2. Seamlessly allow the use of parallel make ("make -j...") in the + test cases, even where redirection of make output is involved + (see automake bug#11413 for a description of the subtle issues + in this area). + + - Several spurious failures have been fixed (they hit especially + MinGW/MSYS builds). See automake bugs #14493, #14494, #14495, + #14498, #14499, #14500, #14501, #14517 and #14528. + + - Some other minor miscellaneous changes and fixlets. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.13.2: + +* Documentation fixes: + + - The long-deprecated but still supported two-arguments invocation form + of AM_INIT_AUTOMAKE is documented once again. This seems the sanest + thing to do, given that support for such usage might need to remain + in place for an unspecified amount of time in order to cater to people + who want to define the version number for their package dynamically at + configure runtime (unfortunately, Autoconf does not yet support this + scenario, so we cannot delegate the work to it). + + - The serial testsuite harness is no longer reported as "deprecated", + but as "discouraged". We have no plan to remove it, nor to make its + use cause runtime warnings. + + - The parallel testsuite is no longer reported as "experimental"; it + is well tested, and should be stable now. + + - The 'shar' and 'tarZ' distribution formats and the 'dist-shar' and + 'dist-tarZ' options are obsolescent, and their use is deprecated + in the documentation. + + - Other minor miscellaneous fixes and improvements; in particular, + some improvements in cross-references. + +* Obsolescent features: + + - Use of suffix-less info files (that can be specified through the + '@setfilename' macro in Texinfo input files) is discouraged, and + its use will raise warnings in the 'obsolete' category. Simply + use the '.info' extension for all your info files, transforming + usages like: + + @setfilename myprogram + + into: + + @setfilename myprogram.info + + - Use of Texinfo input files with '.txi' or '.texinfo' extensions + is discouraged, and its use will raise warnings in the 'obsolete' + category. You are advised to simply use the '.texi' extension + instead. + +* Bugs fixed: + + - When the 'ustar' option is used, the generated configure script no + longer risks hanging during the tests for the availability of the + 'pax' utility, even if the user running configure has a UID or GID + that requires more than 21 bits to be represented. + See automake bug#8343 and bug#13588. + + - The obsolete macros AM_CONFIG_HEADER or AM_PROG_CC_STDC work once + again, as they did in Automake 1.12.x (albeit printing runtime + warnings in the 'obsolete' category). Removing them has turned + out to be a very bad idea, because it complicated distro packing + enormously. Making them issue fatal warnings, as we did in + Automake 1.13, has turned out to be a similarly very bad idea, + for exactly the same reason. + + - aclocal will no longer error out if the first local m4 directory + (as specified by the '-I' option or the 'AC_CONFIG_MACRO_DIRS' or + 'AC_CONFIG_MACRO_DIR' macros) doesn't exist; it will merely report + a warning in the 'unsupported' category. This is done to support + some pre-existing real-world usages. See automake bug#13514. + + - aclocal will no longer consider directories for extra m4 files more + than once, even if they are specified multiple times. This ensures + packages that specify both + + AC_CONFIG_MACRO_DIR([m4]) in configure.ac + ACLOCAL_AMFLAGS = -I m4 in Makefile.am + + will work correctly, even when the 'm4' directory contains no + package-specific files, but is used only to install third-party + m4 files (as can happen with e.g., "libtoolize --install"). + See automake bug#13514. + + - Analysis of make flags in Automake-generated rules has been made more + robust, and more future-proof. For example, in presence of make that + (like '-I') take an argument, the characters in said argument will no + longer be spuriously considered as a set of additional make options. + In particular, automake-generated rules will no longer spuriously + believe to be running in dry mode ("make -n") if run with an invocation + like "make -I noob"; nor will they believe to be running in keep-going + mode ("make -k") if run with an invocation like "make -I kool" + (automake bug#12554). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.13.1: + +* Bugs fixed: + + - Use of the obsolete macros AM_CONFIG_HEADER or AM_PROG_CC_STDC now + causes a clear and helpful error message, instead of obscure ones + (issue introduced in Automake 1.13). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.13: + +* Bugs fixed: + + - ylwrap renames properly header guards in generated header files + (*.h), instead of leaving Y_TAB_H. + + - ylwrap now also converts header guards in implementation files + (*.c). Because ylwrap failed to rename properly #include in the + implementation files, current versions of Bison (e.g., 2.7) + duplicate the generated header file in the implementation file. + The header guard then protects the implementation file from + duplicate definitions from the header file. + +* Version requirements: + + - Autoconf 2.65 or greater is now required. + + - The rules to build PDF and DVI output from Texinfo input now + require Texinfo 4.9 or later. + +* Obsolete features: + + - Support for the "Cygnus-style" trees (once enabled by the 'cygnus' + option) has been removed. See discussion about automake bug#11034 + for more background: . + + - The deprecated aclocal option '--acdir' has been removed. You + should use the options '--automake-acdir' and '--system-acdir' + instead (which have been introduced in Automake 1.11.2). + + - The following long-obsolete m4 macros have been removed: + + AM_PROG_CC_STDC: superseded by AC_PROG_CC since October 2002 + fp_PROG_CC_STDC: broken alias for AM_PROG_CC_STDC + fp_WITH_DMALLOC: old alias for AM_WITH_DMALLOC + AM_CONFIG_HEADER: superseded by AC_CONFIG_HEADERS since July 2002 + ud_PATH_LISPDIR: old alias for AM_PATH_LISPDIR + jm_MAINTAINER_MODE: old alias for AM_MAINTAINER_MODE + ud_GNU_GETTEXT: old alias for AM_GNU_GETTEXT + gm_PROG_LIBTOOL: old alias for AC_PROG_LIBTOOL + fp_C_PROTOTYPES: old alias for AM_C_PROTOTYPES (which was part + of the now-removed automatic de-ANSI-fication + support of Automake) + + - All the "old alias" macros in 'm4/obsolete.m4' have been removed. + + - Use of the long-deprecated two- and three-arguments invocation forms + of the AM_INIT_AUTOMAKE is no longer documented. It's still supported + though (albeit with a warning in the 'obsolete' category), to cater + for people who want to define the version number for their package + dynamically (e.g., from the current VCS revision). We'll have to + continue this support until Autoconf itself is fixed to allow better + support for such dynamic version numbers. + +* Elisp byte-compilation: + + - The byte compilation of '.el' files into '.elc' files is now done + with a suffix rule. This has simplified the compilation process, and + more importantly made it less brittle. The downside is that emacs is + now invoked once for each '.el' files, which cause some noticeable + slowdowns. These should however be mitigated on multicore machines + (which are becoming the norm today) if concurrent make ("make -j") + is used. + + - Elisp files placed in a subdirectory are now byte-compiled to '.elc' + files in the same subdirectory; for example, byte-compiling of file + 'sub/foo.el' file will result in 'sub/foo.elc' rather than in + 'foo.elc'. This behaviour is backward-incompatible with older + Automake versions, but it is more natural and more sane. See also + automake bug#7441. + + - The Emacs invocation performing byte-compilation of '.el' files honors + the $(AM_ELCFLAGS) and $(ELCFLAGS) variables; as typical, the former + one is developer-reserved and the latter one user-reserved. + + - The 'elisp-comp' script, once provided by Automake, has been rendered + obsoleted by the just-described changes, and thus removed. + +* Changes to Automake-generated testsuite harnesses: + + - The parallel testsuite harness (previously only enabled by the + 'parallel-tests' option) is the default one; the older serial + testsuite harness will still be available through the use of the + 'serial-tests' option (introduced in Automake 1.12). + + - The 'color-tests' option is now unconditionally activated by default. + In particular, this means that testsuite output is now colorized by + default if the attached terminal seems to support ANSI escapes, and + that the user can force output colorization by setting the variable + AM_COLOR_TESTS to "always". The 'color-tests' is still recognized + for backward-compatibility, although it's a handled as a no-op now. + +* Silent rules support: + + - Support for silent rules is now always active in Automake-generated + Makefiles. So, although the verbose output is still the default, + the user can now always use "./configure --enable-silent-rules" or + "make V=0" to enable quieter output in the package he's building. + + - The 'silent-rules' option has now become a no-op, preserved for + backward-compatibility only. In particular, its use no longer + disables the warnings in the 'portability-recursive' category. + +* Texinfo Support: + + - The rules to build PDF and DVI files from Texinfo input now require + Texinfo 4.9 or later. + + - The rules to build PDF and DVI files from Texinfo input now use the + '--build-dir' option, to keep the auxiliary files used by texi2dvi + and texi2pdf around without cluttering the build directory, and to + make it possible to run the "dvi" and "pdf" recipes in parallel. + +* Automatic remake rules and 'missing' script: + + - The 'missing' script no longer tries to update the timestamp of + out-of-date files that require a maintainer-specific tool to be + remade, in case the user lacks such a tool (or has a too-old version + of it). It just gives a useful warning, and in some cases also a + tip about how to obtain such a tool. + + - The missing script has thus become useless as a (poor) way to work + around the sketched-timestamps issues that can happen for projects + that keep generated files committed in their VCS repository. Such + projects are now encouraged to write a custom "fix-timestamps.sh" + script to avoid such issues; a simple example is provided in the + "CVS and generated files" chapter of the automake manual. + +* Recursive targets: + + - The user can now define his own recursive targets that recurse + in the directories specified in $(SUBDIRS). This can be done by + specifying the name of such targets in invocations of the new + 'AM_EXTRA_RECURSIVE_TARGETS' m4 macro. + +* Tags: + + - Any failure in the recipe of the "tags", "ctags", "cscope" or + "cscopelist" targets in a subdirectory is now propagated to the + top-level make invocation. + + - Tags are correctly computed also for files in _SOURCES variables that + only list files with non-standard suffixes (see automake bug#12372). + +* Improvements to aclocal and related rebuilds rules: + + - Autoconf-provided macros AC_CONFIG_MACRO_DIR and AC_CONFIG_MACRO_DIRS + are now traced by aclocal, and can be used to declare the local m4 + include directories. Formerly, one had to specify it with an explicit + '-I' option to the 'aclocal' invocation. + + - The special make variable ACLOCAL_AMFLAGS is deprecated; future + Automake versions will warn about its use, and later version will + remove support for it altogether. + +* The depcomp script: + + - Dropped support for libtool 1.4. + + - Various internal refactorings. They should cause no visible change, + but the chance for regression is there anyway, so please report any + unexpected or suspicious behaviour. + + - Support for pre-8.0 versions of the Intel C Compiler has been dropped. + This should cause no problem, since icc 8.0 has been released in + December 2003 -- almost nine years ago. + + - Support for tcc (the Tiny C Compiler) has been improved, and is now + handled through a dedicated 'tcc' mode. + +* The ylwrap script: + + - ylwrap generates header guards with a single '_' for series of non + alphabetic characters, instead of several. This is what Bison >= + 2.5.1 does. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.12.6: + +* Python-related bugs: + + - The default installation location for python modules has been improved + for Python 3 on Debian and Ubuntu systems, changing from: + + ${prefix}/lib/python3/dist-packages + + to + + ${prefix}/lib/python3.x/site-packages + + This change should ensure modules installed using the default ${prefix} + "/usr/local" are found by default by system python 3.x installations. + See automake bug#10227. + + - Python byte-compilation supports the new layout mandated by PEP-3147, + with its __pycache__ directory (automake bug#8847). + +* Build system issues: + + - The maintainer rebuild rules for Makefiles and aclocal.m4 in + Automake's own build system works correctly again (bug introduced + in Automake 1.12.5). + +* Testsuite issues: + + - The Vala-related tests has been changed to adjust to the removal of + the 'posix' profile in the valac compiler. See automake bug#12934 + a.k.a. bug#12522. + + - Some spurious testsuite failures related to older tools and systems + have been fixed. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12.5: + +* Vala support: + + - The AM_PROG_VALAC macro has been enhanced to takes two further + optional arguments; it's signature now being + + AM_PROG_VALAC([MINIMUM-VERSION], [ACTION-IF-FOUND], + [ACTION-IF-NOT-FOUND]) + + - By default, AM_PROG_VALAC no longer aborts the configure invocation + if the Vala compiler found is too old, but simply prints a warning + messages (as it did when the Vala compiler was not found). This + should avoid unnecessary difficulties for end users that just want + to compile the unmodified, distributed Vala-generated C sources, + but happens to have an old Vala compiler in their PATH. This fixes + automake bug#12688. + + - If no proper Vala compiler is found at configure runtime, AM_PROG_VALAC + will set the AC_SUBST'd variable 'VALAC' to 'valac' rather than to ':'. + This is a better default, because with it a triggered makefile rule + invoking a Vala compilation will clearly fail with an informative error + message like "valac: command not found", rather than silently, with + the error possibly going unnoticed or triggering harder-to-diagnose + fallout failures in later steps. + +* Miscellaneous changes: + + - automake and aclocal no longer honours the 'perllibdir' environment + variable. That had always been intended only as an hack required in + the testsuite, not meant for any use beyond that. + +Bugs fixed in 1.12.5: + +* Long-standing bugs: + + - Automake no longer generates spurious remake rules invoking autoheader + to regenerate the template corresponding to header files specified after + the first one in AC_CONFIG_HEADERS (automake bug#12495). + + - When wrapping Microsoft tools, the 'compile' script falls back to + finding classic 'libname.a' style libraries when 'name.lib' and + 'name.dll.lib' aren't available. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12.4: + +* Warnings and deprecations: + + - Warnings in the 'obsolete' category are enabled by default both in + automake and aclocal. + +* Miscellaneous changes: + + - Some testsuite weaknesses and spurious failures have been fixed. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12.3: + +* Miscellaneous changes: + + - The '.m4' files provided by Automake no longer define serial numbers. + This should cause no difference in the behaviour of aclocal though. + + - Some testsuite weaknesses and spurious failures have been fixed. + + - There is initial support for automatic dependency tracking with the + Portland Group C/C++ compilers, thanks to the new new depmode 'pgcc'. + +Bugs fixed in 1.12.3: + +* Long-standing bugs: + + - Instead of renaming only self-references of files (typically for + #lines), ylwrap now also renames references to the other generated + files. This fixes support for GLR and C++ parsers from Bison (PR + automake/491 and automake bug#7648): 'parser.c' now properly + #includes 'parser.h' instead of 'y.tab.h'. + + - Generated files unknown to ylwrap are now preserved. This fixes + C++ support for Bison (automake bug#7648): location.hh and the + like are no longer discarded. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12.2: + +* Warnings and deprecations: + + - Automake now issues a warning (in the 'portability' category) if + 'configure.in' is used instead of 'configure.ac' as the Autoconf + input file. Such a warning will also be present in the next + Autoconf version (2.70). + +* Cleaning rules: + + - Recursive cleaning rules descends into the $(SUBDIRS) in the natural + order (as done by the other recursive rules), rather than in the + inverse order. They used to do that in order to work a round a + limitation in an older implementation of the automatic dependency + tracking support, but that limitation had been lifted years ago + already, when the automatic dependency tracking based on side-effects + of compilation had been introduced. + + - Cleaning rules for compiled objects (both "plain" and libtool) work + better when subdir objects are involved, not triggering a distinct + 'rm' invocation for each such object. They do so by removing *any* + compiled object file that is in the same directory of a subdir + object. See automake bug#10697. + +* Silent rules support: + + - A new predefined $(AM_V_P) make variable is provided; it expands + to a shell conditional that can be used in recipes to know whether + make is being run in silent or verbose mode. + +Bugs fixed in 1.12.2: + +* SECURITY VULNERABILITIES! + + - The 'distcheck' recipe no longer grants temporary world-write + permissions on the extracted distdir. Even if such rights were + only granted for a vanishingly small time window, the implied + race condition proved to be enough to allow a local attacker + to run arbitrary code with the privileges of the user running + "make distcheck". This is CVE-2012-3386. + +* Long-standing bugs: + + - The "recheck" targets behaves better in the face of build failures + related to previously failed tests. For example, if a test is a + compiled program that must be rerun by "make recheck", and its + compilation fails, it will still be rerun by further "make recheck" + invocations. See automake bug#11791. + +* Bugs introduced by 1.12.1: + + - Automake provides once again the '$(mkdir_p)' make variable and the + '@mkdir_p@' substitution (both as simple aliases for '$(MKDIR_P)'), + for better backward-compatibility. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12.1: + +* New supported languages: + + - Support for Objective C++ has been added; it should work similarly to + the support for Objective C. + +* Deprecated obsolescent features: + + - Use of the long-deprecated two- and three-arguments invocation forms + of the AM_INIT_AUTOMAKE macro now elicits a warning in the 'obsolete' + category. Starting from some future major Automake release (likely + post-1.13), such usages will no longer be allowed. + + - Support for the "Cygnus-style" trees (enabled by the 'cygnus' option) is + now deprecated (its use triggers a warning in the 'obsolete' category). + It will be removed in the next major Automake release (1.13). + + - The long-obsolete (since 1.10) automake-provided $(mkdir_p) make + variable, @mkdir_p@ configure-time substitution and AM_PROG_MKDIR + m4 macro are deprecated, eliciting a warning in the 'obsolete' + category. + +* Miscellaneous changes: + + - The Automake test cases now require a proper POSIX-conforming shell. + Older non-POSIX Bourne shells (like Solaris 10 /bin/sh) will no longer + be accepted. In most cases, the user shouldn't have to specify such + POSIX shell explicitly, since it will be looked up at configure time. + Still, when this lookup fails, or when the user wants to override its + conclusion, the variable 'AM_TEST_RUNNER_SHELL' can be used (pointing + to the shell that will be used to run the Automake test cases). + +Bugs fixed in 1.12.1: + +* Bugs introduced by 1.12: + + - Several weaknesses in Automake's own build system and test suite + have been fixed. + +* Bugs introduced by 1.11.3: + + - When given non-option arguments, aclocal rejects them, instead of + silently ignoring them. + +* Long-standing bugs: + + - When the 'color-tests' option is in use, forcing of colored testsuite + output through "AM_COLOR_TESTS=always" works even if the terminal is + a non-ANSI one, i.e., if the TERM environment variable has a value of + "dumb". + + - Several inefficiencies and poor performances in the implementation + of the parallel-tests 'check' and 'recheck' targets have been fixed. + + - The post-processing of output "#line" directives done the ylwrap + script is more faithful w.r.t. files in a subdirectory; for example, + if the processed file is "src/grammar.y", ylwrap will correctly + produce directives like: + #line 7 "src/grammar.y" + rather than like + #line 7 "grammar.y" + as it did before. + +* Bugs with new Perl versions: + + - Aclocal works correctly with perl 5.16.0 (automake bug#11543). + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.12: + +* Obsolete features removed: + + - The never documented nor truly used script 'acinstall' has been + removed. + + - Support for automatic de-ANSI-fication has been removed. + + - The support for the "obscure" multilib feature has been removed + from Automake core (but remains available in the 'contrib/' + directory of the Automake distribution). + + - Support for ".log -> .html" conversion and the check-html and + recheck-html targets has been removed from Automake core (but + remains available in the 'contrib/' directory of the Automake + distribution). + + - The deprecated 'lzma' compression format for distribution archives + has been removed, in favor of 'xz' and 'lzip'. + + - The obsolete AM_WITH_REGEX macro has been removed. + + - The long-deprecated options '--output-dir', '--Werror' and + '--Wno-error' have been removed. + + - The chapter on the history of Automake has been moved out of the + reference manual, into a new dedicated Texinfo file. + +* New targets: + + - New 'cscope' target to build a cscope database for the source tree. + +* Changes to Automake-generated testsuite harnesses: + + - The new automake option 'serial-tests' has been introduced. It can + be used to explicitly instruct automake to use the older serial + testsuite harness. This is still the default at the moment, but it + might change in future versions. + + - The 'recheck' target (provided by the parallel testsuite harness) now + depends on the 'all' target. This allows for a better user-experience + in test-driven development. See automake bug#11252. + + - Test scripts that exit with status 99 to signal an "hard error" (e.g., + and unexpected or internal error, or a failure to set up the test case + scenario) have their outcome reported as an 'ERROR' now. Previous + versions of automake reported such an outcome as a 'FAIL' (the only + difference with normal failures being that hard errors were counted + as failures even when the test originating them was listed in + XFAIL_TESTS). + + - The testsuite summary displayed by the parallel-test harness has a + completely new format, that always list the numbers of passed, failed, + xfailed, xpassed, skipped and errored tests, even when these numbers + are zero (but using smart coloring when the color-tests option is in + effect). + + - The default testsuite driver offered by the 'parallel-tests' option is + now implemented (partly at least) with the help of automake-provided + auxiliary scripts (e.g., 'test-driver'), instead of relying entirely + on code in the generated Makefile.in. + This has two noteworthy implications. The first one is that projects + using the 'parallel-tests' option should now either run automake with + the '--add-missing' option, or manually copy the 'test-driver' script + into their tree. The second, and more important, implication is that + now, when the 'parallel-tests' option is in use, TESTS_ENVIRONMENT can + no longer be used to define a test runner, and the command specified + in LOG_COMPILER (and _LOG_COMPILER) must be a *real* executable + program or script. For example, this is still a valid usage (albeit + a little contorted): + + TESTS_ENVIRONMENT = \ + if test -n '$(STRICT_TESTS)'; then \ + maybe_errexit='-e'; \ + else \ + maybe_errexit=''; \ + fi; + LOG_COMPILER = $(SHELL) $$maybe_errexit + + OTOH, this is no longer a valid usage: + + TESTS_ENVIRONMENT = \ + $(SHELL) `test -n '$(STRICT_TESTS_CHECKING)' && echo ' -e'` + + neither is this: + + TESTS_ENVIRONMENT = \ + run_with_perl_or_shell () \ + { \ + if grep -q '^#!.*perl' $$1; then + $(PERL) $$1; \ + else \ + $(SHELL) $$1; \ + fi; \ + } + LOG_COMPILER = run_with_perl_or_shell + + - The package authors can now use customary testsuite drivers within + the framework provided by the 'parallel-tests' testsuite harness. + Consistently with the existing syntax, this can be done by defining + special makefile variables 'LOG_DRIVER' and '_LOG_DRIVER'. + + - A new developer-reserved variable 'AM_TESTS_FD_REDIRECT' can be used + to redirect/define file descriptors used by the test scripts. + + - The parallel-tests harness generates now, in addition the '.log' files + holding the output produced by the test scripts, a new set of '.trs' + files, holding "metadata" derived by the execution of the test scripts; + among such metadata are the outcomes of the test cases run by a script. + + - Initial and still experimental support for the TAP test protocol is + now provided. + +* Changes to Yacc and Lex support: + + - C source and header files derived from non-distributed Yacc and/or + Lex sources are now removed by a simple "make clean" (while they were + previously removed only by "make maintainer-clean"). + + - Slightly backward-incompatible change, relevant only for use of Yacc + with C++: the extensions of the header files produced by the Yacc + rules are now modelled after the extension of the corresponding + sources. For example, yacc files named "foo.y++" and "bar.yy" will + produce header files named "foo.h++" and "bar.hh" respectively, where + they would have previously produced header files named simply "foo.h" + and "bar.h". This change offers better compatibility with 'bison -o'. + +* Miscellaneous changes: + + - The AM_PROG_VALAC macro now causes configure to exit with status 77, + rather than 1, if the vala compiler found is too old. + + - The build system of Automake itself now avoids the use of make + recursion as much as possible. + + - Automake now prefers to quote 'like this' or "like this", rather + than `like this', in diagnostic message and generated Makefiles, + to accommodate the new GNU Coding Standards recommendations. + + - Automake has a new option '--print-libdir' that prints the path of the + directory containing the Automake-provided scripts and data files. + + - The 'dist' and 'dist-all' targets now can run compressors in parallel. + + - The rules to create pdf, dvi and ps output from Texinfo files now + works better with modern 'texi2dvi' script, by explicitly passing + it the '--clean' option to ensure stray auxiliary files are not + left to clutter the build directory. + + - Automake can now generate silenced rules for texinfo outputs. + + - Some auxiliary files that are automatically distributed by Automake + (e.g., 'install-sh', or the 'depcomp' script for packages compiling + C sources) might now be listed in the DIST_COMMON variable in many + Makefile.in files, rather than in the top-level one. + + - Messages of types warning or error from 'automake' and 'aclocal' + are now prefixed with the respective type, and presence of -Werror + is noted. + + - Automake's early configure-time sanity check now tries to avoid + sleeping for a second, which slowed down cached configure runs + noticeably. In that case, it will check back at the end of the + configure script to ensure that at least one second has passed, to + avoid time stamp issues with makefile rules rerunning autotools + programs. + + - The warnings in the category 'extra-portability' are now enabled by + '-Wall'. In previous versions, one has to use '-Wextra-portability' + to enable them. + +Bugs fixed in 1.12: + + - Various minor bugfixes for recent or long-standing bugs. + +* Bugs introduced by 1.11: + + - The AM_COND_IF macro also works if the shell expression for the + conditional is no longer valid for the condition. + + - The automake-provided parallel testsuite harness no longer fails + with BSD make used in parallel mode when there are test scripts in + a subdirectory, like in: + + TESTS = sub/foo.test sub/bar.test + +* Long-standing bugs: + + - Automake's own build system finally have a real "installcheck" target. + + - Vala-related cleanup rules are now more complete, and work better in + a VPATH setup. + + - Files listed with the AC_REQUIRE_AUX_FILE macro in configure.ac are + now automatically distributed also if the directory of the auxiliary + files coincides with the top-level directory. + + - Automake now detects the presence of the '-d' flag in the various + '*YFLAGS' variables even when their definitions involve indirections + through other variables, such as in: + foo_opts = -d + AM_YFLAGS = $(foo_opts) + + - Automake now complains if a '*YFLAGS' variable has any conditional + content, not only a conditional definition. + + - Explicit enabling and/or disabling of Automake warning categories + through the '-W...' options now always takes precedence over the + implicit warning level implied by Automake strictness (foreign, gnu + or gnits), regardless of the order in which such strictness and + warning flags appear. For example, a setting like: + AUTOMAKE_OPTIONS = -Wall --foreign + will cause the warnings in category 'portability' to be enabled, even + if those warnings are by default disabled in 'foreign' strictness. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.11.5: + +* Bugs introduced by 1.11.3: + + - Vala files with '.vapi' extension are now recognized and handled + correctly again. See automake bug#11222. + + - Vala support work again for projects that contain some program + built from '.vala' (and possibly '.c') sources and some other + program built from '.c' sources *only*. See automake bug#11229. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.11.4: + +* Miscellaneous changes: + + - The 'ar-lib' script now ignores the "s" (symbol index) and "S" (no + symbol index) modifiers as well as the "s" action, as the symbol index + is created unconditionally by Microsoft lib. Also, the "q" (quick) + action is now a synonym for "r" (replace). Also, the script has been + ignoring the "v" (verbose) modifier already since Automake 1.11.3. + + - When the 'compile' script is used to wrap MSVC, it now accepts an + optional space between the -I, -L and -l options and their respective + arguments, for better POSIX compliance. + + - There is an initial, experimental support for automatic dependency + tracking with tcc (the Tiny C Compiler). Its associated depmode is + currently recognized as "icc" (but this and other details are likely + to change in future versions). + + - Automatic dependency tracking now works also with the IBM XL C/C++ + compilers, thanks to the new new depmode 'xlc'. + +Bugs fixed in 1.11.4: + +* Bugs introduced by 1.11.2: + + - A definition of 'noinst_PYTHON' before 'python_PYTHON' (or similar) + no longer cause spurious failures upon "make install". + + - The user can now instruct the 'uninstall-info' rule not to update + the '${infodir}/dir' file by exporting the environment variable + 'AM_UPDATE_INFO_DIR' to the value "no". This is done for consistency + with how the 'install-info' rule operates since automake 1.11.2. + +* Long-standing bugs: + + - It is now possible for a foo_SOURCES variable to hold Vala sources + together with C header files, as well as with sources and headers for + other supported languages (e.g., C++). Previously, only mixing C and + Vala sources was supported. + + - If "aclocal --install" is used, and the first directory specified with + '-I' is non-existent, aclocal will now create it before trying to copy + files in it. + + - An empty declaration of a "foo_PRIMARY" no longer cause the generated + install rules to create an empty $(foodir) directory; for example, if + Makefile.am contains something like: + + pkglibexec_SCRIPTS = + if FALSE + pkglibexec_SCRIPTS += bar.sh + endif + + the $(pkglibexec) directory will not be created upon "make install". + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.11.3: + +* Miscellaneous changes: + + - Automake's own build system is more silent by default, making use of + the 'silent-rules' option. + + - The master copy of the 'gnupload' script is now maintained in gnulib, + not in automake. + + - The 'missing' script no longer tries to wrap calls to 'tar'. + + - "make dist" no longer wraps 'tar' invocations with the 'missing' + script. Similarly, the obsolescent variable '$(AMTAR)' (which you + shouldn't be using BTW ;-) no longer invokes the 'missing' script + to wrap tar, but simply invokes the 'tar' program itself. + The TAR environment variable overrides. + + - "make dist" can now create lzip-compressed tarballs. + + - In the Automake info documentation, the Top node and the nodes about + the invocation of the automake and aclocal programs have been renamed; + now, calling "info automake" will open the Top node, while calling + "info automake-invocation" and "info aclocal-invocation" will access + the nodes about the invocation of respectively automake and aclocal. + + - Automake is now distributed as a gzip-compressed and an xz-compressed + tarball. Previously, bzip2 was used instead of xz. + + - The last relics of Python 1.5 support have been removed from the + AM_PATH_PYTHON macro. + + - For programs and libraries, automake now detects EXTRA_foo_DEPENDENCIES + and adds them to the normal list of dependencies, but without + overwriting the foo_DEPENDENCIES variable, which is normally computed + by automake. + +Bugs fixed in 1.11.3: + +* Bugs introduced by 1.11.2: + + - Automake now correctly recognizes the prefix/primary combination + 'pkglibexec_SCRIPTS' as valid. + + - The parallel-tests harness no longer trips on sed implementations + with stricter limits on the length of input lines (problem seen at + least on Solaris 8). + +* Long-standing bugs: + + - The "deleted header file problem" for *.am files is avoided by stub + rules. This allows 'make' to trigger a rerun of 'automake' also if + some previously needed '.am' file has been removed. + + - The 'silent-rules' option now generates working makefiles even + for the uncommon 'make' implementations that do not support the + nested-variables extension to POSIX 2008. For such 'make' + implementations, whether a build is silent is determined at + configure time, and cannot be overridden at make time with + "make V=0" or "make V=1". + + - Vala support now works better in VPATH setups. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.11.2: + +* Changes to aclocal: + + - The `--acdir' option is deprecated. Now you should use the new options + `--automake-acdir' and `--system-acdir' instead. + + - The `ACLOCAL_PATH' environment variable is now interpreted as a + colon-separated list of additional directories to search after the + automake internal acdir (by default ${prefix}/share/aclocal-APIVERSION) + and before the system acdir (by default ${prefix}/share/aclocal). + +* Miscellaneous changes: + + - The Automake support for automatic de-ANSI-fication has been + deprecated. It will probably be removed in the next major Automake + release (1.12). + + - The `lzma' compression scheme and associated automake option `dist-lzma' + is obsoleted by `xz' and `dist-xz' due to upstream changes. + + - You may adjust the compression options used in dist-xz and dist-bzip2. + The default is now merely -e for xz, but still -9 for bzip; you may + specify a different level via the XZ_OPT and BZIP2 envvars respectively. + E.g., "make dist-xz XZ_OPT=-7" or "make dist-bzip2 BZIP2=-5" + + - The `compile' script now converts some options for MSVC for a better + user experience. Similarly, the new `ar-lib' script wraps Microsoft lib. + + - The py-compile script now accepts empty arguments passed to the options + `--destdir' and `--basedir', and complains about unrecognized options. + Moreover, a non-option argument or a special `--' argument terminates + the list of options. + + - A developer that needs to pass specific flags to configure at "make + distcheck" time can now, and indeed is advised to, do so by defining + the developer-reserved makefile variable AM_DISTCHECK_CONFIGURE_FLAGS, + instead of the old DISTCHECK_CONFIGURE_FLAGS. + The DISTCHECK_CONFIGURE_FLAGS variable should now be reserved for the + user; still, the old Makefile.am files that used to define it will + still continue to work as before. + + - New macro AM_PROG_AR that looks for an archiver and wraps it in the new + 'ar-lib' auxiliary script if the selected archiver is Microsoft lib. + This new macro is required for LIBRARIES and LTLIBRARIES when automake + is run with -Wextra-portability and -Werror. + + - When using DejaGnu-based testsuites, the user can extend the `site.exp' + file generated by automake-provided rules by defining the special make + variable `$(EXTRA_DEJAGNU_SITE_CONFIG)'. + + - The `install-info' rule can now be instructed not to create/update + the `${infodir}/dir' file, by exporting the new environment variable + `AM_UPDATE_INFO_DIR' to the value "no". + +Bugs fixed in 1.11.2: + +* Bugs introduced by 1.11: + + - The parallel-tests driver no longer produces erroneous results with + Tru64/OSF 5.1 sh upon unreadable log files. + + - The `parallel-tests' test driver does not report spurious successes + when used with concurrent FreeBSD make (e.g., "make check -j3"). + + - When the parallel-tests driver is in use, automake now explicitly + rejects invalid entries and conditional contents in TEST_EXTENSIONS, + instead of issuing confusing and apparently unrelated error messages + (e.g., "non-POSIX variable name", "bad characters in variable name", + or "redefinition of TEST_EXTENSIONS), or even, in some situations, + silently producing broken `Makefile.in' files. + + - The `silent-rules' option now truly silences all compile rules, even + when dependency tracking is disabled. Also, when `silent-rules' is + not used, `make' output no longer contains spurious backslash-only + lines, thus once again matching what Automake did before 1.11. + + - The AM_COND_IF macro also works if the shell expression for the + conditional is no longer valid for the condition. + +* Long-standing bugs: + + - The order of Yacc and Lex flags is fixed to be consistent with other + languages: $(AM_YFLAGS) comes before $(YFLAGS), and $(AM_LFLAGS) before + $(LFLAGS), so that the user variables override the developer variables. + + - "make distcheck" now correctly complains also when "make uninstall" + leaves one and only one file installed in $(prefix). + + - A "make uninstall" issued before a "make install", or after a mere + "make install-data" or a mere "make install-exec" does not spuriously + fail anymore. + + - Automake now warns about more primary/directory invalid combinations, + such as "doc_LIBRARIES" or "pkglib_PROGRAMS". + + - Rules generated by Automake now try harder to not change any files when + `make -n' is invoked. Fixes include compilation of Emacs Lisp, Vala, or + Yacc source files and the rule to update config.h. + + - Several scripts and the parallel-tests testsuite driver now exit with + the right exit status upon receiving a signal. + + - A per-Makefile.am setting of -Werror does not erroneously carry over + to the handling of other Makefile.am files. + + - The code for automatic dependency tracking works around a Solaris + make bug triggered by sources containing repeated slashes when the + `subdir-objects' option was used. + + - The makedepend and hp depmodes now work better with VPATH builds. + + - Java sources specified with check_JAVA are no longer compiled for + "make all", but only for "make check". + + - An usage like "java_JAVA = foo.java" will now cause Automake to warn + and error out if `javadir' is undefined, instead of silently producing + a broken Makefile.in. + + - aclocal and automake now honour the configure-time definitions of + AUTOCONF and AUTOM4TE when they spawn autoconf or autom4te processes. + + - The `install-info' recipe no longer tries to guess whether the + `install-info' program is from Debian or from GNU, and adaptively + change its behaviour; this has proven to be frail and easy to + regress. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.11.1: + + - Lots of minor bugfixes. + +* Bugs introduced by 1.11: + + - The `parallel-tests' test driver works around a GNU make 3.80 bug with + trailing white space in the test list (`TESTS = foo $(EMPTY)'). + +* Long standing bugs: + + - On Darwin 9, `pythondir' and `pyexecdir' pointed below `/Library/Python' + even if the `--prefix' argument pointed outside of a system directory. + AM_PATH_PYTHON has been fixed to ignore the value returned from python's + `get_python_lib' function if it points outside the configured prefix, + unless the `--prefix' argument was either `/usr' or below `/System'. + + - The testsuite does not try to change the mode of `ltmain.sh' files from + a Libtool installation (symlinked to test directories) any more. + + - AM_PROG_GCJ uses AC_CHECK_TOOLS to look for `gcj' now, so that prefixed + tools are preferred in a cross-compile setup. + + - The distribution is tarred up with mode 755 now by the `dist*' targets. + This fixes a race condition where untrusted users could modify files + in the $(PACKAGE)-$(VERSION) distdir before packing if the toplevel + build directory was world-searchable. This is CVE-2009-4029. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.11: + +* Version requirements: + + - Autoconf 2.62 or greater is required. + +* Changes to aclocal: + + - The autoconf version check implemented by aclocal in aclocal.m4 + (and new in Automake 1.10) is degraded to a warning. This helps + in the common case where the Autoconf versions used are compatible. + +* Changes to automake: + + - The automake program can run multiple threads for creating most + Makefile.in files concurrently, if at least Perl 5.7.2 is available + with interpreter-based threads enabled. Set the environment variable + AUTOMAKE_JOBS to the maximum number of threads to use, in order to + enable this experimental feature. + +* Changes to Libtool support: + + - Libtool generic flags are now passed to the install and uninstall + modes as well. + + - distcheck works with Libtool 2.x even when LT_OUTPUT is used, as + config.lt is removed correctly now. + +* Languages changes: + + - subdir-object mode works now with Fortran (F77, FC, preprocessed + Fortran, and Ratfor). + + - For files with extension .f90, .f95, .f03, or .f08, the flag + $(FCFLAGS_f[09]x) computed by AC_FC_SRCEXT is now used in compile rules. + + - Files with extension .sx are also treated as preprocessed assembler. + + - The default source file extension (.c) can be overridden with + AM_DEFAULT_SOURCE_EXT now. + + - Python 3.0 is supported now, Python releases prior to 2.0 are no + longer supported. + + - AM_PATH_PYTHON honors python's idea about the site directory. + + - There is initial support for the Vala programming language, when using + Vala 0.7.0 or later. + +* Miscellaneous changes: + + - Automake development is done in a git repository on Savannah now, see + + https://git.sv.gnu.org/gitweb/?p=automake.git + + A read-only CVS mirror is provided at + + cvs -d :pserver:anonymous@pserver.git.sv.gnu.org:/automake.git \ + checkout -d automake HEAD + + - "make dist" can now create xz-compressed tarballs, + as well as (deprecated?) lzma-compressed tarballs. + + - `automake --add-missing' will by default install the GPLv3 file as + COPYING if it is missing. It will also warn that the license file + should be added to source control. Note that Automake will never + overwrite an existing COPYING file, even when the `--force-missing' + option is used. + + - The manual is now distributed under the terms of the GNU FDL 1.3. + + - Automake ships and installs man pages for automake and aclocal now. + + - New shorthand `$(pkglibexecdir)' for `$(libexecdir)/@PACKAGE@'. + + - install-sh supports -C, which does not update the installed file + (and its time stamps) if the contents did not change. + + - The `gnupload' script has been revamped. + + - The `depcomp' and `compile' scripts now work with MSVC under MSYS. + + - The targets `install' and `uninstall' are more efficient now, in that + for example multiple files from one Automake variable such as + `bin_SCRIPTS' are copied in one `install' (or `libtool --mode=install') + invocation if they do not have to be renamed. + + Both install and uninstall may sometimes enter (`cd' into) the target + installation directory now, when no build-local scripts are used. + + Both install and uninstall do not fail anymore but do nothing if an + installation directory variable like `bindir' is set to the empty string. + + For built-in rules, `make install' now fails reliably if installation + of a file failed. Conversely, `make uninstall' even succeeds when + issued multiple times. + + These changes may need some adjustments from users: For example, + some `install' programs refuse to install multiple copies of the + same file in one invocation, so you may need to remove duplicate + entries from file lists. + + Also, within one set of files, say, nobase_data_DATA, the order of + installation may be changed, or even unstable among different hosts, + due to the use of associative arrays in awk. The increased use of + awk matches a similar move in Autoconf to provide for better scaling. + + Further, most undocumented per-rule install command variables such as + binSCRIPT_INSTALL have been removed because they are not needed any + more. Packages which use them should be using the appropriate one of + INSTALL_{DATA,PROGRAM,SCRIPT} or their install_sh_{DATA,PROGRAM,SCRIPT} + counterpart, depending on the type of files and the need for automatic + target directory creation. + + - The "deleted header file problem" for *.m4 files is avoided by + stub rules. This allows `make' to trigger a rerun of `aclocal' + also if some previously needed macro file has been removed. + + - Rebuild rules now also work for a removed `subdir/Makefile.in' in + an otherwise up to date tree. + + - The `color-tests' option causes colored test result output on terminals. + + - The `parallel-tests' option enables a new test driver that allows for + parallel test execution, inter-test dependencies, lazy test execution + for unit-testing, re-testing only failed tests, and formatted result output + as RST (reStructuredText) and HTML. Enabling this option may require some + changes to your test suite setup; see the manual for details. + + - The `silent-rules' option enables Linux kernel-style silent build output. + This option requires the widely supported but non-POSIX `make' feature + of recursive variable expansion, so do not use it if your package needs + to build with `make' implementations that do not support it. + + To enable less verbose build output, the developer has to use the Automake + option `silent-rules' in `AM_INIT_AUTOMAKE', or call the `AM_SILENT_RULES' + macro. The user may then set the default verbosity by passing the + `--enable-silent-rules' option to `configure'. At `make' run time, this + default may be overridden using `make V=0' for less verbose, and `make V=1' + for backward-compatible verbose output. + + - New prefix `notrans_' for manpages which should not be transformed + by --program-transform. + + - New macro AM_COND_IF for conditional evaluation and conditional + config files. + + - For AC_CONFIG_LINKS, if source and destination are equal, do not + remove the file in a non-VPATH build. Such setups work with Autoconf + 2.62 or newer. + + - AM_MAINTAINER_MODE now allows for an optional argument specifying + the default setting. + + - AM_SUBST_NOTMAKE may prevent substitution of AC_SUBSTed variables, + useful especially for multi-line values. + + - Automake's early configure-time sanity check now diagnoses an + unsafe absolute source directory name and makes configure fail. + + - The Automake macros and rules cope better with whitespace in the + current directory name, as long as the relative path to `configure' + does not contain whitespace. To this end, the values of `$(MISSING)' + and `$(install_sh)' may contain suitable quoting, and their expansion + might need `eval'uation if used outside of a makefile. These + undocumented variables may be used in several documented macros such + as $(AUTOCONF) or $(MAKEINFO). + +Bugs fixed in 1.11: + +* Long-standing bugs: + + - Fix aix dependency tracking for libtool objects. + + - Work around AIX sh quoting issue in AC_PROG_CC_C_O, leading to + unnecessary use of the `compile' script. + + - For nobase_*_LTLIBRARIES with nonempty directory components, the + correct `-rpath' argument is used now. + + - `config.status --file=Makefile depfiles' now also works with the + extra quoting used internally by Autoconf 2.62 and newer + (it used to work only without the `--file=' bit). + + - The `missing' script works better with versioned tool names. + + - Semantics for `missing help2man' have been revamped: + + Previously, if `help2man' was not present, `missing help2man' would have + the following semantics: if some man page was out of date but present, then + a warning would be printed, but the exit status was 0. If the man page was + not present at all, then `missing' would create a replacement man page + containing an error message, and exit with a status of 2. This does not play + well with `make': the next run will see this particular man page as being up + to date, and will only error out on the next generated man page, if any; + repeat until all pages are done. This was not desirable. + + These are the new semantics: if some man page is not present, and help2man + is not either, then `missing' will warn and generate the replacement page + containing the error message, but exit successfully. However, `make dist' + will ensure that no such bogus man pages are packaged into a tarball. + + - Targets provided by automake behave better with `make -n', in that they + take care not to create files. + + - `config.status Makefile... depfiles' works fine again in the presence of + disabled dependency tracking. + + - The default no-op recursive rules for these targets also work with BSD make + now: html, install-html, install-dvi, install-pdf, install-pdf, install-info. + + - `make distcheck' works also when both a directory and some file below it + have been added to a distribution variable, such as EXTRA_DIST or *_SOURCES. + + - Texinfo dvi, ps, pdf, and html output files are not removed upon + `make mostlyclean' any more; only the LaTeX by-products are. + + - Renamed objects also work with the `subdir-objects' option and + source file languages which Automake does not know itself. + + - `automake' now correctly complains about variable assignments which are + preceded by a comment, extend over multiple lines with backslash-escaped + newlines, and end in a comment sign. Previous versions would silently + and wrongly ignore such assignments completely. + +* Bugs introduced by 1.10: + + - Fix output of dummy dependency files in presence of post-processed + Makefile.in's again, but also cope with long lines. + + - $(EXEEXT) is automatically appended to filenames of XFAIL_TESTS + that have been declared as programs in the same Makefile. + This is for consistency with the analogous change to TESTS in 1.10. + + - Fix order of standard includes to again be `-I. -I$(srcdir)', + followed by directories containing config headers. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.10: + +* Version requirements: + + - Autoconf 2.60 or greater is required. + + - Perl 5.6 or greater is required. + +* Changes to aclocal: + + - aclocal now also supports -Wmumble and -Wno-mumble options. + + - `dirlist' entries (for the aclocal search path) may use shell + wildcards such as `*', `?', or `[...]'. + + - aclocal supports an --install option that will cause system-wide + third-party macros to be installed in the local directory + specified with the first -I flag. This option also uses #serial + lines in M4 files to upgrade local macros. + + The new aclocal options --dry-run and --diff help to review changes + before they are installed. + + - aclocal now outputs an autoconf version check in aclocal.m4 in + projects using automake. + + For a few years, automake and aclocal have been calling autoconf + (or its underlying engine autom4te) to accurately retrieve the + data they need from configure.ac and its siblings. Doing so can + only work if all autotools use the same version of autoconf. For + instance a Makefile.in generated by automake for one version of + autoconf may stop working if configure is regenerated with another + version of autoconf, and vice versa. + + This new version check ensures that the whole build system has + been generated using the same autoconf version. + +* Support for new Autoconf macros: + + - The new AC_REQUIRE_AUX_FILE Autoconf macro is supported. + + - If `subdir-objects' is set, and AC_CONFIG_LIBOBJ_DIR is specified, + $(LIBOBJS), $(LTLIBOBJS), $(ALLOCA), and $(LTALLOCA) can be used + in different directories. However, only one instance of such a + library objects directory is supported. + +* Change to Libtool support: + + - Libtool generic flags (those that go before the --mode=MODE option) + can be specified using AM_LIBTOOLFLAGS and target_LIBTOOLFLAGS. + +* Yacc and Lex changes: + + - The rebuild rules for distributed Yacc and Lex output will avoid + overwriting existing files if AM_MAINTAINER_MODE and maintainer-mode + is not enabled. + + - ylwrap is now always used for lex and yacc source files, + regardless of whether there is more than one source per directory. + +* Languages changes: + + - Preprocessed assembler (*.S) compilation now honors CPPFLAGS, + AM_CPPFLAGS and per-target _CPPFLAGS, and supports dependency + tracking, unlike non-preprocessed assembler (*.s). + + - subdir-object mode works now with Assembler. Automake assumes + that the compiler understands `-c -o'. + + - Preprocessed assembler (*.S) compilation now also honors + $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES). + + - Improved support for Objective C: + - Autoconf's new AC_PROG_OBJC will enable automatic dependency tracking. + - A new section of the manual documents the support. + + - New support for Unified Parallel C: + - AM_PROG_UPC looks for a UPC compiler. + - A new section of the manual documents the support. + + - Per-target flags are now correctly handled in link rules. + + For instance maude_CFLAGS correctly overrides AM_CFLAGS; likewise + for maude_LDFLAGS and AM_LDFLAGS. Previous versions bogusly + preferred AM_CFLAGS over maude_CFLAGS while linking, and they + used both AM_LDFLAGS and maude_LDFLAGS on the same link command. + + The fix for compiler flags (i.e., using maude_CFLAGS instead of + AM_CFLAGS) should not hurt any package since that is how _CFLAGS + is expected to work (and actually works during compilation). + + However using maude_LDFLAGS "instead of" AM_LDFLAGS rather than + "in addition to" breaks backward compatibility with older versions. + If your package used both variables, as in + + AM_LDFLAGS = common flags + bin_PROGRAMS = a b c + a_LDFLAGS = more flags + ... + + and assumed *_LDFLAGS would sum up, you should rewrite it as + + AM_LDFLAGS = common flags + bin_PROGRAMS = a b c + a_LDFLAGS = $(AM_LDFLAGS) more flags + ... + + This new behavior of *_LDFLAGS is more coherent with other + per-target variables, and the way *_LDFLAGS variables were + considered internally. + +* New installation targets: + + - New targets mandated by GNU Coding Standards: + install-dvi + install-html + install-ps + install-pdf + By default they will only install Texinfo manuals. + You can customize them with *-local variants: + install-dvi-local + install-html-local + install-ps-local + install-pdf-local + + - The undocumented recursive target `uninstall-info' no longer exists. + (`uninstall' is in charge of removing all possible documentation + flavors, including optional formats such as dvi, ps, or info even + when `no-installinfo' is used.) + +* Miscellaneous changes: + + - Automake no longer complains if input files for AC_CONFIG_FILES + are specified using shell variables. + + - clean, distribution, or rebuild rules are normally disabled for + inputs and outputs of AC_CONFIG_FILES, AC_CONFIG_HEADERS, and + AC_CONFIG_LINK specified using shell variables. However, if these + variables are used as ${VAR}, and AC_SUBSTed, then Automake will + be able to output rules anyway. + (See the Automake documentation for AC_CONFIG_FILES.) + + - $(EXEEXT) is automatically appended to filenames of TESTS + that have been declared as programs in the same Makefile. + This is mostly useful when some check_PROGRAMS are listed in TESTS. + + - `-Wportability' has finally been turned on by default for `gnu' and + `gnits' strictness. This means, automake will complain about %-rules + or $(GNU Make functions) unless you switch to `foreign' strictness or + use `-Wno-portability'. + + - Automake now uses AC_PROG_MKDIR_P (new in Autoconf 2.60), and uses + $(MKDIR_P) instead of $(mkdir_p) to create directories. The + $(mkdir_p) variable is still defined (to the same value as + $(MKDIR_P)) but should be considered obsolete. If you are using + $(mkdir_p) in some of your rules, please plan to update them to + $(MKDIR_P) at some point. + + - AM_C_PROTOTYPES and ansi2knr are now documented as being obsolete. + They still work in this release, but may be withdrawn in a future one. + + - Inline compilation rules for gcc3-style dependency tracking are + more readable. + + - Automake installs a "Hello World!" example package in $(docdir). + This example is used throughout the new "Autotools Introduction" + chapter of the manual. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.9: + +* Makefile.in bloat reduction: + + - Inference rules are used to compile sources in subdirectories when + the `subdir-objects' option is used and no per-target flags are + used. This should reduce the size of some projects a lot, because + Automake used to output an explicit rule for each such object in + the past. + + - Automake no longer outputs three rules (.o, .obj, .lo) for each + object that must be built with explicit rules. It just outputs + the rules required to build the kind of object considered: either + the two .o and .obj rules for usual objects, or the .lo rule for + libtool objects. + +* Change to Libtool support: + + - Libtool tags are used with libtool versions that support them. + (I.e., with Libtool 1.5 or greater.) + + - Automake is now able to handle setups where a libtool library is + conditionally installed in different directories, as in + + if COND + lib_LTLIBRARIES = liba.la + else + pkglib_LTLIBRARIES = liba.la + endif + liba_la_SOURCES = ... + +* Changes to aclocal: + + - aclocal now ensures that AC_DEFUNs and AU_DEFUNs it discovers are + really evaluated, before it decides to include them in aclocal.m4. + This solves nasty problems with conditional redefinitions of + Autoconf macros in /usr/share/aclocal/*.m4 files causing extraneous + *.m4 files to be included in any project using these macros. + (Calls to AC_PROG_EGREP causing libtool.m4 to be included is the + most famous instance of this bug.) + + - Do not complain about missing conditionally AC_REQUIREd macros + that are not actually used. In 1.8.x aclocal would correctly + determine which of these macros were really needed (and include + only these in the package); unfortunately it would also require + all of them to be present in order to run. This created + situations were aclocal would not work on a tarball distributing + all the macros it uses. For instance running aclocal on a project + containing only the subset of the Gettext macros in use by the + project did not work, because gettext conditionally requires other + macros. + +* Portability improvements: + + - Tar format can be chosen with the new options tar-v7, tar-ustar, and + tar-pax. The new option filename-length-max=99 helps diagnosing + filenames that are too long for tar-v7. (PR/414) + + - Variables augmented with `+=' are now automatically flattened (i.e., + trailing backslashes removed) and then wrapped around 80 columns + (adding trailing backslashes). In previous versions, a long series + of + VAR += value1 + VAR += value2 + VAR += value3 + ... + would result in a single-line definition of VAR that could possibly + exceed the maximum line length of some make implementations. + + Non-augmented variables are still output as they are defined in + the Makefile.am. + +* Miscellaneous: + + - Support Fortran 90/95 with the new "fc" and "ppfc" languages. + Works the same as the old Fortran 77 implementation; just replace + F77 with FC everywhere (exception: FFLAGS becomes FCFLAGS). + Requires a version of autoconf which provides AC_PROG_FC (>=2.59). + + - Support for conditional _LISP. + + - Support for conditional -hook and -local rules (PR/428). + + - Diagnose AC_CONFIG_AUX_DIR calls following AM_INIT_AUTOMAKE. (PR/49) + + - Automake will not write any Makefile.ins after the first error it + encounters. The previous Makefile.ins (if any) will be left in + place. (Warnings will not prevent output, but remember they can + be turned into errors with -Werror.) + + - The restriction that SUBDIRS must contain direct children is gone. + Do not abuse. + + - The manual tells more about SUBDIRS vs. DIST_SUBDIRS. + It also gives an example of nested packages using AC_CONFIG_SUBDIRS. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.8.5: + +* Long-standing bugs: + + - Define DIST_SUBDIRS even when the `no-dist' or `cygnus' options are used + so that `make distclean' and `make maintainer-clean' can work. + + - Define AR and ARFLAGS even when only EXTRA_LIBRARIES are defined. + + - Fix many rules to please FreeBSD make, which runs commands with `sh -e'. + + - Polish diagnostic when no input file is found. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.8.4: + +* Long-standing bugs: + + - Fix AM_PATH_PYTHON to correctly display $PYTHON when it has been + overridden by the user. + + - Honor PATH_SEPARATOR in various places of the Automake package, for + the sake of OS/2. + + - Adjust dependency tracking mode detection to ICC 8.0's new output. + (PR/416) + + - Fix install-sh so it can install the `mv' binary... using `mv'. + + - Fix tru64 dependency tracking for libtool objects. + + - Work around Exuberant Ctags when creating a TAGS files in a directory + without files to scan but with subdirectories to include. + +* Bugs introduced by 1.8: + + - Fix an "internal error" when @LIBOBJS@ is used in a variable that is + not defined in the same conditions as the _LDADD that uses it. + + - Do not warn when JAVAROOT is overridden, this is legitimate. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.8.3: + +* Long-standing bugs: + + - Quote filenames in installation rules, in case $DESTDIR, $prefix, + or any of the other *dir variables contain a space. + + Please note that Automake does not and cannot support spaces in + filenames that are involved during the build. This change affects + only installation paths, so that `make install' does not bomb out + in packages configured with + ./configure --prefix '/c/Program Files' + + - Fix the depfiles output so it works with GNU sed (<4.1) even when + POSIXLY_CORRECT is set. + + - Do not AC_SUBST(LIBOBJS) in AM_WITH_REGEX. This macro was unusable + since Autoconf 2.54, which defines LIBOBJS itself. + + - Fix a potential (but unlikely) race condition in parallel elisp + builds. (Introduced in 1.7.3.) + + - Do not assume that users override _DEPENDENCIES in all conditions + where Automake will try to define them. + + - Do not use `mkdir -p' in mkinstalldirs, unless this is GNU mkdir. + Solaris 8's `mkdir -p' is not thread-safe and can break parallel + builds. + + This fix also affects the $(mkdir_p) variable defined since + Automake 1.8. It will be set to `mkdir -p' only if mkdir is GNU + mkdir, and to `mkinstalldirs' or `install-sh -d' otherwise. + + - Secure temporary directory creation in `make distcheck'. (PR/413) + + - Do not generate two build rules for `parser.h' when the + parser appears in two different conditionals. + + - Work around a Solaris 8 /bin/sh bug in the test for dependency + checking. Usually ./configure will not pick this shell; so this + fix only helps cases where the shell is forced to /bin/sh. + +* Bugs introduced by 1.8: + + - In some situations (hand-written `m4_include's), aclocal would + call the `File::Spec->rel2abs' method, which was only introduced + in Perl 5.6. This new version reestablish support Perl 5.005. + + It is likely that the next major Automake releases will require at + least Perl 5.6. Consider upgrading your development environment + if you are still using the five-year-old Perl 5.005. + + - Automake would sometimes fail to define rules for targets listed + in variables defined in multiple conditions. For instance on + if C1 + bin_PROGRAMS = a + else + bin_PROGRAMS = b + endif + it would define only the `a.$(OBJEXT): a.c' rule and omit the + `b.$(OBJEXT): b.c' rule. + +* New sections in manual: + + - Third-Party Makefiles: how to interface third party Makefiles. + - Upgrading: upgrading packages to newer Automake versions. + - Multiple Outputs: handling tools that produce many outputs. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bug fixed in 1.8.2: + +* A (well known) portability bug slipped in the changes made to + install-sh in Automake 1.8.1. The broken install-sh would refuse to + install anything on Tru64. + +* Fix install rules for conditionally built python files. (This never + really worked.) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bug fixed in 1.8.1: + +* Bugs introduced by 1.8: + + - Fix Config.pm import error with old Perl versions (at least + 5.005_03). One symptom is that aclocal could not find its macro + directory. + + - Automake 1.8 used `mkdir -m 0755 -p --' to ensure that directories + created by `make install' are always world readable, even if the + installer happens to have an overly restrictive umask (e.g. 077). + This was a mistake and has been reverted. There are at least two + reasons why we must not use `-m 0755': + - it causes special bits like SGID to be ignored, + - it may be too restrictive (some setups expect 775 directories). + + - Fix aclocal to honor definitions located in files which have been + m4_included manually. aclocal 1.8 had been updated to check + m4_included files for new requirements, but forgot that these + m4_included files can also provide new definitions. + + Note that if you have such a setup, we recommend you get rid of + it. In the past, there was a reason to m4_include files manually: + aclocal used to duplicate entire M4 files into aclocal.m4, even + files that were distributed. Some packages were therefore + m4_including the distributed file directly, and playing some + tricks to ensure aclocal would not copy that file to aclocal.m4, + in order to limit the amount of duplication. Since aclocal 1.8.x + will precisely output m4_includes for local M4 files, we recommend + that you clean up your setup, removing all manual m4_includes and + letting aclocal output them. + + - Output detailed menus in the Info version if the Automake manual, + so that Emacs can locate the indexes. + + - configure.ac and configure were listed twice in DIST_COMMON (an + internal variable where Automake lists configury files to + distribute). This was harmless, but unaesthetic. + + - Use `chmod a-w' instead of `chmod -w' as the latter honors umask. + This was an issue only in the Automake package itself, not in + its output. + + - Automake assumed that all AC_CONFIG_LINKS arguments had the form + DEST:SRC. This was wrong, as some packages do + AC_CONFIG_LINKS($computedlinks). This version no longer abort in + that situation. + + - Contrary to mkinstalldirs, $(mkdir_p) was expecting exactly one + argument. This caused two kinds of failures: + - Rules installing data in a conditionally defined directory + failed when that directory was undefined. In this case no + argument was supplied. + - `make installdirs' failed, because several directories were + passed to $(mkdir_p). This was an issue only on platform + were $(mkdir_p) is implemented with `install-sh -d'. + $(mkdir_p) as been changed to accept 0 or more arguments, as + mkinstalldirs did. + +* Long-standing bugs: + + - Fix an unexpected diagnostic occurring when users attempt + to override some internal variables that Automake appends to. + + - aclocal now scans configure.ac for macro definitions (PR/319). + + - Fix a portability issue with OSF1/Tru64 Make. If a directory + distributes files which are outside itself (this usually occurs + when using AC_CONFIG_AUX_DIR([../dir]) to use auxiliary files + from a parent package), then `make distcheck' fails due to an + optimization performed by OSF1/Tru64 Make in its VPATH handling. + (tests/subpkg2.test failure) + + - Fix another portability issue with Sun and OSF1/Tru64 Make. + In a VPATH-build configuration, `make install' would install + nobase_ files to wrong locations. + + - Fix a Perl `uninitialized value' diagnostic occurring when + automake complains that a Texinfo file does not have a + @setfilename statement. + + - Erase config.status.lineno during `make distclean'. This file + can be created by config.status. Automake already knew about + configure.lineno, but forgot config.status.lineno. + + - Distribute all files, even those which are built and installed + conditionally. This change affects files listed in conditionally + defined *_HEADERS and *_PYTHON variable (unless they are nodist_*) + as well as those listed in conditionally defined dist_*_DATA, + dist_*_JAVA, dist_*_LISP, and dist_*_SCRIPTS variables. + + - Fix AM_PATH_LISPDIR to avoid \? in sed regular expressions; it + doesn't conform to POSIX. + + - Normalize help strings for configure variables and options added + by Automake macros. + +* Anticipation: + + - Check for python2.4 in AM_PATH_PYTHON. + +* Spurious failures in test suite: + + - tests/libtool5.test, tests/ltcond.test, tests/ltcond2.test, + tests/ltconv.test: fix failures with CVS Libtool. + - tests/aclocal6.test: fix failure if autom4te.cache is disabled. + - tests/txinfo24.test, tests/txinfo25.test, tests/txinfo28.test: + fix failures with old Texinfo versions. + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +New in 1.8: + +* Meta-News + + - The NEWS file is more verbose. + +* Requirements + + - Autoconf 2.58 or greater is required. + +* New features + + - Default source file names in the absence of a _SOURCES declaration + are made by removing any target extension before appending `.c', so + to make the libtool module `foo.la' from `foo.c', you only need to + do this: + + lib_LTLIBRARIES = foo.la + foo_la_LDFLAGS = -module + + For backward compatibility, foo_la.c will be used instead of + foo.c if this file exists or is the explicit target of a rule. + However -Wobsolete will warn about this deprecated naming. + + - AR's `cru' flags are now set in a global ARFLAGS variable instead + of being hard-coded in each $(AR) invocation, so they can be + substituted from configure.ac. This has been requested by people + dealing with non-POSIX ar implementations. + + - New warning option: -Woverride. This will warn about any user + target or variable definitions which override Automake + definitions. + + - Texinfo rules back up and restore info files when makeinfo fails. + + - Texinfo rules now support the `html' target. + Running this requires Texinfo 4.0 or greater. + + `html' is a new recursive target, so if your package mixes + hand-crafted `Makefile.in's with Automake-generated + `Makefile.in's, you should adjust the former to support (or + ignore) this target so that `make html' recurses successfully. If + you had a custom `html' rule in your `Makefile.am', it's better to + rename it as `html-local', otherwise your rule will override + Automake's new rule (you can check that by running `automake + -Woverride') and that will stop the recursion to subdirectories. + + Last but not least, this `html' rule is declared PHONY, even when + overridden. Fortunately, it appears that few packages use a + non-PHONY `html' rule. + + - Any file which is m4_included from configure.ac will appear as a + configure and Makefile.in dependency, and will be automatically + distributed. + + - The rules for rebuilding Makefiles and Makefile.ins will now + rebuild all Makefiles and all Makefile.ins at once when one of + configure's dependencies has changed. This is considerably faster + than previous implementations, where config.status and automake + were run separately in each directory (this still happens when you + change a Makefile.am locally, without touching configure.ac or + friends). Doing this also solves a longstanding issue: these + rebuild rules failed to work when adding new directories to the + tree, forcing you to run automake manually. + + - For similar reasons, the rules to rebuild configure, + config.status, and aclocal.m4 are now defined in all directories. + Note that if you were using the CONFIG_STATUS_DEPENDENCIES and + CONFIGURE_DEPENDENCIES (formerly undocumented) variables, you + should better define them in all directories. This is easily done + using an AC_SUBST (make sure you prefix these dependencies with + $(top_srcdir) since this variable will appear at different + levels of the build tree). + + - aclocal will now use `m4_include' instead of copying local m4 + files into aclocal.m4. (Local m4 files are those you ship with + your project, other files will be copied as usual.) + + Because m4_included files are automatically distributed, it means + for most projects there is no point in EXTRA_DISTing the list of + m4 files which are used. (You can probably get rid of + m4/Makefile.am if you had one.) + + - aclocal will avoid touching aclocal.m4 when possible, so that + Autom4te's cache isn't needlessly invalidated. This behavior can + be switched off with the new `--force' option. + + - aclocal now uses Autoconf's --trace to detect macros which are + actually used and will no longer include unused macros simply + because they where mentioned. This was often the case for macros + called conditionally. + + - New options no-dist and no-dist-gzip. + + - compile, depcomp, elisp-comp, install-sh, mdate-sh, mkinstalldirs, + py-compile, and ylwrap, now all understand --version and --help. + + - Automake will now recognize AC_CONFIG_LINKS so far as removing created + links as part of the distclean target and including source files in + distributions. + + - AM_PATH_PYTHON now supports ACTION-IF-FOUND and ACTION-IF-NOT-FOUND + argument. The latter can be used to override the default behavior + (which is to abort). + + - Automake will exit with $? = 63 on version mismatch. (So does + Autoconf 2.58) missing knows this, and in this case it will + emulate the tools as if they were absent. Because older versions + of Automake and Autoconf did not use this exit code, this change + will only be useful in projects generated with future versions of + these tools. + + - When using AC_CONFIG_FILES with multiple input files, Automake + generates the first ".in" input file for which a ".am" exists. + (Former versions would try to use only the first input file.) + + - lisp_DATA is now allowed. If you are using the empty ELCFILES + idiom to disable byte-compilation of lisp_LISP files, it is + recommended that you switch to using lisp_DATA. Note that + this is not strictly equivalent: lisp_DATA will install elisp + files even if emacs is not installed, while *_LISP do not + install anything unless emacs is found. + + - Makefiles will prefer `mkdir -p' over mkinstalldirs if it is + available. This selection is achieved through the Makefile + variable $(mkdir_p) that is set by AM_INIT_AUTOMAKE to either + `mkdir -m 0755 -p --', `$(mkinstalldirs) -m 0755', or + `$(install_sh) -m 0755 -d'. + +* Obsolete features + + - Because `mkdir -p' is available on most platforms, and we can use + `install-sh -d' when it is not, the use of the mkinstalldirs + script is being phased out. `automake --add-missing' no longer + installs it, and if you remove mkinstalldirs from your package, + automake will define $(mkinstalldirs) as an alias for $(mkdir_p). + + Gettext 0.12.1 still requires mkinstalldirs. Fortunately + gettextize and autopoint will install it when needed. Automake + will continue to define the $(mkinstalldirs) and to distribute + mkinstalldirs when this script is in the source tree. + + - AM_PROG_CC_STDC is now empty. The content of this macro was + merged in AC_PROG_CC. If your code uses $am_cv_prog_cc_stdc, you + should adjust it to use $ac_cv_prog_cc_stdc instead. (This + renaming should be safe, even if you have to support several, + versions of Automake, because AC_PROG_CC defines this variable + since Autoconf 2.54.) + + - Some users where using the undocumented ACLOCAL_M4_SOURCES + variable to override the aclocal.m4 dependencies computed + (inaccurately) by older versions of Automake. Because Automake + now tracks configure's m4 dependencies accurately (see m4_include + above), the use of ACLOCAL_M4_SOURCES should be considered + obsolete and will be flagged as such when running `automake + -Wobsolete'. + +* Bug fixes + + - Defining programs conditionally using Automake conditionals no + longer leads to a combinatorial explosion. The following + construct used to be troublesome when used with dozens of + conditions. + + bin_PROGRAMS = a + if COND1 + bin_PROGRAMS += a1 + endif + if COND2 + bin_PROGRAMS += a2 + endif + if COND3 + bin_PROGRAMS += a3 + endif + ... + + Likewise for _SOURCES, _LDADD, and _LIBADD variables. + + - Due to implementation constraints, previous versions of Automake + proscribed multiple conditional definitions of some variables + like bin_PROGRAMS: + + if COND1 + bin_PROGRAMS = a1 + endif + if COND2 + bin_PROGRAMS = a2 + endif + + All _PROGRAMS, _LDADD, and _LIBADD variables were affected. + This restriction has been lifted, and these variables now + support multiple conditional definitions as do other variables. + + - Cleanup the definitions of $(distdir) and $(top_distdir). + $(top_distdir) now points to the root of the distribution + directory created during `make dist', as it did in Automake 1.4, + not to the root of the build tree as it did in intervening + versions. Furthermore these two variables are now only defined in + the top level Makefile, and passed to sub-directories when running + `make dist'. + + - The --no-force option now correctly checks the Makefile.in's + dependencies before deciding not to update it. + + - Do not assume that make files are called Makefile in cleaning rules. + + - Update .info files in the source tree, not in the build tree. This + is what the GNU Coding Standard recommend. Only Automake 1.7.x + used to update these files in the build tree (previous versions did + it in the source tree too), and it caused several problems, varying + from mere annoyance to portability issues. + + - COPYING, COPYING.LIB, and COPYING.LESSER are no longer overwritten + when --add-missing and --force-missing are used. For backward + compatibility --add-missing will continue to install COPYING (in + `gnu' strictness) when none of these three files exist, but this + use is deprecated: you should better choose a license yourself and + install it once for all in your source tree (and in your code + management system). + + - Fix ylwrap so that it does not overwrite header files that haven't + changed, as the inline rule already does. + + - User-defined rules override automake-defined rules for the same + targets, even when rules do not have commands. This is not new + (and was documented), however some of the automake-generated + rules have escaped this principle in former Automake versions. + Rules for the following targets are affected by this fix: + + clean, clean-am, dist-all, distclean, distclean-am, dvi, dvi-am, + info, info-am, install-data-am, install-exec-am, install-info, + install-info-am, install-man, installcheck-am, maintainer-clean, + maintainer-clean-am, mostlyclean, mostlyclean-am, pdf, pdf-am, + ps, ps-am, uninstall-am, uninstall-info, uninstall-man + + Practically it means that an attempt to supplement the dependencies + of some target, as in + + clean: my-clean-rule + + will now *silently override* the automake definition of the + rule for this target. Running `automake -Woverride' will diagnose + all such overriding definitions. + + It should be noted that almost all of these targets support a *-local + variant that is meant to supplement the automake-defined rule + (See node `Extending' in the manual). The above rule should + be rewritten as + + clean-local: my-clean-rule + + These *-local targets have been documented since at least + Automake 1.2, so you should not fear the change if you have + to support multiple automake versions. + +* Miscellaneous + + - The Automake manual is now distributed under the terms of the GNU FDL. + + - Targets dist-gzip, dist-bzip2, dist-tarZ, dist-zip are always defined. + + - core dumps are no longer removed by the cleaning rules. There are + at least three reasons for this: + 1. These files should not be created by any build step, + so their removal do not fit any of the cleaning rules. + Actually, they may be precious to the developer. + 2. If such file is created during a build, then it's clearly a + bug Automake should not hide. Not removing the file will + cause `make distcheck' to complain about its presence. + 3. Operating systems have different naming conventions for + core dump files. A core file on one system might be a + completely legitimate data file on another system. + + - RUNTESTFLAGS, CTAGSFLAGS, ETAGSFLAGS, JAVACFLAGS are no longer + defined by Automake. This means that any definition in the + environment will be used, unless overridden in the Makefile.am or + on the command line. The old behavior, where these variables were + defined empty in each Makefile, can be obtained by AC_SUBSTing or + AC_ARG_VARing each variable from configure.ac. + + - CONFIGURE_DEPENDENCIES and CONFIG_STATUS_DEPENDENCIES are now + documented. (The is not a new feature, these variables have + been there since at least Automake 1.4.) + +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Bugs fixed in 1.7.9: +* Fix install-strip to work with nobase_ binaries. +* Fix renaming of #line directives in ylwrap. +* Rebuild with Autoconf 2.59. (1.7.8 was not installable with pdksh.) + +Bugs fixed in 1.7.8: +* Remove spurious blank lines in cleaning rules introduced in 1.7.7. +* Fix detection of Debian's install-info, broken since version 1.5. + (Debian bug #213524). +* Honor -module if it appears in AM_LDFLAGS (i.e., relax name checking) + This was only done for libfoo_LDFLAGS and LDFLAGS in previous versions. + +Bugs fixed in 1.7.7: +* The implementation of automake's --no-force option is unreliable, + so this option is ignored in this version. A real fix will appear in + Automake 1.8. (Debian Bug #206299) +* AM_PATH_PYTHON: really check the whole list of interpreters if no + argument is given. (PR/399) +* Do not warn about leading `_' in variable names, even with -Wportability. +* Support user redefinitions of TEXINFO_TEX. +* depcomp: support AIX Compiler version 6. +* Fix missing rebuilds during `make dist' with BSD make. + (Could produce tarballs containing out-of-date files.) +* Resurrect multilib support. +* Noteworthy manual updates: + - Extending aclocal: how to write m4 macros that won't trigger warnings + with Automake 1.8. + - A Shared Library: Rewrite and split into subsections. + +Bugs fixed in 1.7.6: +* Fix depcomp's icc mode for ICC 7.1. +* Diagnose calls to AC_CONFIG_FILES and friends with not enough arguments. +* Fix maintainer-clean's removal of autom4te.cache in VPATH builds. +* Fix AM_PATH_LISPDIR to work with POSIXLY_CORRECT=1. +* Fix the location reported in some diagnostics related to AUTOMAKE_OPTIONS. +* Remove Latin-1 characters from elisp-comp. +* Update the manual's @dircategory to match the Free Software Directory. + +Bugs fixed in 1.7.5: +* Update install-sh's license to remove an advertising clause. + (Debian bug #191717) +* Fix a bug introduced in 1.7.4, related to BUILT_SOURCE handling, + that caused invalid Makefile.ins to be generated. +* Make sure AM_MAKE_INCLUDE doesn't fail when a `doit' file exists. +* New FAQ entry: renamed objects. + +Bugs fixed in 1.7.4: +* Tweak the TAGS rule to support Exuberant Ctags (in addition to + the Emacs implementation) +* Fix output of aclocal.m4 dependencies in subdirectories. +* Use `mv -f' instead of `mv' in fastdep rules. +* Upgrade mdate-sh to work on OS/2. +* Don't byte-compile elisp files when ELCFILES is set empty. + (this documented feature was broken by 1.7.3) +* Diagnose trailing backslashes on last line of Makefile.am. +* Diagnose whitespace following trailing backslashes. +* Multiple tests are now correctly supported in DEJATOOL. (PR/388) +* Fix rebuilt rules for AC_CONFIG_FILES([Makefile:Makefile.in:Makefile.bot]) + Makefiles. (PR/389) +* `make install' will build `BUILT_SOURCES' first. +* Minor documentation fixes. + +Bugs fixed in 1.7.3: +* Fix stamp files numbering (when using multiple AC_CONFIG_HEADERS). +* Query distutils for `pythondir' and `pythonexecdir', instead of + using an hardcoded path. This should allow builds on 64-bit + distributions that usually use lib64/ instead of lib/. +* AM_PATH_PYTHON will also search for python2.3. +* elisp files are now built all at once instead of one by one. Besides + incurring a speed-up, this is required to support interdependent elisp files. +* Support for DJGPP: + - `make distcheck' will now work in `_inst/' and `_build' instead + of `=inst/' and `=build/' + - use `_dirstamp' when the file-system doesn't support `.dirstamp' + - install/uninstall `*.i[0-9][0-9]'-style info files + - more changes that affect only the Automake package (not its output) +* Fix some incompatibilities with upcoming perl-5.10. +* Properly quote AC_PACKAGE_TARNAME and AC_PACKAGE_VERSION when defining + PACKAGE and VERSION. +* depcomp fixes: + - dashmstdout and dashXmstdout modes: don't use `-o /dev/null', this + is troublesome with gcc and Solaris compilers. (PR/385) + - makedepend mode: work with Libtool. (PR/385 too) + - support for ICC. +* better support for unusual gettext setups, such as multiple po/ directories + (PR/381): + - Flag missing po/ and intl/ directories as warnings, not errors. + - Disable these warnings if po/ does not exist. +* Noteworthy manual updates: + - New FAQ chapter. + - Document how AC_CONFIG_AUX_DIR interacts with missing files. + (Debian Bug #39542) + - Document `AM_YFLAGS = -d'. (PR/382) + +Bugs fixed in 1.7.2: +* Fix installation and uninstallation of Info files built in subdirectories. +* Do not run `./configure --with-included-gettext' during `make distcheck' + if AM_GNU_GETTEXT([external]) is used. +* Correctly uninstall renamed man pages. +* Do not strip escaped newline in variables defined in one condition + and augmented in another condition. +* Fix ansi2knr rules for LIBOBJS sources. +* Clean all known Texinfo index files, not only those which appear to + be used, because we cannot know which indexes are used in included files. + (PR/375, Debian Bug #168671) +* Honor only the first @setfilename seen in a Texinfo file. +* Treat "required file X not found" diagnostics as errors (exit status 1). +* Don't complain that a required file is not found when it is a Makefile + target. (PR/357) +* Don't use single suffix inference rules when building `.info'-less + Info files, for the sake of Solaris make. +* The `check' target now depends on `$(BUILT_SOURCES)'. (PR/359) +* Recognize multiple inference rules such as `.a.b .c.d:'. (PR/371) +* Warn about multiple inference rules when -Wportability is used. (PR/372) +* Fix building of deansified files from subdirectories. (PR/370) +* Add missing `fi' in the .c->.obj rules. +* Improve install-sh to work even when names contain spaces or certain + (but not all) shell metachars. +* Fix the following spurious failures in the test suite: + depcomp2.test, gnits2.test, gnits3.test, python3.test, texinfo13.test +* Noteworthy manual updates: + - Augment the section about BUILT_SOURCES. + - Mention that AM_PROG_CC_STDC is a relic that is better avoided today. + +Bugs fixed in 1.7.1: +* Honor `ansi2knr' for files built in subdirectories, or using per-targets + flags. +* Aclocal should now recognize macro names containing parentheses, e.g. + AC_DEFUN([AC_LANG_PREPROC(Fortran 90)], [...]). +* Erase *.sum and *.log files created by DejaGnu, during `make distclean'. + (Debian Bug#153697) +* Install Python files even if they were built. (PR/369) +* Have stamp-vti dependent upon configure instead of configure.ac, as the + version might not be defined in the latter. (PR/358) +* Reorder arguments passed to a couple of commands, so things works + when POSIXLY_CORRECT=1. +* Fix a regex that can cause Perl to segfault on large input. + (Debian Bug#162583) +* Fix distribution of packages that have some sources defined conditionally, + as in the `Conditional compilation using Automake conditionals' example + of the manual. +* Fix spurious test suite failures on IRIX. +* Don't report a required variable as undefined if it has been + defined conditionally for the "right" conditions. +* Fix cleaning of the /tmp subdirectory used by `make distcheck', in case + `make distcheck' fails. +* Fix distribution of included Makefile fragment, so we don't create + spurious directories in the distribution. (PR/366) +* Don't complain that a target lacks `.$(EXEEXT)' when it has it. + +New in 1.7: +* Autoconf 2.54 is required. +* `aclocal' and `automake' will no longer warn about obsolete + configure macros. This is done by `autoconf -Wobsolete'. +* AM_CONFIG_HEADER, AM_SYS_POSIX_TERMIOS and + AM_HEADER_TIOCGWINSZ_NEEDS_SYS_IOCTL are obsolete (although still + supported). You should use AC_CONFIG_HEADERS, AC_SYS_POSIX_TERMIOS, + and AC_HEADER_TIOCGWINSZ instead. `autoupdate' can upgrade + `configure.ac' for you. +* Support for per-program and per-library `_CPPFLAGS'. +* New `ctags' target (builds CTAGS files). +* Support for -Wmumble and -Wno-mumble, where mumble is a warning category + (see `automake --help' or the manual for a list of them). +* Honor the WARNINGS environment variable. +* Omit the call to depcomp when using gcc3: call the compiler directly. +* A new option, std-options, tests that programs support --help and --version + when `make installcheck' is run. This is enabled by --gnits. +* Texinfo rules now support the `ps' and `pdf' targets. +* Info files are now created in the build directory, not the source directory. +* info_TEXINFOS supports files in subdirectories (this requires Texinfo 4.1 + or greater). +* `make distcheck' will enforce DESTDIR support by attempting + a DESTDIR install. +* `+=' can be used in conditionals, even if the augmented variable + was defined for another condition. +* Makefile fragments (inserted with `include') are always distributed. +* Use Autoconf's --trace interface to inspect configure.ac and get + a more accurate view of it. +* Add support for extending aclocal's default macro search path + using a `dirlist' file within the aclocal directory. +* automake --output-dir is deprecated. +* The part of the distcheck target that checks whether uninstall actually + removes all installed files has been moved to a separate target, + distuninstallcheck, so it can be overridden easily. +* Many bug fixes. + +New in 1.6.3: +* Support for AM_INIT_GETTEXT([external]) +* Bug fixes, including: + - Fix Automake's own `make install' so it works even if `ln' doesn't. + - nobase_ programs and scripts honor --program-transform correctly. + - Erase configure.lineno during `make distclean'. + - Erase YACC and LEX outputs during `make maintainer-clean'. + +New in 1.6.2: +* Many bug fixes, including: + - Requiring the current version works. + - Fix "$@" portability issues (for Zsh). + - Fix output of dummy dependency files in presence of post-processed + Makefile.in's. + - Don't compute dependencies in background to avoid races with libtool. + - Fix handling of _OBJECTS variables for targets sharing source variables. + - Check dependency mode for Java when AM_PROG_GCJ is used. + +New in 1.6.1: +* automake --output-dir is deprecated +* Many bug fixes, including: + - Don't choke on AM_LDFLAGS definitions. + - Clean libtool objects from subdirectories. + - Allow configure variables with reserved suffix and unknown prefix + (e.g. AC_SUBST(mumble_LDFLAGS) when 'mumble' is not a target). + - Fix the definition of AUTOMAKE and ACLOCAL in configure. + +New in 1.6: +* Autoconf 2.52 is required. +* automake no longer run libtoolize. + This is the job of autoreconf (from GNU Autoconf). +* `dist' generates all the archive flavors, as did `dist-all'. +* `dist-gzip' generates the Gzip tar file only. +* Combining Automake Makefile conditionals no longer lead to a combinatorial + explosion. Makefile.in's keep a reasonable size. +* AM_FUNC_ERROR_AT_LINE, AM_FUNC_STRTOD, AM_FUNC_OBSTACK, AM_PTRDIFF_T + are no longer shipped, since Autoconf 2.52 provides them (both as AM_ + and AC_). +* `#line' of Lex and Yacc files are properly set. +* EXTRA_DIST can contain generated directories. +* Support for dot-less extensions in suffix rules. +* The part of the distcheck target that checks whether distclean actually + cleans all built files has been moved to a separate target, distcleancheck, + so it can be overridden easily. +* `make distcheck' will pass additional options defined in + $(DISTCHECK_CONFIGURE_FLAGS) to configure. +* Fixed CDPATH portability problems, in particular for MacOS X. +* Fixed handling of nobase_ targets. +* Fixed support of implicit rules leading to .lo objects. +* Fixed late inclusion of --add-missing files (e.g. depcomp) in DIST_COMMON +* Added uninstall-hook target +* `AC_INIT AM_INIT_AUTOMAKE(tarname,version)' is an obsolete construct. + You can now use `AC_INIT(pkgname,version) AM_INIT_AUTOMAKE' instead. + (Note that "pkgname" is not "tarname", see the manual for details.) + It is also possible to pass a list of global Automake options as + first argument to this new form of AM_INIT_AUTOMAKE. +* Compiler-based assembler is now called `CCAS'; people expected `AS' + to be a real assembler. +* AM_INIT_AUTOMAKE will set STRIP itself when it needs it. Adding + AC_CHECK_TOOL([STRIP], [strip]) manually is no longer required. +* aclocal and automake are also installed with the version number + appended, and some of the install directory names have changed. + This lets you have multiple versions installed simultaneously. +* Support for parsers and lexers in subdirectories. + +New in 1.5: +* Support for `configure.ac'. +* Support for `else COND', `endif COND' and negated conditions `!COND'. +* `make dist-all' is much faster. +* Allows '@' AC_SUBSTs in macro names. +* Faster AM_INIT_AUTOMAKE (requires update of `missing' script) +* User-side dependency tracking. Developers no longer need GNU make +* Python support +* Uses DIST_SUBDIRS in some situations when SUBDIRS is conditional +* Most files are correctly handled if they appear in subdirs + For instance, a _DATA file can appear in a subdir +* GNU tar is no longer required for `make dist' +* Added support for `dist_' and `nodist_' prefixes +* Added support for `nobase_' prefix +* Compiled Java support +* Support for per-executable and per-library compilation flags +* Many bug fixes + +New in 1.4: +* Added support for the Fortran 77 programming language. +* Re-indexed the Automake Texinfo manual. +* Added `AM_FOOFLAGS' variable for each compiler invocation; + e.g. AM_CFLAGS can be used in Makefile.am to set C compiler flags +* Support for latest autoconf, including support for objext +* Can now put `.' in SUBDIRS to control build order +* `include' command and `+=' support for macro assignment +* Dependency tracking no long susceptible to deleted header file problem +* Maintainer mode now a conditional. @MAINT@ is now an anachronism. +* Bug fixes + +New in 1.3: +* Bug fixes +* Better Cygwin32 support +* Support for suffix rules with _SOURCES variables +* New options `readme-alpha' and `check-news'; Gnits mode sets these +* @LEXLIB@ no longer required when lex source seen + Lex support in `missing', and new lex macro. Update your missing script. +* Built-in support for assembly +* aclocal gives error if `AM_' macro not found +* Passed YFLAGS, not YACCFLAGS, to yacc +* AM_PROG_CC_STDC does not have to come before AC_PROG_CPP +* Dependencies computed as a side effect of compilation +* Preliminary support for Java +* DESTDIR support at "make install" time +* Improved ansi2knr support; you must use the latest ansi2knr.c (included) + +New in 1.2: +* Bug fixes +* Better DejaGnu support +* Added no-installinfo option +* Added Emacs Lisp support +* Added --no-force option +* Included `aclocal' program +* Automake will now generate rules to regenerate aclocal.m4, if appropriate +* Now uses `AM_' macro names everywhere +* ansi2knr option can have directory prefix (eg `../lib/ansi2knr') + ansi2knr now works correctly on K&R sources +* Better C++, yacc, lex support +* Will compute _DEPENDENCIES variables automatically if not supplied +* Will interpolate $(...) and ${...} when examining contents of a variable +* .deps files now in build directory, not source directory; dependency + handling generally rewritten +* DATA, MANS and BUILT_SOURCES no longer included in distribution +* can now put config.h into a subdir +* Added dist-all target +* Support for install-info program (see texinfo 3.9) +* Support for "yacc -d" +* configure substitutions are automatically discovered and included + in generated Makefile.in +* Special --cygnus mode +* OMIT_DEPENDENCIES can now hold list of dependencies to be omitted + when making distribution. Some dependencies are auto-ignored. +* Changed how libraries are specified in _LIBRARIES variable +* Full libtool support, from Gord Matzigkeit +* No longer have to explicitly touch stamp-h when using AC_CONFIG_HEADER; + AM_CONFIG_HEADER handles it automatically +* Texinfo output files no longer need .info extension +* Added `missing' support +* Cygwin32 support +* Conditionals in Makefile.am, from Ian Taylor + +New in 1.0: +* Bug fixes +* distcheck target runs install and installcheck targets +* Added preliminary support for DejaGnu. + +New in 0.33: +* More bug fixes +* More checking +* More libtool fixes from Gord Matzigkeit; libtool support is still + preliminary however +* Added support for jm_MAINTAINER_MODE +* dist-zip support +* New "distcheck" target + +New in 0.32: +* Many bug fixes +* mkinstalldirs and mdate-sh now appear in directory specified by + AC_CONFIG_AUX_DIR. +* Removed DIST_SUBDIRS, DIST_OTHER +* AC_ARG_PROGRAM only required when an actual program exists +* dist-hook target now run before distribution packaged up; idea from + Dieter Baron. Other hooks exist, too. +* Preliminary (unfinished) support for libtool +* Added short option names. +* Better "dist" support when gluing together multiple packages + +New in 0.31: +* Bug fixes +* Documentation updates (many from François Pinard) +* strictness `normal' now renamed to `foreign' +* Renamed --install-missing to --add-missing +* Now handles AC_CONFIG_AUX_DIR +* Now handles TESTS macro +* DIST_OTHER renamed to EXTRA_DIST +* DIST_SUBDIRS is deprecated +* @ALLOCA@ and @LIBOBJS@ now work in _LDADD variables +* Better error messages in many cases +* Program names are canonicalized +* Added "check" prefix; from Gord Matzigkeit + +New in 0.30: +* Bug fixes +* configure.in scanner knows about AC_PATH_XTRA, AC_OUTPUT ":" syntax +* Beginnings of a test suite +* Automatically adds -I options for $(srcdir), ".", and path to config.h +* Doesn't print anything when running +* Beginnings of MAINT_CHARSET support +* Can specify version in AUTOMAKE_OPTIONS +* Most errors recognizable by Emacs' M-x next-error +* Added --verbose option +* All "primary" variables now obsolete; use EXTRA_PRIMARY to supply + configure-generated names +* Required macros now distributed in aclocal.m4 +* New documentation +* --strictness=gnu is default + +New in 0.29: +* Many bug fixes +* More sophisticated configure.in scanning; now understands ALLOCA and + LIBOBJS directly, handles AC_CONFIG_HEADER more precisely, etc. +* TEXINFOS and MANS now obsolete; use info_TEXINFOS and man_MANS instead. +* CONFIG_HEADER variable now obsolete +* Can handle multiple Texinfo sources +* Allow hierarchies deeper than 2. From Gord Matzigkeit. +* HEADERS variable no longer needed; now can put .h files directly into + foo_SOURCES variable. +* Automake automatically rebuilds files listed in AC_OUTPUT. The + corresponding ".in" files are included in the distribution. + +New in 0.28: +* Added --gnu and --gnits options +* More standards checking +* Bug fixes +* Cleaned up 'dist' targets +* Added AUTOMAKE_OPTIONS variable and several options +* Now scans configure.in to get some information (preliminary) + +New in 0.27: +* Works with Perl 4 again + +New in 0.26: +* Added --install-missing option. +* Pretty-prints generated macros and rules +* Comments in Makefile.am are placed more intelligently in Makefile.in +* Generates .PHONY target +* Rule or macro in Makefile.am now overrides contents of Automake file +* Substantial cleanups from François Pinard + +New in 0.25: +* Bug fixes. +* Works with Perl 4 again. + +New in 0.24: +* New uniform naming scheme. +* --strictness option +* Works with Perl 5 +* '.c' files corresponding to '.y' or '.l' files are automatically + distributed. +* Many bug fixes and cleanups + +New in 0.23: +* Allow objects to be conditionally included in libraries via lib_LIBADD. + +New in 0.22: +* Bug fixes in 'clean' code. +* Now generates 'installdirs' target. +* man page installation reworked. +* 'make dist' no longer re-creates all Makefile.in's. + +New in 0.21: +* Reimplemented in Perl +* Added --amdir option (for debugging) +* Texinfo support cleaned up. +* Automatic de-ANSI-fication cleaned up. +* Cleaned up 'clean' targets. + +New in 0.20: +* Automatic dependency tracking +* More documentation +* New variables DATA and PACKAGEDATA +* SCRIPTS installed using $(INSTALL_SCRIPT) +* No longer uses double-colon rules +* Bug fixes +* Changes in advance of internationalization + +----- + +Copyright (C) 1995-2021 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS-2.0 b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS-2.0 new file mode 100644 index 0000000..5c56aa6 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS-2.0 @@ -0,0 +1,97 @@ +This file (NEWS-2.0) lists several incompatibilities planned for a +future Automake 2.0 release. + +However, the (few) current Automake maintainers have insufficient interest +and energy to pursue the 2.0 release. We have not even reviewed all +existing bugs. New maintainers are needed! For more information about +helping with Automake development: +https://lists.gnu.org/archive/html/automake/2021-03/msg00018.html + +Therefore, there is no ETA for Automake 2.0, but it is not likely to be +any time soon. So moving these future issues to a separate file seemed +warranted. For more info, see the ./PLANS/ directory. + + +* WARNING: Future backward-incompatibilities! + + - Makefile recipes generated by Automake 2.0 will expect to use an + 'rm' program that doesn't complain when called without any non-option + argument if the '-f' option is given (so that commands like "rm -f" + and "rm -rf" will act as a no-op, instead of raising usage errors). + This behavior of 'rm' is very widespread in the wild, and it will be + required in the next POSIX version: + + + + Accordingly, AM_INIT_AUTOMAKE now expands some shell code that checks + that the default 'rm' program in PATH satisfies this requirement, + aborting the configure process if this is not the case. For the + moment, it's still possible to force the configuration process to + succeed even with a broken 'rm', but that will no longer be the case + for Automake 2.0. + + - Automake 2.0 will require Autoconf 2.71 or later. Exact + dependencies are unknowable at ths time. + + - Automake 2.0 will drop support for the long-deprecated 'configure.in' + name for the Autoconf input file. You are advised to start using the + recommended name 'configure.ac' instead, ASAP. + + - The ACLOCAL_AMFLAGS special make variable will be fully deprecated in + Automake 2.0: it will raise warnings in the "obsolete" category (but + still no hard error of course, for compatibilities with the many, many + packages that still relies on that variable). You are advised to + start relying on the new Automake support for AC_CONFIG_MACRO_DIRS + instead (which was introduced in Automake 1.13). + + - Automake 2.0 will remove support for automatic dependency tracking + with the SGI C/C++ compilers on IRIX. The SGI depmode has been + reported broken "in the wild" already, and we don't think investing + time in debugging and fixing is worthwhile, especially considering + that SGI has last updated those compilers in 2006, and retired + support for them in December 2013: + + + - Automake 2.0 will remove support for MS-DOS and Windows 95/98/ME + (support for them was offered by relying on the DJGPP project). + Note however that both Cygwin and MSYS/MinGW on modern Windows + versions will continue to be fully supported. + + - Automake-provided scripts and makefile recipes might (finally!) + start assuming a POSIX shell in Automake 2.0. There still is no + certainty about this though: we'd first like to wait and see + whether future Autoconf versions will be enhanced to guarantee + that such a shell is always found and provided by the checks in + ./configure. + + In 2020, config.guess was changed by its then-maintainer to require + $(...); the ensuing bug reports and maintenance hassle + (unfortunately the changes have not been reverted) are a convincing + argument that we should not require a POSIX shell until Solaris 10, + at least, is completely gone from the world. + + - Starting from Automake 2.0, third-party m4 files located in the + system-wide aclocal directory, as well as in any directory listed + in the ACLOCAL_PATH environment variable, will take precedence + over "built-in" Automake macros. For example (assuming Automake + is installed in the /usr/local hierarchy), a definition of the + AM_PROG_VALAC macro found in '/usr/local/share/aclocal/my-vala.m4' + should take precedence over the same-named automake-provided macro + (defined in '/usr/local/share/aclocal-2.0/vala.m4'). + +----- + +Copyright (C) 1995-2021 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/README b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/README new file mode 100644 index 0000000..c9d0a9e --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/README @@ -0,0 +1,68 @@ +This is Automake, a Makefile generator. It aims to be portable and +to conform to the GNU Coding Standards for Makefile variables and +targets. + +See the INSTALL file for detailed information about how to configure +and install Automake. + +Automake is a Perl script. The input files are called Makefile.am. +The output files are called Makefile.in; they are intended for use +with Autoconf. Automake requires certain things to be done in your +configure.ac. + +Automake comes with extensive documentation; please refer to it for +more details about its purpose, features, and usage patterns. + +This package also includes the "aclocal" program, whose purpose is +to generate an 'aclocal.m4' based on the contents of 'configure.ac'. +It is useful as an extensible, maintainable mechanism for augmenting +autoconf. It is intended that other package authors will write m4 +macros which can be automatically used by aclocal. The documentation +for aclocal is currently found in the Automake manual. + +Automake has a test suite. Use "make check" to run it. For more +information, see the file t/README. + +Automake's home page: + + https://www.gnu.org/software/automake/ + +Automake has three mailing lists: + + * automake@gnu.org + For general discussions of Automake and its interactions with other + configuration/portability tools like Autoconf or Libtool. + + * bug-automake@gnu.org + Where to send bug reports and feature requests. + + * automake-patches@gnu.org + Where to send patches, and discuss the automake development process + and the design of new features. + +To see the archives of these lists, or to (un)subscribe to them, +refer to . + +New releases are announced to autotools-announce@gnu.org. If you want to +be informed, subscribe to that list by following the instructions at +. + +For any copyright year range specified as YYYY-ZZZZ in this package, +the range specifies every single year in that closed interval. + +----- + +Copyright (C) 1994-2021 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . diff --git a/openocd-win/openocd/distro-info/licenses/automake-1.16.5/THANKS b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/THANKS new file mode 100644 index 0000000..965f280 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/automake-1.16.5/THANKS @@ -0,0 +1,462 @@ +Automake was originally written by David J. MacKenzie . +It would not be what it is today without the invaluable help of these +people: + +Adam J. Richter adam@yggdrasil.com +Adam Mercer ramercer@gmail.com +Adam Sampson ats@offog.org +Adrian Bunk bunk@fs.tum.de +Aharon Robbins arnold@skeeve.com +Akim Demaille akim@gnu.org +Alan Modra amodra@bigpond.net.au +Alex Hornby alex@anvil.co.uk +Alex Unleashed unledev@gmail.com +Alexander Mai st002279@hrzpub.tu-darmstadt.de +Alexander Martens alexander.martens@gtd.es +Alexander V. Lukyanov lav@yars.free.net +Alexander Turbov zaufi@sendmail.ru +Alexandre Duret-Lutz duret_g@epita.fr +Alexey Mahotkin alexm@hsys.msk.ru +Alfred M. Szmidt ams@gnu.org +Allison Karlitskaya allison.karlitskaya@redhat.com +Andrea Urbani matfanjol@mail.com +Andreas Bergmeier lcid-fire@gmx.net +Andreas Buening andreas.buening@nexgo.de +Andreas Köhler andi5.py@gmx.net +Andreas Schwab schwab@suse.de +Andrew Cagney cagney@tpgi.com.au +Andrew Eikum aeikum@codeweavers.com +Andrew Suffield asuffield@debian.org +Andris Pavenis pavenis@lanet.lv +Andy Wingo wingo@pobox.com +Angus Leeming a.leeming@ic.ac.uk +Anthony Green green@cygnus.com +Antonio Diaz Diaz ant_diaz@teleline.es +Arkadiusz Miskiewicz misiek@pld.ORG.PL +Art Haas ahaas@neosoft.com +Arto C. Nirkko anirkko@insel.ch +Assar Westerlund assar@sics.se +Axel Belinfante Axel.Belinfante@cs.utwente.nl +Bas Wijnen shevek@fmf.nl +Ben Pfaff blp@cs.standford.edu +Benoit Sigoure tsuna@lrde.epita.fr +Bernard Giroud bernard.giroud@creditlyonnais.ch +Bernard Urban Bernard.Urban@meteo.fr +Bernd Jendrissek berndfoobar@users.sourceforge.net +Bert Wesarg bert.wesarg@googlemail.com +Bill Currie bcurrie@tssc.co.nz +Bill Davidson bill@kayhay.com +Bill Fenner fenner@parc.xerox.com +Bob Friesenhahn bfriesen@simple.dallas.tx.us +Bob Proulx rwp@hprwp.fc.hp.com +Bob Rossi bob@brasko.net +Bobby Jack bobbykjack@yahoo.co.uk +Boris Kolpackov boris@codesynthesis.com +Braden N. McDaniel braden@endoframe.com +Brandon Black blblack@gmail.com +Brendan O'Dea bod@debian.org +Brian Cameron Brian.Cameron@Sun.COM +Brian Ford ford@vss.fsi.com +Brian Gough bjg@network-theory.co.uk +Brian Jones cbj@nortel.net +Bruce Korb bkorb@gnu.org +Bruno Haible haible@ilog.fr +Carnë Draug carandraug+dev@gmail.com +Carsten Lohrke carlo@gentoo.org +Charles Wilson cwilson@ece.gatech.edu +Chris Hoogendyk hoogendyk@bio.umass.edu +Chris Pickett chris.pickett@mail.mcgill.ca +Chris Provenzano proven@io.proven.org +Christian Cornelssen ccorn@cs.tu-berlin.de +Christina Gratorp christina.gratorp@gmail.com +Claudio Fontana sick_soul@yahoo.it +Clifford Wolf clifford@clifford.at +Colin Watson cjwatson@ubuntu.com +Colomban Wendling lists.ban@herbesfolles.org +Dagobert Michelsen dam@opencsw.org +Daiki Ueno ueno@unixuser.org +Dalibor Topic robilad@kaffe.org +danbp danpb@nospam.postmaster.co.uk +Daniel Jacobowitz drow@false.org +Daniel Kahn Gillmor dkg@fifthhorseman.net +Daniel Richard G. skunk@iskunk.org +Debarshi Ray rishi@gnu.org +Dave Brolley brolley@redhat.com +Dave Goodell goodell@mcs.anl.gov +Dave Hart davehart@gmail.com +Dave Korn dave.korn.cygwin@googlemail.com +Dave Morrison dave@bnl.gov +David A. Swierczek swiercze@mr.med.ge.com +David A. Wheeler dwheeler@dwheeler.com +David Byron dbyron@dbyron.com +David Fang fang@csl.cornell.edu +Davyd Madeley davyd@fugro-fsi.com.au +David Pashley david@davidpashley.com +David Wohlferd dw@limegreensocks.com +David Zaroski cz253@cleveland.Freenet.Edu +Dean Povey dpovey@wedgetail.com +Dennis J. Linse Dennis.J.Linse@SAIC.com +Dennis Schridde devurandom@gmx.net +Derek R. Price derek.price@openavenue.com +Diab Jerius djerius@cfa.harvard.edu +Didier Cassirame faded@free.fr +Diego Elio Pettenò flameeyes@flameeyes.eu +Dieter Baron dillo@stieltjes.smc.univie.ac.at +Dieter Jurzitza DJurzitza@harmanbecker.com +Дилян Палаузов dilyan.palauzov@aegee.org +Dirk Mueller josef.moellers@suse.com +Dimitri Papadopoulos dimitri.papadopoulos@gmail.com +Dmitry Mikhin dmitrym@acres.com.au +Dmitry V. Levin ldv@altlinux.org +Doug Evans devans@cygnus.com +Duncan Gibson duncan@thermal.esa.int +Dilyan Palauzov dilyan.palauzov@aegee.org +Ed Hartnett ed@unidata.ucar.edu +Eleftherios Gkioulekas lf@amath.washington.edu +Elena A. Vengerova helen@oktetlabs.ru +Elmar Hoffmann elho@elho.net +Elrond Elrond@Wunder-Nett.org +Enrico Scholz enrico.scholz@informatik.tu-chemnitz.de +Erez Zadok ezk@cs.columbia.edu +Eric Bavier bavier@cray.com +Eric Blake eblake@redhat.com +Eric Dorland eric@debian.org +Eric Magnien emagnien@club-internet.fr +Eric Siegerman erics_97@pobox.com +Eric Sunshine sunshine@sunshineco.com +Erick Branderhorst branderh@iaehv.nl +Erik Lindahl E.Lindahl@chem.rug.nl +Esben Haabendal Soerensen bart@kom.aau.dk +Ezra Peisach epeisach@MED-XTAL.BU.EDU +Fabian Alenius fabian.alenius@gmail.com +Federico Simoncelli fsimonce@redhat.com +Felix Salfelder felix@salfelder.org +Felix Yan felixonmars@archlinux.org +Flavien Astraud flav42@yahoo.fr +Florian Briegel briegel@zone42.de +Francesco Salvestrini salvestrini@gmail.com +François Pinard pinard@iro.umontreal.ca +Fred Fish fnf@ninemoons.com +Ganesan Rajagopal rganesan@novell.com +Garrett D'Amore garrett@qualcomm.com +Garth Corral garthc@inktomi.com +Gary V Vaughan gvaughan@oranda.demon.co.uk +Gavin Smith gavinsmith0123@gmail.com +Geoffrey Keating geoffk@apple.com +Glenn Amerine glenn@pie.mhsc.org +Gord Matzigkeit gord@gnu.ai.mit.edu +Gordon Sadler gbsadler1@lcisp.com +Graham Reitz grahamreitz@me.com +Greg A. Woods woods@most.weird.com +Greg Schafer gschafer@zip.com.au +Guido Draheim guidod@gmx.de +Guillermo Ontañón gontanonext@pandasoftware.es +Gustavo Carneiro gjc@inescporto.pt +Gwenole Beauchesne gbeauchesne@mandrakesoft.com +H.J. Lu hjl@lucon.org +H.Merijn Brand h.m.brand@hccnet.nl +Hans Ulrich Niedermann hun@n-dimensional.de +Hanspeter Niederstrasser fink@snaggledworks.com +Harald Dunkel harald@CoWare.com +Harlan Stenn Harlan.Stenn@pfcs.com +He Li tippa000@yahoo.com +Henrik Frystyk Nielsen frystyk@w3.org +Hib Eris hib@hiberis.nl +Hilko Bengen bengen@debian.org +Holger Hans Peter Freyther holger@freyther.de +Ian Lance Taylor ian@cygnus.com +Ignacy Gawedzki i@lri.fr +Илья Н. Голубев gin@mo.msk.ru +Imacat imacat@mail.imacat.idv.tw +Infirit infirit@gmail.com +Inoue inoue@ainet.or.jp +Jack Kelly jack@jackkelly.name +Jacob Bachmeyer jcb@gnu.org +James Amundson amundson@users.sourceforge.net +James Bostock james.bostock@gmail.com +James Henstridge james@daa.com.au +James R. Van Zandt jrv@vanzandt.mv.com +James Youngman jay@gnu.org +Jan Engelhardt jengelh@medozas.de +Janos Farkas chexum@shadow.banki.hu +Jared Davis abiword@aiksaurus.com +Jason DeVinney jasondevinney@gmail.com +Jason Duell jcduell@lbl.gov +Jason Molenda crash@cygnus.co.jp +Javier Jardón jjardon@gnome.org +Jeff Bailey Jbailey@phn.ca +Jeff A. Daily jeff.daily@pnl.gov +Jeff Garzik jgarzik@pobox.com +Jeff Squyres jsquyres@lam-mpi.org +Jens Elkner elkner@imsgroup.de +Jens Krüger jens_krueger@physik.tu-muenchen.de +Jens Petersen petersen@redhat.com +Jeremy Nimmer jwnimmer@alum.mit.edu +Jerome Lovy jlovy@multimania.com +Jerome Santini santini@chambord.univ-orleans.fr +Jesse Chisholm jesse@ctc.volant.org +Jim Meyering meyering@na-net.ornl.gov +Joakim Tjernlund Joakim.Tjernlund@transmode.se +Jochen Kuepper jochen@uni-duesseldorf.de +Joel N. Weber II nemo@koa.iolani.honolulu.hi.us +Joerg-Martin Schwarz jms@jms.prima.ruhr.de +Johan Dahlin jdahlin@async.com.br +Johan Danielsson joda@pdc.kth.se +Johan Kristensen johankristensen@gmail.com +Johannes Nicolai johannes.nicolai@student.hpi.uni-potsdam.de +John Calcote john.calcote@gmail.com +John F Trudeau JohnTrudeau@firsthealth.com +John Pierce hawkfan@pyrotechnics.com +John Ratliff autoconf@technoplaza.net +John R. Cary cary@txcorp.com +John W. Coomes jcoomes@eng.Sun.COM +Jonathan L Peyton jonathan.l.peyton@intel.com +Jonathan Nieder jrnieder@gmail.com +Joseph S. Myers joseph@codesourcery.com +Josh MacDonald jmacd@cs.berkeley.edu +Joshua Cowan jcowan@jcowan.reslife.okstate.edu +Joshua Root jmr@macports.org +js pendry js.pendry@msdw.com +Juergen A. Erhard jae@laden.ilk.de +Juergen Keil jk@tools.de +Juergen Leising juergen.leising@gmx.de +Julien Sopena julien.sopena@lip6.fr +Jürg Billeter j@bitron.ch +Karl Berry kb@cs.umb.edu +Karl Heuer kwzh@gnu.org +Kelley Cook kcook@gcc.gnu.org +Kent Boortz kent@mysql.com +Kevin Dalley kevin@aimnet.com +Kevin P. Fleming. kpfleming@cox.net +Kevin Ryde user42@zip.com.au +Kevin Street street@iname.com +Klaus Reichl Klaus.Reichl@alcatel.at +Krzysztof Żelechowski giecrilj@stegny.2a.pl +L. Peter Deutsch ghost@aladdin.com +Ladislav Strojil Ladislav.Strojil@seznam.cz +Larry Daniel larry@larrybrucedaniel.com +Larry Jones larry.jones@sdrc.com +Lars Hecking lhecking@nmrc.ucc.ie +Lars J. Aas larsa@sim.no +Laurent Morichetti laurentm@cup.hp.com +Leo Davis ldavis@fonix.com +Leonardo Boiko leoboiko@conectiva.com.br +Libor Bukata libor.bukata@oracle.com +Loulou Pouchet loulou@lrde.epita.fr +Ludovic Courtès ludo@gnu.org +Lukas Fleischer lfleischer@lfos.de +Luo Yi luoyi.ly@gmail.com +Maciej Stachowiak mstachow@mit.edu +Maciej W. Rozycki macro@ds2.pg.gda.pl +Manu Rouat emmanuel.rouat@wanadoo.fr +Marc Herbert marc.herbert@intel.com +Marcus Brinkmann Marcus.Brinkmann@ruhr-uni-bochum.de +Marcus G. Daniels mgd@ute.santafe.edu +Marius Vollmer mvo@zagadka.ping.de +Marc-Antoine Perennou Marc-Antoine@Perennou.com +Mark D. Baushke mdb@cvshome.org +Mark Eichin eichin@cygnus.com +Mark Elbrecht snowball3@bigfoot.com +Mark Galassi rosalia@nis.lanl.gov +Mark Mitchell mark@codesourcery.com +Mark Phillips msp@nortelnetworks.com +Markku Rossi mtr@ngs.fi +Markus Duft Markus.Duft@salomon.at +Markus F.X.J. Oberhumer k3040e4@wildsau.idv-edu.uni-linz.ac.at +Martin Bravenboer martin@cs.uu.nl +Martin Frydl martin@idoox.com +Martin Waitz tali@admingilde.org +Mathias Doreille doreille@smr.ch +Mathias Froehlich M.Froehlich@science-computing.de +Mathias Hasselmann mathias.hasselmann@gmx.de +Matt Burgess matthew@linuxfromscratch.org +Matt Leach mleach@cygnus.com +Matthew D. Langston langston@SLAC.Stanford.EDU +Matthias Andree matthias.andree@gmx.de +Matthias Clasen clasen@mathematik.uni-freiburg.de +Matthias Klose doko@ubuntu.com +Matthieu Baerts matttbe@glx-dock.org +Max Horn max@quendi.de +Maxim Sinev good@goods.ru +Maynard Johnson maynardj@us.ibm.com +Merijn de Jonge M.de.Jonge@cwi.nl +Michael Brantley Michael-Brantley@deshaw.com +Michael Daniels mdaniels@rim.com +Michael Hofmann mhofma@googlemail.com +Michael Ploujnikov ploujj@gmail.com +Michael Zucchi notzed@gmail.com +Michel de Ruiter mdruiter@cs.vu.nl +Mike Castle dalgoda@ix.netcom.com +Mike Frysinger vapier@gentoo.org +Mike Nolta mrnolta@princeton.edu +Miles Bader miles@ccs.mt.nec.co.jp +Miloslav Trmac trmac@popelka.ms.mff.cuni.cz +Miodrag Vallat miodrag@ifrance.com +Mirko Streckenbach strecken@infosun.fmi.uni-passau.de +Miro Hroncok miro@hroncok.cz +Miroslaw Dobrzanski-Neumann mne@mosaic-ag.com +Morten Eriksen mortene@sim.no +Motoyuki Kasahara m-kasahr@sra.co.jp +Nathanael Nerode neroden@twcny.rr.com +Nelson H. F. Beebe beebe@math.utah.edu +Nicholas Wourms nwourms@netscape.net +Nick Bowler nbowler@elliptictech.com +Nick Brown brownn@brocade.com +Nick Gasson nick@nickg.me.uk +Nicola Fontana ntd@entidi.it +Nicolas Joly njoly@pasteur.fr +Nicolas Thiery nthiery@Icare.mines.edu +NightStrike nightstrike@gmail.com +Nik A. Melchior nam1@cse.wustl.edu +Nikolai Weibull now@bitwi.se +NISHIDA Keisuke knishida@nn.iij4u.or.jp +Noah Friedman friedman@gnu.ai.mit.edu +Norman Gray norman@astro.gla.ac.uk +Nyul Laszlo nyul@sol.cc.u-szeged.hu +OKUJI Yoshinori okuji@kuicr.kyoto-u.ac.jp +Olivier Fourdan fourdan@cena.fr +Olivier Louchart-Fletcher olivier@zipworld.com.au +Olly Betts olly@muscat.co.uk +Oren Ben-Kiki oren@ben-kiki.org +Owen Taylor otaylor@redhat.com +Panther Martin mrsmiley98@lycos.com +Patrick Welche prlw1@newn.cam.ac.uk +Patrik Weiskircher me@justp.at +Paul Berrevoets paul@swi.com +Paul D. Smith psmith@BayNetworks.COM +Paul Eggert eggert@twinsun.com +Paul Jarc prj@po.cwru.edu +Paul Lunau temp@lunau.me.uk +Paul Martinolich martinol@datasync.com +Paul Osmialowski pawel.osmialowski@arm.com +Paul Thomas PTHOMAS@novell.com +Pavel Raiskup praiskup@redhat.com +Pavel Roskin pavel_roskin@geocities.com +Pavel Sanda ps@twin.jikos.cz +Per Bothner bothner@cygnus.com +Per Cederqvist ceder@lysator.liu.se +Per Oyvind Hvidsten poeh@enter.vg +Peter Breitenlohner peb@mppmu.mpg.de +Peter Eisentraut peter_e@gmx.net +Peter Gavin pgavin@debaser.kicks-ass.org +Peter Hutterer peter.hutterer@who-t.net +Peter Johansson trojkan@gmail.com +Peter Mattis petm@scam.XCF.Berkeley.EDU +Peter Muir iyhi@yahoo.com +Peter O'Gorman peter@pogma.com +Peter Rosin peda@lysator.liu.se +Peter Seiderer seiderer123@ciselant.de +Petr Hracek phracek@redhat.com +Petter Reinholdtsen pere@hungry.com +Petteri Räty betelgeuse@gentoo.org +Phil Edwards phil@jaj.com +Phil Nelson phil@cs.wwu.edu +Philip Fong pwlfong@users.sourceforge.net +Philip S Tellis philip@ncst.ernet.in +Philipp A. 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Sammartino ryants@shaw.ca +Sam Hocevar sam@zoy.org +Sam Sirlin sam@kalessin.jpl.nasa.gov +Sam Steingold sds@gnu.org +Samuel Tardieu sam@rfc1149.net +Samy Mahmoudi samy.mahmoudi@gmail.com +Sander Niemeijer niemeijer@science-and-technology.nl +Santiago Vila sanvila@unex.es +Scott James Remnant scott@netsplit.com +Sébastien Wilmet swilmet@gnome.org +Sergey Poznyakoff gray@gnu.org.ua +Sergey Vlasov vsu@mivlgu.murom.ru +Seth Alves alves@hungry.com +Shannon L. Brown slbrow@sandia.gov +Shuhei Amakawa sa264@cam.ac.uk +Shigio Yamaguchi shigio@tamacom.com +Simon Josefsson jas@extundo.com +Simon Richter sjr@debian.org +Stefan Nordhausen nordhaus@informatik.hu-berlin.de +Stefano Lattarini stefano.lattarini@gmail.com +Stepan Kasal kasal@math.cas.cz +Steve M. Robbins steve@nyongwa.montreal.qc.ca +Steve Goetze goetze@dovetail.com +Steven Drake sbd@NetBSD.org +Steven G. Johnson stevenj@alum.mit.edu +Sven Verdoolaege skimo@kotnet.org +Tamara L. Dahlgren dahlgren1@llnl.gov +Tatu Ylonen ylo@ssh.fi +Teun Burgers burgers@ecn.nl +The Crimson Binome steve@nyongwa.montreal.qc.ca +Theodoros V. Kalamatianos thkala@gmail.com +Thien-Thi Nguyen ttn@glug.org +Thomas Fitzsimmons fitzsim@redhat.com +Thomas Gagne tgagne@ix.netcom.com +Thomas Jahns jahns@dkrz.de +Thomas Klausner tk@giga.or.at +Thomas Morgan tmorgan@pobox.com +Thomas Schwinge tschwinge@gnu.org +Thomas Tanner tanner@ffii.org +Toralf Förster toralf.foerster@gmx.de +Tim Goodwin tjg@star.le.ac.uk +Tim Landscheidt tim@tim-landscheidt.de +Tim Mooney mooney@dogbert.cc.ndsu.NoDak.edu +Tim Retout diocles@debian.org +Tim Rice tim@multitalents.net +Tim Van Holder tim.van.holder@pandora.be +Tobias Hansen thansen@debian.org +Toshio Kuratomi toshio@tiki-lounge.com +Tom Epperly tepperly@llnl.gov +Tom Rini tom_rini@mentor.com +Ulrich Drepper drepper@gnu.ai.mit.edu +Ulrich Eckhardt eckhardt@satorlaser.com +Václav Haisman V.Haisman@sh.cvut.cz +Václav Zeman vhaisman@gmail.com +Vadim Zeitlin Vadim.zeitlin@dptmaths.ens-cachan.fr +Vasyl Khalak basiliomail@gmail.com +Vincent Lefevre vincent@vinc17.org +Vladimir Serbinenko phcoder@gmail.com +Volker Boerchers vboerchers@tecon.de +Weiller Ronfini weillerronfini@yahoo.com.br +Werner John john@oswf.de +Werner Koch wk@isil.d.shuttle.de +Werner Lemberg wl@gnu.org +William Pursell bill.pursell@gmail.com +William S Fulton wsf@fultondesigns.co.uk +Yann Droneaud ydroneaud@meuh.eu.org +Younes Younes younes@cs.tu-berlin.de +Zack Weinberg zackw@panix.com +Zbigniew Jędrzejewski-Szmek zbyszek@in.waw.pl +Zoltan Rado z.rado@chello.hu + +;; Local Variables: +;; mode: text +;; coding: utf-8 +;; End: diff --git a/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/AUTHORS.txt b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/AUTHORS.txt new file mode 100644 index 0000000..7193d71 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/AUTHORS.txt @@ -0,0 +1,18 @@ + +HIDAPI Authors: + +Alan Ott : + Original Author and Maintainer + Linux, Windows, and Mac implementations + +Ludovic Rousseau : + Formatting for Doxygen documentation + Bug fixes + Correctness fixes + +libusb/hidapi Team: + Development/maintainance since June 4th 2019 + +For a comprehensive list of contributions, see the commit list at github: + https://github.com/libusb/hidapi/graphs/contributors + diff --git a/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-bsd.txt b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-bsd.txt new file mode 100644 index 0000000..538cdf9 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-bsd.txt @@ -0,0 +1,26 @@ +Copyright (c) 2010, Alan Ott, Signal 11 Software +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Signal 11 Software nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. 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But first, please read +. diff --git a/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-orig.txt b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-orig.txt new file mode 100644 index 0000000..e3f3380 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-orig.txt @@ -0,0 +1,9 @@ + HIDAPI - Multi-Platform library for + communication with HID devices. + + Copyright 2009, Alan Ott, Signal 11 Software. + All Rights Reserved. + + This software may be used by anyone for any reason so + long as the copyright notice in the source files + remains intact. diff --git a/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE.txt b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE.txt new file mode 100644 index 0000000..e1676d4 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE.txt @@ -0,0 +1,13 @@ +HIDAPI can be used under one of three licenses. + +1. The GNU General Public License, version 3.0, in LICENSE-gpl3.txt +2. A BSD-Style License, in LICENSE-bsd.txt. +3. The more liberal original HIDAPI license. LICENSE-orig.txt + +The license chosen is at the discretion of the user of HIDAPI. For example: +1. An author of GPL software would likely use HIDAPI under the terms of the +GPL. + +2. An author of commercial closed-source software would likely use HIDAPI +under the terms of the BSD-style license or the original HIDAPI license. + diff --git a/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/README.md b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/README.md new file mode 100644 index 0000000..257b9f3 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/README.md @@ -0,0 +1,196 @@ +## HIDAPI library for Windows, Linux, FreeBSD and macOS + +| CI instance | Status | +|----------------------|--------| +| `Linux/macOS/Windows (master)` | [![GitHub Builds](https://github.com/libusb/hidapi/workflows/GitHub%20Builds/badge.svg?branch=master)](https://github.com/libusb/hidapi/actions/workflows/builds.yml?query=branch%3Amaster) | +| `Windows (master)` | [![Build status](https://ci.appveyor.com/api/projects/status/xfmr5fo8w0re8ded/branch/master?svg=true)](https://ci.appveyor.com/project/libusb/hidapi/branch/master) | +| `BSD, last build (branch/PR)` | [![builds.sr.ht status](https://builds.sr.ht/~z3ntu/hidapi.svg)](https://builds.sr.ht/~z3ntu/hidapi) | +| `Coverity Scan (last)` | ![Coverity Scan](https://scan.coverity.com/projects/583/badge.svg) | + +HIDAPI is a multi-platform library which allows an application to interface +with USB and Bluetooth HID-Class devices on Windows, Linux, FreeBSD, and macOS. +HIDAPI can be either built as a shared library (`.so`, `.dll` or `.dylib`) or +can be embedded directly into a target application by adding a _single source_ +file (per platform) and a single header.
+See [remarks](BUILD.md#embedding-hidapi-directly-into-your-source-tree) on embedding _directly_ into your build system. + +HIDAPI library was originally developed by Alan Ott ([signal11](https://github.com/signal11)). + +It was moved to [libusb/hidapi](https://github.com/libusb/hidapi) on June 4th, 2019, in order to merge important bugfixes and continue development of the library. + +## Table of Contents + +* [About](#about) + * [Test GUI](#test-gui) + * [Console Test App](#console-test-app) +* [What Does the API Look Like?](#what-does-the-api-look-like) +* [License](#license) +* [Installing HIDAPI](#installing-hidapi) +* [Build from Source](#build-from-source) + + +## About + +### HIDAPI has four back-ends: +* Windows (using `hid.dll`) +* Linux/hidraw (using the Kernel's hidraw driver) +* libusb (using libusb-1.0 - Linux/BSD/other UNIX-like systems) +* macOS (using IOHidManager) + +On Linux, either the hidraw or the libusb back-end can be used. There are +tradeoffs, and the functionality supported is slightly different. Both are +built by default. It is up to the application linking to hidapi to choose +the backend at link time by linking to either `libhidapi-libusb` or +`libhidapi-hidraw`. + +Note that you will need to install an udev rule file with your application +for unprivileged users to be able to access HID devices with hidapi. Refer +to the [69-hid.rules](udev/69-hid.rules) file in the `udev` directory +for an example. + +#### __Linux/hidraw__ (`linux/hid.c`): + +This back-end uses the hidraw interface in the Linux kernel, and supports +both USB and Bluetooth HID devices. It requires kernel version at least 2.6.39 +to build. In addition, it will only communicate with devices which have hidraw +nodes associated with them. +Keyboards, mice, and some other devices which are blacklisted from having +hidraw nodes will not work. Fortunately, for nearly all the uses of hidraw, +this is not a problem. + +#### __Linux/FreeBSD/libusb__ (`libusb/hid.c`): + +This back-end uses libusb-1.0 to communicate directly to a USB device. This +back-end will of course not work with Bluetooth devices. + +### Test GUI + +HIDAPI also comes with a Test GUI. The Test GUI is cross-platform and uses +Fox Toolkit . It will build on every platform +which HIDAPI supports. Since it relies on a 3rd party library, building it +is optional but it is useful when debugging hardware. + +NOTE: Test GUI based on Fox Toolkit is not actively developed nor supported +by HIDAPI team. It is kept as a historical artifact. It may even work sometime +or on some platforms, but it is not going to get any new features or bugfixes. + +Instructions for installing Fox-Toolkit on each platform is not provided. +Make sure to use Fox-Toolkit v1.6 if you choose to use it. + +### Console Test App + +If you want to play around with your HID device before starting +any development with HIDAPI and using a GUI app is not an option for you, you may try [`hidapitester`](https://github.com/todbot/hidapitester). + +This app has a console interface for most of the features supported +by HIDAPI library. + +## What Does the API Look Like? + +The API provides the most commonly used HID functions including sending +and receiving of input, output, and feature reports. The sample program, +which communicates with a heavily hacked up version of the Microchip USB +Generic HID sample looks like this (with error checking removed for +simplicity): + +**Warning: Only run the code you understand, and only when it conforms to the +device spec. Writing data (`hid_write`) at random to your HID devices can break them.** + +```c +#include // printf +#include // wchar_t + +#include + +#define MAX_STR 255 + +int main(int argc, char* argv[]) +{ + int res; + unsigned char buf[65]; + wchar_t wstr[MAX_STR]; + hid_device *handle; + int i; + + // Initialize the hidapi library + res = hid_init(); + + // Open the device using the VID, PID, + // and optionally the Serial number. + handle = hid_open(0x4d8, 0x3f, NULL); + if (!handle) { + printf("Unable to open device\n"); + hid_exit(); + return 1; + } + + // Read the Manufacturer String + res = hid_get_manufacturer_string(handle, wstr, MAX_STR); + printf("Manufacturer String: %ls\n", wstr); + + // Read the Product String + res = hid_get_product_string(handle, wstr, MAX_STR); + printf("Product String: %ls\n", wstr); + + // Read the Serial Number String + res = hid_get_serial_number_string(handle, wstr, MAX_STR); + printf("Serial Number String: (%d) %ls\n", wstr[0], wstr); + + // Read Indexed String 1 + res = hid_get_indexed_string(handle, 1, wstr, MAX_STR); + printf("Indexed String 1: %ls\n", wstr); + + // Toggle LED (cmd 0x80). The first byte is the report number (0x0). + buf[0] = 0x0; + buf[1] = 0x80; + res = hid_write(handle, buf, 65); + + // Request state (cmd 0x81). The first byte is the report number (0x0). + buf[0] = 0x0; + buf[1] = 0x81; + res = hid_write(handle, buf, 65); + + // Read requested state + res = hid_read(handle, buf, 65); + + // Print out the returned buffer. + for (i = 0; i < 4; i++) + printf("buf[%d]: %d\n", i, buf[i]); + + // Close the device + hid_close(handle); + + // Finalize the hidapi library + res = hid_exit(); + + return 0; +} +``` + +You can also use [hidtest/test.c](hidtest/test.c) +as a starting point for your applications. + + +## License + +HIDAPI may be used by one of three licenses as outlined in [LICENSE.txt](LICENSE.txt). + +## Installing HIDAPI + +If you want to build your own application that uses HID devices with HIDAPI, +you need to get HIDAPI development package. + +Depending on what your development environment is, HIDAPI likely to be provided +by your package manager. + +For instance on Ubuntu, HIDAPI is available via APT: +```sh +sudo apt install libhidapi-dev +``` + +HIDAPI package name for other systems/package managers may differ. +Check the documentation/package list of your package manager. + +## Build from Source + +Check [BUILD.md](BUILD.md) for details. diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/AUTHORS b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/AUTHORS new file mode 100644 index 0000000..e8f5a69 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/AUTHORS @@ -0,0 +1,91 @@ +Main developers: + + Intra2net AG + +Contributors in alphabetical order, +see Changelog for full details: + + Adam Malinowski + Alain Abbas + Alex Harford + Alexander Lehmann + Anders Larsen + Andrei Errapart + Andrew John Rogers + Arnim Läuger + Aurelien Jarno + Benjamin Vanheuverzwijn + Chris Morgan + Chris Zeh + Claudio Lanconelli + Clifford Wolf + Dan Dedrick + Daniel Kirkham + David Challis + Davide Michelizza + Denis Sirotkin + Diego Elio Pettenò + Emil + Eneas U de Queiroz + Eric Schott + Eugene Hutorny + Evan Nemerson + Evgeny Sinelnikov + Fabrice Fontaine + Fahrzin Hemmati + Flynn Marquardt + Forest Crossman + Frank Dana + Holger Mößinger + Ian Abbott + Jared Boone + Jarkko Sonninen + Jean-Daniel Merkli + Jochen Sprickerhof + Joe Zbiciak + Jon Beniston + Jordan Rupprecht + Juergen Beisert + Lorenz Moesenlechner + Marek Vavruša + Marius Kintel + Mark Hämmerling + Matthias Janke + Matthias Kranz + Matthias Richter + Matthijs ten Berge + Max + Maxwell Dreytser + Michel Zou + Mike Frysinger + Nathael Pajani + Nathan Fraser + Oleg Seiljus + Paul Fertser + Pawel Jewstafjew + Peter Holik + Raphael Assenat + Richard Shaw + Robby McKilliam + Robert Cox + Robin Haberkorn + Rodney Sinclair + Rogier Wolff + Rolf Fiedler + Roman Lapin + Salvador Eduardo Tropea + Stephan Linz + Steven Turner + Tarek Heiland + Thilo Schulz + Thimo Eichstaedt + Thomas Fischl + Thomas Klose + Tim Ansell + Tom Saunders + Uwe Bonnes + Vladimir Yakovlev + Wilfried Holzke + Xiaofan Chen + Yegor Yefremov + Yi-Shin Li diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING-CMAKE-SCRIPTS b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING-CMAKE-SCRIPTS new file mode 100644 index 0000000..4b41776 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING-CMAKE-SCRIPTS @@ -0,0 +1,22 @@ +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. 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Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/LICENSE b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/LICENSE new file mode 100644 index 0000000..f1831c0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/LICENSE @@ -0,0 +1,25 @@ +The C library "libftdi1" is distributed under the +GNU Library General Public License version 2. + +A copy of the GNU Library General Public License (LGPL) is included +in this distribution, in the file COPYING.LIB. + +---------------------------------------------------------------------- + +The C++ wrapper "ftdipp1" is distributed under the GNU General +Public License version 2 (with a special exception described below). + +A copy of the GNU General Public License (GPL) is included +in this distribution, in the file COPYING.GPL. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file +does not by itself cause the resulting work to be covered +by the GNU General Public License. + +However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based +on this file might be covered by the GNU General Public License. diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README new file mode 100644 index 0000000..c64f884 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README @@ -0,0 +1,67 @@ +-------------------------------------------------------------------- +libftdi version 1.5 +-------------------------------------------------------------------- + +libftdi - A library (using libusb) to talk to FTDI's UART/FIFO chips +including the popular bitbang mode. + +The following chips are supported: +* FT230X +- FT4232H / FT2232H +- FT232R / FT245R +- FT2232L / FT2232D / FT2232C +- FT232BM / FT245BM (and the BL/BQ variants) +- FT8U232AM / FT8U245AM + +libftdi requires libusb 1.x. + +The AUTHORS file contains a list of all the people +that made libftdi possible what it is today. + +Changes +------- +* Implement tc[io]flush methods & deprecate broken purge_buffers methods + + Please check your code for ftdi_usb_purge_rx_buffer(), + ftdi_usb_purge_tx_buffer() and ftdi_usb_purge_buffers() + and migrate to the new ftdi_tc[io]flush() methods. + + Old code will continue to function, but you'll get + a deprecation warning during compilation. + +* Add program to test buffer flush (purge) functionality +* Add kernel driver auto attach/detach. + See new AUTO_DETACH_REATACH_SIO_MODULE option +* Add ftdi_setflowctrl_xonxoff() +* ftdi_eeprom / eeprom handling: + * Unify handling of all boolean eeprom flags + * Add device release number support + * Add channel_a_driver support for type xxR chips + * Add support for group0 drive levels on x232H chips + * Fix handling of high_current_drive parameter + * Fix inverted handling of VCP driver field for TYPE_R chips + * New --verbose option for eeprom decode operation +* Add example code for async mode +* Add SPDX license identifiers to the core library & ftdi_eeprom +* Various python SWIG wrapper improvements +* Various cmake file improvements +* Fix small bugs in error code paths + +You'll find the newest version of libftdi at: +https://www.intra2net.com/en/developer/libftdi + + +Quick start +----------- +mkdir build +cd build + +cmake -DCMAKE_INSTALL_PREFIX="/usr" ../ +make +make install + +More verbose build instructions are in "README.build" + +-------------------------------------------------------------------- +www.intra2net.com 2003-2020 Intra2net AG +-------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.build b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.build new file mode 100644 index 0000000..e130ca0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.build @@ -0,0 +1,96 @@ +Here is a short tutorial on how to build libftdi git under +Ubuntu 12.10, But it is similar on other Linux distros. + +1) Install the build tools +sudo apt-get install build-essential (yum install make automake gcc gcc-c++ kernel-devel) +sudo apt-get install git-core (yum install git) +sudo apt-get install cmake (yum install cmake) +sudo apt-get install doxygen (for building documentations) (yum install doxygen) + +2) Install dependencies +sudo apt-get install libusb-1.0-devel (yum install libusb-devel) +(if the system comes with older version like 1.0.8 or +earlier, it is recommended you build libusbx-1.0.14 or later). + +sudo apt-get install libconfuse-dev (for ftdi-eeprom) (yum install libconfuse-devel) +sudo apt-get install swig python-dev (for python bindings) (yum install swig python-devel) +sudo apt-get install libboost-all-dev (for C++ binding and unit test) (yum install boost-devel) + +3) Clone the git repository +mkdir libftdi +cd libftdi +git clone git://developer.intra2net.com/libftdi + +If you are building the release tar ball, just extract the source +tar ball. + +4) Build the git source and install +cd libftdi +mkdir build +cd build +cmake -DCMAKE_INSTALL_PREFIX="/usr" ../ +make +sudo make install + +5) carry out some tests +cd examples + +mcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$ +./find_all_pp -v 0x0403 -p 0x6001 +Found devices ( VID: 0x403, PID: 0x6001 ) +------------------------------------------------ +FTDI (0x8730800): ftdi, usb serial converter, ftDEH51S (Open OK) +FTDI (0x8730918): FTDI, FT232R USB UART, A8007Ub5 (Open OK) + +mcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$ ./eeprom +2 FTDI devices found: Only Readout on EEPROM done. Use +VID/PID/desc/serial to select device +Decoded values of device 1: +Chip type 1 ftdi_eeprom_size: 128 +0x000: 00 00 03 04 01 60 00 04 a0 16 08 00 10 01 94 0a .....`.. ........ +0x010: 9e 2a c8 12 0a 03 66 00 74 00 64 00 69 00 2a 03 .*....f. t.d.i.*. +0x020: 75 00 73 00 62 00 20 00 73 00 65 00 72 00 69 00 u.s.b. . s.e.r.i. +0x030: 61 00 6c 00 20 00 63 00 6f 00 6e 00 76 00 65 00 a.l. .c. o.n.v.e. +0x040: 72 00 74 00 65 00 72 00 12 03 66 00 74 00 44 00 r.t.e.r. ..f.t.D. +0x050: 45 00 48 00 35 00 31 00 53 00 02 03 00 00 00 00 E.H.5.1. S....... +0x060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ +0x070: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 16 02 ........ ........ +VID: 0x0403 +PID: 0x6001 +Release: 0x0400 +Bus Powered: 44 mA USB Remote Wake Up +Manufacturer: ftdi +Product: usb serial converter +Serial: ftDEH51S +Checksum : 0216 +Enable Remote Wake Up +PNP: 1 +Decoded values of device 2: +Chip type 3 ftdi_eeprom_size: 128 +0x000: 00 40 03 04 01 60 00 00 a0 2d 08 00 00 00 98 0a .@...`.. .-...... +0x010: a2 20 c2 12 23 10 05 00 0a 03 46 00 54 00 44 00 . ..#... ..F.T.D. +0x020: 49 00 20 03 46 00 54 00 32 00 33 00 32 00 52 00 I. .F.T. 2.3.2.R. +0x030: 20 00 55 00 53 00 42 00 20 00 55 00 41 00 52 00 .U.S.B. .U.A.R. +0x040: 54 00 12 03 41 00 38 00 30 00 30 00 37 00 55 00 T...A.8. 0.0.7.U. +0x050: 62 00 35 00 c9 bf 1c 80 00 00 00 00 00 00 00 00 b.5..... ........ +0x060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ +0x070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f 23 ........ .......# +0x080: 2c 04 d3 fb 00 00 c9 bf 1c 80 42 00 00 00 00 00 ,....... ..B..... +0x090: 00 00 00 00 00 00 00 00 38 41 32 52 4a 33 47 4f ........ 8A2RJ3GO +VID: 0x0403 +PID: 0x6001 +Release: 0x0000 +Bus Powered: 90 mA USB Remote Wake Up +Manufacturer: FTDI +Product: FT232R USB UART +Serial: A8007Ub5 +Checksum : 230f +Internal EEPROM +Enable Remote Wake Up +PNP: 1 +Channel A has Mode UART VCP +C0 Function: TXLED +C1 Function: RXLED +C2 Function: TXDEN +C3 Function: PWREN +C4 Function: SLEEP diff --git a/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.mingw b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.mingw new file mode 100644 index 0000000..5b9e65c --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.mingw @@ -0,0 +1,38 @@ +* How to cross compile libftdi-1.x for Windows? * + 1 - Prepare a pkg-config wrapper according to + https://autotools.io/pkgconfig/cross-compiling.html , + additionally export PKG_CONFIG_ALLOW_SYSTEM_CFLAGS and + PKG_CONFIG_ALLOW_SYSTEM_LIBS. + 2 - Write a CMake toolchain file according to + http://www.vtk.org/Wiki/CmakeMingw . Change the path to your future sysroot. + 3 - Get libusb sources (either by cloning the git repo or by downloading a + tarball). Unpack, autogen.sh (when building from git), and configure like this: + ./configure --build=`./config.guess` --host=i686-w64-mingw32 \ + --prefix=/usr --with-sysroot=$HOME/i686-w64-mingw32-root/ + 4 - run + make install DESTDIR=$HOME/i686-w64-mingw32-root/ + 5 - go to libftdi-1.x source directory and run + cmake -DCMAKE_TOOLCHAIN_FILE=~/Toolchain-mingw.cmake \ + -DCMAKE_INSTALL_PREFIX="/usr" \ + -DPKG_CONFIG_EXECUTABLE=`which i686-w64-mingw32-pkg-config` + 6 - run + make install DESTDIR=$HOME/i686-w64-mingw32-root/ + +* How to run libftdi 1.x under Windows * + +On 26-Jan-2014, libusbx and libusb project were merged with the release +of libusb-1.0.18 and now the project is called libusb. + +libusb Windows backend will need to rely on a proper driver to run. +Please refer to the following wiki page for proper driver installation. +https://github.com/libusb/libusb/wiki/Windows#wiki-How_to_use_libusb_on_Windows + +As of 26-Jan-2014, libusb Windows backend supports WinUSB, +libusb0.sys and libusbk.sys driver. However, libusb's support of +libusb0.sys and libusbk.sys is considered to be less mature than +WinUSB. Therefore, WinUSB driver installation using Zadig +is recommended. + +Take note once you replace the original FTDI driver with WinUSB driver, +you can no longer use the functionality the original FTDI driver provides +(eg. Virtual Serial Port or D2XX). diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/AUTHORS b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/AUTHORS new file mode 100644 index 0000000..8bedd79 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/AUTHORS @@ -0,0 +1 @@ +Bruno Haible diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/COPYING b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/COPYING new file mode 100644 index 0000000..94a9ed0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/DEPENDENCIES b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/DEPENDENCIES new file mode 100644 index 0000000..748fb83 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/DEPENDENCIES @@ -0,0 +1,76 @@ +The following packages should be installed before GNU libiconv is installed +(runtime dependencies that are also build dependencies): + +None. + + +The following packages should be installed when GNU libiconv is installed +(runtime dependencies, but not build dependencies): + +None. + + +The following should be installed when GNU libiconv is built, but are not +needed later, once it is installed (build dependencies, but not runtime +dependencies): + +* A C runtime, compiler, linker, etc. + + Mandatory. + Either the platform's native 'cc', or GCC 3.1 or newer. + + GCC Homepage: + https://gcc.gnu.org/ + + Download: + https://ftp.gnu.org/gnu/gcc/ + +* A 'make' utility. + + Mandatory. + Either the platform's native 'make' (for in-tree builds only), + or GNU Make 3.79.1 or newer. + + GNU Make Homepage: + https://www.gnu.org/software/make/ + + Download: + https://ftp.gnu.org/gnu/make/ + +* A shell + + Mandatory. + Either the platform's native 'sh', or Bash. + + Homepage: + https://www.gnu.org/software/bash/ + + Download: + https://ftp.gnu.org/gnu/bash/ + +* Core POSIX utilities, including: + [ basename cat chgrp chmod chown cp dd echo expand expr + false hostname install kill ln ls md5sum mkdir mkfifo + mknod mv printenv pwd rm rmdir sleep sort tee test touch + true uname + + Mandatory. + Either the platform's native utilities, or GNU coreutils. + + Homepage: + https://www.gnu.org/software/coreutils/ + + Download: + https://ftp.gnu.org/gnu/coreutils/ + +* The comparison utilities 'cmp' and 'diff'. + + Mandatory. + Either the platform's native utilities, or GNU diffutils. + + Homepage: + https://www.gnu.org/software/diffutils/ + + Download: + https://ftp.gnu.org/gnu/diffutils/ + +* Grep. + + Mandatory. + Either the platform's native grep, or GNU grep. + + Homepage: + https://www.gnu.org/software/grep/ + + Download: + https://ftp.gnu.org/gnu/grep/ + +* Awk. + + Mandatory. + Either the platform's native awk, mawk, or nawk, or GNU awk. + + Homepage: + https://www.gnu.org/software/gawk/ + + Download: + https://ftp.gnu.org/gnu/gawk/ diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/NEWS b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/NEWS new file mode 100644 index 0000000..9d3cdfb --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/NEWS @@ -0,0 +1,204 @@ +New in 1.17: +* The libiconv library is now licensed under the LGPL version 2.1, instead of + the LGPL version 2.0. The iconv program continues to be licensed under GPL + version 3. +* Added converters for many single-byte EBCDIC encodings: + IBM-{037,273,277,278,280,282,284,285,297,423,424,425,500,838,870,871,875}, + IBM-{880,905,924,1025,1026,1047,1097,1112,1122,1123,1130,1132,1137,1140}, + IBM-{1141,1142,1143,1144,1145,1146,1147,1148,1149,1153,1154,1155,1156,1157}, + IBM-{1158,1160,1164,1165,1166,4971,12712,16804}. + They are available through the configure option '--enable-extra-encodings'. + +New in 1.16: +* The preloadable library has been removed. + +New in 1.15: +* The UTF-8 converter now rejects surrogates and out-of-range code points. +* Added ISO-2022-JP-MS converter. +* Updated the CP1255 converter to map one more character. +* The functions now support strings longer than 2 GB. + +New in 1.14: +* The 'iconv' program now produces its output as soon as it can. It no longer + unnecessarily waits for more input. +* Updated the GB18030 converter to map 25 characters to code points that have + been to Unicode since 2000, rather than to code points in the Private Use + Area. +* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to + BIG5-HKSCS:2004. A new converter BIG5-HKSCS:2008 is added. BIG5-HKSCS is now + an alias for BIG5-HKSCS:2008. +* Fixed a bug in the conversion to wchar_t. +* Fixed a small bug in the CP1258 converter. + +New in 1.13: +* The library and the iconv program now understand platform dependent aliases, + for better compatibility with the platform's own iconv_open function. + Examples: "646" on Solaris, "iso88591" on HP-UX, "IBM-1252" on AIX. +* For stateful encodings, when the input ends with a shift sequence followed + by invalid input, the iconv function now increments the input pointer past + the shift sequence before returning (size_t)(-1) with errno = EILSEQ. This + is also like GNU libc's iconv() behaves. +* The library exports a new function iconv_open_into() that stores the + conversion descriptor in pre-allocated memory, rather than allocating fresh + memory for it. +* Added CP1131 converter. + +New in 1.12: +* The iconv program is now licensed under the GPL version 3, instead of the + GPL version 2. The libiconv library continues to be licensed under LGPL. +* Added RK1048 converter. +* On AIX, an existing system libiconv no longer causes setlocale() to fail. +* Upgraded EUC-KR, JOHAB to include the Korean postal code sign. + +New in 1.11: +* The iconv program has new options --unicode-subst, --byte-subst, + --widechar-subst that allow to specify substitutions for characters that + cannot be converted. +* The iconv program now understands long options: + long option equivalent to + --from-code -f + --to-code -t + --list -l + --silent -s +* The CP936 converter is now different from the GBK converter: it has changed + to include the Euro sign and private area characters. CP936 is no longer an + alias of GBK. +* Updated GB18030 converter to include all private area characters. +* Updated CP950 converter to include the Euro sign and private area characters. +* Updated CP949 converter to include private area characters. +* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to + BIG5-HKSCS:1999 and updated to Unicode 4. New converters BIG5-HKSCS:2001 and + BIG5-HKSCS:2004 are added. BIG5-HKSCS is now an alias for BIG5-HKSCS:2004. +* Added a few irreversible mappings to the CP932 converter. +* Tidy up the list of symbols exported from libiconv (assumes gcc >= 4.0). + +New in 1.10: +* Added ISO-8859-11 converter. +* Updated the ISO-8859-7 converter. +* Added ATARIST converter, available through --enable-extra-encodings. +* Added BIG5-2003 converter (experimental), available through + --enable-extra-encodings. +* Updated EUC-TW converter to include the Euro sign. +* The preloadable library has been renamed from libiconv_plug.so to + preloadable_libiconv.so. +* Portability to mingw. + +New in 1.9: +* Many more transliterations. +* New configuration option --enable-relocatable. See the INSTALL.generic file + for details. + +New in 1.8: +* The iconv program has new options -l, -c, -s. +* The iconv program is internationalized. +* Added C99 converter. +* Added KOI8-T converter. +* New configuration option --enable-extra-encodings that enables a bunch of + additional encodings; see the README for details. +* Updated the ISO-8859-16 converter. +* Upgraded BIG5-HKSCS, EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to + Unicode 3.2. +* Upgraded EUC-KR, CP949, JOHAB converters to include the Euro sign. +* Changed the ARMSCII-8 converter. +* Extended the EUC-JP encoder so that YEN SIGN characters don't cause failures + in Shift_JIS to EUC-JP conversion. +* The JAVA converter now handles characters outside the Unicode BMP correctly. +* Fixed a bug in the CP1255, CP1258, TCVN decoders: The base characters of + combining characters could be dropped at the end of the conversion buffer. +* Fixed a bug in the transliteration that could lead to excessive memory + allocations in libintl when transliteration was needed. +* Portability to BSD/OS and SCO 3.2.5. + +New in 1.7: +* Added UTF-32, UTF-32BE, UTF-32LE converters. +* Changed CP1255, CP1258 and TCVN converters to handle combining characters. +* Changed EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1 + converters to use fullwidth Yen sign instead of halfwidth Yen sign, and + fullwidth tilde instead of halfwidth tilde. +* Upgraded EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to Unicode 3.1. +* Changed the GB18030 converter to not reject unassigned and private-use + Unicode characters. +* Fixed a bug in the byte order mark treatment of the UCS-4 decoder. +* The manual pages are now distributed also in HTML format. + +New in 1.6: +* The iconv program's -f and -t options are now optional. +* Many more transliterations. +* Added CP862 converter. +* Changed the GB18030 converter. +* Portability to DOS with DJGPP. + +New in 1.5: +* Added an iconv(1) program. +* New locale dependent encodings "char", "wchar_t". +* Transliteration is now off by default. Use a //TRANSLIT suffix to enable it. +* The JOHAB encoding is documented again. +* Changed a few mappings in the CP950 converter. + +New in 1.4: +* Added GB18030, BIG5HKSCS converters. +* Portability to OS/2 with emx+gcc. + +New in 1.3: +* Added UCS-2BE, UCS-2LE, UCS-4BE, UCS-4LE converters. +* Fixed the definition of EILSEQ on SunOS4. +* Fixed a build problem on OSF/1. +* Support for building as a shared library on Woe32. + +New in 1.2: +* Added UTF-16BE and UTF-16LE converters. +* Changed the UTF-16 encoder. +* Fixed the treatment of tab characters in the UTF-7 converter. +* Fixed an internal error when output buffer was not large enough. + +New in 1.1: +* Added ISO-8859-16 converter. +* Added CP932 converter, a variant of SHIFT_JIS. +* Added CP949 converter, a variant of EUC-KR. +* Improved the ISO-2022-CN-EXT converter: It now covers the ISO-IR-165 range. +* Updated the ISO-8859-8 conversion table. +* The JOHAB encoding is deprecated and not documented any more. +* Fixed two build problems: 1. "make -n check" failed. 2. When libiconv was + already installed, "make" failed. + +New in 1.0: +* Added transliteration facilities. +* Added a test suite. +* Fixed the iconv(3) manual page and function: the return value was not + described correctly. +* Fixed a bug in the CP1258 decoder: invalid bytes now yield EILSEQ instead of + U+FFFD. +* Fixed a bug in the Georgian-PS encoder: accept U+00E6. +* Fixed a bug in the EUC-JP encoder: reject 0x8E5C and 0x8E7E. +* Fixed a bug in the KSC5601 and JOHAB converters: they recognized some Hangul + characters at some invalid code positions. +* Fixed a bug in the EUC-TW decoder; it was severely broken. +* Fixed a bug in the CP950 converter: it recognized a dubious BIG5 range. + +New in 0.3: +* Reduced the size of the tables needed for the JOHAB converter. +* Portability to Woe32. + +New in 0.2: +* Added KOI8-RU, CP850, CP866, CP874, CP950, ISO-2022-CN-EXT, GBK and + ISO-2022-JP-1 converters. +* Added MACINTOSH as an alias for MAC-ROMAN. +* Added ASMO-708 as an alias for ISO-8859-6. +* Added ELOT_928 as an alias for ISO-8859-7. +* Improved the EUC-TW converter: Treat CNS 11643 plane 3. +* Improved the ISO-2022-KR and EUC-KR converters: Hangul characters are + decomposed into Jamo when needed. +* Improved the CP932 converter. +* Updated the CP1133, MULELAO-1 and ARMSCII-8 mappings. +* The EUC-JP and SHIFT_JIS converters now cover the user-defined range. +* Fixed a possible buffer overrun in the JOHAB converter. +* Fixed a bug in the UTF-7, ISO-2022-*, HZ decoders: a shift sequence a the + end of the input no longer gives an error. +* The HZ encoder now always terminates its output in the ASCII state. +* Use a perfect hash table for looking up the aliases. + +New in 0.1: +* Portability to Linux/glibc-2.0.x, Linux/libc5, OSF/1, FreeBSD. +* Fixed a bug in the EUC-JP decoder. Extended the ISO-2022-JP-2 converter. +* Made TIS-620 mapping consistent with glibc-2.1. + diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/README b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/README new file mode 100644 index 0000000..e7375cb --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/README @@ -0,0 +1,173 @@ + GNU LIBICONV - character set conversion library + +This library provides an iconv() implementation, for use on systems which +don't have one, or whose implementation cannot convert from/to Unicode. + +It provides support for the encodings: + + European languages + ASCII, ISO-8859-{1,2,3,4,5,7,9,10,13,14,15,16}, + KOI8-R, KOI8-U, KOI8-RU, + CP{1250,1251,1252,1253,1254,1257}, CP{850,866,1131}, + Mac{Roman,CentralEurope,Iceland,Croatian,Romania}, + Mac{Cyrillic,Ukraine,Greek,Turkish}, + Macintosh + Semitic languages + ISO-8859-{6,8}, CP{1255,1256}, CP862, Mac{Hebrew,Arabic} + Japanese + EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1, + ISO-2022-JP-MS + Chinese + EUC-CN, HZ, GBK, CP936, GB18030, EUC-TW, BIG5, CP950, BIG5-HKSCS, + BIG5-HKSCS:2004, BIG5-HKSCS:2001, BIG5-HKSCS:1999, ISO-2022-CN, + ISO-2022-CN-EXT + Korean + EUC-KR, CP949, ISO-2022-KR, JOHAB + Armenian + ARMSCII-8 + Georgian + Georgian-Academy, Georgian-PS + Tajik + KOI8-T + Kazakh + PT154, RK1048 + Thai + ISO-8859-11, TIS-620, CP874, MacThai + Laotian + MuleLao-1, CP1133 + Vietnamese + VISCII, TCVN, CP1258 + Platform specifics + HP-ROMAN8, NEXTSTEP + Full Unicode + UTF-8 + UCS-2, UCS-2BE, UCS-2LE + UCS-4, UCS-4BE, UCS-4LE + UTF-16, UTF-16BE, UTF-16LE + UTF-32, UTF-32BE, UTF-32LE + UTF-7 + C99, JAVA + Full Unicode, in terms of 'uint16_t' or 'uint32_t' + (with machine dependent endianness and alignment) + UCS-2-INTERNAL, UCS-4-INTERNAL + Locale dependent, in terms of 'char' or 'wchar_t' + (with machine dependent endianness and alignment, and with OS and + locale dependent semantics) + char, wchar_t + The empty encoding name "" is equivalent to "char": it denotes the + locale dependent character encoding. + +When configured with the option --enable-extra-encodings, it also provides +support for a few extra encodings: + + European languages + CP{437,737,775,852,853,855,857,858,860,861,863,865,869,1125} + Semitic languages + CP864 + Japanese + EUC-JISX0213, Shift_JISX0213, ISO-2022-JP-3 + Chinese + BIG5-2003 (experimental) + Turkmen + TDS565 + Platform specifics + ATARIST, RISCOS-LATIN1 + EBCDIC compatible (not ASCII compatible, very rarely used) + European languages + IBM-{037,273,277,278,280,282,284,285,297,423,500,870,871,875,880}, + IBM-{905,924,1025,1026,1047,1112,1122,1123,1140,1141,1142,1143}, + IBM-{1144,1145,1146,1147,1148,1149,1153,1154,1155,1156,1157,1158}, + IBM-{1165,1166,4971} + Semitic languages + IBM-{424,425,12712,16804} + Persian + IBM-1097 + Thai + IBM-{838,1160} + Laotian + IBM-1132 + Vietnamese + IBM-{1130,1164} + Indic languages + IBM-1137 + +It can convert from any of these encodings to any other, through Unicode +conversion. + +It has also some limited support for transliteration, i.e. when a character +cannot be represented in the target character set, it can be approximated +through one or several similarly looking characters. Transliteration is +activated when "//TRANSLIT" is appended to the target encoding name. + +libiconv is for you if your application needs to support multiple character +encodings, but that support lacks from your system. + + +Installation +------------ + +As usual for GNU packages: + + $ ./configure --prefix=[[PREFIX]] where [[PREFIX]] is e.g. $HOME/local + $ make + $ make install + +After installing GNU libiconv for the first time, it is recommended to +recompile and reinstall GNU gettext, so that it can take advantage of +libiconv. + +On systems other than GNU/Linux, the iconv program will be internationalized +only if GNU gettext has been built and installed before GNU libiconv. This +means that the first time GNU libiconv is installed, we have a circular +dependency between the GNU libiconv and GNU gettext packages, which can be +resolved by building and installing either + - first libiconv, then gettext, then libiconv again, +or (on systems supporting shared libraries, excluding AIX) + - first gettext, then libiconv, then gettext again. +Recall that before building a package for the second time, you need to erase +the traces of the first build by running "make distclean". + +This library installs: + - a library 'libiconv.so', + - a header file ''. + +To use it, simply #include and use the functions. + +To use it in a package that uses GNU autoconf and GNU automake: + - Use gnulib-tool to import the Gnulib module 'iconv'. It consists + of a couple of *.m4 files (iconv.m4 and its dependencies) and a + file 'build-aux/config.rpath'. + - Add to the link command line of libraries and executables that use + the functions the placeholder @LIBICONV@ (or, if using libtool for + the link, @LTLIBICONV@). In Makefile.am files, the right place for + these additions are the *_LDADD variables. + + +Copyright +--------- + +The libiconv and libcharset _libraries_ and their header files are under LGPL, +see file COPYING.LIB. + +The iconv _program_ and the documentation are under GPL, see file COPYING. + + +Download +-------- + + https://ftp.gnu.org/gnu/libiconv/libiconv-1.17.tar.gz + +Homepage +-------- + + https://www.gnu.org/software/libiconv/ + +Bug reports +----------- + +Report bugs + - in the bug tracker at + - or by email to . + + +Bruno Haible diff --git a/openocd-win/openocd/distro-info/licenses/libiconv-1.17/THANKS b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/THANKS new file mode 100644 index 0000000..a6f02ff --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libiconv-1.17/THANKS @@ -0,0 +1,15 @@ + Thanks to for + +Edmund Grimley Evans bug reports + +Taro Muraoka Woe32 DLL support + +Akira Hatakeyama OS/2 support + +Juan Manuel Guerrero + DOS/DJGPP support + +Hironori Sakamoto advice on EUC-JP and JISX0213 + +Ken Lunde detailed information about GB18030 + diff --git a/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/AUTHORS b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/AUTHORS new file mode 100644 index 0000000..4e4904e --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/AUTHORS @@ -0,0 +1,50 @@ +* GNU Libtool was conceived, designed and implemented by: + + Gordon Matzigkeit gord@gnu.org + +* GNU Libtool's Dynamic Loader library (libltdl) was conceived, + designed and implemented by: + + Thomas Tanner tanner@ffii.org + +* GNU Libtool and libltdl have previously been maintained, enhanced, + ported and otherwise advanced by: + + Alexandre Oliva oliva@dcc.unicamp.br + Ossama Othman ossama@debian.org + Robert Boehne rboehne@ricardo-us.com + Scott James Remnant scott@netsplit.com + Peter O'Gorman peter@pogma.com + Ralf Wildenhues Ralf.Wildenhues@gmx.de + Gary V. Vaughan gary@vaughan.pe + Bob Friesenhahn bfriesen@simple.dallas.tx.us + Peter Rosin peda@lysator.liu.se + Noah Misch noah@cs.caltech.edu + Charles Wilson libtool@cwilson.fastmail.fm + Brooks Moses bmoses@google.com + +* GNU Libtool is currently being cajoled, bullied, + rewritten and otherwise dragged into the future by: + + Alex Ameen alex.ameen.tx@gmail.com +-- + Copyright (C) 1996, 1998-2019, 2021-2022 Free Software Foundation, + Inc. + + This file is part of GNU Libtool. + +GNU Libtool is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2 of +the License, or (at your option) any later version. + +GNU Libtool is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU Libtool; see the file COPYING. If not, a copy +can be downloaded from http://www.gnu.org/licenses/gpl.html, +or obtained by writing to the Free Software Foundation, Inc., +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. diff --git a/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/COPYING b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/COPYING new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. 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You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/NEWS b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/NEWS new file mode 100644 index 0000000..ba99fbe --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/NEWS @@ -0,0 +1,1251 @@ +NEWS - list of user-visible changes between releases of GNU Libtool + +* Noteworthy changes in release 2.4.7 (2022-03-16) [stable] + +** New features: + + - Libtool script now supports (configure-time and runtime) ARFLAGS + variable, which obsoletes AR_FLAGS. This is due to naming conventions + among other *FLAGS and to be consistent with Automake's ARFLAGS. + + - Gnulib testsuite is enabled and run during 'make check'. + + - Support the Windows version of the Intel C Compiler (icl) in + libtool script. + + - Pass '-fsanitize=*' flags for GCC and LLVM, and '-specs=*' for GCC + to linker. + + - Pass '-Xassembler=*' and '-Wa,*' flag to compilers and linkers. + + - The variable 'FILECMD' with default value of '/usr/bin/file' was used to + replace existing hard coded references to '/usr/bin/file'. + + - Add MidnightBSD support. + +** Important incompatible changes: + + - Libtool changed ARFLAGS/AR_FLAGS default from 'cru' to 'cr'. + + - Do not pass '-pthread' to Solaris linker. + + - 'libtool' and 'libtoolize' scripts now use '#! /usr/bin/env sh' shebang. + Previously '#! /bin/sh' was used, which presents challenges for + containerized environments. + +** Bug fixes: + + - Fix significant slowdown of libtoolize for certain projects (regression + introduced in 2.4.3 release) caused by infinite m4 macro recursion. + + - Mitigate the slowdown of libtool script (introduced in v2.4.3) caused by + increased number of calls to '$SED $sed_quote_subst' (bug#20006). + + - Properly parse and export TLS symbols on AIX. + + - Various bug fixes surrounding use of 'sed'. + + - Darwin systems set proper "allow undefined" flag on OSX 11, and + PowerPC 10.5. + + - Removed some deprecated tests related to 'Makefile.inc' files. + +* Noteworthy changes in release 2.4.6 (2015-02-15) [stable] + +** New features: + + - LT_SYS_LIBRARY_PATH can be set in config.site, or at configure time + and persists correctly in the generated libtool script. + +** Bug fixes: + + - Fix a race condition in ltdl dryrun test that would cause spurious + random failures of that test. + + - LT_SYS_DLSEARCH_PATH is munged correctly. + + +* Noteworthy changes in release 2.4.5 (2015-01-19) [stable] + +** New features: + + - Libtoolize searches for the best available M4 on the user PATH at + runtime, rather than settling for the first one found. + + - Support munging sys_lib_dlsearch_path_spec with LT_SYS_LIBRARY_PATH + environment variable. + +** Bug fixes: + + - Bail out at configure time if the installed M4 is not sufficient + for the purposes of libtoolize. + + - freebsd-elf library versioning was upgraded incorrectly in 2.4.4, + but now works properly again. + + - Fix a 2.4.4 regression so that libltdl subprojects do not warn + about missing libltdl/libltdl directory as in prior releases. + + - When using Sun C++ on Solaris or GNU/Linux we used to set libtool's + postdeps permanently, based on the contents of $CXX and $CXXFLAGS at + configure time, which was brittle and error-prone. Now, we no + longer check for a SunCC ABI at configure time, but augment the + postdeps at libtool time based on the current invocation flags on + each call. + +** Changes in supported systems or compilers: + + - /usr/local prefixed rpaths are now added to the link-line on + ia64-hp-hpux*, because the default system runtime loader path does + not contain them. + + - Previously, when using Sun C++ on Solaris or GNU/Linux, `-Cstd -Crun` + flags were added to $postdeps unless CXX or CXXFLAGS contained + `-library=stlport4`. Newer releases have added other compiler flags + that are also incompatible with `-Cstd -Crun`, so now we don't add + them if any of `-std=c++[0-9][0-9]`, `-library=stdcxx4` or + `-compat=g` were found in CXX or CXXFLAGS when the Sun C++ compiler + is detected. + + +* Noteworthy changes in release 2.4.4 (2014-11-29) [stable] + +** New features: + + - Libltdl maintains its own fork of argz, with macros and files in + the LT_ and lt__ namespaces (resp.) where they cannot clash with + client projects' use of gnulib argz. + +** Bug fixes: + + - Installation of 'libtoolize' once again obeys '--program-prefix', + '--program-suffix' and '--program-transform-name' configure options. + + - `libtoolize` doesn't remove any files that it can't reinstall, + including old versions of the snippet directory, and gnulib's + version of the argz module and supporting files. + + - LT_FUNC_DLYSM_USCORE now works correctly on systems that don't + support self dlopen()ing. + +** Important incompatible changes: + + - LT_LIB_DLLOAD no longer prepends -ldl or -ldld to LIBS, causing + duplicate occurrences in libltdl link lines. If you need to + add a library for dlopen() or shl_load() in your Makefile, then + use $(LIBADD_DLOPEN) or $(LIBADD_SHL_LOAD) respectively. If you + are using libltdl, this all happens automatically, and the only + difference you'll see is no more duplicated library names in the + verbose link line. + +** Changes in supported systems or compilers: + + - Preliminary support for tcc on linux*. Although it already worked + sometimes in previous releases, making sure to set LD correctly now + avoids mis-matching GNU ld with tcc: + + ./configure CC=tcc LD=tcc + + - Added -os2dllname option to work around 8 character base name + limit on OS/2. The option has no effect on other systems. + + - Support for DLL versioning, -export-symbols and -export-symbols-regex + on OS/2. + + - Support filename-based shared library versioning on AIX. See manual + for details. + + +* Noteworthy changes in release 2.4.3 (2014-10-27) [stable] + +** New features: + + - Moved to gnulib release infrastructure. + + - M4 is now used for scanning the M4 macros in your configure.ac that + 'libtoolize' looks at to determine what files you want, and where you + would like them installed. This means that you can compose your + version number or any other argument that Libtoolize needs to know at + M4 time using git-version-gen from gnulib, for example. + + - Invoking 'libtoolize --ltdl' no longer maintains a separate autoconf + macro directory in the libltdl tree, but automatically adjusts the + installed libltdl configuration files to share whatever macro + directory is declared by the parent project. (Note: if you were + already sharing a macro directory with AC_CONFIG_MACRO_DIR(ltdl/m4) + or similar, that still works as does any other directory choice). + + - Invoking 'libtoolize --ltdl' no longer maintains a separate auxiliary + scripts directory in the libltdl tree, but automatically adjusts the + installed libltdl configuration files to share whatever auxiliary + scripts directory is declared by the parent project. (Note: if you + were already sharing an auxiliary directory with subproject libltdl + using AC_CONFIG_AUX_DIR(ltdl/config) or similar, that still works as + does any other directory choice). + + - The legacy tests have all been migrated to the Autotest harness. + + - The Autotest testsuite can be run without the especially time consuming + tests with: + + make check-local TESTSUITEFLAGS='-k "!expensive"' + +** Bug fixes: + + - Fix a long-standing latent bug in autom4te include path for autotests + with VPATH builds. + - Fix a long-standing latent bug in libtoolize that could delete lines + from libltdl/Makefile.am in recursive mode due to underquoting in a + sed script. + - Fix a long-standing bug in libtoolize, by outputting the 'putting + auxiliary files in' header with 'libtoolize --ltdl --subproject'. + - Fix a long-standing bug in libtoolize subproject installation, by not + installing a set of autoconf macro files into the parent project if + there is no configure.ac present to use them. + - The libtoolize subproject mode selector is now named '--subproject' + and is equivalent to the implied '--subproject' mode when no other + mode is selected; '--standalone' never worked, and is no longer + accepted. + - Libtool and libtoolize no longer choke on paths with a comma in them. + - In the case where $SHELL does not have the same enhanced features + (e.g. the ability to parse 'var+=append') as $CONFIG_SHELL, libtool + will now correctly fallback to using only vanilla shell features + instead of failing with a parse at startup. + - Correctly recognize import libraries when Microsoft dumpbin is used + as the name lister and extend the dumpbin wrapper to find symbols + in import libraries using the -headers option of dumpbin. Also fix a + bug in the dumpbin wrapper that could lead to broken symbol listings + in some corner cases. + - Use the improved Microsoft dumpbin support to mend preloading of + import libraries for Microsoft Visual C/C++. + - No longer mangle module-definition (.def) files when feeding them to + the Microsoft Visual C/C++ linker via the -export-symbols argument to + the libtool script, thus matching how .def files are handled when + using GNU tools. + - Recognize more variants (e.g. those starting with a LIBRARY statement) + of module-definitions (.def) files when using them instead of a raw + list of symbols to export. + - Fix a long-standing bug when using libtoolize without automake; we + no longer remove install-sh with --force, since it's not a file + libtoolize will reinstall without --install.. + +** Important incompatible changes: + + - GNU M4 is required to run libtoolize in a directory with a + 'configure.ac' (or 'configure.in') that needs tracing to determine + what modes and directories have been specified. + + - The use of the idiosyncratically named 'Makefile.inc' in nonrecursive + libltdl builds is deprecated, although it will be supported for one + more year or until the next release, whichever takes longer. Please + upgrade to the more standard naming of 'ltdl.mk' in keeping with other + GNU projects. + + - libtoolize now behaves consistenty in respect of multiple directory + arguments to ACLOCAL_AMFLAGS and multiple invocations of AC_CONFIG- + _MACRO_DIRS, where the first directory is always selected. Previous + releases took the first ACLOCAL_AMFLAGS argument, but the last + invocation of AC_CONFIG_MACRO_DIRS. + + - The libtoolize program now advises use of the new Autoconf + AC_CONFIG_MACRO_DIRS declaration. If you follow that advice, all + your developers will need at least autoconf-2.70 and automake-1.13 + to rebootstrap your probject. If you still need to support + bootstrap with older Autotools, then you should add the following + to your configure.ac file: + + m4_ifndef([AC_CONFIG_MACRO_DIRS], + [m4_define([AC_CONFIG_MACRO_DIRS], + m4_defn([AC_CONFIG_MACRO_DIR]))]) + + - Overhead of probing for a non-backslash crippled echo equivalent + during initialization of every script has been removed in favor of + trusting that "printf %s\n" works out of the box on all non-museum + host architectures. Manually setting ECHO appropriately in the + build environment will be necessary on some ancient architectures. + +** Changes in supported systems or compilers: + + - Support for bitrig (*-*-bitrig*). + + - Solaris 7 and earlier requires ECHO=/usr/ucb/echo in the build + environment, to build and use libtool. + +New in 2.4.2 2011-10-17: git version 2.4.1a, Libtool team: + +* New features: + + - The --with-pic configure option now supports a list of comma-separated + package names. This can be used to build some static libraries with PIC + objects while building others with non-PIC objects. + + - Initial support for Go, using the gccgo compiler. + + - On Mac OS X .dylib is now tried as well as .so with + lt_dlopenext(). + +* Bug fixes: + + - The generic approximation of the command line length limit (when getconf is + not available) works again. Regression introduced in v2.2.6-39-g9c3d4d8. + - The bug that leaked developer tool paths into the release tarballs + from ./bootstrap is fixed. + - Improved support for the Cuda Compiler Driver (nvcc) on Darwin. + - For GCC LTO support, the -fuse-linker-plugin switch is now also removed + when computing compiler postdeps. + +* Important incompatible changes: + + - The undocumented hardcode_libdir_flag_spec_ld tag variable has been + removed in favor of using hardcode_libdir_flag_spec with $wl set to empty. + +* Changes in supported systems or compilers: + + - Fixes for gfortran on Darwin, XL Fortran on GNU/Linux. + - Support for FreeBSD 1.x (outdated since 1994) has been removed. + +New in 2.4 2010-09-22: git version 2.2.11a, Libtool team: + +* New features: + + - Sysroot support. This allows you to build cross-compiled packages + with the same prefix that will be used on the destination machine, + and still find dependent libraries under the compiler's "sysroot". + Without sysroot support, paths internal to the build system may leak + into the product of the build. + + Sysroot support is disabled unless the --with-sysroot configure + option is passed to configure, because .la files generated with + sysroot support will _not_ be usable in general with older Libtools. + + - On non-cygwin Windows systems, we now lookup potential library + file names without regard to file name case. + - The old testsuite now uses the 'parallel-tests' Automake test driver + now for more concurrency and better test logging. For this, tests are + run in verbose mode by default now. + +* Important incompatible changes: + + - Autoconf 2.62 and Automake 1.11.1 or newer are now required for + bootstrapping Libtool. For using Libtool in your own projects, + Autoconf 2.59 and Automake 1.9.6 should still work. + - The fix_srcfile_path variable has been replaced by a more thorough + mechanism triggered by the to_tool_file_cmd variable. + +* Changes in supported systems or compilers: + + - Initial support for the Microsoft C/C++ Compiler, with help from + the compile script in unreleased Automake 1.12. Override the manifest + tool used to embed the manifest resource through the environment + variable MANIFEST_TOOL. Please note that the import library naming + has changed (from foo-2.lib to foo.dll.lib) from when the code lived + in its own git branch. + - Initial support for the NAG Fortran compiler on GNU/Linux. + +* Bug fixes: + + - The 'check-interactive' and 'check-noninteractive' convenience make + targets now also work for the old testsuite. + - Warnings from Autoconf v2.67-36-g1e604ec about incomplete programs + passed to AC_*_IFELSE tests have been fixed. + - On IRIX, the test for -Wl,-exported_symbol now also works with gfortran. + +New in 2.2.10 2010-06-10: git version 2.2.9a, Libtool team: + +* New features: + + - On non-cygwin Windows systems, we no longer try to lookup the POSIX + format path recorded in $libdir of a pseudo-library when looking up + the location of the library with the native tools. + +New in 2.2.8 2010-06-05: git version 2.2.7c, Libtool team: + +* No new features: + + - Bumped version number and promoted 2.2.7b release candidate to a full + stable release. + +New in 2.2.7b 2010-05-20: git version 2.2.7a, Libtool team: + +* New features: + + - Libtool ships and installs man pages for libtool and libtoolize now. + - New libtool command line flag --help-all. + - New libtool command line flag --no-silent (with alternate spelling + --no-quiet). This flag (re)enables the default informational messages, + but has no effect on so-called "verbose" output messages. + - New libtool command line flag --no-verbose, which disables only + the extra "verbose" output messages and has no effect on the + default informational messages. + - New convenience make targets 'check-noninteractive' to avoid long testsuite + runs on Windows with popup windows in the middle, and 'check-interactive' + for the complement set of tests. + - New link mode flag -bindir to specify the location for installed PE DLLs. + - Wrapper scripts and wrapper executables for programs linked against + uninstalled shared libraries now support command-line options --lt-debug + and --lt-dump-script. + +* Important incompatible changes: + + - The wrapper command line option support described above introduces the + following incompatibility: the wrapper will remove any command line + options that begin with '--lt-*' from the argument list before launching + (uninstalled) programs. Any '--lt-*' option on the command line not + recognized by the wrapper will result in an error. + - The type of the symbol lists variables (lt_*_LTX_preloaded_symbols) has + been fixed in the manual and in a couple of tests to match the actual + implementation. + +* Changes in supported systems or compilers: + + - Improved support for 64bit Windows (mingw64). + - Improved support for cegcc (Windows CE/PocketPC). + - Support for GNU/kOpenSolaris (kopensolaris*-gnu). + - Initial support for compilers on BlueGene BG/P. + - Improved support for Atari FreeMiNT. + - With binutils 2.19.50+, shared libraries can be built on AIX. + - Initial support for the Cuda Compiler Driver on GNU/Linux. + - Support for Haiku (i586-pc-haiku). + - Initial support for GCC link-time optimization (LTO) flags. + +* Bug fixes: + + - Fix 2.2.6 regression that prevented using the libltdl macros together + with Autoconf 2.59 ('possibly undefined macro: LT_LIBEXT'). + - Fix 2.2.4 regression that caused arguments with special characters + to be mangled by the compile wrapper for uninstalled programs on MinGW. + - libtool command line flag --verbose now also enables explicit + verbose output, in addition to its previous behavior of (re)enabling + only the default informational output. See New Features, --no-silent. + - Link tests are guarded by cache variables so they can be avoided for + bootstrapping purposes (e.g., when link tests are not possible). + - Argument mangling of execute mode has been improved (i.e., lessened). + - Fix 2.1b regression that caused nm to not be the default name lister. + The regression affected mainly (arguably broken) cross compiles. + - Fix long standing bug that caused compiler checks for Fortran and + C++ compilers to run twice. + - Link mode works around a parallel build failure on Darwin 9.6.0 due + to the 'ar' 'flock'ing an archive upon extraction, by protecting the + extraction of convenience archives with a lock. + - The Libtool macro files do not contain instances of __oline__ any more, + easing merges for configure scripts that are added to version control. + - Fix ancient bug where "-Wc," was turned into "$wl" (typically "-Wl,") + when using the compiler driver to link programs. Now "-Wc," is stripped + just as it is when linking libraries through the compiler driver. + - Symbol versioning works with the GNU gold linker now. + - Fixes for detection of shared library dependencies on MinGW systems. + - Fixed Sun compiler detection on Solaris with sunCC, sunf77 etc. names. + +* Miscellaneous changes: + + - The manual is distributed under the terms of the GNU FDL 1.3 now. + +New in 2.2.6 2008-09-05: git version 2.2.5a, Libtool team: + +* New features: + + - New lt_dloadvise_preload() call to set a hint that only preloadeded + modules can be opened. + - libtoolize no longer removes config.guess and config.sub, even when + --install is passed. + +* Changes in supported systems or compilers: + + - Fixes for ifort on Darwin, and newer Intel compilers (icc 10, ifort 9) + on GNU/Linux. + - Fixes for cwrapper (cygwin/mingw) under -stdc=c99. + - Support cross compile of MinGW with Wine. + - Initial support for cegcc (Windows CE/PocketPC) cross compilation. + - Initial support for lf95 (Lahey Fortran 8.1) on GNU/Linux. + +* Bug fixes: + + - Several testsuite issues have been fixed, thanks to user feedback. + + - Fix 2.2 regression that caused argz symbols to be exported from + libltdl unrenamed on systems that do not have working argz. + + - Revert "lt_dlopen(NULL) works on AIX again.". It was not the + correct fix. + + - Diagnose '-L' arguments correctly. + + - Libtool no longer tries to open devices as files in execute mode. + + - Libtool no longer removes *.gcno profile information from GCC. + +New in 2.2.4: 2008-05-04: git version 2.2.3a, Libtool team: + +* New features: + + - New libtoolize option --no-warn, for users that want to continue to + use old libtool style without being nagged. + - Options --debug, --no-warn, --quiet and --verbose can be passed to + libtoolize through the environment variable LIBTOOLIZE_OPTIONS, for + cleaner interaction between the user and libtoolize when called by + autoreconf. + +* Bug fixes: + + - The documentation for lt_dlopenadvise showed the wrong type for + the lt_dladvise parameter. + - The public declarations for lt_dlhandle and lt_dladvise are now + incomplete struct types rather than void*, which means that nearly + all casting is eliminated allowing the compiler to provide more + type checking. + - libtoolize no longer reports up-to-date files that it would have + copied, unless --force is passed. + - No longer reports that lt~obsolete.m4 needs to be added to aclocal.m4 + when it is already there. + - When 'aclocal' copied the libtool macros directly into 'aclocal.m4' + (i.e. AC_CONFIG_MACRO_DIR is not being used), libtoolize no longer + reports that all macros need to be added to 'aclocal.m4', and + diagnoses only the macro files that are missing or not up-to-date. + - libtoolize now advises use of AC_CONFIG_MACRO_DIR to keep matching + libtool macros in-tree where appropriate. + - libtoolize now advises use of 'ACLOCAL_AMFLAGS = -I m4' (or + equivalent) where appropriate, and errors out when ACLOCAL_AMFLAGS + names a different directory to AC_CONFIG_MACRO_DIR. + +New in 2.2.2: 2008-04-01: CVS version 2.2.1a, Libtool team: + +* New features: + + - In compile mode, compiler output occurs in the user locale. This + feature has been present in 1.5.26 but not in 2.2. + +* Changes in supported systems or compilers: + + - Initial shared library support for AmigaOS4 on powerpc. + +* Bug fixes: + + - Fix 2.2 regression in libltdl that causes memory corruption upon + repeated 'lt_dlinit(); lt_dlexit()'. + - Fix 2.2 regression in libltdl that skipped the dlopen loader if + the system also supports other loaders (e.g., Cygwin, HP-UX). + - Fix 2.2 regression in that 'libtool --mode=execute CMD ARGS' does not + transform ARGS that do not look like shell or C wrappers of libtool + programs. + - Fix 2.2 regression that kept cross-compiling to w32 from working. + - Several testsuite issues have been fixed, thanks to user feedback. + +New in 2.2: 2008-03-01; CVS version 2.1c, Libtool team: + +* Bug fixes: + + - argz.c, lt__dirent.c and lt__strl.c are correctly distributed with + parent projects using nonrecursive libltdl. + - libtoolize no longer tries to install libtool files when libltdl is + used in a non-autoconf parent package. + - Don't add the CXX tag to libtool when there is no C++ compiler, even + if AC_PROG_CXX sets a default g++ compiler where no such compiler + actually exists. + - make distcheck DISTCHECK_CONFIGURE_FLAGS=--disable-ltdl-install + works again. + +New in 2.1b: 2008-02-01; CVS version 2.1a, Libtool team: + +* Important incompatible changes and obsoleted features: + + - Removed deprecated APIs from libltdl: lt_dlcaller_register, + lt_dlhandle_next, lt_dlhandle_find, lt_dlforeach, lt_dlmutex_register, + lt_dlmutex_lock, lt_dlmutex_unlock, lt_dlmutex_seterror, + lt_dlmutex_geterror, lt_dlmalloc, lt_dlrealloc, lt_dlfree. + - The Libtool and libltdl macros and the testsuite now assume a C89 + environment, consequently do not test for headers such as string.h, + strings.h, memory.h any more. + - Fix regression in libltdl symbol exports on Cygwin. Side effect: + LT_GLOBAL_DATA and LT_SCOPE are now explicitly defined as + declspec(dllexport), bypassing auto-export logic on Cygwin. + This tracks existing behavior on MinGW. + - The libtool script has been optimized a bit for more modern shells. + This breaks use of the stdin file descriptor in libtool, and can + break if a different shell is used to execute the libtool script + than the one it was configured for. + - The macros AC_ENABLE_SHARED, AC_DISABLE_SHARED, AC_ENABLE_STATIC, and + AC_DISABLE_STATIC have been un-deprecated after deprecation in + 1.9b. + - The macro LT_WITH_LTDL has been renamed to LTDL_INIT. + - Fixed a branch-1-5/HEAD regression to only link uninstalled libraries + statically with '-static'. In order to compensate for this, there + is a new link flag '-static-libtool-libs' to provide the previous + '-static' semantics. + +* New features: + + - Fix installation of libltdl so that it does not need Autoconf and + Automake installed, in order to be usable in another package. This + lifts the restrictions introduced in 1.9b. + - Default convenience or installable libltdl builds can optionally + be declared using new 'convenience' or 'installable' options to the + LTDL_INIT macro (as an alternative to individual LTDL_CONVENIENCE + or LTDL_INSTALLABLE invocations). + - New configure-time options to allow libltdl parent project builder + to choose between installed and shipped libltdl, when invoking + LTDL_INIT: --with-included-ltdl, --with-ltdl-include, + --with-ltdl-lib. + - New LT_CONFIG_LTDL_DIR macro to specify a different directory name + for a convenience libltdl. + - libtoolize has been completely overhauled. + - 'libtoolize --install' now also installs 'install-sh'. + - New libtoolize options: --non-recursive, --recursive, --subproject. + These options control the way libltdl is installed into a package by + libtoolize. The new recursive and non-recursive build modes for + libltdl don't require a subconfigure any more. + The Libtool package itself builds libltdl nonrecursively. + - The 'nonrecursive', 'recursive' and 'subproject' libltdl build + modes are given as LTDL_INIT options. + - New make variable LTDLDEPS for use in output_DEPENDENCIES. + - New multi-module-loader safe libltdl handle iteration APIs: + lt_dlhandle_iterate, lt_dlhandle_fetch, lt_dlhandle_map. + - New lt_dlinterface_register to maintain separation of concerns + between modules loaded by different libraries. + - New lt_dlopenadvise takes a new lt_dladvise type argument, which + lets the caller request local or global symbol visibility from the + module loader with lt_dladvise_local and lt_dladvise_global + respectively. If neither is given, or if lt_dlopen (or lt_dlopenext) + are called, then the system default module symbol visibility is used. + - The new lt_dladvise_init/lt_dladvise_destroy based APIs also allow + caller requests for a filename extension search with lt_dladvise_ext, + and for marking a module unloadable with lt_dladvise_resident. + - Allow shell special characters like '$' in source file names, but + not in object names, to enhance GCJ support. + - An entire new Autotest-based testsuite in addition to the old one. + Both testsuites have been made more useful for testing + cross-compilers. The new testsuite exposes many more issues, but + may also be a little rocky on exotic systems. + - In 1.9b, a new variable inherited_linker_flags has been added to the + libtool library files. This variable takes flags that should be + used by dependent libraries and programs, but that do not fit into + 'dependency_libs' for both clarity and backward-compatibility. + +* Changes in supported systems or compilers: + + - Removed bitrotted support for xlc on Mac OS X. + - Detection of compiler wrappers distcc/ccache and $host_alias prefix. + - Basic support for PIE (position-independent executables). + - Support for DragonFly BSD, improved support for FreeBSD. + - Improved support for GNU/kFreeBSD and GNU/NetBSD. + - Support for Interix 3 (Windows SFU) and newer versions. + - Support for AIX 6.1. + - Improved support for UnixWare. + - Initial support for RDOS. + - Initial Support for FC (modern Fortran). + - Support for Portland Group compiler, the Sun compiler suite on GNU/Linux, + and initial support for the IBM compiler suite on GNU/Linux/ppc. + - Support for linux-dietlibc ('diet' as well as 'diet-dyn', separately). + - Building libltdl with a C++ compiler has been undusted. + - On (AIX?,) HP-UX, and OpenBSD, hardcoding has been changed to prefer + rpath over absolute dependent library names. This fixes DESTDIR + installs, among others, on the non-HP-UX/PA systems. + - Use of C++ templates together with shared libraries has been + improved on some systems and with some compilers, but is still + ongoing work. Feedback is desirable here. + +* Bug fixes: + + - Fix libltdl on static platforms. + - Search paths with GCC on multilib systems like x86_64 have been fixed. + - Fixed a regression that prevented use of libltdl without autotools. + - Fix error with -version-info on systems with version_type=none, such + as BeOS. + - Fix symbol exporting for cases where command line length limits are + exceeded. + - Improve linking with C++ libraries on Solaris with Sun compiler. + - Fix installation of libraries that are required by installation + commands such as 'ln' or 'rm'. + - More robust parsing of mangled '.la' files inside libltdl, fixing a + possible overrun and a crash due to memory exhaustion. + - Fix compile command line for gcj on MinGW. + - Some configure variables have been renamed to fix caching: + lt_prog_compiler_pic_works to lt_cv_prog_compiler_pic_works + lt_prog_compiler_static_works to lt_cv_prog_compiler_static_works. + - Fix 1.9b regression: lt_dlopen(NULL) works on AIX again. + - Loads of smaller bug fixes. + + +New in 1.9f: 2004-10-23; CVS version 1.9e, Libtool team: +* Fix a regression in 1.9d, where ECHO was always set to 'echo' and the + backslash quoting tests were never run. +* Fix a regression in 1.9d, where progpath was used for --no-reexec before it + was set. +* Fix a regression in 1.9d, which required an installed automake to build the + bootstrapped tarball. +* Fix hanging bug on MinGW. + +New in 1.9d: 2004-10-03; CVS version 1.9c, Libtool team: +* If non-pic objects were not compiled, and libtool is called in link mode, + libtool no longer silently creates an empty archive, but rather falls + back to pic objects. +* When compiling C glue code with $LTCC, libtool now saves the setting of + $compiler_flags from the C tag, and passes those flags to $LTCC. +* libtool no longer dies when concurrently creating directories with + 'make -j' on multi-processor hosts. +* Return type, and name parameter of lt_dlloader_remove are no longer + 'const'. +* Name parameter of lt_dlloader_find is no longer 'const'. +* The API for the slist ADT has been updated: slist_new has been replaced + by slist_box; slist_unbox and slist_sort are new; the footprint of + slist_remove and slist_fnid have changed; SListCallback and SListCompare + types have been exchanged. See libltdl/slist.c for documentation. +* libltdl is C89 compatible again. lt_dlsymbol type removed, and lt_dlsymlist + structure changed to avoid using C99 flexible arrays. +* Support self dlopening for executables on cygwin and mingw. +* Improved support for linux-gnu/ia64. +* Initial support for s390x-ibm-tpf. +* Fixed some memory leaks in libltdl. +* Improved support for OpenBSD (use rpath instead of hardcoding absolute + file names). + +New in 1.9b: 2004-08-29; CVS version 1.5a, Libtool team: +* The /^_?LT_[A-Z_]+$/ namespace is now reserved for Libtool's own macros. + If you have any shell variables in this namespace they will need to be + renamed. If you have any macros in this namespace please rename them to + prevent any possible future clash with libtool supplied macros. +* New LT_PREREQ macro for specifying minimum libtool requirement. +* New LT_INIT interface replaces AC_PROG_LIBTOOL, AC_ENABLE_SHARED, + AC_DISABLE_SHARED, AC_ENABLE_STATIC, AC_DISABLE_STATIC, + AC_ENABLE_FAST_INSTALL, AC_DISABLE_FAST_INSTALL, AC_LIBTOOL_DLOPEN, + AC_LIBTOOL_WIN32_DLL and AC_LIBTOOL_PIC_MODE. Use autoupdate to modernise + your configure.ac files after installing this release. +* New LT_LANG interface to enable libtool support for a specific language. +* Language support is now only included if your configure.ac enables it, + either through a call to AC_PROG_CXX etc. or LT_LANG. +* The libtool script will complain if it was built from mismatched ltmain.sh + and libtool m4 macro versions. +* Like automake, libtoolize no longer installs config.guess and config.sub by + default. Use new --install option to get the old behaviour. +* libtoolize no longer supports the --ltdl-tar option. +* libtool script is now created by config.status. Instead of interrogating + './libtool' from configure.ac after calling AC_PROG_LIBTOOL, use the + variable names directly. +* libltdl is no longer a self-contained package, and shares configury with + the top level directory now. +* Shared objects (.lo) are no longer created when '-static' is passed in + compile mode. +* New compile mode option '-shared' prevents creation of static objects (.o). +* New link mode option '-shared' creates only shared libraries at link time. +* If you configure libtool with --disable-shared (or if libtool does not + support shared libraries on your platform) trying to build a library using + '-shared' is a fatal error. +* New link mode option '-weak' tells libtool when not to propagate dependency + libraries from dlpreopened modules. +* libtoolize installs libtool.m4, (ltdl.m4 if used,) and various supporting + m4 definitions to AC_CONFIG_MACRO_DIR. +* Mode inferrence removed, shorthand for choosing modes added. +* Specifying -allow-undefined is now an error. +* Speed up max_cmd_len check. +* libltdl can now preopen modules from within a library, and libtool will + accept -dlpreopen options when linking either a shared library or a + convenience library. +* New function in libltdl: lt_dlhandle_find provides access to module handles + by module name. +* New function in libltdl: lt_dlpreload_open opens all preloaded modules. +* libltdl no longer loads shared libraries with global symbol resolution, + this caused problems when the symbols were intended to be overriden further + up the stack; it is also not recommended practice. +* New function in libltdl: lt_dlhandle_first, primes handle iterations (using + lt_dlhandle_next) to filter by module interface. +* libltdl no longer tries to support multi-threaded programming with + lt_dlmutex_register(), which was unusable with POSIX threads anyway. + The symbols are deprecated but exported for backwards compatibility. +* libltdl no longer uses lt_dlmalloc, lt_dlrealloc and lt_dlfree. The symbols + are still exported for backwards compatibility. +* The lt_dlinfo struct has a new module field that can be used by dlloaders. +* libltdl no longer supports pre-c89 compilers. Some of the pre89 portability + functions had compile time bugs in them anyway, so you guys can't have been + using it :-) +* make install now deletes preexisting $prefix/share/libtool before installing + latest files. +* Extracting symbols from an import library on cygwin and win32 now works. +* Initial support for amigaos-ppc. +* Improved support for OpenBSD. +* Support for Intel C++ version 8.0. +* New support for IBM's xlc and xlc++ on Mac OS X. +* Finished support for QNX RTOS. +* Bug fixes. + +New in 1.5.8: 2004-08-07; CVS version 1.5.7a, Libtool team: +* Support for Intel C++ version 8.0. +* Improved support for OpenBSD. +* Support for xlc on Mac OS X. +* Better support for zsh as /bin/sh. +* Much faster check for command line length on all BSD systems. +* Better Mac OS X/darwin support. +* Bug Fixes. + +New in 1.5.6: 2004-04-11; CVS version 1.5.5a, Libtool team: +* Installs libltdl files properly in $prefix/share/libtool/libltdl. 1.5.4 + did not install them at all. +* libltdl correctly guesses the extension for loadable modules again. + +New in 1.5.4: 2004-04-03; CVS version 1.5.3a, Libtool team: +* Bug fixes. + +New in 1.5.2: 2004-01-25; CVS version 1.5.0a, Libtool team: +* lt_dlrealloc is an official part of the libltdl API. +* --tag, --silent and --debug options are preserved and reused when libtool + calls itself for relinking etc. +* '-pthread' and similar options are honoured when linking shared libraries. +* -no-suppress in compile mode shows compiler output for both PIC and non-PIC + object compilation. +* New link mode option '-precious-files-regex' to prevent accidental removal + of files you want to keep, such as test coverage data, from the temporary + output directory. +* Directories specified in /etc/ld.so.conf are no longer hardcoded on GNU/Linux. +* Recognises the 'R' symbol type on Solaris so read-only symbols can be + exported. +* Bug fixes. + +New in 1.5.1: 2003-??-??; CVS version 1.5.0a, Libtool team: +* lt_dlrealloc is an official part of the libltdl API. +* Bug fixes. + +New in 1.5: 2003-04-14; CVS version 1.4e, Libtool team: +* First stable release of multi-language architecture. +* libtool and libltdl support for Mac OS/X. +* libltdl will now use cygwins dlopen API instead of always forcing + LoadLibrary. +* Support auto-import patch to binutils on cygwin for much improved dll + support. +* Bug fixes. + +New in 1.4.3: 2002-10-13; CVS version 1.4.2a, Robert Boehne: +* The libltdl subdirectory now bootstraps correctly with Automake 1.5. +* srcdir != builddir builds with Automake 1.5 work correctly. +* Support for mips-compaq-nonstopux. +* New command line argument, --preserve-dup-deps prevents removal of + duplicate dependent libraries. + +New in 1.4d: 2002-01-07; CVS version 1.4c, Libtool team: +* Help strings display correctly again. +* Better error messages when library linking fails. +* Better error messages from libltdl when loading fails. +* Better search path management in libltdl with 'lt_dlinsertsearchdir' call. +* Support /lib/w32api in recent cygwin releases. +* Support cross compilation to mingw. +* Support for .rc files (Windows resource compiler). +* Improved handling of mingw gcc. +* Improved handling of $PATH with entries containing spaces. +* Improved support for linking with gcc on aix4* and aix5*. +* Improved support for GCC 3.0. +* Initial support for QNX RTOS, UnixWare 7 and OpenUNIX 8. +* Bug fixes to the OpenBSD port. +* Bug fixes. + +New in 1.4.2: 2001-09-11; CVS version 1.4.1a, Gary V. Vaughan: +* libltdl now builds on solaris again +* diagnose and warn about not-quite-working combinations of gcc and + ld on solaris. +* Improved OpenBSD support. +* Improved cygwin support. +* Bugfixes. + +New in 1.4.1: 2001-09-03; CVS version 1.4.0a, Libtool team: +* Better error messages from libltdl when loading fails. +* Don't leave here-doc files behind. +* Improved support for OpenBSD. +* Libtool will build with autoconf-2.50 and higher. +* Plug memory management bugs in libltdl. +* Prefer shl_load to dlopen for better operation on HP-UX. + +New in 1.4b: 2001-07-09; CVS version 1.4a, Libtool team: +* Now bootstraps with autoconf-2.50 and automake-1.4-p4. +* Always try to build at least a static lib, even if both static and + shared libs were disabled. +* Full support for C++ compiler. +* Support for GNU gcj compiler. +* libltdl can now load all modules in a given path according to user + supplied criteria with 'lt_dlforeachfile' call. +* Improved support for AIX ia64, djgpp, HPUX, hurd, OpenBSD, sco3.2*. +* Internal mutex handling no longer has namespace clashes on NCR MP-RAS. +* New pdemo and tagdemo tests. +* Bug fixes. + +New in 1.4: 2001-04-25; CVS version 1.3e, Libtool team: +* Support for aix5*. +* Bugfixes. + +New in 1.3d: 2001-04-02; CVS version 1.3c, Libtool team: +* ltconfig is no more. Generation of libtool happens directly from + the configure file. +* Multithread safe with lt_dlmutex_register callback registration. +* New -no-install flag to avoid the use of executable wrapper scripts. +* New --with-pic, -prefer-pic and -prefer-non-pic flags to control + the generation of PIC/non-PIC code. +* Support for hardcoding run-time paths (-R) into libraries. +* Support -dlopen and -dlpreopen for libraries. +* Libtool now allows you to link shared libraries against static code. +* New functions in libltdl: + lt_dlgetinfo, lt_dlhandle_next and lt_dlforeach provide access to module + specific data in handles. + lt_dlcaller_register, lt_dlcaller_set_data and lt_dlcaller_get_data provide + management for user storage of per module data. + lt_dlloader_next, lt_dlloader_name, lt_dlloader_find, lt_dlloader_add and + lt_dlloader_remove can be used for adding new types of module loaders. + lt_dladderror, lt_dlseterror integrate user module loaders with lt_dlerror. +* "-Xcompiler" and "-Wc," does now work in compile mode, too. +* Support recent dlltool formats. +* Start of support code for cross-compiling to win32. +* libltdl can now be built as a dll with win32. +* m4 macros needed to configure libltdl split out into libltdl/ltdl.m4. +* New port to NEWS-OS Release 6. +* Improved support for darwin (rhapsody), mingw32, NetBSD, Compaq Tru64 V5.0 + and Digital Unix V4.*. +* Initial support for ia64 linux. +* Initial support for a.out freebsd shared libs. +* Initial support for Paul Sokolovsky's pw32 POSIX over win32 layer. +* Many bugfixes (especially in libltdl) + +New in 1.3b: 1999-07-02; CVS version 1.3a, Libtool team: +* Complete inter-library dependencies support. It's now possible + to link libtool libraries against other libtool libraries. +* Libtool is able to find already-installed libtool libraries, + even if they were moved out of their installation directory. +* New "-Wc,flag" and "-Xcompiler flag" flags to pass flags + directly to the compiler +* New "-Wl,flag" and "-Xlinker flag" flags to pass flags + directly to the linker +* New "-no-fast-install" flag to selectively disable fast-install mode. +* Support for installing stripped libraries using GNU strip (install -s). + Automake >= 1.5 will install stripped libraries with "make install-strip". +* Allow linking shared libraries against static ones + on FreeBSD, GNU/Linux, GNU Hurd and Solaris +* Support for linking DLLs on Win32 +* New 'clean' mode to delete uninstalled files. +* New demos and tests +* Various bugfixes + +New in 1.3.5: 2000-05-27, CVS version 1.3.4a, Libtool team: +* Support for mac OS X (rhapsody). +* Support for *-sequent-sysv4. +* Support for Cygwin-1.1.0. +* Support recent dlltool formats. +* Bugfixes. + +New in 1.3.4: 1999-12-08, CVS version 1.3.3a, Libtool team: +* Support for Compaq Tru64 V5.0. +* Improved support for Digital Unix V4.*. +* Improved support for NetBSD, FreeBSD and Unixware. +* Many fine bugfixes. + +New in 1.3.3: 1999-07-02, CVS version 1.3.2a, Libtool team: +* New '-dlpreopen force' flag to ensure that + lt_preloaded_symbols is always defined. +* Work around self-dlclose bug in FreeBSD 3.1. +* Expand convenience libraries when creating reloadable objects. +* Do not forget to import -L flags of convenience libraries. +* Do not pass -whole-archive or equivalent to symbol extractor. +* Create directory to expand convenience libraries only when needed. +* Improved support for Cygwin, DJGPP and NetBSD +* Various bugfixes + +New in 1.3.2: 1999-05-26, CVS version 1.3.1a, Libtool team: +* Avoid circular links of objects and libraries. +* Look for dlerror when dlopen was found in -ldl (typo). +* Disable shared libraries with broken GNU ld on Solaris. + +New in 1.3.1: 1999-05-21, CVS version 1.3.0a, Libtool team: +* Documentation improvements; recommend automake users to insert libtool.m4 + in acinclude.m4 +* AC_LIBLTDL_CONVENIENCE and AC_LIBLTDL_INSTALLABLE now set INCLTDL. +* New port to NEC UX/4800. +* cygwin-b20.1 passes all tests. +* Slightly improved BeOS support. +* Many AIX 4.3.2 test failures have gone. +* Pass unknown -L arguments through to the linker (for -LANG:* support). +* Close a security hole with mode 777 directory during libltdl installation. +* Fixed the infamous 'ifelse' bug in libtool.m4 + +New in 1.3: 1999-04-29, Libtool team: +* This is just a summary of the changes since 1.2. + See the news of intermediate alpha releases below for details. +* Support for convenience archives. +* New maintainers. Anonymous CVS and home page at gnu.org. +* Portable dlopening interface with libltdl, new -module flag. +* Correctly link installed libtool libraries into programs and other + libtool libraries. Linking of uninstalled libtool libraries into + libraries is under development for 1.4. +* Do not drop library dependencies on platforms that allow them. +* Linking with uninstalled libraries no longer picks installed ones by + mistake. +* Use libraries from the build tree when running uninstalled + executables (may require double linking). +* Allow developers to optimize for build-tree executions. +* Support -export-symbols-regex for controlled symbol exporting. +* Support -R to hardcode directories in library search paths. +* New ports, demos and tests. Lots of improvements and bug fixes. + +New in CVS version 1.2g, Libtool team: +* AM_PROG_LIBTOOL is smaller and faster +* AC_LIBTL_L_WIN32_DLL is required in configure.in for libtool to + attempt to build dlls on win32 hosts +* Shared libraries on AmigaOS up to version 4 are now disabled + since they don't meet libtool's requirements for shared libraries +* -L supports now relative directories +* Libltdl has a new license: LGPL with a special exception +* Libltdl can be used as stand-alone package +* dlopen support for BeOS +* Partial support for Motorola System V 4 +* Improved support for AIX, BeOS, Cygwin, DJGPP, DU, IRIX and HP/UX +* Documentation updates +* New tests +* Bugfixes + +New in 1.2f: 1999-03-15; CVS version 1.2e, Libtool team: +* libtool will correctly link uninstalled libraries into programs + and prefer uninstalled libraries to installed ones +* Library paths that are in the system default run-time search path + are no longer hardcoded into executables. +* New fast installation mode, which links the final executable + in order to avoid relinking during installation. + Programs in the build-tree are relinked when executed. +* New AC_DISABLE_FAST_INSTALL macro to set the default for + the fast-install mode to disabled +* New -export-symbols-regex flag, to export symbols selectively by + a regular expression +* Support -R for specifying run-time path of programs and library dependencies +* New -avoid-version option to avoid versioning for libraries +* libtool module names no longer need to have a "lib" prefix + (requires automake 1.4). +* New -thread-safe flag, to build thread-safe libraries +* Major improvements in libltdl: API documentation, installable version, + support for module search paths, support for lt_dlopen(0), + can be embedded into packages as a tar file (libltdl.tar.gz), + dynamic buffer allocation and buffer overflow checks, + new macro LTDL_SET_PRELOADED_SYMBOLS() which must be used in the + main program, dynamic memory allocation functions are user-defineable +* New AC_LIBLTDL_CONVENIENCE and AC_LIBLTDL_INSTALLABLE macros, to select + convenience and/or installable versions of libltdl. +* libltdl is now built and installed unless --disable-ltdl-install +* New "-dlopen self" flag for dlopening the executable itself +* New AC_LIBTOOL_DLOPEN macro to check for dlopen support, + required if you use -dlopen or -dlpreopen +* If libtool could not satisfy all dependencies of a module + it will only build a static version of it +* dld_preloaded_symbols was renamed to lt_preloaded_symbols +* Support for BeOS +* Improved support for FreeBSD, AIX, IRIX, OSF, SysV 4.3, HP/UX, DJGPP + BSD/OS 4.x and NetBSD +* In order for libtool to attempt to link a shared library (dll) on win32 + platforms, you must pass the -no-undefined flag to libtool in link mode. +* The path to GNU ld now works on cygwin-b18 to cygwin-b20.2 at least. +* Support for IRIX library versioning. +* New demos and tests +* Various bugfixes + +New in 1.2d: 1998-12-16; CVS version 1.2c, Libtool team: +* libtool will correctly link already-installed libraries into programs. +* New -module flag, to create loadable modules. +* New libltdl, a small library for portable dlopening of modules. + It is still undocumented, but you can already find some examples in: +* New mdemo directory, with tests of -module and dlopening examples. + Be aware that libltdl is only known to work on a few platforms such as + GNU/Linux and Solaris2. Some mdemo tests are known to FAIL on several + other platforms; please ignore these failures by now (or work to fix + them :-). +* Inter-library dependencies patch finally integrated, but there's + still much porting to do. See PORTING for details (some plans for the + future in mail/deplibs in the CVS tree). +* New option -export-symbols to control symbol exporting when possible. +* Fixed -export-dynamic problem with C++ programs in egcs 1.1. +* New dlpreopen structure. +* libtool now supports '-c -o' and subdirectories in sources and + target object names even in platforms whose compilers do not support + this. In this case, file locking occurs to avoid problems with + parallel builds. +* New 'echo' variant that should fix most problems with long command + lines and broken printf programs. +* Support for DG/UX, UnixWare 7.x and FreeBSD 3.0, and improved + support for Microsoft Windows +* Various bugfixes +* We now have anonymous CVS access to GNU libtool. CVSROOT is + :pserver:anoncvs@anoncvs.gnu.org:/gd/gnu/anoncvsroot. The password + is empty. The directory is libtool. Check our home-page at + http://www.gnu.org/software/libtool/libtool.html for details. +* Alexandre Oliva, Thomas Tanner and Gary V. Vaughan have taken over + the maintenance of libtool. +* Arguments to ltconfig have been changed to allow creation of a + libtool C program, totally unusable as of this release. + +New in 1.2b - 1998-07-01, Gordon Matzigkeit: +* Libtool needs a new maintainer, since Gordon Matzigkeit has quit. + If you think you can do the job, send mail to bug-libtool@gnu.org. +* Bug fixes. +* Support for libtool convenience archives. + +New in 1.2a - 1998-04-19, Gordon Matzigkeit: +* Bug fixes. +* ltconfig accepts an '--output' option to specify the name of the + generated libtool. +* New '--debug' flag to turn on shell script tracing for libtool, + libtoolize, and ltconfig. +* Added 'libtool --config' to print out all configuration variables. +* Support for *-*-hpux11*. + +New in 1.2 - 1998-03-20, Gordon Matzigkeit: +* Minor bug fixes to provide a stable public release. +* Libtool no longer cseses Solaris printf to barf due to silly + 2110-byte static buffers. + +New in 1.1 - 1998-03-08, Gordon Matzigkeit: +* Bug fixes. +* http://www.profitpress.com/libtool/ is libtool's homepage. +* 'AM_PROG_LIBTOOL' supports turning shared or static libraries off + with the '--enable-shared=PKGS' and '--enable-static=PKGS' configure + flags. See (libtool)AM_PROG_LIBTOOL. +* Use the 'AM_DISABLE_SHARED' or 'AM_DISABLE_STATIC' macros if you + wish to modify the default behaviour of 'AM_PROG_LIBTOOL' for your + package. +* New rules for 'AM_PROG_LD' to use gcc's '-print-prog-name' flag in + order to find ld, if possible. +* Suppress duplicate compiler output during 'compile' mode. +* Deleted 'dlname' mode. Dlopen applications should only use the + runtime search method described in (libtool)Finding the dlname. +* Experimental support for dynamically loaded modules, even on + static-only platforms, via new '-dlopen' and '-dlpreopen' link + flags. +* 'compile' mode honours the '-static' flag to prevent libtool + from building PIC objects. +* New 'execute' mode to support debugging uninstalled libtool + libraries and executables. +* '-allow-undefined' is now the default. You can use '-no-undefined' + to declare that a shared library is completely self-contained. +* Inter-library dependencies are automatically handled when linking + against an uninstalled '.la' file. +* New '-all-static' flag to prevent any dynamic linking. The regular + '-static' flag now just prevents dynamic linking of libtool libraries. +* New '-release' flag to encode release numbers into libtool + libraries. This breaks binary compatibility, but is useful for + libraries whose interfaces change very frequently. See + (libtool)Versioning. +* The '-rpath' flag can be used to hardcode absolute directories when + linking executables using libtool. +* New robust quoting code to handle any metacharacters passed in + arguments to libtool commands. +* Full support for broken collect2 on AIX 3. Shared libraries + can now be built with all working versions of GCC on AIX. +* Shell script speed optimizations for old and buggy /bin/sh systems, + such as HP-UX 9 and SunOS 4.1.4. +* Maybe use '_libs' as a temporary libtool directory instead of '.libs' + in order to cope with MS-DOS filenames. +* Portability fixes for Windows NT. +* Refuse to create libtool libraries that don't begin with 'lib'. + This allows us to correctly handle OSes that don't have the 'lib' + prefix by default, such as OS/2. +* Support for *-*-amigaos*, *-*-os2*, *-*-sysv4.2uw2*, and *-*-uts4*. + +New in 1.0 - 1997-07-08, Gordon Matzigkeit: +* Bug fixes. +* Better configuration test to find the system linker. The old test + was failing because people frequently install GNU ld, but don't + necessarily configure GCC to use it. +* Automake support for Libtool now uses the LTLIBRARIES primary. See + the Automake documentation for more information. +* Added new '--disable-static' flag to disable building static + libraries on platforms that have shared libs. +* New '-allow-undefined' link flag to build shared libs that contain + references to unresolved symbols. +* Removed all support for creating static-only libraries. +* Basic support for dynamically loaded modules: new '-export-dynamic' + linking flag and corresponding 'dlname' mode. +* New '--features' flag to display configured libtool attributes. +* Added support for installing libtool objects, both in absolute and + relative directories. +* Support *-*-linux-gnu* as an alias for *-*-linux*. +* Support for *-*-openbsd* and *-*-freebsd3*. + +New in 0.9 - 1997-02-03, Gordon Matzigkeit: +* Bug fixes. +* The libtool demo now uses the libm cos(3) function, to demonstrate + inter-library dependencies. +* The PLATFORMS file has been moved to doc/platforms.texi. + +New in 0.8 - 1997-01-26, Gordon Matzigkeit: +* Bug fixes, and more documentation. +* Basic support for other language compilers (C++, Fortran, and + preprocessed assembler). +* Libtool is now more persistent when linking with the '-static' + flag fails. +* New test for hardcoding system linkers, to verify that libtool + neither creates incorrect binaries, nor takes unnecessary + precautions while linking against uninstalled shared libraries. +* For clarity, the demo subdirectory no longer uses ansi2knr, and has + been rewritten to avoid ANSI-only constructs. +* Support for *-*-irix5, *-*-irix6*, and *-*-sco3.2v5*. + +New in 0.7 - 1996-12-08, Gordon Matzigkeit: +* Total rewrite of libtool, along with a new model for library building. +* Completely rewritten documentation for the new paradigm. +* Sane handling of broken system linkers, such as the ones on AIX + and HP-UX. +* configure mode is now a separate program, 'ltconfig' +* The libinfo helper script has been incorporated into the main + libtool program. +* Automatic mode guessing, based on the command line. +* Full support for Automake 1.2 (including ansi2knr features). +* Support to create reloadable objects using link mode. +* Support for new '-static' linking flag. +* Support for stripping libraries during installation. +* Library version information is now passed on the command line, not + through a version file. + +Version 0.6 was never released. + +New in 0.5: +* Disabled install-progs until next version, when it will be correctly + implemented. +* Clearer library versioning documentation. See (libtool)Versioning. +* Renamed gm_PROG_LIBTOOL to AM_PROG_LIBTOOL +* Libtool now creates pseudo-objects named foo.lo and pseudo-archives named + libfoo.la instead of foo.o and libfoo.a. See the documentation. +* libtool compile doesn't interfere with user CFLAGS if they don't + conflict with the current objtype. From Karl Berry. +* Created new libinfo helper script. +* libversion.in files are obsolete -- libtool uses libinfo to read the + new LIBINFO files. +* Libtool is better at finding its config file and helper scripts. +* Support for *-*-gnu* + +New in 0.4: +* Bug fixes and new regression tests +* On unsupported configurations, 'libtool configure' demotes OBJTYPES to + 'standard' instead of aborting +* Added new object type, 't', for tcov(1) support +* Support for *-*-aix3*, *-*-aix4*, *-*-hpux10*, *-*-osf3*, and *-*-solaris2* + +New in 0.3: +* Bug fixes and new regression tests +* Added new uninstall-libs mode +* Added a host argument to configure mode +* Fixed debugging/hyper-optimizing flags conflict (from Karl Berry) +* Support for --no-whole-archive when needed by GNU ld (from Ulrich Drepper) +* Implementation of --enable-linktype, --enable-profile, --enable-shared, + --enable-static in gm_PROG_LIBTOOL macro +* New 'libtoolize' program (modeled after GNU gettext's 'gettextize') to help + conversion to libtool +* New ABOUT-LIBS document for inclusion with libtool-supported packages + +New in 0.2: +* Support for *-*-linux +* Better checking for GNU ld +* Reimplemented the config file so that it corresponds more closely to the + variables listed in (libtool)Porting Libtool. +* Reimplemented the shared library version scheme. See (libtool)Versioning. +* Replaced '--config-file' and '--version-file' options with '--confdir' +* Added new install-libs and install-progs modes + +New in 0.1: +* First release of libtool +* Support for: *-*-freebsd*, *-*-netbsd*, *-*-sunos4*, *-*-ultrix4* +-- + +Copyright (C) 1996, 1998-2019, 2021-2022 Free Software Foundation, Inc. + +This file is part of GNU Libtool. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. This file is offered as-is, +without warranty of any kind. diff --git a/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/README b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/README new file mode 100644 index 0000000..0984306 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/README @@ -0,0 +1,261 @@ +# GNU Libtool + +1. Introduction +=============== + +[GNU Libtool][libtool] is a generic library support script. +[Libtool][] hides the complexity of using shared libraries behind a +consistent, portable interface. + +Libtool's home page is: + + http://www.gnu.org/software/libtool/libtool.html + +See the file [NEWS][] for a description of recent changes to Libtool. + +Please note that you can build GNU Libtool from this directory using a +vendor Make program as long as this is an official release tarball; +otherwise you will need GNU Make for sane VPATH support. See the file +[INSTALL][] for complete generic instructions on how to build and install +Libtool. Also, see the file [doc/notes.txt][notes] for some platform- +specific information. + +See the info node (libtool)Tested Platforms. (or the file +[doc/PLATFORMS][platforms]) for a list of platforms that Libtool already +supports. + +Please try it on all the platforms you have access to: + + * If it builds and passes the test suite (`gmake check`), please send + a short note to the [libtool mailing list][libtool list] with a + subject line including the string `[PLATFORM]`, and containing the + details from the end of `./libtool --help` in the body. + * Otherwise, see _Reporting Bugs_ below for how to help us fix any + problems you discover. + +To use Libtool, add the new generic library building commands to your +`Makefile`, `Makefile.in`, or `Makefile.am`. See the documentation for +details. + +[install]: http://git.savannah.gnu.org/cgit/libtool.git/tree/INSTALL +[libtool]: http://www.gnu.org/s/libtool +[libtool list]: mailto:libtool@gnu.org +[news]: http://git.savannah.gnu.org/cgit/libtool.git/tree/NEWS +[notes]: http://git.savannah.gnu.org/cgit/libtool.git/tree/doc/notes.texi +[platforms]: http://git.savannah.gnu.org/cgit/libtool.git/tree/doc/PLATFORMS + + +2. Reporting Bugs +================= + +If this distribution doesn't work for you, before you report the +problem, at least try upgrading to the latest released version first, +and see whether the issue persists. If you feel able, you can also +check whether the issue has been fixed in the development sources for +the next release (see _Obtaining the Latest Sources_ below). + +Once you've determined that your bug is still not fixed in the latest +version, please send a full report to the libtool [bug mailing list][], +including: + + 1. the information from the end of the help message given by + `./libtool --help`, and the verbose output of any failed tests + (see _The Test Suites_ immediately below); + 2. complete instructions for how to reproduce your bug, along with + the results you were expecting, and how they differ from what you + actually see; + 3. a workaround or full fix for the bug, if you have it; + 4. a copy of `tests/testsuite.log` if you are experiencing failures + in the Autotest testsuite. + 5. new test cases for the testsuite that demonstrate the bug are + especially welcome, and will help to ensure that future releases + don't reintroduce the problem - if you're not able to write a + complete testsuite case, a simple standalone shell script is + usually good enough to help us write a test for you. + +If you have any other suggestions, or if you wish to port Libtool to a +new platform, please send email to the [mailing list][libtool list]. + +Please note that if you send us an non-trivial code for inclusion in a +future release, we may ask you for a copyright assignment (for brief +details see the 'Copyright Assignment' section on our +[Contributing][contribute] webpage. + +[bug mailing list]: mailto:bug-libtool@gnu.org +[contribute]: http://www.gnu.org/software/libtool/contribute.html + + +3. The Test Suite +================= + +Libtool comes an integrated sets of tests to check that your build +is sane. You can run like this, assuming that `gmake` refers to GNU +make: + + gmake check + +The new, Autotest-driven testsuite is documented in: + + info Autoconf 'testsuite Invocation' + +but simple help may also be obtained through: + + gmake check TESTSUITEFLAGS='--help' + +For verbose output, add the flag '-v', for running only a subset of the +independent tests, merely specify them by number or by keyword, both of +which are displayed with the '--list' flag. For example, the 'libtool' +keyword is used for the tests that exercise only this script. So it is +possible to test an installed script, possibly from a different Libtool +release, with: + + gmake check \ + TESTSUITEFLAGS="-k libtool LIBTOOL=/path/to/libtool" + +Some tests, like the one exercising `max_cmd_len` limits, make use of +this to invoke the testsuite recursively on a subset of tests. For these +tests, the variable `INNER_TESTSUITEFLAGS` may be used. It will be +expanded right after the `-k libtool`, without separating whitespace, so +that further limiting of the recursive set of tests is possible. For +example, to run only the template tests within the `max_cmd_len`, use: + + gmake check TESTSUITEFLAGS="-v -x -k max_cmd_len \ + INNER_TESTSUITEFLAGS=',template -v -x'" + +If you wish to report test failures to the libtool list, you need to +send the file `tests/testsuite.log` to the [bug mailing list][]. + + +4. Obtaining the Latest Sources +=============================== + +* With the exception of ancient releases, all official GNU Libtool + releases have a detached GPG signature file. With this you can verify + that the corresponding file (i.e. without the `.sig` suffix) is the + same file that was released by the owner of it's GPG key ID. First, + be sure to download both the .sig file and the corresponding release, + then run a command like this: + + gpg --verify libtool-x.y.z.tar.gz.sig + + If that command fails because you don't have the required public key, + then run this command to import it: + + gpg --keyserver keys.gnupg.net --recv-keys 2983D606 + + and then rerun the `gpg --verify` command. + +* Official stable releases of GNU Libtool, along with these detached + signature files are available from: + + ftp://ftp.gnu.org/gnu/libtool + + To reduce load on the main server, please use one of the mirrors + listed at: + + http://www.gnu.org/order/ftp.html + +* Alpha quality pre-releases of GNU Libtool, also with detached + signature files are available from: + + ftp://alpha.gnu.org/gnu/libtool + + and some of the mirrors listed at: + + http://www.gnu.org/order/ftp.html + +* The master libtool repository is stored in git. + + If you are a member of the savannah group for GNU Libtool, a writable + copy of the libtool repository can be obtained by: + + git clone @git.sv.gnu.org:/srv/git/libtool.git + + If you are behind a firewall that blocks the git protocol, you may + find it useful to use + + git config --global url.http://git.sv.gnu.org/r/.insteadof \ + git://git.sv.gnu.org/ + + to force git to transparently rewrite all savannah git references to + use http. + + If you are not a member of the savannah group for GNU Libtool, you can + still fetch a read-only copy with either: + + git clone git://git.sv.gnu.org/libtool.git + + or using the CVS pserver protocol: + + cvs -d:pserver:anonymous@pserver.git.sv.gnu.org:/srv/git/libtool.git \ + co -d libtool HEAD + +* Before you can build from git, you need to bootstrap. This requires: + - Autoconf 2.64 or later + - Automake 1.11.1 or later + - Help2man 1.29 or later + - Xz 4.999.8beta or later (from [tukaani.org](http://tukaani.org/xz)) + - Texinfo 4.8 or later + - Any prerequisites of the above (such as m4, perl, tex) + + Note that these bootstrapping dependencies are much stricter than + those required to use a destributed release for your own packages. + After installation, GNU Libtool is designed to work either standalone, + or optionally with: + - Autoconf 2.59 or later + - Automake 1.9.6 or later + +* The `bootstrap` script sets up the source directory for you to hack. + + +5. Version Numbering +==================== + +People have complained that they find the version numbering scheme under +which libtool is released confusing... so we've changed it! + +It works like this: + + . + +Releases with a **major-number** less than 1 were not yet feature +complete. Releases with a **major-number** of 1 used the old numbering +scheme that everyone disliked so much. Releases with a **major-number** +of 2 us the new scheme described here. If libtool ever undergoes a +major rewrite or substantial restructuring, the **major-number** will be +incremented again. + +If we make a patch release to fix bugs in a stable release, we use a +third number, so: + + 2.4.2 + +If we make an alpha quality prerelease, we use a fourth number for the +number of changsets applied since the version it's based on: + + 2.4.2.418 + +And finally, if you build an unreleased version it will have a short git +revision hash string in hexadecimal appended to all of that: + + 2.4.2.418.3-30eaa + +-- + Copyright (C) 2004-2010, 2015-2019, 2021-2022 Free Software + Foundation, Inc. + + Written by Gary V. Vaughan, 2004 + + This file is part of GNU Libtool. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. This file is offered as-is, +without warranty of any kind. + + +Local Variables: +mode: text +fill-column: 72 +End: +vim:tw=72 diff --git a/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/THANKS b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/THANKS new file mode 100644 index 0000000..fa5f6ee --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libtool-2.4.7/THANKS @@ -0,0 +1,342 @@ +These people have contributed to GNU Libtool. Some have reported problems, +others have contributed improvements to the documentation and actual code. +The particular contributions are described in the version control logs and +ChangeLog files. If your name has been left out, if you'd rather not be +listed, or if you'd prefer a different address be used, please send a +note to the bug-report mailing list (as seen at end of e.g., libtool --help). + +## +aakropotkin alex.ameen.tx@gmail.com +Akim Demaille akim@epita.fr +Alan Hourihane alanh@fairlite.co.uk +Alan Modra amodra@bigpond.net.au +Alan W. Irwin irwin@beluga.phys.uvic.ca +Albert Cheng acheng@ncsa.uiuc.edu +Albert Chin-A-Young china@thewrittenword.com +Alex Ameen alex.ameen.tx@gmail.com +Alexander Hass alexander.hass@sap.com +Alexander Shevchenko sav_ix@ukr.net +Alexandre Duret-Lutz adl@gnu.org +Alexei Sheplyakov varg@theor.jinr.ru +Alex Potapenko opotapeno@gmail.com +Alfred M. Szmidt ams@kemisten.nu +Allan McRae allan@archlinux.org +Allan Sandfeld Jensen snowwolf@one2one-networks.com +Alon Bar-Lev alon.barlev@gmail.com +Andreas Jaeger aj@suse.de +Andreas Schiffler aschiffler@ferzkopp.net +Andreas Schwab schwab@linux-m68k.org +Andrew C. Feren aferen@CetaceanNetworks.com +Andrew Suffield asuffield@debian.org +Andrey Slepuhin pooh@msu.ru +Aneesh Kumar K.V kvaneesh@hotmail.com +Anthony Green green@redhat.com +Archie Cobbs archie@whistle.com +Arkadiusz Miśkiewicz arekm@maven.pl +Arne Woerner woerner@mediabase-gmbh.de +Assar Westerlund assar@sics.se +Bart Van Assche bvanassche@acm.org +Benjamin Reed ranger@befunk.com +Bernhard Fischer spam.protected +Bernhard Rosenkraenzer bero@redhat.de +Bernhard Voelker mail@bernhard-voelker.de +Bert Driehuis bert_driehuis@compuware.com +Bert Wesarg bert.wesarg@googlemail.com +Bob McElrath bob+libtool@mcelrath.org +Boyd Lynn Gerber gerberb@zenez.com +Brad brad@comstyle.com +Brad Smith brad@comstyle.com +Brent Leback brent.leback@st.com +Brian Barrett brbarret@osl.iu.edu +Brian W. Barrett bbarrett@lanl.gov +Brice De Bruyne bricedb@gmail.com +Brook Moses bmoses@google.com +Brooks Moses bmoses@google.com +Bruce Korb bkorb@gnu.org +Bruno Haible bruno@clisp.org +Camilo La Rota camilo.larota@ens-lyon.fr +Carl D. Roth roth@cse.ucsc.edu +Chad Cunningham ccunning@math.ohio-state.edu +Chris Demetriou cgd@google.com +Chris Lattner sabre@skylab.org +Chris P. Ross cross@eng.us.uu.net +Christiaan Welvaart cjw@daneel.dyndns.org +Christian Biesinger cbiesinger@web.de +Christian Cornelssen ccorn@cs.tu-berlin.de +Christian Rössel christian.roessel@gmx.de +Christoph Egger Christoph_Egger@gmx.de +Christopher A. Knight chriskn@crt.com +Christopher Hulbert cchgroupmail@gmail.com +Christopher Pfisterer cp@chrisp.de +Christoph Pfisterer cp@chrisp.de +Craig Dooley xlnxminusx@gmail.com +Craig Tierney Craig.Tierney@noaa.gov +Cristophe Jarry christophe.jarry@ouvaton.org +Dalibor Topic robilad@kaffe.org +Daniel Harvey daniel@amristar.com.au +Daniel Kobras kobras@linux.de +Daniel Reed djr@redhat.com +Daniel Richard G. skunk@iSKUNK.ORG +Dan McMahill mcmahill@mtl.mit.edu +Dan McNichol mcnichol@austin.ibm.com +Dave Brolley brolley@redhat.com +Dave Korn dave.korn.cygwin@googlemail.com +Dave Vasilevsky thevas@mac.com +Dave Yost Dave@Yost.com +David 'Digit' Turner digit@google.com +David Edelsohn dje.gcc@gmail.com +David Heine dlheine@truffle.Stanford.EDU +David Jones jones@mosaid.com +Derek R. Price derek@ximbiot.com +Dirk Mueller dmueller@suse.de +DJ Delorie dj@delorie.com +Donald Anderson dda@world.std.com +Donald D. Anderson dda@sleepycat.com +Donn Washburn n5xwb@comcast.net +Doug Evans devans@casey.cygnus.com +Ed Maste emaste@freebsd.org +Edouard G. Parmelan Edouard.Parmelan@France.NCR.COM +Edward M. Lee tailbert@yahoo.com +Elizabeth Barham soggytrousers@yahoo.com +Erez Zadok ezk@cs.columbia.edu +Eric Bavier bavier@cray.com +Eric Blake ebb9@byu.net +Eric Estievenart eric@via.ecp.fr +Eric Lindahl erik@theophys.kth.se +Erik van Pienbroek erik-gnu@vanpienbroek.nl +Ethan Mallove ethan.mallove@sun.com +Fabian Groffen grobian@gentoo.org +Frank Ch. Eigler fche@cygnus.com +Fred Cox sailorfred@yahoo.com +Fred Fish fnf@be.com +Fredrik Estreen estreen@algonet.se +Fritz Elfert felfert@to.com +Gary Kumfert kumfert@llnl.gov +Geoffrey Keating geoffk@apple.com +George Bosilca bosilca@cs.utk.edu +Gerald Pfeifer gerald@pfeifer.com +Greg Eisenhauer eisen@cc.gatech.edu +Guido Draheim guidod-2001q3@gmx.de +Henning Nielsen Lund hnl_dk@amigaos.dk +Hiroyuki Sato hiroysato@gmail.com +H.J. Lu hjl@gnu.org +Howard Chu hyc@highlandsun.com +Ian Lance Taylor ian@cygnus.com +Ingo Weinhold ingo_weinhold@gmx.de +Jacob Meuser jakemsr@jakemsr.com +Jakub Bogusz qboosh@pld-linux.org +Jakub Jelinek jakub@redhat.com +James E Wilson wilson@specifixinc.com +James Su james.su@gmail.com +Jan Engelhardt jengelh@inai.de +Jan Kratochvil project-libtool@jankratochvil.net +Jay Krell jay.krell@cornell.edu +Jean-Frederic Clere jfrederic.clere@fujitsu-siemens.com +Jeff Squyres jsquyres@cisco.com +Jens Petersen petersen@redhat.com +Jeremie LE HEN tataz@sitadelle.com +Jeremy C. Reed reed@reedmedia.net +Jeremy Huddleston Sequoia jeremyhu@macports.org +Jim Meyering jim@meyering.net +Jim Pick jim@kaffe.org +Jim Tison jtison@us.ibm.com +Jiro Takabatake jiro@din.or.jp +Joakim Tjernlund joakim.tjernlund@transmode.se +Joel N. Weber II devnull@gnu.org +Joe Orton joe@manyfish.co.uk +Joerg Sonnenberger joerg@netbsd.org +John Bowler jbowler@acm.org +John David Anglin dave.anglin@nrc-cnrc.gc.ca +John R. Cary cary@txcorp.com +John Wehle john@feith.com +John Wolfe jlw@sco.com +Jon Meredith jonm@alchemetrics.co.uk +Joseph Beckenbach III jrb3@best.com +Joseph Prostko joe.prostko@gmail.com +Juergen Reuter reuter@t00pcx17094.desy.de +Jürgen Reuter juergen.reuter@physik.uni-freiburg.de +Justin Lecher jlec@gentoo.org +Karl Berry karl@freefriends.org +Kean Johnston jkj@sco.com +Keith Packard keithp@keithp.com +Ken Block block@zk3.dec.com +Kenneth Albanowski kjahds@kjahds.com +Kevin P. Fleming kpfleming@backtobasicsmgmt.com +Kevin Ryde user42@zip.com.au +Khem Raj raj.khem@gmail.com +KO Myung-Hun komh78@gmail.com +Kurt D. Zeilenga Kurt@OpenLDAP.Org +Kurt Roeckx kurt@roeckx.be +Lawrence Velázquez larryv@macports.org +Leif Ekblad leif@rdos.net +Lennart Poettering lennart@poettering.net +Lionel Landwerlin llandwerlin@gmail.com +Loren James Rittle rittle@latour.rsch.comm.mot.com +Lucas Holt luke@foolishgames.com +Maciej Helminiak dion2@wp.pl +Maciej W. Rozycki macro@ds2.pg.gda.pl +Mahesh Narayanamurthi mahesh.mach@gmail.com +Makoto Ishisone ishisone@sra.co.jp +Manfred Weichel Manfred.Weichel@pdb.siemens.de +Manish Singh yosh@gimp.org +Marcel Loose loose@astron.nl +Marc Espie espie@nerim.net +Marc Glisse marc.glisse@inria.fr +Marc J. Fraioli fraioli@dg-rtp.dg.com +Marcus Comstedt marcus@mc.pp.se +Marius Vollmer mvo@zagadka.de +Mark Kettenis kettenis@gnu.org +Markus Duft markus.duft@salomon.at +Markus F.X.J. Oberhumer markus@oberhumer.com +Martin Doucha doucha@integri.cz +Masahiro Nobori nobori@ss.titech.ac.jp +Mats Rynge rynge@isi.edu +Matthieu Herrb matthieu.herrb@laas.fr +Matthijs Kooijman matthijs@stdin.nl +Max Bowsher maxb@ukf.net +Michael Forster email@michael-forster.de +Michael Haubenwallner michael.haubenwallner@salomon.at +Michael Matz matz@ifh.de +Michael Pruett michael@68k.org +Michael Schmitz mschmitz@iname.com +Michael Tiemann tiemann@cygnus.com +Micheal E. Faenza mfaenza@mitre.org +Mike Frysinger vapier@gentoo.org +Mike Gorchak lestat@i.com.ua +Mike Miller mtmiller@ieee.org +Mike Stump mrs@apple.com +Mikhail Zabaluev mikhail.zabaluev@gmail.com +Misty De Meo misty@brew.sh +Mocha netbsd_alpha@yahoo.com +Mo DeJong mdejong@redhat.com +Morten Eriksen mortene@sim.no +Mumit Khan khan@xraylith.wisc.edu +Naofumi Yasufuku naofumi@yasufuku.net +Nick Bowler nbowler@draconx.ca +Nick Hudson nick@nthcliff.demon.co.uk +Nick Rasmussen nick@jive.org +NIIBE Yutaka gniibe@m17n.org +Nix nix@esperi.org.uk +Noah Misch noah@cs.caltech.edu +Norihiro Tanaka noritnk@kcn.ne.jp +Olaf Lenz olenz@fias.uni-frankfurt.de +Olivier Blin olivier.blin@softathome.com +Ollie Wild aaw@google.com +Olly Betts olly@muscat.co.uk +Ondřej Bílka neleai@seznam.cz +Ozkan Sezer sezeroz@gmail.com +Pádraig Brady P@draigBrady.com +Paolo Bonzini bonzini@gnu.org +Patrice Fromy patrice.fromy@u-psud.fr +Patrick Welche prlw1@newn.cam.ac.uk +Paul Berrevoets paul@swi.com +Paul Biggar paul.biggar@gmail.com +Paul Eggert eggert@cs.ucla.edu +Paul Laight plaight@quantxautomation.co.uk +Paul Seidler sepek@lavabit.com +Paul Sokolovsky Paul.Sokolovsky@technologist.com +Pavel (Pasha) Shamis shamisp@ornl.gov +Pavel Raiskup praiskup@redhat.com +Pavel Roskin pavel_roskin@geocities.com +Paweł Daniluk pawel@bioexploratorium.pl +Per Bothner per@bothner.com +Peter Breitenlohner peb@mppmu.mpg.de +Peter Eisentraut peter_e@gmx.net +Peter Ekberg peda@axentia.se +Peter Fritzsche peter.fritzsche@gmx.de +Peter Jeremy peterjeremy@optushome.com.au +Peter Johansson trojkan@gmail.com +Peter Kjellerstedt peter.kjellerstedt@axis.com +Peter Rosin peda@lysator.liu.se +Philip Allison philip.allison@smoothwall.net +Pierre Ossman ossman@ossman.lkpg.cendio.se +Rainer Emrich r.emrich@de.tecosim.com +Rainer Orth ro@CeBiTec.Uni-Bielefeld.DE +Rainer Tammer tammer@tammer.net +Raja R Harinath harinath@cs.umn.edu +Ralf Menzel menzel@ls6.cs.uni-dortmund.de +Ralph Schleicher rs@nunatak.allgaeu.org +Reid Spencer reid@x10sys.com +Reuben Thomas rrt@sc3d.org +Richard B. Kreckel kreckel@ginac.de +Richard Dawe rich@phekda.freeserve.co.uk +Richard Moseley dickie.moseley@virgin.net +Richard Palo richard.palo@baou.fr +Richard Purdie rpurdie@rpsys.net +Richard Sandiford richards@transitive.com +Richard W.M. Jones rjones@redhat.com +Rico Tzschichholz ricotz@ubuntu.com +Robert Garron Robert.Garron@Access3000.net +Robert Millan rmh@aybabtu.com +Roberto Bagnara bagnara@cs.unipr.it +Robert Ögren lists@roboros.com +Robert Yang liezhi.yang@windriver.com +Roger Cornelius rac@tenzing.org +Roland Mainz roland.mainz@nrubsig.org +Roumen Petrov bugtrack@roumenpetrov.info +Rudolf Leitgeb r.leitgeb@x-pin.com +Ryan Hill dirtyepic@gentoo.org +Ryan Schmidt libtool@ryandesign.com +Sam Thursfield ssssam@gmail.com +Samuel Meder meder@mcs.anl.gov +Samuel Thibault samuel.thibault@ens-lyon.org +Sascha Schumann sascha@schumann.cx +Scott McCreary scottmc2@gmail.com +Sebastian Wilhelmi wilhelmi@ira.uka.de +Simon Josefsson jas@extundo.com +Stacey Marshall stacey.marshall@oracle.com +Stas Maximov smaximov@ieee.org +Stefan Nordhausen nordhaus@informatik.hu-berlin.de +Stefan Sperling stsp@elego.de +Stepan Kasal kasal@ucw.cz +Stephane Conversy Stephane.Conversy@lri.fr +Stephan Kulow coolo@kde.org +Steve Ellcey sellcey@mips.com +Steven M. Schultz sms@moe.2bsd.com +Steve Price sprice@hiwaay.net +Svante Signell srs@kth.se +Sven Verdoolaege skimo@liacs.nl +Syd Polk spolk@redhat.com +Terry D. Dontje Terry.Dontje@Sun.COM +Thorsten Glaser tg@66h.42h.de +Tijl Coosemans tijl@FreeBSD.org +Tilman Koschnick til@subnetz.org +Tim Mooney mooney@dogbert.cc.ndsu.NoDak.edu +Timothy Wall twall@oculustech.com +Tim Rice tim@multitalents.net +Tim Van Holder tim.van.holder@pandora.be +Titus von Boxberg titus@v9g.de +Tobias Stoeckmann tobias@stoeckmann.org +Todd C. Miller Todd.Miller@courtesan.com +Todd Vierling tv@duh.org +Tod Milam tmilam@traclabs.com +Tom Kacvinsky tjk@ams.org +Tom Tromey tromey@cygnus.com +Tony Wyatt wyattaw@optushome.com.au +Tor Lillqvist tml@iki.fi +Török Edwin edwintorok@gmail.com +Toshio Kuratomi badger@prtr-13.ucsc.edu +Ulrich Drepper drepper@ipd.info.uni-karlsruhe.de +Utz-Uwe Haus haus@mail.math.uni-magdeburg.de +Václav Haisman vhaisman@gmail.com +Václav Zeman vhaisman@gmail.com +Vadim vadim@olly.ru +Vadim Zeitlin vz-libtool@zeitlins.org +Vincent Lefevre vincent@vinc17.net +Vincent Torri doursse@users.sf.net +Vladimir Kushnir kushn@mail.kar.net +Volker Christian voc@soft.uni-linz.ac.at +Warren Dodge warren.l.dodge@Tektronix.com +Wesley W. Terpstra terpstra@ito.tu-darmstadt.de +Wilfredo Sanchez wsanchez@apple.com +William M. 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See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! + + diff --git a/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/NEWS b/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/NEWS new file mode 100644 index 0000000..4fc85af --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/NEWS @@ -0,0 +1,2 @@ +For the latest libusb news, please refer to the ChangeLog file, or visit: +http://libusb.info diff --git a/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/README b/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/README new file mode 100644 index 0000000..f72faae --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/libusb-1.0.26/README @@ -0,0 +1,28 @@ +# libusb + +libusb is a library for USB device access from Linux, macOS, +Windows, OpenBSD/NetBSD, Haiku and Solaris userspace. +It is written in C (Haiku backend in C++) and licensed under the GNU +Lesser General Public License version 2.1 or, at your option, any later +version (see COPYING). + +libusb is abstracted internally in such a way that it can hopefully +be ported to other operating systems. Please see the PORTING +file for more information. + +libusb homepage: +http://libusb.info/ + +Developers will wish to consult the API documentation: +http://api.libusb.info + +Use the mailing list for questions, comments, etc: +http://mailing-list.libusb.info + +- Hans de Goede +- Xiaofan Chen +- Ludovic Rousseau +- Nathan Hjelm +- Chris Dickens + +(Please use the mailing list rather than mailing developers directly) diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS new file mode 100644 index 0000000..2a989f3 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS @@ -0,0 +1,12 @@ +Dominic Rath +Magnus Lundin +Michael Fischer +Spencer Oliver +Carsten Schlote +Øyvind Harboe +Duane Ellis +Michael Schwingen +Rick Altherr +David Brownell +Vincint Palatin +Zachary T Welch diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS.ChangeLog b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS.ChangeLog new file mode 100644 index 0000000..b2b5e6b --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS.ChangeLog @@ -0,0 +1,10 @@ +drath:Dominic Rath +mlu:Magnus Lundin +mifi:Michael Fischer +ntfreak:Spencer Oliver +duane:Duane Ellis +oharboe:Øyvind Harboe +kc8apf:Rick Altherr +zwelch:Zachary T Welch +vpalatin:Vincent Palatin +bodylove:Carsten Schlote diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/COPYING b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/COPYING new file mode 100644 index 0000000..0e8db92 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/COPYING @@ -0,0 +1,16 @@ +OpenOCD is provided under: + + SPDX-License-Identifier: GPL-2.0-or-later + +Being under the terms of the GNU General Public License version 2 or +later, according with: + + LICENSES/preferred/GPL-2.0 + +In addition, other licenses may also apply. Please see: + + LICENSES/license-rules.txt + +for more details. + +All contributions to OpenOCD are subject to this COPYING file. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS new file mode 100644 index 0000000..9db6c5f --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS @@ -0,0 +1,35 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + +Boundary Scan: + +Target Layer: + +Flash Layer: + +Board, Target, and Interface Configuration Scripts: + +Server Layer: + +RTOS: + +Documentation: + +Build and Release: + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.10.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.10.0 new file mode 100644 index 0000000..e3b1e25 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.10.0 @@ -0,0 +1,155 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * New driver for J-Link adapters based on libjaylink + (including support for FPGA configuration, SWO and EMUCOM) + * FTDI improvements to work at 30MHz clock + * BCM2835 native driver SWD and Raspberry Pi2 support + * BCM2835 is set to 4ma drive, slow slew rate + * ixo-usb-jtag (emulation of an Altera Bus Blaster I on + Cypress FX2 IC) support + * JTAG pass-through mode for CMSIS-DAP (including support for + FPGA configuration) + * OpenJTAG support for Cypress CY7C65215 + * connect_assert_srst support for SWD + * Xilinx Virtex-II Series7 bitstream loading support + * Use JEP106 data to decode IDs + * Deprecated "ft2232" driver removed (use "ftdi" instead) + * GPL-incompatible FTDI D2XX library support dropped (Presto, + OpenJTAG and USB-Blaster I are using libftdi only now) + * ZY1000 support dropped (unmaintained since long) + * oocd_trace support dropped + +Boundary Scan: + +Target Layer: + * ARMv7-A, Cortex-M, Cortex-A/R important fixes and + improvements (allowing e.g. simultaneous debugging of A8 and + M3 cores, JTAG WAIT support etc.) + * ARM Cortex-A,R allow interrupt disable during single-step + (maskisr command) + * Semihosting support for ARMv7-A + * ARM Cortex-M7 support + * Intel Quark mcu D2000 support + * Freescale LS102x SAP support + * ThreadX RTOS support on ARM926E-JS + * Cortex-M RTOS stack alignment fixes + * FreeRTOS FPU support + * uC/OS-III RTOS support + * bridging semihosting to GDB's File-I/O support + * -defer-examine option added to target create command + * verify_image_checksum command added + +Flash Layer: + * Atmel SAM4S, SAM4N, SAM4C support + * Atmel SAMV, SAMS, SAME (Cortex-M7) support + * Atmel AT91SAMD handle reset run/halt in DSU, other fixes + * Atmel AT91SAML21, SAML22, SAMC20/SAMC21, SAMD09 support + * ST STM32F4x support + * ST STM32F74x/76x/77x, STM32L4 support + * ST STM32L0 categories 1, 2 and 5 support + * Kinetis K02, K21, K22, K24, K26, K63, K64, K66 support + * Kinetis KE, KVx, K8x families support + * Kinetis FlexNVM handling + * Kinetis flash protection, security, mass_erase improvements + * Infineon XMC4xxx family support + * Infineon XMC1000 flash driver + * Energy Micro EFM32 Happy Gecko support + * Energy Micro EFM32 debug interface lock support + * Analog Devices ADuCM360 support + * Unified Nuvoton NuMicro flash driver + * NIIET K1921VK01T (Cortex-M4) support + * Nordic Semiconductor nRF51 improvements + * Spansion FM4 flash (including MB9BFx64/x65, S6E2DH) driver + * Ambiq Micro Apollo flash driver + * PIC32MX new device IDs, 17x/27x flash support + * read_bank() and verify_bank() NOR flash internal API to + allow reading (and verifying) non-memory-mapped devices + * JTAGSPI driver to access SPI NOR flashes via a trivial + FPGA proxy + * Milandr read/verify for Info memory support + * Various discrete SPI NOR flashes support + * CFI 16-bit flash reversed endianness support + +Board, Target, and Interface Configuration Scripts: + * Digilent JTAG-HS2, JTAG-HS3 interfaces configs + * FTDI UM232H module as JTAG interface config + * 100ask's OpenJTAG interface config + * MBFTDI interface config + * XDS100v3 interface config + * Freescale Vybrid VF6xx target config + * EmCraft VF6 SOM and baseboard configs + * Freescale SabreSD board config + * Freescale VF65GS10 tower board config + * Pipistrello Xilinx Spartan6 LX45 FPGA board config + * miniSpartan6+ board config + * Xilinx Kintex7 Development board config + * Parallella-I board config + * Digilent Atlys and Analog Discovery board configs + * Numato Opsis board config + * Xilinx Spartan 6 FPGA "Device DNA" reading support + * Altera 10M50 FPGA (MAX10 family) target config + * Altera EPM240 CPLD (MAXII family) target config + * Marsohod2, Marsohod3 FPGA, Marsohod CPLD boards configs + * Novena's integrated FPGA board config + * XMOS XS1-XAU8A-10's ARM core config + * XMOS xCORE-XA Core Module board config + * Exynos5250 target config + * Arndale board config + * FM4 MB9BFxxx family configs + * Spansion SK-FM4-U120-9B560 board config + * Diolan LPC4357-DB1 board config + * ST STM32F469 discovery board config + * ST STM32F7-DISCO, STM327[4|5]6G-EVAL boards configs + * ST STM32L4 discovery, NUCLEO L476RG, STM32F429I-DISC1 boards + configs + * Atheros AR2313, AR2315 targets config + * Netgear WP102 board config + * La Fonera FON2200 board config + * Linksys WAG200G board config + * LPC-Link2 board config + * NXP LPC4370 target config + * Atmel SAMV, SAMS, SAME target configs + * Atmel SAM E70 Xplained, SAM V71 Xplained Ultra boards + configs + * Nordic nRF52 target config + * Nordic nRF51-DK, nRF52-DK boards configs + * Infineon XMC4700 Relax Kit, XMC4800 Relax EtherCAT Kit, + XMC4300 Relax EtherCAT Kit boards configs + * Renesas S7G2 target config + * Renesas DK-S7G2 board config + * Altera EP3C10 FPGA (Cyclone III family) target config + * TI MSP432P4xx target config + * Cypress PSoC 5LP target config + * Analog Devices ADSP-SC58x target config (Cortex-A5 core only) + +Server Layer: + * tcl_trace command for async target trace output via Tcl RPC + +Documentation: + +Build and Release: + * Various fixes thanks to http://coccinellery.org/ + * libftdi is now autodetected with pkgconfig + * Releases should now support reproducible builds + * Conversion to non-recursive make, requires automake >= 1.14 + * Udev rules modified to add uaccess tag and moved to + 60-openocd.rules + * Support searching for scripts relative to the openocd binary + for all major architectures + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.10.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.11.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.11.0 new file mode 100644 index 0000000..4542aa2 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.11.0 @@ -0,0 +1,238 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * add debug level 4 for verbose I/O debug + * bitbang, add read buffer to improve performance + * Cadence SystemVerilog Direct Programming Interface (DPI) adapter driver + * CMSIS-DAP v2 (USB bulk based) adapter driver + * Cypress KitProg adapter driver + * FTDI FT232R sync bitbang adapter driver + * Linux GPIOD bitbang adapter driver through libgpiod + * Mellanox rshim USB or PCIe adapter driver + * Nuvoton Nu-Link and Nu-Link2 adapter drivers + * NXP IMX GPIO mmap based adapter driver + * ST-Link consolidate all versions in single config + * ST-Link read properly old USB serial numbers + * STLink/V3 support (for ST devices only !) + * STM8 SWIM transport + * TI XDS110 adapter driver + * Xilinx XVC/PCIe adapter driver + +Boundary Scan: + +Target Layer: + * 64 bit address support + * ARCv2 target support + * ARM Cortex-A hypervisor mode support + * ARM Cortex-M fast PC sampling support for profiling + * ARM generic CTI support + * ARM generic mem-ap target support + * ARMv7-A MMU tools + * ARMv7m traces add TCP stream server + * ARMv8 AARCH64 target support and semihosting support + * ARMv8 AARCH64 disassembler support through capstone library + * ARMv8-M target support + * EnSilica eSi-RISC target support, including instruction tracing + eSi-Trace support + * MIPS64 target support + * Motorola SREC S6 record image file support + * RISC-V target support + * SEGGER Real Time Transfer (RTT) initial support (for single target, + Cortex-M only) + * ST STM8 target support + * Various MIPS32 target improvements + +Flash Layer: + * Atheros (ath79) SPI interface support + * Atmel atmega128rfa1 support + * Atmel SAM D21, D51, DA1, E51, E53, E54, G55, R30 support + * Atmel SAMC2?N* support + * Cypress PSoC5LP, PSoC6 support + * EnSilica eSi-RISC support + * Foshan Synwit Tech SWM050 support + * Maxim Integrated MAX32XXX support + * Nordic Semiconductor nRF51822, nRF52810, nRF52832 support + * NXP Kinetis K27, K28, KE1x, KEAx, KL28, KL8x, KV5x, KWx support + * Renesas RPC HF support + * SH QSPI support + * SiFive Freedom E support + * Silicon Labs EFR-family, EZR32HG support + * ST BlueNRG support + * ST STM32 QUAD/OCTO-SPI interface support for Flash, FRAM and EEPROM + * ST STM32F72x, STM32F4x3, STM32H7xx support + * ST STM32G0xx, STM32G4xx, STM32L4x, STM32WB, STM32WL support + * ST STM32L5x support (non secure mode) + * TI CC13xx, CC26xx, CC32xx support + * TI MSP432 support + * Winner Micro w600 support + * Xilinx XCF platform support + * Various discrete SPI NOR flashes support + +Board, Target, and Interface Configuration Scripts: + * 8devices LIMA board config + * Achilles Instant-Development Kit Arria 10 board config + * Amazon Kindle 2 and DX board config + * Analog Devices ADSP-SC58x, ADSP-SC584-EZBRD board config + * Andes Technology ADP-XC7KFF676 board config + * Andes Technology Corvette-F1 board config + * ARM Musca A board config + * Arty Spartan 7 FPGA board config + * Atmel SAMD10 Xplained mini board config + * Atmel SAMD11 Xplained Pro board config + * Atmel SAM G55 Xplained Pro board config + * AVNET UltraZED EG StarterKit board config + * Blue Pill STM32F103C8 board config + * DP Busblaster v4.1a board config + * DPTechnics DPT-Board-v1 board config + * Emcraft imx8 SOM BSB board config + * Globalscale ESPRESSObin board config + * Kasli board config + * Kintex Ultrascale XCKU040 board config + * Knovative KC-100 board config + * LeMaker HiKey board config + * Microchip (Atmel) SAME54 Xplained Pro board config + * Microchip (Atmel) SAML11 Xplained Pro board config + * Nordic module NRF52 board config + * Numato Lab Mimas A7 board config + * NXP Freedom FRDM-LS1012A board config + * NXP IMX7SABRE board config + * NXP IMX8MP-EVK board config + * NXP MC-IMX8M-EVK board config + * QuickLogic QuickFeather board config + * Renesas R-Car E2, H2, M2 board config + * Renesas R-Car Salvator-X(S) board config + * Renesas RZ/A1H GR-Peach board config + * Rigado BMD-300 board config + * Sayma AMC board config + * Sifive e31arty, e51arty, hifive1 board config + * ST B-L475E-IOT01A board config + * ST BlueNRG idb007v1, idb008v1, idb011v1 board config + * ST STM32F412g discovery board config + * ST STM32F413h discovery board config + * ST STM32F469i discovery board config + * ST STM32F7 Nucleo board config + * ST STM32F723e discovery board config + * ST STM32F746g discovery board config + * ST STM32F769i discovery board config + * ST STM32H735g discovery board config + * ST STM32H743zi Nucleo board config + * ST STM32H745i discovery board config + * ST STM32H747i discovery board config + * ST STM32H750b discovery board config + * ST STM32H7b3i discovery board config + * ST STM32H7x_dual_qspi board config + * ST STM32H7x3i Eval boards config + * ST STM32L073 Nucleo board config + * ST STM32L476g discovery board config + * ST STM32L496g discovery board config + * ST STM32L4p5g discovery board config + * ST STM32L4r9i discovery board config + * ST STM32L5 Nucleo board config + * ST STM32MP15x DK2 board config + * ST STM32WB Nucleo board config + * ST STM8L152R8 Nucleo board config + * Synopsys DesignWare ARC EM board config + * Synopsys DesignWare ARC HSDK board config + * TI BeagleBone family boards config + * TI CC13xx, CC26xx, CC32xx LaunchPad board config + * TI MSP432 LaunchPad board config + * Tocoding Poplar board config + * TP-Link WDR4300 board config + * Allwinner V3s target config + * Andes Technology NDS V5 target config + * Atmel atmega128rfa1 target config + * ARM corelink SSE-200 target config + * Atheros_ar9344 target config + * Cypress PSoC5LP, PSoC6 target config + * EnSilica eSi-RISC target config + * Foshan Synwit Tech SWM050 target config + * GigaDevice GD32VF103 target config + * Hisilicon Hi3798 target config + * Hisilicon Hi6220 target config + * Infineon TLE987x target config + * Marvell Armada 3700 target config + * Maxim Integrated MAX32XXX target config + * Mellanox BlueField target config + * Microchip (Atmel) SAME5x, SAML1x target config + * NXP IMX6SX, IMX6UL, IMX7, IMX7ULP, IMX8 target config + * NXP Kinetis KE1xZ, KE1xF target config + * NXP LPC84x, LPC8Nxx, LS1012A, NHS31xx target config + * Qualcomm QCA4531 target config + * QuickLogic EOS S3 target config + * Renesas R-Car E2, H2, M2 target config + * Renesas R-Car Gen3 target config + * Renesas RZ/A1H target config + * Rockchip RK3308 target config + * ST BlueNRG target config + * ST STM32G0, STM32G4, STM32H7, STM32L0, STM32L5 target config + * ST STM32MP15x target config + * ST STM32WBx, STM32WLEx target config + * ST STM8L152, S003, S103, S105 target config + * Synopsys DesignWare ARC EM target config + * Synopsys DesignWare ARC HS Development Kit SoC target config + * TI CC13xx, CC26xx, CC32xx target config + * TI TNETC4401 target config + * Xilinx UltraScale+ target config + * Altera 5M570Z (MAXV family) CPLD config + * Xilinx Ultrascale, XCF CPLD config + * Intel (Altera) Arria10 FPGA config + * Cadence SystemVerilog Direct Programming Interface (DPI) interface config + * Cypress KitProg interface config + * Digilent SMT2 NC interface config + * DLN-2 example of Linux GPIOD interface config + * FTDI C232HM interface config + * HIE JTAG Debugger interface config + * In-Circuit's ICprog interface config + * isodebug isolated JTAG/SWD+UART interface config + * Mellanox rshim USB or PCIe interface config + * Nuvoton Nu-Link interface config + * NXP IMX GPIO mmap based interface config + * Steppenprobe open hardware interface config + * TI XDS110 interface config + +Server Layer: + * 64 bit address support + * default bind to IPv4 localhost + * gdb: allow multiple connections + * gdb: architecture element support + * gdb: vCont, vRun support + * telnet: handle Ctrl+A, Ctrl+E and Ctrl+K + +RTOS: + * Chromium-EC rtos support + * hwthread pseudo rtos support + * NuttX rtos support + * RIOT rtos support + +Documentation: + * Improve STM32 flash driver + * Various typo fix and improvements + +Build and Release: + * Add libutil to support jimtcl version 0.80 + * Clang warning fixes + * GitHub workflow for Win32 snapshot binaries + * Handle Tcl return values consistently + * Mitigation for CVE-2018-5704: Prevent some forms of Cross + Protocol Scripting attacks + * Support for libftdi 1.5 + * Travis-CI basic support + * Update libjaylink to version 0.2.0 + * Update jimtcl to version 0.79 + * Use external (optional) library capstone for ARM and AARCH64 disassembly + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.11.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.12.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.12.0 new file mode 100644 index 0000000..208146a --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.12.0 @@ -0,0 +1,132 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * add default to adapter speed when unspecified (100 kHz) + * AM335X gpio (BeagleBones) adapter driver + * BCM2835 support for SWD + * Cadence Virtual Debug (vdebug) adapter driver + * CMSIS-DAP support for SWO and SWD multidrop + * Espressif USB JTAG Programmer adapter driver + * Remote bitbang support for Windows host + * ST-LINK add TCP server support to adapter driver + * SWD multidrop support + +Boundary Scan: + +Target Layer: + * aarch64: support watchpoints + * arm: support independent TPIU and SWO for trace + * arm adi v5: support Large Physical Address Extension + * arm adi v6: support added, for jtag and swd transport + * cortex_a: support watchpoints + * elf 64bit load support + * Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores + * semihosting: support user defined operations + * Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP + +Flash Layer: + * Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support + * GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support + * Nuvoton NPCX series support + * onsemi RSL10 support + * Raspberry Pi Pico RP2040 support + * ST BlueNRG-LPS support + * ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support + * ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support + +Board, Target, and Interface Configuration Scripts: + * Ampere Computing eMAG8180, Altra ("Quicksilver") and Altra Max ("Mystique") board config + * Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config + * Digilent Nexys Video board config + * Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config + * Espressif ESP32 via ESP USB Bridge generic board config + * Espressif ESP32-S2 Kaluga 1 board config + * Espressif ESP32-S2 with ESP USB Bridge board config + * Espressif ESP32-S3 example board config + * Kontron SMARC-sAL28 board config + * LambdaConcept ECPIX-5 board config + * Microchip ATSAMA5D27-SOM1-EK1 board config + * Microchip EVB-LAN9255 board config + * Microchip SAME51 Curiosity Nano board config + * NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config + * NXP RT6XX board config + * Olimex H405 board config + * Radiona ULX3S board config + * Raspberry Pi 3 and Raspberry Pi 4 model B board config + * Raspberry Pi Pico-Debug board config + * Renesas R-Car V3U Falcon board config + * ST BlueNRG-LPS steval-idb012v1 board config + * ST NUCLEO-8S208RB board config + * ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config + * ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config + * ST STM32MP13x-DK board config + * TI AM625 EVM, AM642 EVM and AM654 EVM board config + * TI J721E EVM, J721S2 EVM and J7200 EVM board config + * Ampere Computing eMAG, Altra ("Quicksilver") and Altra Max ("Mystique") target config + * Cadence Xtensa generic and Xtensa VDebug target config + * Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config + * Espressif ESP32, ESP32-S2 and ESP32-S3 target config + * Microchip ATSAMA5D2 series target config + * NanoXplore NG-Ultra SoC target config + * NXP IMX8QM target config + * NXP LS1028A, LS1046A and LS1088A target config + * NXP RT600 (Xtensa HiFi DSP) target config + * onsemi RSL10 target config + * Raspberry Pi Pico RP2040 target config + * Renesas R8A779A0 V3U target config + * Renesas RZ/Five target config + * Renesas RZ/G2 MPU family target config + * Rockchip RK3399 target config + * ST BlueNRG-LPS target config + * ST STM32MP13x target config + * TI AM625, AM654, J721E and J721S2 target config + * Ashling Opella-LD interface config + * Aspeed AST2600 linuxgpiod based interface config + * Blinkinlabs JTAG_Hat interface config + * Cadence Virtual Debug (vdebug) interface config + * Espressif ESP32-S2 Kaluga 1 board's interface config + * Espressif USB Bridge jtag interface config + * Infineon DAP miniWiggler V3 interface config + * PLS SPC5 interface config + * Tigard interface config + * Lattice MachXO3 family FPGA config + +Server Layer: + * GDB: add per-target remote protocol extensions + * GDB: more 'Z' packets support + * IPDBG JtagHost server functionality + * semihosting: I/O redirection to TCP server + * telnet: support for command's autocomplete + +RTOS: + * 'none' rtos support + * Zephyr rtos support + +Documentation: + +Build and Release: + * Add json extension to jimtcl build + * Drop dependency from libusb0 + * Drop repository repo.or.cz for submodules + * Move gerrit to https://review.openocd.org/ + * Require autoconf 2.69 or newer + * Update jep106 to revision JEP106BF.01 + * Update jimtcl to version 0.81 + * Update libjaylink to version 0.3.1 + * New configure flag '--enable-jimtcl-maintainer' for jimtcl build + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.2.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.2.0 new file mode 100644 index 0000000..7426926 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.2.0 @@ -0,0 +1,80 @@ +The OpenOCD 0.2.0 source archive release includes numerous improvements +that were made since the initial 0.1.0 source archive release. Many +contributors helped make this release a great success, and the community +of developers and maintainers look forward to any response. + +In addition to the list of changes below, countless bug fixing and +cleaning was performed across the tree. Various TCL command parameters +must past stricter value checks, and many more error conditions have +been handled correctly. These efforts helped to make the 0.2.0 release +more stable and robust, though some changes may expose latent bugs in +your existing configuration scripts. + +This release does not maintain backward compatibility in all respects, +so some target or configuration scripts may need to be updated. In some +cases, you may also see warnings; resolve those, because they indicate +commands that will be removed in the future. + +The following areas of OpenOCD functionality changed in this release: + +JTAG Layer: +- Improves modularity: core, TCL, driver commands, and interface have + been separated, encapsulated, and documented for developers. Mostly. +- Improves JTAG TAP transition tables: + * Makes TAP paths variable length, rather than being fixed at 7 steps. + * Fixes problems with some targets that did not like longer paths. +- Improves JTAG driver/minidriver modularity and encapsulation. +- New drivers: + * Adds stub minidriver for developing new embedded JTAG interfaces. +- Improves drivers: + * ft2232+ftd2xx: + + Adds initial high-speed device support: --enable-ftd2xx-highspeed + + Supports more types of FTDI-based devices. + * jlink: + + Works with more versions of the firmware (v3 and newer) + + Supports dynamically detects device capabilities and limits + * vsllink: + + Supports very long scan chains + * amtjtagaccel: + + Fixes broken ID code detection problems. + +Target Layer: +- New devices: AVR, FA526 +- Improved support: ARM ADI, ARM11, MIPS +- Numerous other bug fixes and improvements + +Flash Layer: +- Improved drivers: mflash +- New drivers: AT91SAM3, AVR, Davinci NAND + +Board, Interface, and Target Configuration Scripts: +- Many new and improved targets and boards are now available. +- Better separation of "board" and "target" configuration +- Moved all TCL files to top-level "tcl" directory in the source tree +- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'. +- Site-specific files should be installed under '$pkgdatadir/site/'; + files that exist this tree will be used in preference to default + distribution configurations in '$pkgdatadir/scripts/'. + +Documentation: +- Updated User Guide: http://openocd.berlios.de/doc/html/index.html + * Partially re-written and re-organized. + * Standardized presentation for all commands. + * Covers many drivers and commands that were previously omitted. + * New index for commands and drivers. +- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html + * Now includes architecture, technical primers, style guides, and more. + * Available in-tree and on-line. + +Build and Release: +- Increased configuration and compilation warning coverage. + * Use --disable-werror to work around build errors caused by warnings. +- Use libtool to produce helper libraries as a step toward "libopenocd". +- New processes and scripting to facilitate future source releases. + +For more details about what has changed since 0.1.0, see the ChangeLog +associated with this release. + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.3.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.3.0 new file mode 100644 index 0000000..80e8823 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.3.0 @@ -0,0 +1,82 @@ +This file should include highlights of the changes made in the +OpenOCD openocd-0.3.0 source archive release. See the repository +history for details about what changed, including bugfixes and +other issues not mentioned here. + +JTAG Layer: + FT2232H (high speed USB) support doesn't need separate configuration + New FT2232H JTAG adapters: Amontec, Olimex, Signalyzer + New reset_config options for SRST gating the JTAG clock (or not) + TAP declaration no longer requires ircapture and mask attributes + Scan chain setup should be more robust, with better diagnostics + New TAP events: + "post-reset" for TAP-invariant setup code (TAPs not usable yet) + "setup" for use once TAPs are addressable (e.g. with ICEpick) + Overridable Tcl "init_reset" and "jtag_init" procedures + Simple "autoprobe" mechanism to help simplify server setup + +Boundary Scan: + SVF bugfixes ... parsing fixes, better STATE switch conformance + XSVF bugfixes ... be more correct, handle Xilinx tool output + +Target Layer: + Warn on use of obsolete numeric target IDs + New commands for use with Cortex-M3 processors: + "cortex_m3 disassemble" ... Thumb2 disassembly (UAL format) + "cortex_m3 vector_catch" ... traps certain hardware faults + without tying up breakpoint resources + If you're willing to help debug it + VERY EARLY Cortex-A8 and ARMv7A support + Updated BeagleBoard.org hardware support + you may need to explicitly "reset" after connect-to-Beagle + New commands for use with XScale processors: "xscale vector_table" + ARM + bugfixes to single-stepping Thumb code + ETM: unavailable registers are not listed + ETB, ETM: report actual hardware status + ARM9 + name change: "arm9 vector_catch" not "arm9tdmi vector_catch" + ARM11 + single stepping support for i.MX31 + bugfix for missing "arm11" prefix on "arm11 memwrite ..." + GDB support + gdb_attach command is gone + +Flash Layer: + The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips + New drivers: + lpc2900, for NXP LPC2900 chips (ARM968 based) + mx3_nand, for imx31 + New "last" flag for NOR "flash erase_sector" and "flash protect" + The "nand erase N" command now erases all of bank N + Speed up davinci_nand by about 3x + +Board, Target, and Interface Configuration Scripts: + Amontec JTAGkey2 support + Cleanup and additions for the TI/Luminary Stellaris scripts + LPC1768 target (and flash) support + Keil MCB1700 eval board + Samsung s3c2450 + Mini2440 board + Numeric TAP and Target identifiers now trigger warnings + PXA255 partially enumerates + +Documentation: + Capture more debugging and setup advice + Notes on target source code changes that may help debugging + +Build and Release: + Repository moved from SVN at Berlios to GIT at SourceForge + Clean builds on (32-bit) Cygwin + Clean builds on 64-bit MinGW + +For more details about what has changed since the last release, +see the git repository history. With gitweb, you can browse that +in various levels of detail. + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.4.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.4.0 new file mode 100644 index 0000000..cbd5526 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.4.0 @@ -0,0 +1,98 @@ +This file includes highlights of the changes made in the +OpenOCD 0.4.0 source archive release. See the repository +history for details about what changed, including bugfixes +and other issues not mentioned here. + +JTAG Layer: + Support KT-Link JTAG adapter. + Support USB-JTAG, Altera USB-Blaster and compatibles. + +Boundary Scan: + +Target Layer: + General + - Removed commands which have been obsolete for at least + a year (from both documentation and, sometimes, code). + - new "reset-assert" event, for systems without SRST + ARM + - supports "reset-assert" event (except on Cortex-M3) + - renamed "armv4_5" command prefix as "arm" + - recognize TrustZone "Secure Monitor" mode + - "arm regs" command output changed + - register names use "sp" not "r13" + - add top-level "mcr" and "mrc" commands, replacing + various core-specific operations + - basic semihosting support (ARM7/ARM9 only, for now) + ARM11 + - Should act much more like other ARM cores: + * Preliminary ETM and ETB hookup + * accelerated "flash erase_check" + * accelerated GDB memory checksum + * support "arm regs" command + * can access all core modes and registers + * watchpoint support + - Shares some core debug code with Cortex-A8 + Cortex-A8 + - Should act much more like other ARM cores: + * support "arm regs" command + * can access all core modes and registers + * watchpoint support + - Shares some core debug code with ARM11 + Cortex-M3 + - Exposed DWT registers like cycle counter + - vector_catch settings not clobbered by resets + - no longer interferes with firmware's fault handling + ETM, ETB + - "trigger_percent" command moved ETM --> ETB + - "etm trigger_debug" command added + MIPS + - use fastdata writes + Freescale DSP563xx cores (partial support) + +Flash Layer: + 'flash bank' and 'nand device' take as first argument. + With this, flash/NAND commands allow referencing banks by name: + - : reference the bank with its defined name + - [.N]: reference the driver's Nth bank + New 'nand verify' command to check bank against an image file. + The "flash erase_address" command now rejects partial sectors; + previously it would silently erase extra data. If you + want to erase the rest of the first and/or last sectors + instead of failing, you must pass an explicit "pad" flag. + New at91sam9 NAND controller driver. + New s3c64xx NAND controller driver. + +Board, Target, and Interface Configuration Scripts: + ARM9 + - ETM and ETB hookup for iMX2* targets + Add $HOME/.openocd to the search path. + Handle Rev C of LM3S811 eval boards. + - use "luminary-lm3s811.cfg" for older boards + - use "luminary.cfg" for RevC and newer + +Core Jim/TCL Scripting: + New 'usage' command to provide terse command help. + Improved command 'help' command output (sorted and indented). + Improved command handling: + - Most boolean settings now accept any of the following: + on/off, enable/disable, true/false, yes/no, 1/0 + - More error checking and reporting. + +Documentation: + New built-in command development documentation and primer. + +Build and Release: + Use --enable-doxygen-pdf to build PDF developer documentation. + Consider upgrading to libftdi 0.17 if you use that library; it + includes bugfixes which improve FT2232H support. + +For more details about what has changed since the last release, +see the git repository history. With gitweb, you can browse that +in various levels of detail. + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.5.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.5.0 new file mode 100644 index 0000000..90ea35c --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.5.0 @@ -0,0 +1,73 @@ +This file includes highlights of the changes made in the +OpenOCD 0.5.0 source archive release. See the repository +history for details about what changed, including bugfixes +and other issues not mentioned here. + +JTAG Layer: + New driver for "Bus Pirate" + Rename various commands so they're not JTAG-specific + There are migration procedures for most of these, but you should + convert your scripts to the new names, since those procedures + will not be around forever. + jtag jinterface ... is now adapter_name + jtag_khz ... is now adapter_khz + jtag_nsrst_delay ... is now adapter_nsrst_delay + jtag_nsrst_assert_width ... is now adapter_nsrst_assert_width + Support Voipac VPACLink JTAG Adapter. + +Boundary Scan: + +Transport framework core ... supporting future work for SWD, SPI, and other +non-JTAG ways to debug targets or program flash. + +Target Layer: + ARM: + - basic semihosting support for ARMv7M. + - renamed "armv7m" command prefix as "arm" + MIPS: + - "ejtag_srst" variant removed. The same functionality is + obtained by using "reset_config none". + - added PIC32MX software reset support, this means srst is not + required to be connected anymore. + OTHER: + - preliminary AVR32 AP7000 support. + +Flash Layer: + New "stellaris recover" command, implements the procedure + to recover locked devices (restoring non-volatile + state to the factory defaults, including erasing + the flash and its protection bits, and possibly + re-enabling hardware debugging). + PIC32MX now uses algorithm for flash programming, this + has increased the performance by approx 96%. + New 'pic32mx unlock' cmd to remove readout protection. + New STM32 Value Line Support. + New 'virtual' flash driver, used to associate other addresses + with a flash bank. See pic32mx.cfg for usage. + New iMX27 NAND flash controller driver. + +Board, Target, and Interface Configuration Scripts: + Support IAR LPC1768 kickstart board (by Olimex) + Support Voipac PXA270/PXA270M module. + New $PARPORTADDR tcl variable used to change default + parallel port address used. + Remove lm3s811.cfg; use "stellaris.cfg" instead + +Core Jim/TCL Scripting: + New "add_script_search_dir" command, behaviour is the same + as the "-s" cmd line option. + +Documentation: + +Build and Release: + +For more details about what has changed since the last release, +see the git repository history. With gitweb, you can browse that +in various levels of detail. + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.6.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.6.0 new file mode 100644 index 0000000..0acd242 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.6.0 @@ -0,0 +1,54 @@ +This file includes highlights of the changes made in the +OpenOCD source archive release. See the +repository history for details about what changed, including +bugfixes and other issues not mentioned here. + +JTAG Layer: + New STLINK V1/V2 JTAG/SWD adapter support. + New OSJTAG adapter support. + New Tincantools Flyswatter2 support. + Improved ULINK driver. + Improved RLINK driver. + Support for adapters based on FT232H chips. + New experimental driver for FTDI based adapters, using libusb-1.0 in asynchronous mode. + +Boundary Scan: + +Target Layer: + New Cortex-M0 support. + New Cortex-M4 support. + Improved Working area algorithm. + New RTOS support. Currently linux, FreeRTOS, ThreadX and eCos. + Connecting under reset to Cortex-Mx and MIPS chips. + +Flash Layer: + New SST39WF1601 support. + New EN29LV800BB support. + New async algorithm support for selected targets, stm32, stellaris and pic32. + New Atmel SAM3S, SAM3N support. + New ST STM32L support. + New Microchip PIC32MX1xx/2xx support. + New Freescale Kinetis K40 support. + +Board, Target, and Interface Configuration Scripts: + Support Dangerous Prototypes Bus Blaster. + Support ST SPEAr Family. + Support Gumstix Verdex boards. + Support TI Beaglebone. + +Documentation: + Improved HACKING info for submitting patches. + Fixed numerous broken links. + +Build and Release: + +For more details about what has changed since the last release, +see the git repository history. With gitweb, you can browse that +in various levels of detail. + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.7.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.7.0 new file mode 100644 index 0000000..47a8fa6 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.7.0 @@ -0,0 +1,43 @@ +This file includes highlights of the changes made in the +OpenOCD source archive release. See the +repository history for details about what changed, including +bugfixes and other issues not mentioned here. + +JTAG Layer: + New TI ICDI adapter support. + Support Latest OSBDM firmware. + Improved MIPS EJTAG Support. + +Boundary Scan: + +Target Layer: + New ARMv7R and Cortex-R4 support. + Added ChibiOS/RT support. + +Flash Layer: + New NXP LPC1850 support. + New NXP LPC4300 support. + New NXP SPIFI support. + New Energy Micro EFM32 support. + New ST STM32W support. + New ST STM32f2 write protection and lock/unlock support. + Ability to override STM32 flash bank size. + +Board, Target, and Interface Configuration Scripts: + Support Freescale i.MX6 series targets. + +Documentation: + New MIPS debugging info. + +Build and Release: + +For more details about what has changed since the last release, +see the git repository history. With gitweb, you can browse that +in various levels of detail. + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.8.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.8.0 new file mode 100644 index 0000000..33b3af4 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.8.0 @@ -0,0 +1,111 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * New CMSIS-DAP driver + * Andes AICE debug adapter support + * New OpenJTAG driver + * New BCM2835 (RaspberryPi) driver + * JTAG VPI client driver (for OpenRISC Reference Platform SoC) + * Xilinx BSCAN_* for OpenRISC support + * ST-LINKv2-1 support + * ST-LINKv2 SWO tracing support (UART emulation) + * JLink-OB (onboard) support + * Altera USB Blaster driver rewrite, initial Blaster II + support + * ULINK driver ported to libusb-1.0, OpenULINK build fixes + * Support up to 64 bit IR lengths + * SVF playback (FPGA programming) fixes + * "ftdi" interface driver got extensive testing and is now + recommended over the old ft2232 implementation + +Boundary Scan: + +Target Layer: + * New target: Andes nds32 + * New target: OpenRISC OR1K + * New target: Intel Quark X10xx + * MIPS EJTAG 1.5/2.0 support + * MIPS speed improvements + * Cortex-M, Cortex-A (MEM-AP, APB-AP) targets working with BE + hosts now + * XScale vector_catch support, reset fixes + * dsp563xx ad-hoc breakpoint/watchpoint support + * RTOS support for embKernel + * Target profiling improvements + * Memory access functions testbench + +Flash Layer: + * STM32 family sync with reference manuals, other bugfixes + * STM32F401, STM32F07x support + * Atmel SAM4L, SAMG5x support + * at91sam3sd8{a,b}, at91sam3s8{a,b,c}, at91sam4s, + at91sam3n0{a,b,0a,0b} support, bugfixes + * Atmel SAMD support + * Milandr 1986ВЕ* support + * Kinetis KL, K21 support + * Nuvoton NuMicro MINI5{1,2,4} support + * Nuvoton NUC910 series support + * NXP LPC43xx, LPC2000 fixes + * NXP LPC800, LPC810 support + * More ATmega parts supported + * Fujitsu MB9Ax family support + * EFM32 Wonder Gecko family support + * Nordic nRF51 support + +Board, Target, and Interface Configuration Scripts: + * STM32W108xx generic target config + * STM32F429 discovery board config + * STM32 Nucleo boards configs + * DENX M53EVK board config + * Altera Cyclone V SoC, SoCkit config + * New TI Launchpads board configs + * TI am43xx devices, AM437x GP EVM, AM438x ePOS EVM board + configs + * Marvell Armada 370 family initial support + * TI TMDX570LS31USB (TMS570, Cortex-R4) support scripts + * Freescale FRDM-KL25Z, KL46Z board configs + * Digilent Zedboard config + * Asus RT-N16, Linksys WRT54GL, BT HomeHub board configs + * Atmel Xplained initial support + * Broadcom bcm28155_ap board config + * TUMPA, TUMPA Lite interface configs + * Digilent JTAG-SMT2 interface config + * New RAM testing functions + * Easy-to-use firmware recovery helpers targetting ordinary + users with common equipment + +Server Layer: + * Auto-generation of GDB target description for ARMv7-M, + ARM4, nds32, OR1K, Quark + * GDB File-I/O Remote Protocol extension support + * Default GDB flashing events handlers to initialise and reset + the target automatically when "load" is used + +Documentation: + * Extensive README* changes + * The official User's Guide was proofread + * Example cross-build script + * RTOS documentation improvements + * Tcl RPC documentation and examples added + +Build and Release: + * *BSD, OS X, clang, ARM, windows build fixes + * New pkg-config support changes the way libusb (and other + dependencies) are handled. Many adapter drivers are now + selected automatically during the configure stage. + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.8.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.9.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.9.0 new file mode 100644 index 0000000..77ae4b0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.9.0 @@ -0,0 +1,110 @@ +This file includes highlights of the changes made in the OpenOCD +source archive release. + +JTAG Layer: + * SWD support with FTDI, Versaloon, J-Link, sysfsgpio + * CMSIS-DAP massive speed and stability improvements + * Versaloon driver ported to libusb-1.0 + * STLink can reestablish communication with a target that was + disconnected or rebooted + * STLink FAULT and WAIT SWD handling improved + * New hla_serial command to distinguish between several HLA + adapters attached to a single machine + * Serial number support for CMSIS-DAP and J-Link adapters + * Support for more J-Link adapters + * TAP autoprobing improvements + * Big speedup for SVF playback with USB Blaster + +Boundary Scan: + +Target Layer: + * Stability improvements for targets that get disconnected or + rebooted during a debug session + * MIPS speed and reliability improvements + * MIPS 1.5/2.0 fixes + * ARMv7-R improvements + * Cortex-A improvements, A7, A15 MPCores support + * FPU support for ARMv7-M (Cortex-M4F) + * TPIU/ITM support (including SWO/SWV tracing), can be + captured with external tools or STLink + * JTAG Serial Port (Advanced Debug System softcore) support + * Profiling support for OpenRISC + * ChibiOS/RT 3.0 support (with and without FPU) + * FreeRTOS current versions support + * Freescale MQX RTOS support + * GDB target description support for MIPS + * The last created target is auto-selected as the current + +Flash Layer: + * nRF51 async loader to improve flashing performance and stability + * Cypress PSoC 41xx/42xx and CCG1 families flash driver + * Silabs SiM3 family flash driver + * Marvell Wireless Microcontroller SPI flash driver + * Kinetis mass erase (part unsecuring) implemented + * lpcspifi stability fixes + * STM32 family sync with reference manuals, L0 support, bugfixes + * LPC2000 driver automatically determines part and flash size + * NXP LPC11(x)xx, LPC13xx, LPC15xx, LPC8xx, LPC5410x, LPC407x support + * Atmel SAMD, SAMR, SAML21 devices support + * Atmel SAM4E16 support + * ZeroGecko family support + * TI Tiva C Blizzard and Snowflake families support + * Nuvoton NuMicro M051 support + * EZR32 support in EFM32 driver + +Board, Target, and Interface Configuration Scripts: + * Normal target configs can work with HLA (STLink, ICDI) adapters + * STM32 discovery and Nucleo boards configs + * Gumstix AeroCore board config + * General Plus GP326XXXA target config + * Micrel KS869x target config + * ASUS RT-N66U board config + * Atmel SAM4E-EK board config + * Atmel AT91SAM4L proper reset handling implemented + * TI OMAP/AM 3505, 3517 target configs + * nRF51822-mKIT board config + * RC Module К1879ХБ1Я target config + * TI TMDX570LS20SUSB board config + * TI TMS570 USB Kit board config + * TI CC2538, CC26xx target configs + * TI AM437x major config improvements, DDR support + * TI AM437X IDK board config + * TI SimpleLink Wi-Fi CC3200 LaunchPad configs + * Silicon Labs EM357, EM358 target configs + * Infineon XMC1000, XMC4000 family targets and boards configs + * Atheros AR9331 target config + * TP-LINK TL-MR3020 board config + * Alphascale asm9260t target and eval kit configs + * Olimex SAM7-LA2 (AT91SAM7A2) board config + * EFM32 Gecko boards configs + * Spansion FM4 target and SK-FM4-176L-S6E2CC board configs + * LPC1xxx target configs were restructured + * IoT-LAB debug adapter config + * DP BusBlaster KT-Link compatible config + +Server Layer: + * Polling period can be configured + * "shutdown" command has an immediate effect + * The "program" command doesn't lead to a shutdown by + default, use optional "exit" parameter for the old behaviour + * Proper OS signal handling was implemented + * Async target notifications for the Tcl RPC + +Documentation: + +Build and Release: + + +This release also contains a number of other important functional and +cosmetic bugfixes. For more details about what has changed since the +last release, see the git repository history: + +http://sourceforge.net/p/openocd/code/ci/v0.9.0/log/?path= + + +For older NEWS, see the NEWS files associated with each release +(i.e. NEWS-). + +For more information about contributing test reports, bug fixes, or new +features and device support, please read the new Developer Manual (or +the BUGS and PATCHES.txt files in the source archive). diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README new file mode 100644 index 0000000..7d3f10d --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README @@ -0,0 +1,356 @@ +Welcome to OpenOCD! +=================== + +OpenOCD provides on-chip programming and debugging support with a +layered architecture of JTAG interface and TAP support including: + +- (X)SVF playback to facilitate automated boundary scan and FPGA/CPLD + programming; +- debug target support (e.g. ARM, MIPS): single-stepping, + breakpoints/watchpoints, gprof profiling, etc; +- flash chip drivers (e.g. CFI, NAND, internal flash); +- embedded TCL interpreter for easy scripting. + +Several network interfaces are available for interacting with OpenOCD: +telnet, TCL, and GDB. The GDB server enables OpenOCD to function as a +"remote target" for source-level debugging of embedded systems using +the GNU GDB program (and the others who talk GDB protocol, e.g. IDA +Pro). + +This README file contains an overview of the following topics: + +- quickstart instructions, +- how to find and build more OpenOCD documentation, +- list of the supported hardware, +- the installation and build process, +- packaging tips. + + +============================ +Quickstart for the impatient +============================ + +If you have a popular board then just start OpenOCD with its config, +e.g.: + + openocd -f board/stm32f4discovery.cfg + +If you are connecting a particular adapter with some specific target, +you need to source both the jtag interface and the target configs, +e.g.: + + openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \ + -f target/ti_calypso.cfg + + openocd -f interface/stlink.cfg -c "transport select hla_swd" \ + -f target/stm32l0.cfg + +After OpenOCD startup, connect GDB with + + (gdb) target extended-remote localhost:3333 + + +===================== +OpenOCD Documentation +===================== + +In addition to the in-tree documentation, the latest manuals may be +viewed online at the following URLs: + + OpenOCD User's Guide: + http://openocd.org/doc/html/index.html + + OpenOCD Developer's Manual: + http://openocd.org/doc/doxygen/html/index.html + +These reflect the latest development versions, so the following section +introduces how to build the complete documentation from the package. + +For more information, refer to these documents or contact the developers +by subscribing to the OpenOCD developer mailing list: + + openocd-devel@lists.sourceforge.net + +Building the OpenOCD Documentation +---------------------------------- + +By default the OpenOCD build process prepares documentation in the +"Info format" and installs it the standard way, so that "info openocd" +can access it. + +Additionally, the OpenOCD User's Guide can be produced in the +following different formats: + + # If PDFVIEWER is set, this creates and views the PDF User Guide. + make pdf && ${PDFVIEWER} doc/openocd.pdf + + # If HTMLVIEWER is set, this creates and views the HTML User Guide. + make html && ${HTMLVIEWER} doc/openocd.html/index.html + +The OpenOCD Developer Manual contains information about the internal +architecture and other details about the code: + + # NB! make sure doxygen is installed, type doxygen --version + make doxygen && ${HTMLVIEWER} doxygen/index.html + + +================== +Supported hardware +================== + +JTAG adapters +------------- + +AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835, +Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP, +Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H, +embedded projects, Espressif USB JTAG Programmer, +eStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2, +FTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey, +JTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick, +Mellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO, +OOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee, +Remote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits, +ST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick, +sysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster, +USB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe, +Xverve. + +Debug targets +------------- + +ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M), +FA526, Feroceon/Dragonite, XScale. +ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64), +ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8, +Xtensa. + +Flash drivers +------------- + +ADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI, +DSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI, +GD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx, +LPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro, +NUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6, +Raspberry RP2040, Renesas RPC HF and SH QSPI, +S3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32, +STM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050, +TI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF, +XMC1xxx, XMC4xxx. + + +================== +Installing OpenOCD +================== + +A Note to OpenOCD Users +----------------------- + +If you would rather be working "with" OpenOCD rather than "on" it, your +operating system or JTAG interface supplier may provide binaries for +you in a convenient-enough package. + +Such packages may be more stable than git mainline, where +bleeding-edge development takes place. These "Packagers" produce +binary releases of OpenOCD after the developers produces new "release" +versions of the source code. Previous versions of OpenOCD cannot be +used to diagnose problems with the current release, so users are +encouraged to keep in contact with their distribution package +maintainers or interface vendors to ensure suitable upgrades appear +regularly. + +Users of these binary versions of OpenOCD must contact their Packager to +ask for support or newer versions of the binaries; the OpenOCD +developers do not support packages directly. + +A Note to OpenOCD Packagers +--------------------------- + +You are a PACKAGER of OpenOCD if you: + +- Sell dongles and include pre-built binaries; +- Supply tools or IDEs (a development solution integrating OpenOCD); +- Build packages (e.g. RPM or DEB files for a GNU/Linux distribution). + +As a PACKAGER, you will experience first reports of most issues. +When you fix those problems for your users, your solution may help +prevent hundreds (if not thousands) of other questions from other users. + +If something does not work for you, please work to inform the OpenOCD +developers know how to improve the system or documentation to avoid +future problems, and follow-up to help us ensure the issue will be fully +resolved in our future releases. + +That said, the OpenOCD developers would also like you to follow a few +suggestions: + +- Send patches, including config files, upstream, participate in the + discussions; +- Enable all the options OpenOCD supports, even those unrelated to your + particular hardware; +- Use "ftdi" interface adapter driver for the FTDI-based devices. + + +================ +Building OpenOCD +================ + +The INSTALL file contains generic instructions for running 'configure' +and compiling the OpenOCD source code. That file is provided by +default for all GNU autotools packages. If you are not familiar with +the GNU autotools, then you should read those instructions first. + +The remainder of this document tries to provide some instructions for +those looking for a quick-install. + +OpenOCD Dependencies +-------------------- + +GCC or Clang is currently required to build OpenOCD. The developers +have begun to enforce strict code warnings (-Wall, -Werror, -Wextra, +and more) and use C99-specific features: inline functions, named +initializers, mixing declarations with code, and other tricks. While +it may be possible to use other compilers, they must be somewhat +modern and could require extending support to conditionally remove +GCC-specific extensions. + +You'll also need: + +- make +- libtool +- pkg-config >= 0.23 or pkgconf + +OpenOCD uses jimtcl library; build from git can retrieve jimtcl as git +submodule. + +Additionally, for building from git: + +- autoconf >= 2.69 +- automake >= 1.14 +- texinfo >= 5.0 + +Optional USB-based adapter drivers need libusb-1.0. + +Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter +drivers need: + - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php + +Optional CMSIS-DAP adapter driver needs HIDAPI library. + +Optional linuxgpiod adapter driver needs libgpiod library. + +Optional J-Link adapter driver needs libjaylink library. + +Optional ARM disassembly needs capstone library. + +Optional development script checkpatch needs: + +- perl +- python +- python-ply + +Permissions delegation +---------------------- + +Running OpenOCD with root/administrative permissions is strongly +discouraged for security reasons. + +For USB devices on GNU/Linux you should use the contrib/60-openocd.rules +file. It probably belongs somewhere in /etc/udev/rules.d, but +consult your operating system documentation to be sure. Do not forget +to add yourself to the "plugdev" group. + +For parallel port adapters on GNU/Linux and FreeBSD please change your +"ppdev" (parport* or ppi*) device node permissions accordingly. + +For parport adapters on Windows you need to run install_giveio.bat +(it's also possible to use "ioperm" with Cygwin instead) to give +ordinary users permissions for accessing the "LPT" registers directly. + +Compiling OpenOCD +----------------- + +To build OpenOCD, use the following sequence of commands: + + ./bootstrap (when building from the git repository) + ./configure [options] + make + sudo make install + +The 'configure' step generates the Makefiles required to build +OpenOCD, usually with one or more options provided to it. The first +'make' step will build OpenOCD and place the final executable in +'./src/'. The final (optional) step, ``make install'', places all of +the files in the required location. + +To see the list of all the supported options, run + ./configure --help + +Cross-compiling Options +----------------------- + +Cross-compiling is supported the standard autotools way, you just need +to specify the cross-compiling target triplet in the --host option, +e.g. for cross-building for Windows 32-bit with MinGW on Debian: + + ./configure --host=i686-w64-mingw32 [options] + +To make pkg-config work nicely for cross-compiling, you might need an +additional wrapper script as described at + + https://autotools.io/pkgconfig/cross-compiling.html + +This is needed to tell pkg-config where to look for the target +libraries that OpenOCD depends on. Alternatively, you can specify +*_CFLAGS and *_LIBS environment variables directly, see "./configure +--help" for the details. + +For a more or less complete script that does all this for you, see + + contrib/cross-build.sh + +Parallel Port Dongles +--------------------- + +If you want to access the parallel port using the PPDEV interface you +have to specify both --enable-parport AND --enable-parport-ppdev, since +the later option is an option to the parport driver. + +The same is true for the --enable-parport-giveio option, you have to +use both the --enable-parport AND the --enable-parport-giveio option +if you want to use giveio instead of ioperm parallel port access +method. + + +========================== +Obtaining OpenOCD From GIT +========================== + +You can download the current GIT version with a GIT client of your +choice from the main repository: + + git://git.code.sf.net/p/openocd/code + +You may prefer to use a mirror: + + http://repo.or.cz/r/openocd.git + git://repo.or.cz/openocd.git + +Using the GIT command line client, you might use the following command +to set up a local copy of the current repository (make sure there is no +directory called "openocd" in the current directory): + + git clone git://git.code.sf.net/p/openocd/code openocd + +Then you can update that at your convenience using + + git pull + +There is also a gitweb interface, which you can use either to browse +the repository or to download arbitrary snapshots using HTTP: + + http://repo.or.cz/w/openocd.git + +Snapshots are compressed tarballs of the source tree, about 1.3 MBytes +each at this writing. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.Windows b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.Windows new file mode 100644 index 0000000..64bf5c0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.Windows @@ -0,0 +1,56 @@ +Building OpenOCD for Windows +---------------------------- + +You can build OpenOCD for Windows natively with either MinGW-w64/MSYS +or Cygwin (plain MinGW might work with --disable-werror but is not +recommended as it doesn't provide enough C99 compatibility). +Alternatively, one can cross-compile it using MinGW-w64 on a *nix +host. See README for the generic instructions. + +Also, the MSYS2 project provides both ready-made binaries and an easy +way to self-compile from their software repository out of the box. + +Native MinGW-w64/MSYS compilation +----------------------------- + +As MSYS doesn't come with pkg-config pre-installed, you need to add it +manually. The easiest way to do that is to download pkg-config-lite +from: + + http://sourceforge.net/projects/pkgconfiglite/ + +Then simply unzip the archive to the root directory of your MinGW-w64 +installation. + +USB adapters +------------ + +For the adapters that use a HID-based protocol, e.g. CMSIS-DAP, you do +not need to perform any additional configuration. + +For all the others you usually need to have WinUSB.sys (or +libusbK.sys) driver installed. Some vendor software (e.g. for +ST-LINKv2) does it on its own. For the other cases the easiest way to +assign WinUSB to a device is to use the latest Zadig installer: + + http://zadig.akeo.ie + +When using a composite USB device, it's often necessary to assign +WinUSB.sys to the composite parent instead of the specific +interface. To do that one needs to activate an advanced option in the +Zadig installer. + +If you need to use the same adapter with other applications that may +require another driver, a solution for Windows Vista and above is to +activate the IgnoreHWSerNum registry setting for the USB device. + +That setting forces Windows to associate the driver per port instead of +per serial number, the same behaviour as when the device does not contain +a serial number. So different drivers can be installed for the adapter on +different ports and you just need to plug the adapter into the correct +port depending on which application to use. + +For more information, see: + + https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-device-specific-registry-settings + http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.macOS b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.macOS new file mode 100644 index 0000000..91d5e92 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.macOS @@ -0,0 +1,54 @@ +Building OpenOCD for macOS +-------------------------- + +There are a few prerequisites you will need first: + +- Xcode (install from the AppStore) +- Command Line Tools (install from Xcode -> Preferences -> Downloads) +- Gentoo Prefix (http://www.gentoo.org/proj/en/gentoo-alt/prefix/bootstrap.xml) + or +- Homebrew (http://mxcl.github.io/homebrew/) + or +- MacPorts (http://www.macports.org/install.php) + + +If you're building manually you need Texinfo version 5.0 or later. The +simplest way to get it is to use Homebrew (brew install texinfo) and +then ``export PATH=/usr/local/opt/texinfo/bin:$PATH``. + + +With Gentoo Prefix you can build the release version or the latest +devel version (-9999) the usual way described in the Gentoo +documentation. Alternatively, install the prerequisites and build +manually from the sources. + + +With Homebrew you can either run: + brew install [--HEAD] openocd (where optional --HEAD asks brew to + install the current git version) + or + brew install libtool automake libusb [hidapi] [libftdi] + (to install the needed dependencies and then proceed with the + manual building procedure) + + +For building with MacPorts you need to run: + sudo port install libtool automake autoconf pkgconfig \ + libusb [libftdi1] + +You should also specify LDFLAGS and CPPFLAGS to allow configure to use +MacPorts' libraries, so run configure like this: + LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options] + + +See README for the generic building instructions. + +If you're using a USB adapter and have a driver kext matched to it, +you will need to unload it prior to running OpenOCD. E.g. with Apple +driver (OS X 10.9 or later) for FTDI run: + sudo kextunload -b com.apple.driver.AppleUSBFTDI +for FTDI vendor driver use: + sudo kextunload FTDIUSBSerialDriver.kext + +To learn more on the topic please refer to the official libusb FAQ: +https://github.com/libusb/libusb/wiki/FAQ diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/exceptions/eCos-exception-2.0 b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/exceptions/eCos-exception-2.0 new file mode 100644 index 0000000..d21109f --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/exceptions/eCos-exception-2.0 @@ -0,0 +1,20 @@ +SPDX-Exception-Identifier: eCos-exception-2.0 +SPDX-URL: https://spdx.org/licenses/eCos-exception-2.0.html +SPDX-Licenses: GPL-2.0-only, GPL-2.0-or-later +Usage-Guide: + This exception is used together with one of the above SPDX-Licenses. + To use this exception add it with the keyword WITH to one of the + identifiers in the SPDX-Licenses tag: + SPDX-License-Identifier: WITH eCos-exception-2.0 +License-Text: + +As a special exception, if other files instantiate templates or use +macros or inline functions from this file, or you compile this +file and link it with other works to produce a work based on this +file, this file does not by itself cause the resulting work to be +covered by the GNU General Public License. However the source code for +this file must still be made available in accordance with section (3) +of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/license-rules.txt b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/license-rules.txt new file mode 100644 index 0000000..c751929 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/license-rules.txt @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later + +OpenOCD licensing rules +======================= + +The OpenOCD source code is provided under the terms of the GNU General +Public License version 2 or later (GPL-2.0-or-later), as provided in +LICENSES/preferred/GPL-2.0. + +The OpenOCD documentation is provided under the terms of the GNU Free +Documentation License version 1.2 or later without Invariant Sections +(GFDL-1.2-no-invariants-or-later). + +Few stand-alone applications coexist in the same code tree of OpenOCD +and are provided under the terms of the GNU General Public License +version 3 (GPL-3.0), as provided in LICENSES/stand-alone/GPL-3.0. + +This documentation file provides a description of how each source file +should be annotated to make its license clear and unambiguous. +It doesn't replace the OpenOCD's license. + +The license described in the COPYING file applies to the OpenOCD source +as a whole, though individual source files can have a different license +which is required to be compatible with the GPL-2.0: + + GPL-1.0-or-later : GNU General Public License v1.0 or later + GPL-2.0-or-later : GNU General Public License v2.0 or later + LGPL-2.0 : GNU Library General Public License v2 only + LGPL-2.0-or-later : GNU Library General Public License v2 or later + LGPL-2.1 : GNU Lesser General Public License v2.1 only + LGPL-2.1-or-later : GNU Lesser General Public License v2.1 or later + +Aside from that, individual files can be provided under a dual license, +e.g. one of the compatible GPL variants and alternatively under a +permissive license like BSD, MIT etc. + +The common way of expressing the license of a source file is to add the +matching boilerplate text into the top comment of the file. Due to +formatting, typos etc. these "boilerplates" are hard to validate for +tools which are used in the context of license compliance. + +An alternative to boilerplate text is the use of Software Package Data +Exchange (SPDX) license identifiers in each source file. SPDX license +identifiers are machine parsable and precise shorthands for the license +under which the content of the file is contributed. SPDX license +identifiers are managed by the SPDX Workgroup at the Linux Foundation and +have been agreed on by partners throughout the industry, tool vendors, and +legal teams. For further information see https://spdx.org/ + +OpenOCD requires the precise SPDX identifier in all source files. +The valid identifiers used in OpenOCD are explained in the section +`License identifiers` and have been retrieved from the official SPDX +license list at https://spdx.org/licenses/ along with the license texts. + +License identifier syntax +------------------------- + +1. Placement: + + The SPDX license identifier in OpenOCD files shall be added at the + first possible line in a file which can contain a comment. For the + majority of files this is the first line, except for scripts which + require the '#!PATH_TO_INTERPRETER' in the first line. For those + scripts the SPDX identifier goes into the second line. + +2. Style: + + The SPDX license identifier is added in form of a comment. The comment + style depends on the file type:: + + C source: // SPDX-License-Identifier: + C header: /* SPDX-License-Identifier: */ + ASM: /* SPDX-License-Identifier: */ + makefiles: # SPDX-License-Identifier: + scripts: # SPDX-License-Identifier: + texinfo: @c SPDX-License-Identifier: + text: # SPDX-License-Identifier: + + If a specific tool cannot handle the standard comment style, then the + appropriate comment mechanism which the tool accepts shall be used. This + is the reason for having the "/\* \*/" style comment in C header + files. There was build breakage observed with generated .lds files where + 'ld' failed to parse the C++ comment. This has been fixed by now, but + there are still older assembler tools which cannot handle C++ style + comments. + +3. Syntax: + + A is either an SPDX short form license + identifier found on the SPDX License List, or the combination of two + SPDX short form license identifiers separated by "WITH" when a license + exception applies. When multiple licenses apply, an expression consists + of keywords "AND", "OR" separating sub-expressions and surrounded by + "(", ")" . + + License identifiers for licenses like [L]GPL with the 'or later' option + are constructed by using a "-or-later": + + // SPDX-License-Identifier: GPL-2.0-or-later + // SPDX-License-Identifier: LGPL-2.1-or-later + + WITH should be used when there is a modifier to a license needed. + Exceptions can only be used with particular License identifiers. The + valid License identifiers are listed in the tags of the exception text + file. + + OR should be used if the file is dual licensed and only one license is + to be selected. For example, some source files are available under dual + licenses: + + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-1-Clause + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + + AND should be used if the file has multiple licenses whose terms all + apply to use the file. For example, if code is inherited from another + project and permission has been given to put it in OpenOCD, but the + original license terms need to remain in effect:: + + // SPDX-License-Identifier: GPL-2.0-or-later AND MIT + +License identifiers +------------------- + +The licenses currently used, as well as the licenses for code added to +OpenOCD, can be broken down into: + +1. `Preferred licenses`: + + Whenever possible these licenses should be used as they are known to be + fully compatible and widely used. These licenses are available from the + directory: + + LICENSES/preferred/ + + in the OpenOCD source tree. + + The files in this directory contain the full license text and + `Metatags`. The file names are identical to the SPDX license + identifier which shall be used for the license in source files. + + Examples: + + LICENSES/preferred/GPL-2.0 + + Contains the GPL version 2 license text and the required metatags. + + `Metatags`: + + The following meta tags must be available in a license file: + + - Valid-License-Identifier: + + One or more lines which declare which License Identifiers are valid + inside the project to reference this particular license text. Usually + this is a single valid identifier, but e.g. for licenses with the 'or + later' options two identifiers are valid. + + - SPDX-URL: + + The URL of the SPDX page which contains additional information related + to the license. + + - Usage-Guidance: + + Freeform text for usage advice. The text must include correct examples + for the SPDX license identifiers as they should be put into source + files according to the `License identifier syntax` guidelines. + + - License-Text: + + All text after this tag is treated as the original license text + + File format examples:: + + Valid-License-Identifier: GPL-2.0 + Valid-License-Identifier: GPL-2.0-only + Valid-License-Identifier: GPL-2.0-or-later + SPDX-URL: https://spdx.org/licenses/GPL-2.0.html + Usage-Guide: + To use this license in source code, put one of the following SPDX + tag/value pairs into a comment according to the placement + guidelines in the licensing rules documentation. + For 'GNU General Public License (GPL) version 2 only' use: + SPDX-License-Identifier: GPL-2.0 + or + SPDX-License-Identifier: GPL-2.0-only + For 'GNU General Public License (GPL) version 2 or any later version' use: + SPDX-License-Identifier: GPL-2.0-or-later + License-Text: + Full license text + +2. Exceptions: + + Some licenses can be amended with exceptions which grant certain rights + which the original license does not. These exceptions are available + from the directory:: + + LICENSES/exceptions/ + + in the OpenOCD source tree. The files in this directory contain the full + exception text and the required `Exception Metatags`_. + + Examples:: + + LICENSES/exceptions/eCos-exception-2.0 + + Exception Metatags: + + The following meta tags must be available in an exception file: + + - SPDX-Exception-Identifier: + + One exception identifier which can be used with SPDX license + identifiers. + + - SPDX-URL: + + The URL of the SPDX page which contains additional information related + to the exception. + + - SPDX-Licenses: + + A comma separated list of SPDX license identifiers for which the + exception can be used. + + - Usage-Guidance: + + Freeform text for usage advice. The text must be followed by correct + examples for the SPDX license identifiers as they should be put into + source files according to the `License identifier syntax`_ guidelines. + + - Exception-Text: + + All text after this tag is treated as the original exception text + + File format examples:: + + SPDX-Exception-Identifier: eCos-exception-2.0 + SPDX-URL: https://spdx.org/licenses/eCos-exception-2.0.html + SPDX-Licenses: GPL-2.0-only, GPL-2.0-or-later + Usage-Guide: + This exception is used together with one of the above SPDX-Licenses. + To use this exception add it with the keyword WITH to one of the + identifiers in the SPDX-Licenses tag: + SPDX-License-Identifier: WITH eCos-exception-2.0 + License-Text: + Full license text + +3. Stand-alone licenses: + + These licenses should only be used for stand-alone applications that are + distributed with OpenOCD but are not included in the OpenOCD binary. + These licenses are available from the directory: + + LICENSES/stand-alone/ + + in the OpenOCD source tree. + + Examples: + + SPDX-License-Identifier: GPL-3.0 + +The format and requirements of the license files in the other sub-directories +of directory + + LICENSES + +have to follow the same format and requirements of the `Preferred licenses`. + +All SPDX license identifiers and exceptions must have a corresponding file +in the LICENSES subdirectories. This is required to allow tool +verification (e.g. checkpatch.pl) and to have the licenses ready to read +and extract right from the source, which is recommended by various FOSS +organizations, e.g. the `FSFE REUSE initiative `. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-1-Clause b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-1-Clause new file mode 100644 index 0000000..c63b05b --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-1-Clause @@ -0,0 +1,28 @@ +Valid-License-Identifier: BSD-1-Clause +SPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html +Usage-Guide: + To use the BSD 1-clause License put the following SPDX + tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: BSD-1-Clause +License-Text: + +Copyright (c) . All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause new file mode 100644 index 0000000..da366e2 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause @@ -0,0 +1,32 @@ +Valid-License-Identifier: BSD-2-Clause +SPDX-URL: https://spdx.org/licenses/BSD-2-Clause.html +Usage-Guide: + To use the BSD 2-clause "Simplified" License put the following SPDX + tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: BSD-2-Clause +License-Text: + +Copyright (c) . All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause-Views b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause-Views new file mode 100644 index 0000000..abfb0ff --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause-Views @@ -0,0 +1,37 @@ +Valid-License-Identifier: BSD-2-Clause-Views +SPDX-URL: https://spdx.org/licenses/BSD-2-Clause-Views.html +Usage-Guide: + To use the BSD 2-clause with views sentence License put the following SPDX + tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: BSD-2-Clause-Views +License-Text: + +Copyright (c) . All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation +are those of the authors and should not be interpreted as representing +official policies, either expressed or implied, of the copyright holders +or contributors. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-3-Clause b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-3-Clause new file mode 100644 index 0000000..34c7f05 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-3-Clause @@ -0,0 +1,36 @@ +Valid-License-Identifier: BSD-3-Clause +SPDX-URL: https://spdx.org/licenses/BSD-3-Clause.html +Usage-Guide: + To use the BSD 3-clause "New" or "Revised" License put the following SPDX + tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: BSD-3-Clause +License-Text: + +Copyright (c) . All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-Source-Code b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-Source-Code new file mode 100644 index 0000000..622cd3a --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-Source-Code @@ -0,0 +1,32 @@ +Valid-License-Identifier: BSD-Source-Code +SPDX-URL: https://spdx.org/licenses/BSD-Source-Code.html +Usage-Guide: + To use the BSD Source Code Attribution License put the following SPDX + tag/value pair into a comment according to the placement guidelines in + the licensing rules documentation: + SPDX-License-Identifier: BSD-Source-Code +License-Text: + +Copyright (c) . All rights reserved. + +Redistribution and use of this software in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. 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AGGREGATION WITH INDEPENDENT WORKS + +A compilation of the Document or its derivatives with other separate +and independent documents or works, in or on a volume of a storage or +distribution medium, is called an "aggregate" if the copyright +resulting from the compilation is not used to limit the legal rights +of the compilation's users beyond what the individual works permit. +When the Document is included in an aggregate, this License does not +apply to the other works in the aggregate which are not themselves +derivative works of the Document. + +If the Cover Text requirement of section 3 is applicable to these +copies of the Document, then if the Document is less than one half of +the entire aggregate, the Document's Cover Texts may be placed on +covers that bracket the Document within the aggregate, or the +electronic equivalent of covers if the Document is in electronic form. +Otherwise they must appear on printed covers that bracket the whole +aggregate. + + +8. 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By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. 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And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. 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Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. 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Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. 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But first, please read +. diff --git a/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/AUTHORS b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/AUTHORS new file mode 100644 index 0000000..1e88ca0 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/AUTHORS @@ -0,0 +1,11 @@ +Original authors +---------------- +James Henstridge original pkg-config +Tim Janik the PKG_CHECK_VERSION macro +Havoc Pennington rewrite in C +Scott James Remnant m4 cleanups and maintainer + for a while + +Maintainer +---------- +Tollef Fog Heen diff --git a/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/COPYING b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/COPYING new file mode 100644 index 0000000..d159169 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. 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But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. 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For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. 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The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/NEWS b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/NEWS new file mode 100644 index 0000000..7f64855 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/NEWS @@ -0,0 +1,307 @@ +pkg-config 0.29.2 +================= + +- Improved pkg-config's recursive package list expansion performance. + Thanks to Matthew Hanna for the fix. +- Handle an empty prefix setting correctly when --define-prefix is used. + (#97453) +- Lazily load pc files instead of reading all available pc files during + initialization. Thanks to Marco Diego Aurélio Mesquita for the fix. + (#98215) +- Check the CPATH environment variable when determining system include + paths like GCC does. Document the system search path behavior. Thanks + to v4hn for the fix. (#99224) +- Make PKG_CHECK_MODULES show the module list rather than the variable + prefix in configure output. Thanks to Russ Albery for the fix. + (#98334) +- Fix bundled glib build with GCC 6. (#98334) +- Handle -isystem and -idirafter when PKG_CONFIG_SYSROOT_DIR is set. + (#97337) +- Check the INCLUDE environment variable when determining system include + paths on Windows builds when --msvc-syntax is used. (#94729) + +pkg-config 0.29.1 +================= + +- Fixed a regression from 0.29 with unquoting values queried with + --variable. In some cases, this would cause shell special characters to + be escaped in ways they weren't before. Instead, the unquoting only + occurs if the value appears to be quoted. (#93284) +- Add support for building pkg-config with Microsoft Visual Studio. + Thanks to Chun-wei Fan for the fix. (#92489) +- Allow overriding pkg-config variables with environment variables. By + setting an environment variable of the form + PKG_CONFIG_$PACKAGE_$VARIABLE, a pkg-config variable can be set + globally without always having to pass --define-variable. Thanks to + Alex Larsson for the fix. (#90917) +- Honor -Wl,-framework in addition to -framework so that multiple + frameworks are handled on OSX. (#1278) +- Fix the OSX build using --with-internal-glib. Thanks to Rudá Moura for + the initial fix and Adam Mercer for testing the final patch. (#92902) + +pkg-config 0.29 +=== + +- Fixed a regression from 0.28 in system -L flag handling. If the pc + file has multiple system -L flags, every other flag will be left as + is. Thanks to Andrew Oakley for the fix. (#78077) +- Quoting of variables queried through --variable is removed so that the + output can be used verbatim in subsequent shell commands. Thanks to + Marek Kasik for the fix. (#67904) +- Fixed a regression from 0.28 in -L flag handling on Windows. A .libs + suffix was inadvertantly being added to the library path. +- Added a --validate option to check pc file syntax. This works just + like --exists, but package dependencies are disabled. (#7000) +- Added the PKG_PREREQ autoconf macro. Whereas PKG_PROG_PKG_CONFIG is + used to check the version of the pkg-config tool, this is used to + check the version of the pkg-config autoconf macros in use. +- Added the PKG_CHECK_MODULES_STATIC autoconf macro. This will + temporarily add --static to the pkg-config calls while invoking + PKG_CHECK_MODULES. (#19541) +- Many fixes to the testsuite for Windows. It should now pass for a + MinGW, Cygwin, and cross-compiled MinGW using Wine for test execution. + (#66939) +- More consistent handling of prefix redefinition. On Windows, the + prefix was always being redefined based on the pc file path. This + feature can now be enabled or disabled at runtime on all platforms + using the --define-prefix and --dont-define-prefix options. (#63602) +- Continue listing packages with --list-all even if there are errors in + pc files. (#26615) +- Various documentation improvements. (#62018, #62374, #66155) +- Fixed a bug when multiple -isystem arguments are used. (#72584) +- pkg-config is now built with largefile support to ensure that it works + correctly on filesystems with 64 bit inodes. Thanks to Peter Jones for + the fix. (#90078) +- Bugs fixed: 7000, 19541, 26615, 62018, 62374, 63602, 66155, 66939, + 67904, 70690, 72584, 78077, 80378, 80380, 89267, 90078, 90437, 92002. + +pkg-config 0.28 +=== +- Fixed a pair of long-standing and intertwined bugs involving unwanted + removal of flags. The first is that other Libs flags like -Wl are now + kept in context order with -l flags. The second is that aggressive + removal of all duplicate arguments has been scaled back so that just + consecutive duplicate arguments are removed. One result of this change + is that some flags could be repeated in the final output, especially + flags from non-pkg-config packages like -lm. Since pkg-config rarely + has enough knowledge here about the right thing to do, we throw the + duplicate arguments at the compiler/linker and trust it will do the + right thing. +- Fixed an old bug to allow circular Requires. This fix brings along a + small behavior change in that pkg-config resolves requires depth + first, causing some lower level flags to show up earlier in the output + than previously. +- Cleaned up many corner-case bugs and ambiguous behavior in + pkg-config's interface. Thanks to Michał Górny for finding so many of + these. +- New autoconf macro PKG_CHECK_VAR for reading variables from .pc files. +- Default to suppressing -L/lib and/or -L/lib64 like their /usr + counterparts. +- To help support multiarch scenarios out of the box, $host-pkg-config + is now installed unless --disable-host-tool is passed to configure. +- Added optional gcov usage through the --with-gcov configure option. As + a result, many more tests were added to greatly increase the coverage + of the code to 86% of executed lines on a Fedora 18 machine. +- Bugs fixed: 130, 7331, 16101, 17053, 19950, 34504, 48098, 54231, + 54271, 54379, 54384, 54386, 54388, 54389, 54390, 54391, 54427, 54463, + 54716, 57078, 58363, 59435. + +pkg-config 0.27.1 +=== + + - Various fixes for using the internal glib snapshot. It should now be + usable pretty much everywhere with the exception that universal + builds are not supported on OS X. + - Remove usage of gettext from the internal glib to avoid gettext and + libintl dependencies. + - Update internal glib snapshot to 2.32.4. + - Fix check for POSIX shell used in tests to work better. + - Handle spaces in autodetected prefix on Windows. + - Bugs fixed 3550, 51883, 52031, 53493. + +pkg-config 0.27 +=== + + - Drop usage of popt for equivalent API in glib2. + - Add back an internal snapshot of glib2 to break circular dependency. + This can be used by passing --with-internal-glib to configure. On + Windows it may still be required to use an installed glib. + - Fix --exists to check for Requires and Requires.private. This ensures + that all necessary packages are installed prior to using --cflags, + --libs, etc. + - Various fixes for MinGW which should allow it to be used unpatched on + that system. + - New autoconf macros PKG_INSTALLDIR and PKG_NOARCH_INSTALLDIR to help + determine the .pc file install directory. + - Fix handling of --exact/atleast/max-version vs. =/>=/<=. + - Fix errors in man page source. + - Ensure testing only searches in the check directory. + - Bump glib requirement to 2.16 to avoid deprecated + g_win32_get_package_installation_subdirectory(). + - Autotools refresh and update. The required versions now are + autoconf-2.62, automake-1.11 and libtool-2.2. + - Use g_alloca from glib instead of figuring out alloca ourselves. + - Remove search for setresuid & setreuid only needed for internal popt. + - Bugs fixed: 833, 2458, 5214, 5326, 5703, 6074, 8653, 9135, 9143, + 9584, 10652, 11464, 14396, 17053, 23922, 28776, 29011, 29801, 31699, + 31700, 32622, 34382, 37266, 39646, 41081, 43149, 44843, 45599, 45742, + 48743 + +pkg-config 0.26 +=== + + - Build system fixes + - More tests + - pkg.m4 fixups which makes autoconf 2.66 happier. + - Drop support for legacy -config scripts. Those should already be + gone and cause problems in cross-compilation environments. + - Drop embedded glib + - Fix up pkg.m4 to handle the case of --exists working and --cflags + or --libs failing. + - Various documentation updates + - Allow $() through without escaping it. + - Add --with-system-include-path instead of hard-coding + /usr/include. + +pkg-config 0.25 +=== + + - 0.24 included a too strict whitespace/shell metacharacter filter + leading to some legal characters like = and : being escaped in the + output. This has been fixed. + - when building with newer and external libpopt, it would be confused + over being asked to split an empty string, leading to errors with + packages that included empty fields in their .pc files. + - Make the COPYING file explicitly GPLv2. The COPYING file in 0.24 + was inadvertently GPLv3 rather than the correct GPLv2. + - Minor changes to documentation + +pkg-config 0.24 +=== + - Fix up bug in PKG_CONFIG_SYSROOT handling which mangled non-I and + non-L arguments + - Put /usr/lib/pkgconfig and /usr/share/pkgconfig into the default + search path when no prefix is passed to configure. + - Portability fixes for Windows and NetBSD + - Various man page updates + - Add logging support to log how pkg-config is being called. + - Skip Requires.private unless we need them for Cflags + - Add a variable, pc_path to the compiled-in pkg-config package that + you can query for the compiled-in PKG_CONFIG_PC_PATH. + - Various updates to pkg.m4. + - Update rpmvercmp with bugfixes from upstream. + - Add introductory guide to pkg-config, thanks to Dan Nicholson for + the patch. + - Add listing of variables in a package + - Make it possible to use external popt. + - Add --print-provides and --print-requires(-private) options + - Add support for paths containing whitespace and shell metacharacters + +pkg-config 0.23 +=== + - Add support for setting sysroot through PKG_CONFIG_SYSROOT_DIR in + the environment. + - Update included glib to 1.2.10. + - Other minor fixes, including a segfault. + +pkg-config 0.22 +=== + - Make Requires.private a whole lot more useful by traversing the + whole tree, not just the top-level, for Cflags. + - Add support for using the system glib. + - Update URL to pkg-config website + - Fix some win32 problems. + - Other minor fixes. + +pkg-config 0.21 +=== + - Fix some cosmetic output from pkg.m4 + - Fix build problems with !gcc due to always passing -Wall + - Documentation fixes + - We now always add the Cflags from packages we depend on, whether + they are public or private dependencies. The discussion surrouding + this change can be found in http://bugs.debian.org/340904 . + - Add internal pkg-config package which can be queried for version + number and other information. + +pkg-config 0.20 +=== + - Fix test suite to work on Solaris. Yay non-POSIX /bin/sh :-( + - Fix segfault on --help with gcc4. Fix segfault on bigendian arches + in some cases. + - Win32 fixes + - Add --short-errors, now used by pkg.m4 if available. This gives a + better error message if some libraries can't be found. + +pkg-config 0.19 +=== + - Fix a segfault + - Fix default search path + - Fix cosmetic bug in pkg.m4 where AC_MSG_RESULT wasn't called in + some cases. + +pkg-config 0.18.1 +=== + - Fix up pkg.m4 to not end up with pkg_failed=untried always. + +pkg-config 0.18 +=== + - The inter-library dependencies check was too tight and caused + problems if one used the --no-undefined flag to libtool on Solaris + (since it there expands to -Wl,-z,defs which disallows undefined + symbols). Add a new name to .pc files: Libs.private which will not + be listed in the output of --libs unless --static is also given. + + Private libraries are libraries which are needed in the case of + static linking or on platforms not supporting inter-library + dependencies. They are not supposed to be used for libraries which + are exposed through the library in question. An example of an + exposed library is GTK+ exposing Glib. A common example of a private + library is libm. + + Generally, if include another library's headers in your own, it's a + public dependency and not a private one. + + Thanks a lot to James Henstridge for both the bug and the following + discussion. + +pkg-config 0.17.2 +=== + - Don't go into an infinite loop allocating more and more memory when + the same name is specified twice on the command line and we're in + "direct dependencies only"-mode. + +pkg-config 0.17.1 +=== + - Now actually sets CFLAGS and LIBS instead of trying to set those in + a subshell. (Only affects if you've autoreconfiscated with 0.17) + - Fix detection of inter-library dependencies. + +pkg-config 0.17 +=== + + - Evaluate second argument to PKG_CHECK_MODULES again + - Portability fixes (MacOS, BeOS, Cygwin) + - Handle inter-library dependencies and assume those are in place if + the platform supports them. Disable with --enable-indirect-deps. + - Add initial test framework + - Build fixes (make distcheck now works) + +pkg-config 0.16 +=== + + - Use a search path, rather than a single default directory. + - Fix a bunch of bugs in glib by backporting + - More man page fixes + - Lots of small fixes and cleanups over the place. + - pkg-config now grabs _PKG_* and PKG_*, so don't use variables + starting with that in any configure scripts. + +pkg-config 0.15 +=== + + - add PKG_CONFIG_LIBDIR for cross-compiling (David Schleef) + - add --libs-only-other/--cflags-only-other (Zack Rusin) + - apply man page fixes (Pter Breitenlohner) + - C portability fix (David Robins) + - fix to win32 build (Tor Lillqvist) diff --git a/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README new file mode 100644 index 0000000..5a53aeb --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README @@ -0,0 +1,61 @@ +pkg-config is a script to make putting together all the build +flags when compiling/linking a lot easier. + +Report bugs at http://bugzilla.freedesktop.org/ + +To use pkg-config, do something like the following in your configure.ac + + PKG_CHECK_MODULES([GNOME], [gtk > 1.2.8 gnomeui >= 1.2.0]) + +This puts the neccesary include flags to compile/link something against +libgnomeui and all its dependencies in $(GNOME_CFLAGS), and the -L/-l flags +for linking in $(GNOME_LIBS). + +Users can define the PKG_CONFIG environment variable to point at the +right one, or if they cross-compile and have a correctly named pkg-config +(eg. arm-linux-pkg-config) in their PATH that will be used in preference. + +Users can also define the GNOME_CFLAGS and GNOME_LIBS environment variables +if they think they know better, pkg-config will not be called if they do +that. + +The "gtk > 1.2.8" part is only neccesary if you want to specifically check +if libgtk is version 1.2.8 or higher. Otherwise, the flags for gtk +will be included automatically, since libgnomeui depends on gtk. +So you could just say: + + PKG_CHECK_MODULES([GNOME], [gnomeui]) + +for any version of gnomeui. + +For more info, there's even a man page, try 'man pkg-config' + +Building +======== +pkg-config depends on glib. Note that glib build-depends on pkg-config, +but you can just set the corresponding environment variables (ZLIB_LIBS, +ZLIB_CFLAGS are the only needed ones when this is written) to build it. + +pkg-config also either needs an earlier version of itself to find glib +or you need to set GLIB_CFLAGS and GLIB_LIBS to the correct values for +where it's installed in your system. + +If this requirement is too cumbersome, a bundled copy of a recent glib +stable release is included. Pass --with-internal-glib to configure to +use this copy. + +If you're cross-compiling and you need to build the bundled glib, refer +to the glib documentation for cross-compiling glib. In short, this will +require setting some autoconf cache variables in cases where glib would +need to run a program to determine the correct value. See the glib +documentation: + +http://developer.gnome.org/glib/stable/glib-cross-compiling.html + +If you need to use the bundled glib on Mac OS X, you'll most likely need +to build for a single architecture rather than as a universal binary. +This is because glib (as of version 2.32) does not support building for +multiple architectures out of the box. The glib2 from MacPorts or +Homebrew may be available as a universal binary and usable for +pkg-config as described above. Nothing in pkg-config itself precludes +being built as a universal binary. diff --git a/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README.win32 b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README.win32 new file mode 100644 index 0000000..c5b7ba2 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README.win32 @@ -0,0 +1,46 @@ +pkg-config on Win32 +=================== + +This file describes pkg-config for "native" Win32. (On Cygwin, +pkg-config builds fine right out of the box. Cygwin is just another +Unix variant, as far as pkg-config is concerned.) I don't call this +"native" Win32 target MinGW, as pkg-config on Windows is supposed to +be useable also by MSVC users. + +When pkg-config.exe is invoked, it uses the glib function +g_win32_get_package_installation_directory_of_module() to find the +directory it's being run from. It then adds the "lib" and "share" +subdirectories to the pkg-config search path unless PKG_CONFIG_LIBDIR is +set in the environment. This allows pkg-config to adjust to being +relocated on Windows. + +For each .pc file encountered, pkg-config will replace the prefix +variable to the base of it's currently installed directory unless the +command line option --dont-define-prefix is set. It will take the .pc +directory and strip off either lib\pkgconfig or share\pkgconfig to +determine the prefix. This allows the paths encoded in .pc files at +build time to be replaced with appropriate values at runtime. + +In order to use the output of pkg-config with MSVC, the option +--msvc-syntax can be used to convert UNIX style library output to +arguments that work with MSVC. This means -Lfoo will be converted to +/libpath:foo, and -lfoo will be converted to foo.lib. + +Building pkg-config is now supported on Visual Studio/MSVC as well. To +build it, you will need to have a glib installation. Note that MSVC +builds of glib does not have a build-time dependency on pkg-config, +unlike the normal autotools builds. The headers and libs either need to +be found in your default %INCLUDE% and %LIB% respectively, or they need +to be found in $(GLIB_PREFIX)\include and $(GLIB_PREFIX)\lib respectively; +please see Makefile.vc for adjusting $(GLIB_PREFIX) to suit your needs. +To build pkg-config with MSVC, run in a Visual Studio command prompt: + +"nmake /f Makefile.vc CFG=release" (release builds) -or- +"nmake /f Makefile.vc CFG=debug" (debug builds) + +The resulting pkg-config.exe will be found in [release|debug]\[win32|x64]; +a 'clean' target is supported to clean up the build. MSVC 2008 +through 2015 is supported; older versions may work as well but is not +tested. Note that building with the glib bundled with this source +distribution is not currently supported-the glib DLL and all of its +dependent DLLs are required at runtime. diff --git a/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/AUTHORS b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/AUTHORS new file mode 100644 index 0000000..8dc2095 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/AUTHORS @@ -0,0 +1,58 @@ +Texinfo authors. + + Copyright 2003-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. + +Adrian Aichner texi2html. +Olaf Bachmann texi2html. +Karl Berry all files. +Per Bothner makeinfo/xml.c, makeinfo/docbook.c updates. +Torsten Bronger texinfo.dtd. +Bob Chassell texinfo.tex, original texinfo.txi. +Lionel Cons original texi2html. +Akim Demaille texi2dvi, util/* tests. +Patrice Dumas texi2html, texi2html.texi, texinfo.txi, tp author. +Alper Ersoy makeinfo: enhancements in all files, especially + html-, xml-, and docbook-related. +Brian Fox all makeinfo/* and info/* files, info-stnd.texi. +Noah Friedman original texi2dvi. +Oleg Katsitadze doc/* +Dave Love original makeinfo/html.[ch]. +Karl Heinz Marbaise original makeinfo language support, most files, + texi2html manual. +Philippe Martin original makeinfo xml/docbook output. +Sergey Poznyakoff all files. +Derek Price texi2html. +Arnold Robbins literate (texi+awk) texindex. +Paul Rubin original makeinfo/multi.c. +Andreas Schwab texinfo.tex, configure.ac, most makeinfo files. +Gavin Smith all files. +Richard Stallman original texinfo.tex, install-info.c, + texindex.c, texinfo.txi. +Zack Weinberg texinfo.tex: @macro implementation. +Ralf Wildenhues util/gendocs.sh, makeinfo/tests/*, + makeinfo/html.c, makeinfo/cmds.c, makeinfo/footnote.c, + doc/texinfo.txi, + Makefile.am, configure.ac. +Eli Zaretskii all files. + +See http://translationproject.org/team/index.html for the +translation teams for a given language LL. Additional info for +original texi2html translations: +fr: Patrice Dumas and Jean-Charles Malahieude +de: Reinhold Kainhofer +pt_BR, +pt: Jorge Barros de Abreu +ja: Found in Fedora. Don't know the author. +es: Francisco Vila +it: Federico Bruni +hu: Dénes Harmath + +Images in the images directory come from the Singular project: +http://www.singular.uni-kl.de/ + +Many files included in the Texinfo distribution are copied from other +locations, no author information is given for those. See util/srclist*. diff --git a/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/COPYING b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/COPYING new file mode 100644 index 0000000..f288702 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/NEWS b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/NEWS new file mode 100644 index 0000000..aaa812e --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/NEWS @@ -0,0 +1,1618 @@ +This NEWS file records noteworthy changes, very tersely. +See the manual for detailed information. + + Copyright 1992-2023 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. + +------------------------------------------------------------------------------ + +7.0.3 (26 March 2023) +This is a bug-fix release with minimal changes. + +* texi2any + . fix performance regression when Perl binary extension (XS) modules + are not being used (e.g. with TEXINFO_XS=omit) + +* info + . further fix of recoding of UTF-8 files to ASCII to avoid text + disappearing from nodes + . avoid possible freeze at start of a file with `-v nodeline=pointers' + + +7.0.2 (22 January 2023) +This is a bug-fix release with minimal changes. + +* texi2any + . do not distribute architecture-dependent files + . build fixed on OpenIndiana 11 + +* info + . further fix of recoding of UTF-8 files to ASCII + . fix check for presence of man pages on Solaris + +* install-info + . fix build by avoiding function name clash on some platforms + . compiler warning re strncat silenced + + +7.0.1 (30 November 2022) +This is a bug-fix release with minimal changes. + +* texi2any + . avoid crashes on empty @image argument and other potential crashes + (with "Can't use an undefined value as an ARRAY reference" message) + . avoid hang on @ref command inside section command + +* info + . fix recoding of UTF-8 files to ASCII when run in C locale + +* js + . index search fixed for new HTML output + . some obsolete files removed from distribution + + +7.0 (7 November 2022) +* texi2any + . LaTeX added as an output format, selected with --latex + . EPUB 3 added as an output format, selected with --epub3 + . reform throughout the code in general + . thorough review of character encoding issues + . new customization variables involved with character encoding: + INPUT_FILE_NAME_ENCODING, OUTPUT_FILE_NAME_ENCODING, + DOC_ENCODING_FOR_INPUT_FILE_NAME, DOC_ENCODING_FOR_OUTPUT_FILE_NAME, + MESSAGE_ENCODING and COMMAND_LINE_ENCODING + . warn if full-text commands (@ref, @footnote, @anchor) appear in @w + . new variable NO_TOP_NODE_OUTPUT + . IGNORE_BEFORE_SETFILENAME variable removed. former effect + is now always on. + . HTML output: + . use manual_name_html as output directory for split HTML instead of + manual_name or manual_name.html + . default DOCTYPE declaration changed to plain HTML5 style rather than + HTML4 DTD reference + . output only the CSS rules that are needed in an output file + . remove CSS_LINES variable and add SHOW_BUILTIN_CSS_RULES + (custom CSS can still be output using EXTRA_HEAD) + . use tag for the output of @t and @verb instead of + . use for @acronym instead of + . link to table of contents from short table of contents only if a + table of contents is actually output + . prefix classes from @example arguments with `user-' + . percent encode URL in @url/@uref, @email, @image and external + manual file + . new USE_XML_SYNTAX, HTML_ROOT_ELEMENT_ATTRIBUTES and + NO_CUSTOM_HTML_ATTRIBUTE variables can be used to output + valid XHTML + . systematic addition of classes attribute in HTML elements based on the + Texinfo @-command names. renaming of class attributes to avoid + confusion with @-commands formatting and describe the role in the + document rather than the formatting style. + . COPIABLE_ANCHORS renamed to COPIABLE_LINKS + . do not add a title by default; SHOW_TITLE or NO_TOP_NODE_OUTPUT has + to be set + . USE_TITLEPAGE_FOR_TITLE is now true by default + . L2H variable removed, replaced by HTML_MATH set to `l2h' + . rename OVERVIEW_LINK_TO_TOC to SHORT_TOC_LINK_TO_TOC + . rename BEFORE_OVERVIEW to BEFORE_SHORT_TOC_LINE + . rename AFTER_OVERVIEW to AFTER_SHORT_TOC_LINES + . remove PRE_ABOUT, AFTER_ABOUT, and add PROGRAM_NAME_IN_ABOUT + . remove KEEP_TOP_EXTERNAL_REF + . new variables IGNORE_REF_TO_TOP_NODE_UP, CONVERT_TO_LATEX_IN_MATH, + HTMLXREF_MODE and HTMLXREF_FILE + . DocBook output: + . do not output Top node or text before the first @node or sectioning + @-command. NO_TOP_NODE_OUTPUT can be set to false to output Top node + for now. + . replace @definfocenlose defined @-commands by the argument as-is + to be more consistent with printed output + . HTML/DocBook output: + . USE_NUMERIC_ENTITY changed to mean to use numeric entities instead + of named entities. former effect is now always on. + . ENABLE_ENCODING_USE_ENTITY variable removed. former effect is now + always off. + . Info output + . quote problematic node names (with :, comma...) by default + . new customization variable ASCII_PUNCTUATION to use plain ASCII + characters for quotation marks and a few other symbols + +* texinfo.tex + . `@microtype on' uses microtypography in formatting for pdfTeX and LuaTeX + . do not ignore @part page immediately following Top node + . do `@set txicodevaristt' to get slanted typewriter for @var in code, + `@clear txicodevaristt' to use slanted, variable-width roman font for + @var everywhere. flag is @set by default, but we may turn this off + in the future. + . new file doc/texinfo-zh.tex for Texinfo documents in Chinese. + new support file doc/txi-zh.tex for Chinese. doc/short-sample-zh.texi is + a sample document. + +* info + . better support for index entries containing parentheses + . better support for getting bold text etc. when displaying manpages + . bug fixed where the first index entry in a file could be ignored + . M-C-f closes as well as opens footnotes window + . do not crash if run in Brazilian Portuguese locale + +* Language + . @deftype* commands use typewriter font in argument list + . new commands @latex, @iflatex, @ifnotlatex for new LaTeX output format + . do `@set txidefnamenospace' to omit space after a definition name + +* Other + . build fixed for glibc 2.34 + + +6.8 (3 July 2021) +* Language + . new command @displaymath for formatting of mathematical notation + . @example takes an argument to specify the language + . mark these commands as deprecated, not to be used: + @centerchap, @definfoenclose, @refill, @inforef. + . new paper size @bsixpaper + +* texi2any + . should be faster as Perl XS parser is enabled by default + . SHOW_MENU customization variable replaced by FORMAT_MENU. + FORMAT_MENU set to 'menu' is the same as SHOW_MENU set to 1, and + FORMAT_MENU set to 'nomenu' is the same as SHOW_MENU set to 0. + . only check menu structure if CHECK_NORMAL_MENU_STRUCTURE variable is set + . changes to HTML output: + . MathJax support for display of math. new variables HTML_MATH, + MATHJAX_SCRIPT and MATHJAX_SOURCE. + . new variables JS_WEBLABELS and JS_WEBLABELS_FILE to support + JavaScript License Web Labels + . by default, use sectional tables of contents instead of menus + . use section names in links by default (configure with + xrefautomaticsectiontitle customization variable) + . CONTENTS_OUTPUT_LOCATION sets location of table of contents + . document sections wrapped in
elements + . new variable USE_NODE_DIRECTIONS to use node or section structure + for node directions + . copiable anchor links for definitions with COPIABLE_ANCHORS variable + . experimental JavaScript browsing interface enabled with INFO_JS_DIR + . don't add an extra period before file extension given as an argument + to @image if image file is not found + +* info + . support compressed dir files + +* texi2dvi + . stop on first error in input file + +* texinfo.tex + . put logical page numbers into PDF's ('page labels') + . put chapter numbers in the PDF outline + . new Finnish translation + +* Distribution + . autoconf 2.71, automake 1.16.3, gettext 0.21 + + +6.7 (23 September 2019) +* Language: + . support of index subentries and sub-subentries with @subentry + . new commands @seeentry and @seealso in index entries + . no need to wrap Top node in @ifnottex - omitted automatically when + processed with TeX + . UTF-8 is the default input encoding + +* texi2any + . for HTML output, mark index nodes in menus and tables of contents + with the 'rel' attribute of the 'a' tag. + . TOP_NODE_UP is now only used in HTML if TOP_NODE_UP_URL is set. + Also TOP_NODE_UP should now be formatted in the output format. + In HTML TOP_NODE_UP should be suitable for inclusion in HTML + element attributes, so for instance should not contain elements. + . support of noderename.cnf files has been removed + . INPUT_PERL_ENCODING, INPUT_ENCODING_NAME, NODE_FILE_EXTENSION, + NODE_FILENAMES, SHORTEXTN and TOP_NODE_FILE removed as customization + variables. + . TOP_NODE_FILE_TARGET now contains the extension. + . error messages translated when the XS parser module is in use + +* texi2dvi + . unconditionally run in --batch mode, i.e. without stopping if there + is a TeX error + . keep on going after a TeX error if the index files changed + . with --tidy (or --build-dir), avoid reading index files from previous + runs where --tidy was not used + +* info + . for a tree search (with M-/), '}' and '{' work as well as 'M-}' and + 'M-{' to go through the results + +* Distribution: + . Several obsolete portability checks removed + . gettext 0.20.1, automake 1.16.1 + + +6.6 (16 February 2019) +* Language: + . new commands @&, @ampchar{} + . @cropmarks command removed + . @ctrl is no longer recognised (it was a way to insert literal + control characters in Info files, but deprecated since the + time of Texinfo version 2) + . \usebracesinindexestrue is no longer recommended for using braces in + index entries, and has been a no-op for some time + +* texi2any + . extension modules fixed to work with the "thread-safe locales" of + Perl 5.28 and newer + . some code changed to stop warnings being given by newer versions of Perl + . for HTML output, use `id' to define link targets instead of the `name' + attribute on + . A native-code implementation of the Texinfo parser has been included + on an experimental basis, which makes texi2any a lot faster. Set the + `TEXINFO_XS_PARSER' environment variable to 1 to use. + . changes to HTML output: + . omit colon after node name in menus by default (use + `MENU_ENTRY_COLON' to add it back) + . no special CSS for commands like @smallexample + . new customization variable `SECTION_NAME_IN_TITLE' to use the + section name as the document + . use section names instead of node names in generated menus + . pass on flags set with -D to TeX + . useless static libraries are not installed + . the newline after an @insertcopying is not output + . warning given for @multitable prototypes not in braces + . @indent and @noindent are not allowed inside the arguments to + commands where they are not meaningful + . @quote-arg and @allow-recursion are not recognised (these two used + to be recognised by makeinfo in macro definitions but were never + implemented in texinfo.tex) + . `FIX_TEXINFO' removed as a customization variable + . do not recognise or warn about obsolete customization variables + +* info + . debugging output with -x is not diverted to a separate infodebug file + +* Development: + . switch from Subversion to git + - https://savannah.gnu.org/git/?group=texinfo + . automake 1.16 + + +6.5 (12 September 2017) +* info: + . some bugs fixed: + . a bug where a segfault could happen in the regex search, for + example when the user entered a single \ as the search string + . another bug which could make nodes inaccessible in long "split" + info files + . a bug where it was not possible to follow a cross-reference + that was split across more than one line has been fixed + . do not fall back to a man page if following a cross-reference in an + info file failed + . if looking for a file failed, do not convert the name of a file to + lower-case and look for it again + +* texinfo.tex + . some faulty definitions for Unicode characters have been changed or + removed + . fix indentation in table of contents for entries that are split + across multiple lines + +* texi2dvi + . a bug that broke the processing of LaTeX files that did not + use BibTeX has been fixed + +* texi2any + . output the encoding declaration of a HTML file earlier so it + will always occur within first 1024 bytes of file + . `INLINE_INSERTCOPYING' removed as a customization variable + + +6.4 (23 June 2017) +* texi2any: + . for HTML output, place section names before the manual in page + titles, instead of after them, so it is easier to distinguish pages + if titles are truncated + . starting points for ordered lists beginning with 0 or a letter of + the alphabet are output as attributes on the <ol> tag, as was + case for Texinfo 4.13 and earlier + . a bit faster + . some discrepancies in paragraph formatting between Perl extension + modules and interpreted Perl modules have been fixed + . `MACRO_BODY_IGNORES_LEADING_SPACE' customization variable removed, + and `indent_menu_descriptions' is no longer a possible value for + `TREE_TRANSFORMATIONS' (as these features did not work as + documented) + +* info: + . the `up-line' and `down-line' commands now are like the other + scrolling commands and are no longer confined to a single node + (depending on the value of `scroll-behaviour') + . supplying the --all option with --index-search displays a list + of matching index entries + . the style variables like `link-style' can now be set while info + is running + . display bug fixed where color could be turned off prematurely + . several other bugs fixed + . better portability in test suite + . do not fall back to showing the dir node if a manual isn't found + . Do not attempt any kind of conversion of CR LF line endings, + except on MS-DOS/Windows, when it is done unconditionally. (This + replaces a more complicated approach, where this conversion would + take place if there was a problem finding a node in a file.) The + main effect of this change is that Info files with CR LF line + endings, which would have been produced on MS-DOS/Windows with old + versions of makeinfo, are only supported on such operating systems. + . a few of the key bindings under --vi-keys have been changed for + consistency or to match the documentation + +* texinfo.tex + . a DVI file with a single empty page can be output again, which + restores the behavior from Texinfo 6.0 and earlier + +* Distribution + . autoconf 2.69, automake 1.15, gettext 0.19.8 + + + +6.3 (10 September 2016) + +* Language: + . The commands `@setcontentsaftertitlepage' and + `@setshortcontentsaftertitlepage' have been removed. + . @-commands are no longer supported within `@errormsg'. + +* texinfo.tex: + . For a couple of characters (opening and closing braces), use glyphs + from the standard TeX math fonts instead of using EC fonts which are + less likely to be installed. + . Use of user-defined macros in the text of an index entry is more + reliable when the text contains Texinfo @-commands. + . @synindex and @syncodeindex have been fixed (broken in the last + release). + . Support added for native UTF-8 support with XeTeX and LuaTeX. + . Support of PDF output with XeTeX improved. + . You can use a new file doc/texinfo-ja.tex for Texinfo documents in + Japanese. doc/short-sample-ja.tex is a sample document. New + support file doc/txi-ja.tex for Japanese. + +* texi2any: + . Fix handling of compiler options when building Perl extension modules. + +* texi2dvi: + . Can now process files whose absolute paths contain space characters, + as long a relative path to the file is given. Better support of + files with unusual characters in their names. + . No longer exits prematurely in some circumstances (due to the script + running under "set -e"). + . Bug fixed which made the `--command' and `--tidy' options + incompatible. + +* info: + . Handling of "invalid" value in infokey file fixed. + +6.2 (withdrawn) + + + +6.1 (06 February 2016) + +* Language: + . You can now omit the @menu from nodes with other nodes below them in + the document structure. If you use "@validatemenus off" near the + start of a Texinfo file, makeinfo will, where needed, create a menu + for nodes lacking one given explicitly. + . An @setfilename line is no longer required at the start of a + Texinfo file. (Be aware, though, that some other tools may require + it, for example Automake.) + . For processing with TeX, a comma is automatically provided following + a cross-reference command (such as @xref) when needed to separate + the page number from following text, so you don't need to add one + yourself. See the `Parts of a Cross Reference' node in the manual + for details. Behavior when followed by punctuation, as always + recommended previously, is unchanged. + +* texi2any: + . Some Perl modules have been rewritten in C to increase speed. + If Perl extensions can be created, they are used by default; + otherwise the pure Perl implementations are still used. + Disable at build time with "configure --disable-perl-xs". The + environment variable TEXINFO_XS controls how they are used by + texi2any. + . Quotation marks are left out for node names and index entries in + Info output where they would have been produced by commands such + as @file or @option. + . New customization variable INFO_SPECIAL_CHARS_QUOTE to allow use of + a quoting mechanism for problematic constructs in Info output, for + example node names containing colons or commas. + . Commands like @heading are affected by @lowersections and @raisesections + again, as was the case before Texinfo 5.0. + +* texinfo.tex: + . You may explicitly specify a sort key for an index entry by preceding + the text of the entry with the @sortas commmand with the sort key + desired as a braced argument. Additionally, you may choose to + ignore all occurences of the characters \, @, <, and - using new + flags you can specify with @set: `txiindexbackslashignore', + `txiindexatsignignore', `txiindexlessthanignore', and + `txiindexhyphenignore' respectively. + . Changes to macro handling to more closely match makeinfo. Ends of + lines are preserved in an argument to a macro taking a single + argument. + . By default, suppress heading line on a page with a chapter on it, to + avoid having the chapter title repeated. + . Use a larger font for arguments in a @deffn line and similar. + . The default indices (cp, ky and so on) now don't get a file opened + for them unless they are actually used. This reduces the number of + files that a run of TeX produces, and also allows for a greater + number of user-defined indices, because you will not bump into TeX's + limit of 16 open files at once so soon. + . For initials in indices that are non-alphanumeric characters (for + example, backslash, or braces), avoid use of a typewriter font. + This gives a more consistent appearance. + . Have a stronger preference for breaking a column in an index before + a letter heading. + . Formatting improvements in tables of contents and indices. Entries + can extend slightly into the margin instead of being broken across + two lines, and text is split more evenly across lines. Reduce + chance of an orphaned index entry appearing at the top of a column. + . Support character encodings beyond ASCII for XeTeX and LuaTeX by + reading file input byte-by-byte. + +* texi2dvi: + . Support for determining the output files using the `-recorder' + option to TeX, to help to support more TeX engines. + +* info: + . New user variables `link-style', `active-link-style', and + `match-style' enable customization of how cross-references and search + matches are highlighted. + . By default only the node pointers are displayed at the top of a node. + Customize this with the `nodeline' variable. + . New command M-x tree-search to search all subnodes of a node. + . Now tries to find referenced manuals in the same directory as the + current file first, before looking in search path. Customize this + with new variable `follow-strategy'. + . The `mouse' variable is now off by default, in order not to + interfere with the selection of text in a terminal emulator window. + . `q' closes a window instead of quitting altogether if there's more + than one, for example if a help window is open. + . Several bug fixes, including: + . one causing the wrong position in a node to be shown when + following an "anchor" cross-reference + . one causing a test failure in the t/c-u-m-x-scroll-forward.sh + test on some platforms + . Internal changes to reduce memory use and increase speed of + searches, relative to last release + . The meaning of the `key-time' variable has changed when its value + is 0. This value meant to wait forever in the last release, but now + it means that the next byte must be available immediately. + +* Documentation: + . The `info.info' file (and `info.texi' source) is no longer + distributed with Texinfo. Now this manual is only in Emacs. + +* Distribution: + . automake-1.15, gettext-0.19.6. + + +6.0 (26 June 2015) +* Language: + . new commands @sub and @sup, for textual subscripts and superscripts. + . new command @U to insert a Unicode character by code point. + +* texinfo.tex: + . @url/@uref output in PDF now the same as in DVI, showing the url + even if the second argument is given, not just as a link target. + TeX option \urefurlonlylinktrue gives previous behavior, of invisible urls. + PDF-only \linkcolor and \urlcolor specify colors (default black). + +* texi2any: + . customization variable TOP_NODE_UP_URL now replaces all (dir) references; + recommended setting for GNU packages is /manual/. + . new customization variable INDEX_SPECIAL_CHARS_WARNING to complain + when index entries contain a colon. + . Docbook output no longer uses <lineannotation> for @r. + . -D'var val' on the command line works as intended again. + . --plaintext output can be split. + . a bit faster. + +* info: + . invoking as `info foo bar' looks for bar as an index entry in manual + foo, if not found as a top-level menu item. + . invoking info with an absolute or explicitly relative file name + (./foo.info, /tmp/foo.info, etc.) just visits that file. + . separate `infokey' program has been removed - the .infokey file is + now read directly by Info. + . new option --init-file allows overriding ~/.infokey. + . new variable `highlight-searches' allows highlighting results from a + search + . support for mouse scrollwheel, controlled by `mouse' variable. + . new variable `key_time' to control how long to wait for byte + sequences sent by special keys. + . new variable `hide-note-references' alters appearance of displayed nodes + . new variable `infopath-no-defaults' allows omitting the compile-time + Info directory from the Info search path. + . support input of multibyte characters for searches in a UTF-8 locale. + . if reading an Info file that is known to be in a different character + encoding to that of the user's environment, convert its contents + when displayed and substitute missing characters + . new command M-x info-version. + . the M-x kill-node command has been removed. + . test suite at build time. + +* texindex: + . completely new implementation as a literate program using Texinfo + and (portable) awk (called TexiWeb Jr.), thanks to Arnold Robbins. + (Requires gawk 4.0+ if .twjr source is modified.) + . the -o (--output) is not supported, unless we hear of someone using it. + . duplicated sort keys with different display texts result in one + merged index entry, using the first display text. + . better sorting and parsing in unusual cases; most notably, { and } + characters can appear as initials. + +* install-info: + . handle compressed input file names containing spaces. + . exit successfully if --remove is given and the dir file does not exist. + . new option --defsection, to be used instead of "Miscellaneous" when + a section is not present in the Info file. + +* texi2dvi: + . look for the environment variable THUMBPDF_CMD instead of THUMBPDF, + since thumbpdf itself has used THUMBPDF for options since 2000. + . remove --recode and --recode-from options, since they haven't + worked as intended for years, so evidently no one needs them. + +* Distribution: + . new translation ca (catalan). + . automake-1.15, gettext-0.19.4. + + +5.2 (26 September 2013) +* Language: + . new commands @inlinefmtifelse, @inlineifset, @inlineifclear, for + more brace-delimited alternatives to the conditional environments. + +* texi2any: + . warns about node names, menu items, and cross-references (but not + index entries) containing problematic characters; can be disabled + with -c INFO_SPECIAL_CHARS_WARNING=0. + +* info: + . new option -x (--debug) for debugging output; -x -1 to get everything. + . new option -v (--variable) assigns a value to an Info variable, + with the usual syntax, -v VARIABLE=VALUE. + . new option -a (--all) instructs Info to display all documents + matching the command line arguments, not just the first. In + conjunction with the -w option, it shows full names of all Info + files matching the command line arguments; with -o, it outputs all + matching files. + . new variable search-skip-screen controls the starting position for + repeated search commands ({ and }). When set to On, repeated + searches skip the lines displayed on the screen, i.e., + forward searches (}) start at the beginning of the next page, and + backward searches ({) start at the end of the previous page. + . new command display-file-info (bound to = by default, C-g in vi mode) + shows full file name of the node being displayed and position in it. + +* texi2dvi: + . support for biblatex+biber. + +* Distribution: automake-1.14, gettext-0.18.3.1. + + +5.1 (12 March 2013) +* texi2any: + . irregular sectioning trees (see 5.0 news item) produce a warning + rather than an error. + . @set in the middle of the line no longer produces a warning. + +* info: + . lzip (.lz) compression supported. + +* install-info: + . lzip (.lz) compression supported. + +* Development: switch from CVS to Subversion. + https://savannah.gnu.org/svn/?group=texinfo + + +5.0 (16 February 2013) +* Language: + . Texinfo commands are supported in node names. + . #line directives are recognized. + . @-commands are now recognized in raw format blocks. Therefore, for + example, lone @, { and } characters in @tex, @html and similar + environments must be converted to the normal @@, @{, and @} commands. + . new commands @inlinefmt and @inlineraw for brace-delimited conditionals. + . new conditionals @ifcommanddefined and @ifcommandnotdefined to test + if a Texinfo command is available. + . new command @part for a group of chapters. + . new environments @raggedright, @smallquotation, + @indentedblock, and @smallindentedblock. + . new commands @codequoteundirected and @codequotebacktick, + for a better interface than "@set txicodequoteundirected" and + "@set txicodequotebacktick"; now respected by @kbd. + . new command @xrefautomaticsectiontitle to allow using section titles + in cross references by default, instead of node names. + . new commands for Texinfo special characters: + @atchar{} @lbracechar{} @rbracechar{} @backslashchar{} @hashchar{}. + . new commands @deftypefnnewline to print return types on their own lines. + . new command @headitemfont for the sake of template rows. + . new command @urefbreakstyle to control breaking of @url/@uref in TeX. + . new diacritic command @ogonek. + . new commands for Icelandic letters eth and thorn: @DH{} @dh{} @TH{} @th{}. + . new command @errormsg to report an error. + . five-argument xrefs can refer to a whole manual, by omitting the + section name and either omitting the node name or using "Top". + . DEL (0x7f = 0177 = 127) is a true comment character (catcode 14 in TeX). + +* texi2any is the new generic converter for Texinfo that can produce all + supported output formats, both those from texi2dvi (PDF/DVI) and from + makeinfo (Info/HTML/etc.). texi2any and makeinfo are now different + names for the same program; there are no differences in behavior based + on the program name. + + The new implementation is in Perl, requiring Perl 5.7.3 (released in + March 2002) and its standard Encode module. + + The Perl texi2any/makeinfo both replaces and is intended to be (for + all practical purposes) upward-compatible with the C makeinfo. It has + many new features not in the C makeinfo. For example, cross-manual + references are now fully supported, and allows for extensive + customization of the HTML output. See the `Generic Translator + texi2any' chapter in the manual (among other places) for more about + this reimplementation. + + The new program is, unfortunately, noticeably slower at present than + the C program was. We hope all the many improvements make the new + version worthwhile for users nevertheless. + +* Intentional incompatibilities with the previous implementation of + makeinfo, through version 4.13: + + . The old implementation accepted a lone block of text inside @itemize, + @enumerate, etc., without any @item. This is semantically + inconsistent, leading to problems with some backends, and thus now + produces a warning. + + . The old implementation accepted ``irregular'' sectioning trees. Now, + when @node pointers are implicitly determined, the consistency of + @menu and the sectioning tree is checked. (If node pointers are + explicitly specified in the document, the tree can still be irregular.) + + . The old implementation always added blank lines between function + definitions if they weren't already there. Now blank lines are not + added. (Both old and new implementations preserve blank lines that + are present.) + + . The old implementation processed macros in place, formatting the + replacement text with the output. Now the replacement text is + textually substituted as Texinfo source. A consequence of the old + behavior is that ends of lines from expansion of an @macro + definition did not end an @-command line-delimited argument + (@chapter, @center, etc.). Now they do. (A detailed example is in + the manual, node Macro Details.) + +* pod2texi is a new (Perl) program that uses the capabilities of + texi2any to translate Perl pod documentation to Texinfo. + +* texinfo.tex: + . urls (given to @uref and @url) are broken by default at special + characters; behavior controllable with @urefbreakstyle. + . support some per-language hyphenation, when the underlying TeX + engine does (for instance, etex/pdfetex from TeX Live 2008 or + later). Words with accented letters are still not handled properly. + . @title, text will be broken if needed, and @* can be used to override. + . new Icelandic translation: txi-is.tex. + . new Hungarian translation: txi-hu.tex. + . official updates between full package releases available at + http://ftpmirror.gnu.org/texinfo/texinfo.tex. + +* texi2dvi: + . new option --max-iterations. + . official updates between full package releases available at + http://ftpmirror.gnu.org/texinfo/texi2dvi. + +* info: + . INFOPATH is determined from PATH by default, or if an element "PATH" + is specified. + . New command Info-virtual-index, bound to I by default, following Emacs. + . Info keywords not found by searches. + . A lower limit on the length of search patterns, default 1, + specified by the variable min-search-length. + . Use ASCII versions of images, if supplied by the document. + . xz compression supported. + +* install-info: + . xz compression supported. + +* Documentation: + . new appendix with a technical description of the Info file format. + . information on the customizations of the HTML output now possible. + +* Distribution: + . new file htmlxref.cnf is installed to support cross-manual + references; official updates between full package releases available + at http://ftpmirror.gnu.org/texinfo/htmlxref.cnf. + . language support for no removed/renamed to nb, per Norwegian translators. + . new translations: id it, + and document translations: eo pl. + . texinfo.cat file removed since it is (to our knowledge) unused. + . documentation license now GFDLv1.3 or later. + . autoconf 2.69, automake 1.13.1, gettext 0.18.2. + + +4.13 (18 September 2008) + +* A reference card for Texinfo is now available, in doc/refcard. For + convenience, preformatted PDF's for letter-size and A4 paper are included. + +* makeinfo: + . new option --internal-links for HTML output, to write a tsv file + mapping indexed/toc terms to links, for easy reference from external + documents. + . - as an input file name reads standard input. + +* info: + . support for multibyte encodings such as UTF-8. + . new option --show-malformed-multibytes, to display malformed multibyte + sequences. + . new environment variable INFO_MAN_COMMAND sets the name of man executable + (use it if you a need to override PATH settings). + +* install-info: + . bug fix: support names with embedded periods (e.g., config.status) again. + +* Distribution: + . autoconf 2.63. + + +4.12 (20 April 2008) + +* Language: + . new commands @clicksequence, @click, and @clickstyle for documenting + GUI sequences, and @arrow for the default glyph used. + . new commands @geq{} and @leq{} for the normal >= and <= relations. + +* install-info: + . lzma compression supported. + . Much work towards compatibility with Debian's independent + implementation. Changes in behavior: + - new entries are formatted to start at column 34 by default. + - existing entries are replaced by default. + - new sections are alphabetized among existing sections. + - if an entry being removed is the last one in a section, the + section is also removed. + . Also many new options: + --section REGEX TITLE. + --no-indent: disable formatting of new entries. + --menuentry, --name: specify left-hand side of an entry. + --dry-run: alias for --test. + --regex REGEX: renamed from --section regex, adds to all sections + matching REGEX by default. + --add-once: add only to first specified or matching section. + --align COL: start description at column COL. + --calign COL: start continuation lines in description at COL. + --max-width COL: wrap the description at COL. + . New section in the Texinfo manual describing all this. + +* info: + Our goal with these changes to the default interface is to make Info + documents more easily and quickly readable, especially by non-experts. + . the PageUp and PageDown keys move through the whole document by + default, instead of just the current node. + . the h command shows the basic help, and H starts the Info tutorial. + . the newly-bound x command deletes the current window, e.g., within help. + . the scroll-step variable is set to 1 by default, for smooth scrolling. + . the cursor-movement-scrolls-p variable is set to 1 by default, so + link searches look through the whole document. + . regular expression searches are supported, and are the default for + both regular and incremental searches. + . the new R command toggles between regexp and literal-string searches. + . the new variable scroll-last-node controls scrolling at the end of + the last node; by default, it now simply reports there are no more + nodes. To restore the old behavior, set scroll-last-node=Scroll. + . the precise line number specified in index entries is used if available. + . --usage=info shows usage for standalone Info. + . lzma compression supported. + +* Distribution: + . language support for no removed/renamed to nb, per Norwegian translators. + . new translation: es. + . bug fixes in make check (and elsewhere). + . gettext 0.17, automake 1.10.1, autoconf 2.62. + + +4.11 (9 September 2007) + +* Language: + . @documentlanguage now supports an optional country code + specification after the language code, a la gettext. + . new command @allowcodebreaks controls breaks at _ and - within @code. + . new command @frenchspacing controls spacing after sentences. + . new command @fonttextsize allows changing body text font size to 10pt. + . new command @textdegree{} produces the normal degrees symbol. + . new command @thischapternum can be used in TeX headers/footers. + . new commands for quotes: @quotedblleft @quotedblright + @quoteleft @quoteright @quotedblbase @quotesinglbase + @guillemetleft @guillemetright @guilsinglleft @guilsinglright. + . new option @set txicodequoteundirected produces an undirected quote + in code and example output, instead of the regular right quote. + . new option @set txicodequotebacktick produces a grave accent in + code and example output, instead of the regular left quote. +* makeinfo: + . The @documentlanguage locale is used to translate various document strings. + . --enable-encoding is now the default, meaning Info and plain text + output use 8-bit characters given a supported @documentencoding. + . new option --css-ref=URL for creating a stylesheet <link> in HTML output. + . new option --transliterate-file-names to use a reduction-to-ASCII + algorithm for split HTML file names, useful for non-Latin-based languages. + . @enddots{} outputs three dots instead of four, for consistency with + texinfo.tex. + . the Local Variables coding: setting written by --enable-encoding now + comes at the very end, after the tags table, so that Emacs can find + it in more cases. + . @allow-recursion (never documented) is deprecated and produces a warning. + . @quote-args (never documented) is now the default behavior. + . centering and such take account of character widths. + . the --reference-limit option is now a no-op. + . improvements to XML and Docbook output and the DTD. +* texinfo.tex: + . @thissection can now be used in custom headings, and @thischapter + works reliably even without @set chapternewpage. Custom headings + have additional flexibility as well. +* texi2dvi: + . pdftexi2dvi is a new wrapper to `texi2dvi --pdf', equal to texi2pdf, + for the sake of AUC-TeX which prepends `pdf' to the compilation + command when requested to produce PDF. +* info: + . look for info files in the current directory first, by default. + . when calling man, use -a if no explicit section is found. + . avoid showing the top(1) man page for nonexistent info files. +* install-info: + . new options --section-regex, --remove-exactly, --debug, --test. +* Distribution: + . autoconf 2.60, automake 1.10, gettext 0.16.1. + . gettext support now [external]. + . new translations: hu (Hungarian), rw (Kinyarwandan), vi (Vietnamese). + . most common sources imported from gnulib. + +4.10 (omitted) + + +4.9 (29 June 2007) +* GPLv3. +* texi2dvi: + . new mode --build=tidy which supports compilation in a separate + directory, where intermediate files are preserved. + . new option --build-dir, to specify where the tidy build will take + place, either locally or globally. This allows avoiding the clutter + while preserving auxiliary files. + . new support for AUC-TeX: texi2dvi (weakly) supports arguments a la + TeX such as `\nonstopmode\input{file.tex}'. + . new options --ps and --dvipdf, useful especially for pstricks documents. + . new option --src-specials, passed to TeX. +* texinfo.tex: + . Latin1, Latin2, Latin9, and UTF-8 are supported -- only as well as + the Computer Modern fonts can manage, which means primarily English + and western European languages, to a limited extent. + . png and jpg images supported in pdf output. + . new Russian, Serbian, and Ukrainian translations for texinfo.tex: + txi-ru.tex, txi-sr.tex, txi-uk.tex. + . section names with \ characters work properly in pdf outlines. + . have .toc files use @ as the escape character, instead of \. + + +4.8 (31 December 2004) +* Language: + . new command @euro for the Euro currency symbol, and + @documentencoding has some support for ISO-8859-15. + . new command @abbr for general abbreviations. + . new command @slanted to typeset text in a slanted font, + and @sansserif to typeset in a sans serif font. +* makeinfo: + . An empty first argument to cross-reference commands, such as @xref, + causes an error. This change was made in 4.1, but not mentioned in NEWS. + . HTML output: + - <a name="..."> constructs are added for the old-style + conversion of node names to HTML names, so that external references + to them can continue to work. + - "g_t" prefixed to targets for node names beginning with a + nonletter, for XHTML compatibility. + . Docbook output: recognize more image formats. +* texi2dvi: + . new option --recode, to call recode for input character translation. +* Distribution: + . new convenience script texi2pdf, equivalent to texi2dvi --pdf (from tetex). + . some cross-compiling support in configure && make. + . new configure option --disable-install-warnings, for TeX. + distributions which do have the files installed. + . automake 1.9.4. + + +4.7 (9 April 2004) +* Language: + . new commands @float, @caption, @shortcaption, @listoffloats for + initial implementation of floating material (figures, tables, etc). + Ironically, they do not yet actually float anywhere. + . new commands @docbook, @ifdocbook, @ifnotdocbook for conditional Docbook. + . new commands @ordf{} and @ordm{} for Spanish feminine/masculine ordinals. + . new commands @deftypecv[x] for class variables in typed OO languages. + . new command @registeredsymbol for the r-in-a-circle symbol. + . new command @headitem to make a heading row in @multitable. + . new command @LaTeX{} for the LaTeX logo. + . new command @comma{} to avoid comma-parsing problems. + . @url is now a synonym for @uref; new command @indicateurl has the + old meaning of just displaying a url as text. + . @quotation now accepts an optional argument for labelling the text + as a `Note', `Tip', etc. + . @defun (et al.) heading lines can now be continued with a lone @. + . @acronym accepts an optional argument for the meaning of the acronym. +* makeinfo: + . New environment variable TEXINFO_OUTPUT_FORMAT determines the output + format at runtime, if no options are specified. + . New option --plaintext, equivalent to --no-headers with Info output. + . All outputs: + - sections are numbered by default. + . Info output: + - punctuation is inserted after @pxref and @ref, if needed to make + cross-references valid. + - line numbers included in index menus, so Info readers can go to + the exact line of an entry, not just a node. Also in plaintext output. + - ^@^H[index^@^H] cookie included in index menus, so Info readers + can handle the ] etc. commands better. + . HTML output: + - new algorithm for cross-references to other manuals, for maximum + portability and stability. + - include node name in <title> with split output. + - @multicolumn fractions become percentages. + - entities used for bullets, quotes, dashes, and others. + - index entries are links to the exact locations. + - <h4> and <h5> used for @sub and @subsubsections again. + - accented dotless i supported. + . XML output: many new tags and structure to preserve more source features. + . Docbook output: + - upgraded DTD to Docbook XML 4.2, no longer using Docbook SGML. + - improved translation in general, for instance: + - line annotations and marked quotations. +* texi2dvi: + . if available, use etex (pdfetex if --pdf) by default. + . if the input file includes thumbpdf.sty (for LaTeX), then run thumbpdf. + . more output if --debug. +* texinfo.tex: + . @defun names are now printed in typewriter (instead of bold), and + within the arguments, @var text is printed in slanted typewriter. + . @tex code is executed inside a TeX group, so that any changes must + be prefixed with \global (or the equivalent) to be effective. (This + change was actually made years ago, but never made it into the NEWS.) +* info: + . new option --where (aka --location, -w) to report where an Info file + would be found, instead of reading it. + . by default, output ANSI terminal escape sequences as-is; new option + --no-raw-escapes overrides this. + . use the newly-generated index line numbers. +* Distribution: + . new script gendocs.sh (not installed), for use by GNU maintainers in + getting their manuals on the GNU web site. Documented in + maintain.texi (http://www.gnu.org/prep/maintain/). + . Most code uses ANSI C prototypes, to some extent. + . New translation: nb. + . automake 1.8.3, autoconf 2.59, gettext 0.14.1. + + +4.6 (10 June 2003) +* Language: + . new command @/ specifies an allowable breakpoint within a line. + . new command @dofirstparagraphindent to control whether the first + paragraph following a section heading is indented. Default is to + omit this indentation, unlike the output up to now. + . new command @indent for explicitly indenting a paragraph. + . makeinfo writes a new construct for @image in Info output, so that + graphical Info browsers (such as Emacs Info under X) can display an + actual image. (Standalone Info ignores this, since it runs in a tty.) +* makeinfo: + . Common: + - search for image files in the include file search path. + - warns if @value is used on an undefined variable. + . Info output: + - default --split-size now 300,000 bytes, up from 50,000. + - with --enable-encoding and a given @documentencoding, + output a Local Variables section specifying that encoding, for use + with Emacs. + . HTML output: + - uses <h3> at the smallest. + - a few css <style> definitions are included to better + implement @format, @display, @small..., etc. + - new option --css-include=FILE includes FILE in the <style>. + - @cartouche now outputs a <table> with a border. +* texinfo.tex: + . new Polish translation txi-pl.tex. +* texi2dvi: + . --command=CMD replaces --texinfo=CMD; it inserts CMD at the first + line of LaTeX files now, or after the @setfilename for Texinfo files. +* info: + . RET now goes to the nearest xref (rather like Emacs Info), + instead of the next xref starting on the current line. +* Distribution: + . new Romanian (ro) translation. + . variables now declared const where appropriate. + . gettext 0.12.1, automake 1.7.5. + + +4.5 (4 February 2003) +* info: + . a bug in 4.4 prevented compressed info files from being found. +* Distribution: + . detect sys/ptem.h on Solaris. + + +4.4 (31 January 2003) +* Language: + . The ' (ASCII apostrophe/right quote) character is finally allowed in + node and anchor names. Thus, after installing this texinfo.tex, + existing .aux files will cause errors! Remove them and rerun TeX to + generate good ones. + . @value constructs are now expanded in the filename arguments to + @include and @verbatiminclude. +* makeinfo: + . @macro names may no longer include ^ or _, for the sake of math mode. + . bug fix: @copying text is now reflected in tag table positions; + before, nodes may not have been found with a long-enough @copying. + . bug fix: html @verb arg is quoted properly, and does not imply + a paragraph break. +* texinfo.tex: + . @smallexample and the like now output in a smaller font (9pt) in all + paper formats, not just @smallbook and @afourpaper. + . new translation txi-tr.tex. + . bug fix: <>| and other characters do not disappear when they are + first on a line in @verbatim. +* install-info: + . bug fix: don't translate the `* Menu' info keyword. +* info: + . CTRL-H is treated like DEL in incremental search. + . arrow keys once again work in isearch contexts under Solaris. +* infokey: + . use .info key bindings before defaults. + . allow prefix keys to be disabled. +* Distribution: + . update to GNU FDL 1.2 (http://www.gnu.org/licenses/fdl.html). + . getopt and other common library files updated from gnulib + (http://savannah.gnu.org/projects/gnulib/). + . autoconf 2.57, automake 1.7.2. + + +4.3 (14 November 2002) +* Language: + . new command @tie{} to do a real tie (unbreakable interword space). +* makeinfo: + . html output for @defun and friends now has font changes. + . html output has some class attributes. + . xml and docbook output improved in many details. +* texinfo.tex: + . new Italian translations, txi-it.tex. + . pdf bookmarks for unnumbered sections work. + . type name for @defun and friends no longer extends into margin. +* info: + . automatic-footnotes now off by default, for emacs compatibility. + . crash when MALLOC_CHECK_=2 fixed. +* install-info: + . new option --infodir synonym for --info-dir, for compatibility with + the Debian install-info. + . support for bzip2-compressed files. +* texindex: + . omit initial if the entire index is under one character. +* Distribution: + . development sources now available under CVS, see + http://savannah.gnu.org/projects/texinfo/ + . Turkish message translation. + . gettext 0.11.5, autoconf 2.54, automake 1.7.1. + + +*** NEWS FOR ALL AUTHORS OF TEXINFO MANUALS *** + +As of version 4.2, Texinfo has a command @copying to define the +copyright and copying permissions for a manual. If you haven't already, +please switch to using it in your next release, because the historical +method of doing copyright permissions using @ifinfo failed to output +copyright information in the HTML (or XML) formats. The manual has +detailed explanations and examples. For convenience, here's a url to +one of the relevant sections: + http://www.gnu.org/software/texinfo/manual/texinfo/html_node/Document-Permissions.html + +4.2 (1 April 2002) +* Language: + . new command @copying to define copying permissions. See above. + . new conditionals @ifplaintext, @ifnotplaintext for the plain text + (--no-headers) output format. + . new command @\ to produce literal \ inside @math, since \ by itself + no longer works. +* makeinfo: + . emit accesskey attributes for keyboard shortcuts to menu items. + . @{even,every,odd}{footing,header} are ignored by makeinfo now, so + they no longer need to be enclosed in @iftex. +* texinfo.tex: + . bug fix for pdf-format table of contents. +* info: + . bug fixes for -R (--raw-escapes). + . --help shows short option names. +* Distribution: + . the doc.c, funs.h, and key.c files in info/ are no longer generated + at make time, to appease Automake's make distcheck. + . gettext 0.11.1, autoconf 2.53, automake 1.6 (with install-info kludge). + + +4.1 (4 March 2002) +* Language: + . new commands @verbatim and @verb for printing verbatim inserts. + . new command @verbatiminclude for verbatim include of files. + . new environment @documentdescription for defining the HTML description. + . new command @afivepaper for the A5 paper size. +* makeinfo: + . supports xml and docbook output. + . supports HTML splitting by node, which is now the default. + . new option --split-size to control maximum size of split info files. + . new option --enable-encoding to enable +* info: + . user-specified key bindings supported. + . ANSI escape sequences (as produced by groff) removed from man output + by default; use --raw-escapes to let them through if your terminal + supports them. + . RET terminates incremental search normally. +* texinfo.tex: + . @math implies @tex, so all the usual plain TeX math is supported. + . smaller fonts for @smallexample, in all page sizes. + . improvements in the PDF support. +* texi2dvi: + . new option -o to explicitly specify output filename. +* Distribution: + . switch to GNU Free Documentation License (http://www.gnu.org/copyleft/). + . update to GNU gettext 0.11, autoconf 2.52, and automake 1.5. + . Danish, Swedish, and Hebrew message translations. + + +4.0 (28 September 1999) +* Language: + . New command @anchor for cross references to arbitrary points. + . New commands @documentlanguage sets the main document language, + and @documentencoding sets the document input encoding (although not + much is done yet with either). + . New command @pagesizes allows limited control of text area for typesetting. + . New command @acronym for abbreviations in all caps, such as `NASA'. + . New command @alias for simple command aliases. + . New command @definfoenclose for better control of info output. + . New commands @deftypeivar for typed instance variables of a class + and @deftypeop for typed operations of a class. + . New command @novalidate suppresses cross-reference checking and (in + TeX) auxiliary file creation. + . New commands @setcontentsaftertitlepage and + @setshortcontentsaftertitlepage to force printing the table of + contents after @end titlepage. Also, @contents and @shortcontents + themselves can now appear at the beginning of the document as + well as the end. + . New markup commands: @env (for environment variables), @command (for + command names), @option (for command-line options). + . New commands @smallformat and @smalldisplay, a la @smallexample. + . New command @exampleindent to set indentation of example-like + environments a la @paragraphindent. + . @uref takes an optional third argument of text to show instead of + (rather than in addition to) the url for info and dvi output. + . @footnote works in an @item for a @table. +* texinfo.tex: + . latest version always at ftp://ftp.gnu.org/gnu/texinfo/texinfo.tex + (and mirrors). + . implements @macro. + . implements @paragraphindent (except asis). + . @emph and @i use true italic type (cmti) instead of slanted (cmsl). + . implements pdf output when run with pdftex. + . better support for internationalization via txi-??.tex files. + . footnotes now set in a smaller point size. +* makeinfo: + . supports HTML output with the --html option. + . implication of --html: @top nodes should be wrapped in @ifnottex + rather than @ifinfo. @ifinfo conditionals are not expanded with --html. + . new option --number-sections to output chapter/section numbers. + . dashes and quotes are not treated specially in node names. + . new option --commands-in-node-names to allow @-commands in node names. + (Not implemented in TeX, and most likely never will be.) + . @emph output uses _underscores_. + . @image looks for .png files before .jpg. + . only output `Making ... file' line when verbose. + . allow -v as synonym for --verbose. + . new command line options to specify which conditionals to process + (but --iftex is not fully implemented). + . warns if @var contains any of ,[](). + . @quote-arg implicitly done for all one-argument macros, so commas in + the argument text are allowed. + . \\ required in macro body to get single \, no other `escapes' defined. +* info: + . ISO Latin 1 characters are displayed and input as-is by default. + . new option --vi-keys to enable vi-like and less-like key bindings. + . new command S does case-sensitive searching. + . new commands C-x n and C-x N repeat last search, respectively, in the + same and in reverse direction, without prompting for the string. These + commands are bound to n and N under --vi-keys, like in Less. + . new command G menu1 menu2 ... searches for menu items from (dir), + as allowed on the command line. + . new command O (capital o, not zero) goes directly to the node that + describes command-line options. + . new command-line option --show-options causes the node which + describes command-line options to be the first node displayed. + . M-prior and M-DEL do new command info-scroll-other-window-backward. + . / searches like s does. + . If the search string includes upper-case letters, in both incremental + and non-incremental search, the search is case-sensitive. + . S searches case-sensitively even if the search string is all + lower-case. + . - makes the argument negative (so e.g. `- /' searches backward). + . l restores point in the window returned to. + . SPC/DEL do not move outside the current document. + . foo.info is found before foo. + . `info foo --index-search=bar' now searches for bar in foo's index. + . support for files compressed with bzip2. +* install-info: + . handles gzipped dir files. + . sort entries into alphabetical order. + . install direntries only in preceding dircategory, not in all. + . --delete does not require the info file to exist. + . --delete can handle XEmacs-style dir entries. +* texi2dvi: + . bug fixed: now uses only the @iftex and @tex parts of the source. + . process LaTeX source as well as Texinfo source. + . output PDF (using pdftex) with new option --pdf. + . handles --OPTION=ARG style of command line arguments. + . new option --batch for progress reports but no interaction. + . new option --clean to remove all auxiliary files. + . new option --quiet for silence (unless there are errors). + . new option -I for specifying directories for @include to search. + . handles LaTeX files (running BibTeX etc.). +* Fixes to util/gen-dir-node and util/fix-info-dir (formerly util/update-info). +* Distribution: + . Man pages included. + . Czech and Norwegian message translations. + . Various translations for texinfo.tex fixed words included. + . DJGPP support. + + +3.12 (3 March 1998) +* Elisp files removed, since they are only usefully distributed with Emacs. +* Restore inclusion of compile-time $(infodir) to INFOPATH. +* install-info creates a proper dir file. +* Various portability fixes. + + +3.11 (31 July 1997) +* New commands: + - @uref to make a reference to a url; @url now only indicates such. + - @image to include graphics (epsf for TeX). + - @deftypemethod and @deftypemethodx to document methods in strongly + typed object-oriented languages, such as C++. + - @html for raw HTML. + - @ifnothtml @ifnotinfo @ifnottex for more precise conditionals. + - @kbdinputstyle to control when @kbd uses the slanted typewriter font. + - @email takes second optional argument. +* texinfo.tex reads texinfo.cnf (if present) for site-wide TeX + configuration; for example, A4 paper sizes. +* info: + - arrow keys supported. + - trailing : in INFOPATH appends default path. + - new option --index-search for online help support. +* makeinfo: + - output files removed if errors unless (new option) --force. + - new option -P to prepend to search path. + - macro expansion file can be standard output. +* install-info creates a new dir file if necessary. +* update-info script to create a dir file from all info files. +* Elisp: texnfo-tex.el and detexinfo.el removed from the distribution; + - texnfo-tex features are now part of standard TeX & Texinfo packages; + - makeinfo --no-headers does a better job than detexinfo.el. +* Documentation: + - Updates, revisions, corrections in the manual. + - makeinfo.texi removed, as it was a copy of what was in texinfo.texi. +* gettext support in sources, French and German translations included. +* info man page removed; use the Texinfo manual. +* Automake used, other portability fixes. + +3.10 (omitted) + + +3.9 (4 October 1996) +* makeinfo: + - Give a suppressible (with --no-validate) error for references + outside of any node. + - Keep track of multitable output correctly for split files; this + caused nodes after the first multitable to be ``undefined''. +* install-info: + - Rename --infodir option to --info-dir. + - More robust error checking to avoid various crashes. +* configure: Include replacements for memcpy and memmove functions in + the distribution, in case they are missing. + + +3.8 (30 September 1996) +* Define and/or document new and/or previously existing commands: + Accents: @" @' @, @" @= @^ @` @~ @H @d @dotaccent @dotless @ringaccent + @tieaccent @u @ubaraccent @v + Special characters: @AA @AE @L @O @OE @aa @ae @exclamdown @l @o @oe + @pounds @questiondown @ss + Special punctuation: @! @? @enddots + dir file maintenance: @dircategory @direntry; also new program, install-info + HTML support: @email @url @ifhtml...@end ifhtml + Macros: @macro @unmacro + Tables: @multitable @tab + Hyphenation: @- @hyphenation + Spacing: @ @<TAB> @<NEWLINE> + Sectioning: + @headings singleafter/doubleafter (change heading style after current page) + @centerchap + @setchapterstyle + Other: + @shorttitlepage (simple title pages) + @detailmenu...@end detailmenu (help makeinfo parse master menus) +* Makeinfo prefers an input file named `foo.texinfo' or `foo.texi' or + `foo.txinfo' to just `foo' (the latter most likely being an executable). +* Makeinfo implements @. @! @? correctly, as end-of-sentence punctuation. +* @key marks its argument with a lozenge in TeX and <...> in Info. +* TeX output has substantially decreased interline spacing and other + formatting changes. +* Remove these obsolete and never-documented commands: + @infotop + @infoappendix @infoappendixsec @infoappendixsubsec @infoappendixsubsubsec + @infochapter @infosection @infosubsection @infosubsubsection + @infounnumbered @infounnumberedsec @infounnumberedsubsec + @infounnumberedsubsubsec + @input + @smallbreak @medbreak + @overfullrule + @br +* Deprecate these obsolete commands, to be removed in the next release: + @ctrl + @infoinclude + @iappendix @iappendixsection @iappendixsec @iappendixsubsec + @iappendixsubsubsec + @ichapter @isection @isubsection @isubsubsection + @iunnumbered @iunnumberedsec @iunnumberedsubsec @iunnumberedsubsubsec + @setchapterstyle + @titlespec + + +3.7 (24 December 1995) +* Have --version print texinfo release number as well as the individual + program version. +* Better man page cleaning. +* Update Elisp files from current Emacs release. + + +3.6 (21 June 1995) +* Unmatched brace error reporting improved. +* Missing comment terminator prevented compilation. + + +3.5 (20 June 1995) +* Autoconf update. +* Support for parallel makes. +* make install does not install Elisp files. + + +3.4 (19 June 1995) +* Handle @ifhtml in Elisp. +* Update FSF address. + + +3.3 (15 June 1995) +* Portability changes. +* Compile Elisp files. +* Don't distribute .info* files. + + +3.2 (9 June 1995) +* Standalone Info can read Unix man pages. +* New commands: @! @? @^ @" @enddots. +* makeinfo -E does macro expansion (and nothing else). + + +3.1 (23 May 1993) +Just bug fixes, see ChangeLog for full details. + + +3.0: first release of Texinfo version 2, with many new commands. + + + +Here is the separate NEWS for old releases of Info: + +Version 2.11, Sat Apr 1 09:15:21 1995 + +Changes since 2.7 beta: + +Although the basic code remains the same, there are numerous nits +fixed, including some display bugs, and a memory leak. Some changes +that have taken place with larger impact include the way in which the +(dir) node is built; I have added in support for "localdir" +directories among other things. Info files may be stored in +compressed formats, and in their own subdirectories; menu items which +do not explicitly name the node to which they are attached have the +menu item name looked up as an Info file if it is not found within the +current document. This means that the menu item: + +* Info:: The Info documentation reader. + +in (dir) refers to the info node "(info)Top". + +Please see the ChangeLog and documentation for details on other +changes. + +Version 2.7 beta, Wed Dec 30 02:02:38 1992 +Version 2.6 beta, Tue Dec 22 03:58:07 1992 +Version 2.5 beta, Tue Dec 8 14:50:35 1992 +Version 2.4 beta, Sat Nov 28 14:34:02 1992 +Version 2.3 beta, Fri Nov 27 01:04:13 1992 +Version 2.2 beta, Tue Nov 24 09:36:08 1992 +Version 2.1 beta, Tue Nov 17 23:29:36 1992 + +Changes since 2.5 beta: + +Note that versions 2.6 and 2.7 Beta were only released to a select group. + +* "info-" removed from the front of M-x commands. + +* Automatic footnote display. When you enter a node which contains + footnotes, and the variable "automatic-footnotes" is "On", Info pops + up a window containing the footnotes. Likewise, when you leave that + node, the window containing the footnotes goes away. + +* Cleaner built in documentation, and documentation functions. + + Use: + o `M-x describe-variable' to read a variable's documentation + o `M-x describe-key' to find out what a particular keystroke does. + o `M-x describe-function' to read a function's documentation. + o `M-x where-is' to find out what keys invoke a particular function. + +* Info can "tile" the displayed windows (via "M-x tile-windows"). If + the variable "automatic-tiling" is "On", then splitting a window or + deleting a window causes the remaining windows to be retiled. + +* You can save every keystroke you type in a "dribble file" by using the + `--dribble FILENAME' option. You can initially read keystrokes from an + alternate input stream with `--restore FILENAME', or by redirecting + input on the command line `info < old-dribble'. + +* New behaviour of menu items. If the label is the same as the + target node name, and the node couldn't be found in the current file, + treat the label as a file name. For example, a menu entry in "DIR" + might contain: + + * Emacs:: Cool text-editor. + + Info would not find the node "(dir)Emacs", so just plain "(emacs)" + would be tried. + +* New variable "ISO-Latin" allows you to use European machines with + 8-bit character sets. + +* Cleanups in echo area reading, and redisplay. Cleanups in handling the + window which shows possible completions. + +* Info can now read files that have been compressed. An array in filesys.c + maps extensions to programs that can decompress stdin, and write the results + to stdout. Currently, ".Z"/uncompress, ".z"/gunzip, and ".Y"/unyabba are + supported. The modeline for a compressed file shows "zz" in it. + +* There is a new variable "gc-compressed-files" which, if non-zero, says + it is okay to reclaim the file buffer space allocated to a file which + was compressed, if, and only if, that file's contents do not appear in + any history node. + +* New file `nodemenu.c' implements a few functions for manipulating + previously visited nodes. `C-x C-b' (list-visited-nodes) produces a + menu of the nodes that could be reached by info-history-node in some + window. `C-x b' (select-visited-node) is similar, but reads one of + the node names with completion. + +* Keystroke `M-r' (move_to_screen_line) allows the user to place the cursor at + the start of a specific screen line. Without a numeric argument, place the + cursor on the center line; with an arg, place the cursor on that line. + +* Interruptible display implemented. Basic display speedups and hacks. +* The message "*** Tags Out of Date ***" now means what it says. +* Index searching with `,' (info-index-next) has been improved. +* When scrolling with C-v, C-M-v, or M-v, only "Page Only" scrolling + will happen. + +* Continuous scrolling (along with `]' (info-global-next) and `[' + (info-global-prev) works better. `]' and `[' accept numeric + arguments, moving that many nodes in that case. + +* `C-x w' (info-toggle-wrap) controls how lines wider than the width + of the screen are displayed. If a line is too long, a `$' is + displayed in the rightmost column of the window. + +* There are some new variables for controlling the behaviour of Info + interactively. The current list of variables is as follows: + + Variable Name Default Value Description + ------------- ------------- ----------- + `automatic-footnotes' On When "On", footnotes appear and + disappear automatically. + + `automatic-tiling' Off When "On", creating of deleting a + window resizes other windows. + + `visible-bell' Off If non-zero, try to use a visible bell. + + `errors-ring-bell' On If non-zero, errors cause a ring. + + `show-index-match' On If non-zero, the portion of the string + matched is highlighted by changing its + case. + + `scroll-behaviour' Continuous One of "Continuous", "Next Only", or + "Page Only". "Page Only" prevents you from + scrolling past the bottom or top of a node. + "Next Only" causes the Next or Prev node to + be selected when you scroll past the bottom + or top of a node. "Continous" moves + linearly through the files hierarchical + structure. + + `scroll-step' 0 Controls how scrolling is done for you when + the cursor moves out of the current window. + Non-zero means it is the number of lines + you would like the screen to shift. A + value of 0 means to center the line + containing the cursor in the window. + + `gc-compressed-files' Off If non-zero means it is okay to reclaim the + file buffer space allocated to a file which + was compressed, if, and only if, that + file's contents do not appear in the node + list of any window. + + `ISO-Latin' Off Non-zero means that you are using an ISO + Latin character set. By default, standard + ASCII characters are assumed. +________________________________________ +This release of Info is version 2.5 beta. + +Changes since 2.4 beta: + +* Index (i) and (,) commands fully implemented. +* "configure" script now shipped with Info. +* New function "set-variable" allows users to set various variables. +* User-settable behaviour on end or beginning of node scrolling. This + supersedes the SPC and DEL changes in 2.3 beta. + +________________________________________ +This release of Info is version 2.4 beta. + +Changes since 2.3 beta: + +* info-last-node now means move to the last node of this info file. +* info-history-node means move backwards through this window's node history. +* info-first-node moves to the first node in the Info file. This node is + not necessarily "Top"! +* SPC and DEL can select the Next or Prev node after printing an informative + message when pressed at the end/beg of a node. + +---------------------------------------- +This release of Info is version 2.3 beta. + +Changes since 2.2 beta: + +* M-x command lines if NAMED_COMMANDS is #defined. Variable in Makefile. +* Screen height changes made quite robust. +* Interactive function "set-screen-height" implements user height changes. +* Scrolling on some terminals is faster now. +* C-l with numeric argument is fixed. + +---------------------------------------- +This release of Info is version 2.2 beta. + +Changes since 2.0: + +* C-g can now interrupt multi-file searches. +* Incremental search is fully implemented. +* Loading large tag tables is much faster now. +* makedoc.c replaces shell script, speeding incremental builds. +* Scrolling in redisplay is implemented. +* Recursive uses of the echo area made more robust. +* Garbage collection of unreferenced nodes. diff --git a/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README new file mode 100644 index 0000000..a6f5ed5 --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README @@ -0,0 +1,119 @@ +This is the README file for the GNU Texinfo distribution. Texinfo is +the preferred documentation format for GNU software. + + Copyright 1992-2022 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. + +Home page: https://www.gnu.org/software/texinfo/ + +Primary distribution point: https://ftp.gnu.org/gnu/texinfo/ + automatic mirror redirection: https://ftpmirror.gnu.org/texinfo/ + mirror list: https://www.gnu.org/prep/ftp.html + +Texinfo is a documentation system that uses a single source to produce +many forms of output: +- a PDF or DVI document (via the TeX typesetting system) with the normal + features of a book, including sectioning, cross references, indices, etc. +- an Info file with analogous features +- a plain text (ASCII) file +- HTML output suitable for use with a web browser +- an EPUB 3 e-book +- a LaTeX file, which can then be used to create a PDF +- a Docbook file + +See ./INSTALL* for installation instructions. + +To get started with Texinfo, you can read the Texinfo manual +online at https://www.gnu.org/software/texinfo/manual/texinfo. + +If you don't have Internet access, you can read the manual locally: +- first, build the distribution. +- then, for HTML, run: make -C doc html + and you can start reading at doc/texinfo_html/index.html. +- for PDF, if you have a working TeX, run: make -C doc pdf +- for Info, you can read the manual: + ./info/ginfo doc/info-stnd + and/or read the Texinfo manual: + ./info/ginfo doc/texinfo + +Texinfo mailing lists and archives: +- https://lists.gnu.org/mailman/listinfo/bug-texinfo + for bug reports, enhancement suggestions, technical discussion. +- https://lists.gnu.org/mailman/listinfo/help-texinfo + for authoring questions and general discussion. + +Bug reports: +Please include enough information for the maintainers to reproduce the +problem. Generally speaking, that means: +- the contents of all input files needed to reproduce the bug (crucial!). +- a statement of the problem and any samples of the erroneous output. +- the version number of Texinfo and the program(s) involved (use --version). +- hardware and operating system information (uname -a). +- unusual options you gave to configure, if any (try ./config.status --help). +- anything else that you think could be helpful. + +Patches are welcome; if possible, please make them with diff -c or +git diff and include ChangeLog entries. + +See README-hacking for information on the Texinfo development +environment -- any interested parties are welcome. If you're a +programmer and wish to contribute, this should get you started. + +This distribution includes the following files, among others: + README This file. + README-hacking Texinfo developer information. + + INSTALL Texinfo-specific installation notes. + NEWS Summary of new features by release. + +Texinfo documentation files + doc/texinfo.texi Describes the Texinfo language and many + of the associated tools. It tells how to use + Texinfo to write documentation, how to use + Texinfo mode in GNU Emacs, TeX, texi2any, and + much else. + + doc/info-stnd.texi How to use the standalone GNU Info reader that is + included in this distribution (./info). + +Printing-related files: + doc/texinfo.tex This implements Texinfo in TeX, to typeset a + Texinfo file into a DVI or PDF file. + + util/texi2dvi This is a shell script for producing an + indexed DVI file using TeX and texindex. + + util/texi2pdf Generate PDF (wrapper for texi2dvi). + +Source directories: + djgpp/ Support for compiling under DJGPP. + gnulib/ Support files from Gnulib. + info/ Standalone Info reader. + install-info/ Maintain the Info dir file. + tp/ Texinfo Parser in Perl, includes texi2any. + texindex/ The `texindex' program that generates + sorted indices used by TeX when + typesetting a file for printing. + +Translation support: + po/ Strings of the programs. + po_document/ Strings in generated Texinfo documents. + +Installation support: + Makefile.am Read by Automake to create a Makefile.in. + Makefile.in Read by configure to make a Makefile, + created by Automake. + configure.ac Read by Autoconf to create `configure'. + configure Configuration script for local conditions, + created by Autoconf. + build-aux/ Common files. + +The util/ directory contains a few other scripts, e.g., examples of +using texi2any in various ways. See util/README. + +Some files in this package have their copyright years stated as a range +('2008-2010') rather than listed as individual years ('2008, 2009, +2010'). diff --git a/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README-hacking b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README-hacking new file mode 100644 index 0000000..5a92d9b --- /dev/null +++ b/openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README-hacking @@ -0,0 +1,362 @@ +This file describes the development environment for Texinfo. + + Copyright 2002-2022 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. + +The development sources for GNU Texinfo are available through git +at Savannah: + https://savannah.gnu.org/git/?group=texinfo + +This distribution uses whatever versions of Automake, Autoconf, and +Gettext are listed in NEWS; usually the latest official releases. If +you are getting the sources from the development repository (or change +configure.ac), you'll need to have these tools installed to (re)build. +You'll also need help2man. If you modify texindex/ti.twjr, you'll need +gawk >= 4.0. All of these programs are available from +http://ftp.gnu.org/gnu. + +After getting the development sources, and installing the tools above, +you can run + ./autogen.sh +and then, for example, + ./configure -C CFLAGS='-g' PERL_EXT_CFLAGS='-g' +and then + make + +The -C tells configure to cache test results, which usually speeds +things up a bit. + +After the initial autogen && configure, simply running make should suffice. + +Gettext or help2man not installed do not cause configure to fail, +though configure shows if they were found. This is because a release +does not require those tools. Indeed, both prerequisites and +result files are shipped in a release, such that the tools are only +needed if the prerequisite changed. The tools are needed when building +from developpement sources, however, as result files are not under version +control. Make will fail with an explicit missing command for help2man, +and with a command not found error for a Gettext utility command. + +Running make in one particular subdirectory is possible, for example +make -C info. However there are interdependencies between the +subdirectories, notably on gnulib, so if you don't want to run "make", +you may have to run "make -C gnulib/lib" first. + +Additionally, make dist may not work until make has been run at least +once, because of rules to create man pages under the man/ directory. + +"make dist" will fail if the use of Perl XS extension modules is +disabled and there is no Makefile in the XSParagraph subdirectory. + + +Using git +--------- + +This section is if you have write access to the git repository. + +Usually commits to the git repository should include a ChangeLog +entry. Please follow the existing style (the GNU Coding Standards +has a guide). + +You can automatically use the contents of the most recent ChangeLog +entry with a git commit hook .git/hooks/prepare-commit-msg + +------------------------------------ +#!/bin/sh + +# $1 - file that contains commit log message +# $2 - source of commit message + +outfile="$1" + +case $2 in + message|template|merge|squash|commit) + ;; + *) + # Use latest ChangeLog entry as commit message + sed -n -e '1,/^\w*$/d' -e '/^[^ ]/q' -e '{s/^ //;p}' ChangeLog >"$outfile" +;; +esac +------------------------------------ + +When unable to push commits due to other commits being made, please +use "git pull --rebase" (the default for "git pull" complicates the +git history). To deal with conflicts in the ChangeLog, you should +install the git-merge-changelog program. + +You can get better output from "git diff" for Texinfo files by putting +the following section in your .gitconfig file: + +[diff "texinfo"] + xfuncname = "^(@node .*)$" + +This shows which node each change occurred in. + + +Gnulib +------ + +This distribution uses Gnulib (http://www.gnu.org/software/gnulib) +to share common files. Gnulib files used in Texinfo are checked in to +the repository. A Gnulib directory is setup in two locations, in +the main directory and in tp/Texinfo/XS/. + +To update the gnulib files, get a checkout of gnulib in a separate +directory, then run, say + + ../gnulib/gnulib-tool --add-import + +in your top-level Texinfo directory and + + ../../../../gnulib/gnulib-tool --add-import + +under tp/Texinfo/XS. (gnulib-tool is in the gnulib source tree.) + +The currently-used gnulib modules and other gnulib information are +recorded in gnulib/m4/gnulib-cache.m4. + +gnulib-tool --add-import may also be used to add another gnulib module: + ../gnulib/gnulib-tool --add-import other_gnulib_module + +After running gnulib-tool --add-import or otherwise adding modules, it is +necessary to check what files were added or removed (e.g., run "git +status -u") and add new files to the repository with "git add". +Add any new generated files (typically gnulib/lib/foo.h from foo.h.in) +to the ignore list in .gitignore. + + +Subdirectories in repository +---------------------------- + +In addition to the subdirectories listed in README, there is the +following directory in the source control repository: + +js/ - Work on enhanced browsing of HTML manuals with JavaScript +infog/ - HTML-Info reader using WebKitGTK library + +Finally, the contrib/ directory contains additional files from users +provided for your reading and/or hacking pleasure. They aren't part of +Texinfo proper or maintained by the Texinfo developers. + + + + +About running the Texinfo programs from a development source tree: + +- Once the distribution is built, you can run the compiled programs +(info, install-info) out of the build tree without special settings; +they don't try to read any installed data files. + +- The texi2dvi script and texinfo.tex can be run as-is, since they +are standalone and don't require compilation. For the same reasons, +they are officially updated between full Texinfo releases, at +http://ftpmirror.gnu.org/texinfo. + +- Regarding texi2any (aka makeinfo), you can run tp/texi2any.pl +directly. This is the original source file for the program, so it's +convenient to be able to make changes and then run it. + +To run the output "tp/texi2any" instead, you can set the environment +variable TEXINFO_DEV_SOURCE to 1. Otherwise, it will try to use +Texinfo's Perl modules in the installed locations. "tp/texi2any" uses +the Perl interpreter found by configure, so you might want to run that +instead of texi2any.pl if it's different to the default interpreter in +your environment. + + + +References for working on various parts of the system: + +If you want to delve into making a new backend for the Perl makeinfo, +the documentation in tp/Texinfo/Convert/Converter.pm is a good starting +point, as it describes the existing backends and other places to look. + +If you want to delve into texinfo.tex, a thorough plain TeX reference +is available under the GFDL: + TeX by Topic - http://www.eijkhout.net/texbytopic/texbytopic.html +Another book on plain TeX, also available under the GFDL, is a GNU package: + TeX for the Impatient - http://www.gnu.org/software/teximpatient/ +Occasionally you may need to know about the details of the PDF format. +A reference for this is the PDF reference, Sixth Edition, version 1.7, +downloadable at http://www.adobe.com/devnet/pdf/pdf_reference_archive.html + +The texindex program is implemented using the TexiWebJR literate +programming system, combining Texinfo and Awk +(https://github.com/arnoldrobbins/texiwebjr). Running "make ti.pdf" +in the texindex/ subdirectory creates the printable form of the +program. All the usual Texinfo output formats are possible. + + + +Steps for making a release (pretest or official): + +- When close to official release: + +check at latest automake/autoconf/gettext version, and mention in NEWS +(to upgrade gettext, run + gettextize -f --po-dir=po --po-dir=po_document +after installing new version of gettext. +check that this does not actually downgrade files due to files also +being updated from gnulib --add-import) + +# Under the top level, and also under tp/Texinfo/XS, which uses +# a separate gnulib import. +gnulib-tool --add-import +'git status -u' and add untracked files + +After upgrading automake/autoconf/gettext, run ./autogen.sh +and/or "autoreconf --verbose --force --install" to update ancilliary +files in build-aux and elsewhere. Check changes before committing. + +Use util/srclist-txi for checking files to be copied from gnulib + +run all tests with valgrind: +* under info/t, put valgrind in $ginfo, then check t/*.val.log files after + running test suite +* edit install-info/tests/defs.in, uncomment valgrind line and run + config.status to regenerate defs + +parsetexi memory leak checks with valgrind + +NYTProf profiling for Perl code +* e.g. 'perl -d:NYTProf ../tp/texi2any.pl FILE.texi'. See Devel::NYTProf + man page. + + +try groff.texinfo from groff source repo. +Check "make ccheck" and "make vcheck" work in "doc/refcard". +process doc/texinfo-tex-test.texi with TeX and check that output is good. +check for C compiler warnings by configuring with + + ./configure CFLAGS='-Wall -Wdeclaration-after-statement' \ + PERL_EXT_CFLAGS='-Wall -Wdeclaration-after-statement' + +-Wdeclaration-after-statement is useful because a) intermixing +declarations with statements is an easy thing to do accidentally, +b) gcc doesn't warn about it by default, and c) other compilers that +don't support it are still widespread. + +Not all compiler warnings have to be fixed, though. + +Have a look at the output of "git status -u" to check for files that + should be tracked in git or ignored. +make po-check # update po/POTFILES.in as needed + +check indices of Texinfo manuals and check for duplicates (with <1> in Info) + +- Official releases only: +make V=1 pdf and fix underfull/overfull boxes. + +- Final (easy) checks: + +check OpenCSW build reports at + https://buildfarm.opencsw.org/buildbot/waterfall?category=texinfo +Check that translations have been updated, e.g.: + rsync -Lrtzv translationproject.org::tp/latest/texinfo/ po + rsync -Lrtzv translationproject.org::tp/latest/texinfo_document/ \ + po_document # note the trailing slashes in these commands +make +make update-po # both po and po_document needed, build a dist first +Ensure texinfo.tex, texi2dvi, and htmlxref.cnf are updated on ftp.gnu.org. +Ensure TXI_XLATE in doc/Makefile.am matches actual file list. +Check that LINGUAS under po and po_document match actual file list. +Check that TEXINFO_DTD_VERSION has been updated to the next version in + configure.ac if the DTD has been modified since the last release. + See comments in configure.ac, and run (at the top level) make dtd-check. +Check "dist-xz" is in the option list in configure.ac (often removed +for speed when testing). +update version in configure.ac, notice in ChangeLog. +check up to date copyright years in files relevant to --version calls +(tp/texi2any.pl, info/info.c, install-info/install-info.c) +version number in texi2dvi, texi2pdf, txirefcard.tex. +check that texindex version is updated properly + (cd texindex ; rm texindex.awk ; make) +(cd tp && ./maintain/change_perl_modules_version.sh auto) + -- this updates all the version numbers in the Perl modules +(cd tp ; maintain/regenerate_file_lists.pl) # list all test results + +- Official releases only: +version and date in NEWS. +version number in txirefcard.tex. +(cd tp && maintain/regenerate_documentlanguages-loc.pl) + -- regenerates tp/Texinfo/Documentlanguages.pm (requires Text::CSV) + +one last "git diff" to check release commit looks good +make distcheck +(export MALLOC_CHECK_=2; make distcheck) # repeat until clean +git commit and push + +after uploading distribution, +pretest announcement -> bug-texinfo / beebe / platform-testers to try. +bcc coordinator@translationproject.org. + + + +- To do the actual upload: +pkg=texinfo +ver=7.0 + +then do one of: +gnupload --to alpha.gnu.org:$pkg $pkg-$ver.tar.xz #pretest +gnupload --to ftp.gnu.org:$pkg $pkg-$ver.tar.{gz,xz} *.diff.xz #official + Use --user option if not using default key + texinfo.tex and texi2dvi should already be up to date, but check. Use +gnupload --replace --to ftp.gnu.org:texinfo texi2dvi + +# Official releases only: tag source tree +git tag texinfo-6.6 +git push --tags + +# ... set up dtd directory on web pages: +cd $HOME/gnu/www/texinfo/dtd # or wherever webpages checkout is +mkdir $ver && cvs add $ver +cp $tutil/texinfo.dtd $ver +cvs add -kb $ver $ver/texinfo.dtd +cvs commit -m$ver $ver + + +- When official release is out there ... +update home page (texinfo.html) and commit as needed. +including: + pod2html $txi/Pod-Simple-Texinfo/pod2texi.pl \ + | grep -Fv 'rev="made"' >manual/pod2texi.html + +check for http links that should be changed to https - then delete +this item + +Build web documentation with + make -C doc wwwdoc-build + +Copy documentation files to web checkout with, e.g. + make -C doc \ + wwwdoc-install www_target=../../TEXINFO_WEB_PAGES/texinfo/manual/ +Check for removed files with, e.g. ls -ltu $(www_target)/*/html_node, +followed by cvs rm -f. Likewise, check for added files with +cvs -qn update, followed by cvs add. When done, run cvs commit. + +# Official releases only: Contact root@tug.org to update texinfo at tug.org. +# If root@tug.org doesn't reply, can try webmaster@tug.org, +# or (last resort) board@tug.org. + + +# For official releases: +send announcement to info-gnu, + cc bug-texinfo and bcc coordinator@translationproject.org. +news item at savannah. + +# ... post-release, or when development resumes: +configure.ac, util/texi2dvi: add "dev" to versions for clarity, +until it's time to do pretests again. + +after next release: +rename old ChangeLog and start a new one +check TODO file and do pending tasks +discuss on mailing list changing the git branch structure to allow quick + bug fix releases for severe bugs (e.g. glibc 2.34 incompatibility, info crash + in Brazillian Portuguese locale) +delete these lines from README-hacking + + diff --git a/openocd-win/openocd/distro-info/scripts/README-OUT.md b/openocd-win/openocd/distro-info/scripts/README-OUT.md new file mode 100644 index 0000000..4e7bbf2 --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/README-OUT.md @@ -0,0 +1,14 @@ +# The xPack OpenOCD + +The **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD) +is the **xPack** version of **OpenOCD**, +an open-source project. + +For more details, please read the corresponding release pages: + +- <https://xpack.github.io/openocd/releases/> +- <https://openocd.org> + +Thank you for using open source software, + +Liviu Ionescu diff --git a/openocd-win/openocd/distro-info/scripts/VERSION b/openocd-win/openocd/distro-info/scripts/VERSION new file mode 100644 index 0000000..c78e7e5 --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/VERSION @@ -0,0 +1 @@ +0.12.0-2 diff --git a/openocd-win/openocd/distro-info/scripts/application.sh b/openocd-win/openocd/distro-info/scripts/application.sh new file mode 100644 index 0000000..586696a --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/application.sh @@ -0,0 +1,45 @@ +# ----------------------------------------------------------------------------- +# This file is part of the xPack distribution. +# (https://xpack.github.io) +# Copyright (c) 2019 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# Application specific definitions. Included with source. + +# Used to display the application name. +XBB_APPLICATION_NAME=${XBB_APPLICATION_NAME:-"OpenOCD"} + +# Used as part of file/folder paths. +XBB_APPLICATION_LOWER_CASE_NAME=${XBB_APPLICATION_LOWER_CASE_NAME:-"openocd"} + +XBB_APPLICATION_DISTRO_NAME=${XBB_APPLICATION_DISTRO_NAME:-"xPack"} +XBB_APPLICATION_DISTRO_LOWER_CASE_NAME=${XBB_APPLICATION_DISTRO_LOWER_CASE_NAME:-"xpack"} +XBB_APPLICATION_DISTRO_TOP_FOLDER=${XBB_APPLICATION_DISTRO_TOP_FOLDER:-"xPacks"} + +XBB_APPLICATION_DESCRIPTION="${XBB_APPLICATION_DISTRO_NAME} ${XBB_APPLICATION_NAME}" + +declare -a XBB_APPLICATION_DEPENDENCIES=( openocd ) +declare -a XBB_APPLICATION_COMMON_DEPENDENCIES=( libusb1 libusb-w32 libusb0 libftdi libiconv hidapi autotools texinfo ) + +# ----------------------------------------------------------------------------- + +XBB_GITHUB_ORG="${XBB_GITHUB_ORG:-"xpack-dev-tools"}" +XBB_GITHUB_REPO="${XBB_GITHUB_REPO:-"${XBB_APPLICATION_LOWER_CASE_NAME}-xpack"}" +XBB_GITHUB_PRE_RELEASES="${XBB_GITHUB_PRE_RELEASES:-"pre-releases"}" + +XBB_NPM_PACKAGE="${XBB_NPM_PACKAGE:-"@xpack-dev-tools/${XBB_APPLICATION_LOWER_CASE_NAME}@next"}" + +# ----------------------------------------------------------------------------- + +# If you want to build OpenOCD from another repo then uncomment the +# following defines and tweak as needed. + +# XBB_APPLICATION_OPENOCD_GIT_URL="https://github.com/openocd-org/openocd.git" +# XBB_APPLICATION_OPENOCD_GIT_BRANCH="master" +# XBB_APPLICATION_OPENOCD_GIT_COMMIT="HEAD" + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/scripts/build.sh b/openocd-win/openocd/distro-info/scripts/build.sh new file mode 100644 index 0000000..c4707de --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/build.sh @@ -0,0 +1,86 @@ +#!/usr/bin/env bash +# ----------------------------------------------------------------------------- +# DO NOT EDIT! Generated from xpacks/@xpack-dev-tools/xbb-helper/templates/*. +# +# This file is part of the xPack distribution. +# (https://xpack.github.io) +# Copyright (c) 2022 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d). + +if [[ ! -z ${DEBUG} ]] +then + set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty. +else + DEBUG="" +fi + +set -o errexit # Exit if command failed. +set -o pipefail # Exit if pipe failed. +set -o nounset # Exit if variable not set. + +# Remove the initial space and instead use '\n'. +IFS=$'\n\t' + +# ----------------------------------------------------------------------------- +# Identify the script location, to reach, for example, the helper scripts. + +build_script_path="$0" +if [[ "${build_script_path}" != /* ]] +then + # Make relative path absolute. + build_script_path="$(pwd)/$0" +fi + +script_folder_path="$(dirname "${build_script_path}")" +script_folder_name="$(basename "${script_folder_path}")" + +# ============================================================================= +# Build the application. + +scripts_folder_path="${script_folder_path}" +project_folder_path="$(dirname ${script_folder_path})" +helper_folder_path="${project_folder_path}/xpacks/@xpack-dev-tools/xbb-helper" + +# ----------------------------------------------------------------------------- + +source "${scripts_folder_path}/application.sh" + +# Common definitions. +source "${helper_folder_path}/scripts/build-common.sh" + +source "${scripts_folder_path}/versioning.sh" + +if [ ${#XBB_APPLICATION_COMMON_DEPENDENCIES[@]} -ne 0 ] +then + for dependency in ${XBB_APPLICATION_COMMON_DEPENDENCIES[@]} + do + echo "Including ${helper_folder_path}/dependencies/${dependency}.sh..." + source "${helper_folder_path}/dependencies/${dependency}.sh" + done +fi + +if [ ${#XBB_APPLICATION_DEPENDENCIES[@]} -ne 0 ] +then + for dependency in ${XBB_APPLICATION_DEPENDENCIES[@]} + do + echo "Including ${scripts_folder_path}/dependencies/${dependency}.sh..." + source "${scripts_folder_path}/dependencies/${dependency}.sh" + done +fi + +# ----------------------------------------------------------------------------- + +help_message=" bash $0 [--win] [--debug] [--develop] [--jobs N] [--help]" +build_common_parse_options "${help_message}" "$@" + +build_common_run + +exit 0 + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/scripts/dependencies/openocd.sh b/openocd-win/openocd/distro-info/scripts/dependencies/openocd.sh new file mode 100644 index 0000000..38f7ced --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/dependencies/openocd.sh @@ -0,0 +1,336 @@ +# ----------------------------------------------------------------------------- +# This file is part of the xPack distribution. +# (https://xpack.github.io) +# Copyright (c) 2019 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- + +function openocd_download() +{ + if [ ! -d "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}" ] + then + ( + cd "${XBB_SOURCES_FOLDER_PATH}" + git_clone "${XBB_OPENOCD_GIT_URL}" "${XBB_OPENOCD_GIT_BRANCH}" \ + "${XBB_OPENOCD_GIT_COMMIT}" "${openocd_src_folder_name}" + cd "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}" + git submodule update --init --recursive --remote + ) + fi +} + +# ----------------------------------------------------------------------------- + +# https://github.com/archlinux/svntogit-community/blob/packages/openocd/trunk/PKGBUILD + +# ----------------------------------------------------------------------------- + +function openocd_build() +{ + echo_develop + echo_develop "[${FUNCNAME[0]} $@]" + + local openocd_version="$1" + + local openocd_src_folder_name="${XBB_OPENOCD_SRC_FOLDER_NAME:-"openocd.git"}" + local openocd_folder_name="openocd-${openocd_version}" + + mkdir -pv "${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}" + + local openocd_stamp_file_path="${XBB_STAMPS_FOLDER_PATH}/stamp-${openocd_folder_name}-installed" + if [ ! -f "${openocd_stamp_file_path}" ] + then + ( + openocd_download + + xbb_activate_dependencies_dev + + cd "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}" + + ( + if [ ! -d "autom4te.cache" ] + then + ./bootstrap + fi + ) 2>&1 | tee "${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/configure-output-$(ndate).txt" + + # Personalise the greeting message + run_verbose sed -i.bak -e 's|"Open On-Chip Debugger "|"xPack Open On-Chip Debugger "|' "src/openocd.c" + + run_verbose diff "src/openocd.c.bak" "src/openocd.c" || true + + # Simplify protections for the USB devices, allow access for all. + run_verbose sed -i.bak -e 's|MODE="660".*|MODE="666"|' "contrib/60-openocd.rules" + + run_verbose diff "contrib/60-openocd.rules.bak" "contrib/60-openocd.rules" || true + + mkdir -pv "${XBB_BUILD_FOLDER_PATH}/${openocd_folder_name}" + cd "${XBB_BUILD_FOLDER_PATH}/${openocd_folder_name}" + + CPPFLAGS="${XBB_CPPFLAGS}" + CFLAGS="${XBB_CFLAGS_NO_W}" + CXXFLAGS="${XBB_CXXFLAGS_NO_W}" + + # It makes little sense to use -static-libgcc here, since + # several shared libraries will refer to it anyway. + LDFLAGS="${XBB_LDFLAGS_APP}" + + LIBS="" + if [ "${XBB_HOST_PLATFORM}" == "linux" ] + then + # LIBS+=" -lpthread -lrt -ludev" + LIBS+=" -ludev" + fi + + xbb_adjust_ldflags_rpath + + export CPPFLAGS + export CFLAGS + export CXXFLAGS + + export LDFLAGS + export LIBS + + export JAYLINK_CFLAGS='${XBB_CFLAGS} -fvisibility=hidden' + + if [ ! -f "config.status" ] + then + + # May be required for repetitive builds, because this is an executable built + # in place and using one for a different architecture may not be a good idea. + rm -rfv "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/jimtcl/autosetup/jimsh0" + + ( + xbb_show_env_develop + + echo + echo "Running openocd configure..." + + if [ "${XBB_IS_DEVELOP}" == "y" ] + then + bash "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/configure" --help + fi + + config_options=() + + config_options+=("--prefix=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}") + + config_options+=("--build=${XBB_BUILD_TRIPLET}") + config_options+=("--host=${XBB_HOST_TRIPLET}") + config_options+=("--target=${XBB_TARGET_TRIPLET}") + + config_options+=("--datarootdir=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}") + config_options+=("--localedir=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/share/locale") + + config_options+=("--mandir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/man") + config_options+=("--pdfdir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/pdf") + config_options+=("--infodir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/info") + config_options+=("--docdir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/") + + config_options+=("--disable-wextra") + config_options+=("--disable-werror") + config_options+=("--disable-gccwarnings") + config_options+=("--disable-doxygen-html") + config_options+=("--disable-doxygen-pdf") + + config_options+=("--disable-debug") # HB + config_options+=("--disable-dependency-tracking") # HB + if [ "${XBB_IS_DEVELOP}" == "y" ] + then + config_options+=("--disable-silent-rules") # HB + fi + + # The internal libjaylink is now deprecated. + # https://github.com/openocd-org/openocd/commit/8bb926eb01022998ceefe666f8df102e59404015 + config_options+=("--enable-internal-libjaylink") + + # Add explicit functionality. + config_options+=("--enable-aice") + config_options+=("--enable-armjtagew") + config_options+=("--enable-at91rm9200") + config_options+=("--enable-bcm2835gpio") + config_options+=("--enable-cmsis-dap") + config_options+=("--enable-dummy") + config_options+=("--enable-ep93xx") + config_options+=("--enable-ft232r") + config_options+=("--enable-ftdi") + config_options+=("--enable-imx_gpio") + config_options+=("--enable-jlink") + config_options+=("--enable-jtag_vpi") + config_options+=("--enable-kitprog") + # Deprecated + # config_options+=("--enable-oocd_trace") + config_options+=("--enable-opendous") + config_options+=("--enable-openjtag") + config_options+=("--enable-osbdm") + config_options+=("--enable-presto") + config_options+=("--enable-remote-bitbang") + config_options+=("--enable-rlink") + config_options+=("--enable-stlink") + config_options+=("--enable-ti-icdi") + config_options+=("--enable-ulink") + config_options+=("--enable-usb-blaster") + config_options+=("--enable-usb_blaster_2") + config_options+=("--enable-usbprog") + config_options+=("--enable-vsllink") + config_options+=("--enable-xds110") + + # Disable drivers that apparently failed to build on all platforms. + config_options+=("--disable-zy1000-master") + config_options+=("--disable-zy1000") + config_options+=("--disable-ioutil") + config_options+=("--disable-minidriver-dummy") + config_options+=("--disable-parport-ppdev") + + if [ "${XBB_HOST_PLATFORM}" == "win32" ] + then + + export OUTPUT_DIR="${XBB_BUILD_FOLDER_PATH}" + + # Without it, mingw redefines it as 0. + CPPFLAGS+=" -D__USE_MINGW_ANSI_STDIO=1" + + # --enable-minidriver-dummy -> configure error + # --enable-zy1000 -> netinet/tcp.h: No such file or directory + + # --enable-openjtag_ftdi -> --enable-openjtag + # --enable-presto_libftdi -> --enable-presto + # --enable-usb_blaster_libftdi -> --enable-usb_blaster + + config_options+=("--enable-amtjtagaccel") + config_options+=("--enable-gw16012") + config_options+=("--enable-parport") + config_options+=("--enable-parport-giveio") + + # --enable-sysfsgpio -> available only on Linux + config_options+=("--disable-sysfsgpio") + # --enable-buspirate -> not supported on mingw + config_options+=("--disable-buspirate") + + # oocd_trace.h:22:10: fatal error: termios.h: No such file or directory + config_options+=("--disable-oocd_trace") + + elif [ "${XBB_HOST_PLATFORM}" == "linux" ] + then + + # --enable-minidriver-dummy -> configure error + + # --enable-openjtag_ftdi -> --enable-openjtag + # --enable-presto_libftdi -> --enable-presto + # --enable-usb_blaster_libftdi -> --enable-usb_blaster + + config_options+=("--enable-amtjtagaccel") + config_options+=("--enable-buspirate") + config_options+=("--enable-gw16012") + config_options+=("--enable-parport") + config_options+=("--enable-parport-giveio") + config_options+=("--enable-sysfsgpio") + + # Deprecated + # config_options+=("--enable-oocd_trace") + + elif [ "${XBB_HOST_PLATFORM}" == "darwin" ] + then + + # --enable-minidriver-dummy -> configure error + + # --enable-openjtag_ftdi -> --enable-openjtag + # --enable-presto_libftdi -> --enable-presto + # --enable-usb_blaster_libftdi -> --enable-usb_blaster + + config_options+=("--enable-buspirate") + + # --enable-amtjtagaccel -> 'sys/io.h' file not found + config_options+=("--disable-amtjtagaccel") + # --enable-gw16012 -> 'sys/io.h' file not found + config_options+=("--disable-gw16012") + config_options+=("--disable-parport") + config_options+=("--disable-parport-giveio") + # --enable-sysfsgpio -> available only on Linux + config_options+=("--disable-sysfsgpio") + + # /Users/ilg/Work/openocd-0.10.0-14/openocd.git/src/target/oocd_trace.c: In function ‘oocd_trace_init’: + # /Users/ilg/Work/openocd-0.10.0-14/openocd.git/src/target/oocd_trace.c:121:54: error: ‘B2500000’ undeclared (first use in this function) + config_options+=("--disable-oocd_trace") + + else + + echo "Unsupported XBB_HOST_PLATFORM=${XBB_HOST_PLATFORM} in ${FUNCNAME[0]}()" + exit 1 + + fi + + run_verbose bash ${DEBUG} "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/configure" \ + "${config_options[@]}" + + cp "config.log" "${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/config-log-$(ndate).txt" + ) 2>&1 | tee "${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/configure-output-$(ndate).txt" + + fi + + ( + echo + echo "Running openocd make..." + + # Build. + # run_verbose make -j ${XBB_JOBS} bindir="bin" pkgdatadir="" + run_verbose make -j ${XBB_JOBS} + + if [ "${XBB_WITH_STRIP}" == "y" ] + then + run_verbose make install-strip + else + run_verbose make install + fi + + if [ "${XBB_HOST_PLATFORM}" == "win32" ] + then + rm -f "${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/bin/openocdw.exe" + fi + + ) 2>&1 | tee "${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/make-output-$(ndate).txt" + + copy_license \ + "${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}" \ + "${openocd_folder_name}" + ) + + mkdir -pv "${XBB_STAMPS_FOLDER_PATH}" + touch "${openocd_stamp_file_path}" + + else + echo "Component openocd already installed" + fi + + tests_add "openocd_test" "${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/bin" +} + +function openocd_test() +{ + local test_bin_path="$1" + + echo + echo "Checking the openocd shared libraries..." + show_host_libs "${test_bin_path}/openocd" + + echo + echo "Checking if openocd starts..." + + run_host_app_verbose "${test_bin_path}/openocd" --version + + run_host_app_verbose "${test_bin_path}/openocd" \ + -c "adapter driver dummy" \ + -c "adapter speed 1000" \ + -c "adapter list" \ + -c "transport list" \ + -c "target types" \ + -c "echo baburiba" \ + -c "shutdown" + +} + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/scripts/templates/body-github-release-liquid.md b/openocd-win/openocd/distro-info/scripts/templates/body-github-release-liquid.md new file mode 100644 index 0000000..2fcd9fd --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/templates/body-github-release-liquid.md @@ -0,0 +1,11 @@ +![Github Releases (by Release)](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/v{{ XBB_RELEASE_VERSION }}/total.svg) + +Version **{{ XBB_RELEASE_VERSION }}** is a maintenance release of the **xPack OpenOCD** package; it updates to the latest upstream master. + +Or (TODO: edit!): + +Version **{{ XBB_RELEASE_VERSION }}** is a new release of the **xPack OpenOCD** package, following the upstream OpenOCD release. + +[Continue reading »](TODO: edit, add URL!) + +_At this moment the binaries are provided for tests only!_ diff --git a/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-1-liquid.md b/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-1-liquid.md new file mode 100644 index 0000000..7b3b6d6 --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-1-liquid.md @@ -0,0 +1,238 @@ +--- +title: xPack OpenOCD v{{ XBB_RELEASE_VERSION }} released + +TODO: select one summary + +summary: "Version **{{ XBB_RELEASE_VERSION }}** is a maintenance release; it updates to +the latest upstream master." + +summary: "Version **{{ XBB_RELEASE_VERSION }}** is a new release; it follows the upstream release." + +upstream_version: "0.12.0" +upstream_commit: "9ea7f3d" +upstream_release_date: "15 Jan 2022" + +version: "{{ XBB_RELEASE_VERSION }}" +npm_subversion: "1" + +download_url: https://github.com/xpack-dev-tools/openocd-xpack/releases/tag/v{{ XBB_RELEASE_VERSION }}/ + +comments: true + +date: {{ RELEASE_DATE }} + +categories: + - releases + - openocd + +tags: + - releases + - openocd + +--- + +[The xPack OpenOCD](https://xpack.github.io/openocd/) +is a standalone cross-platform binary distribution of +[OpenOCD](https://openocd.org). + +There are separate binaries for **Windows** (Intel 64-bit), +**macOS** (Intel 64-bit, Apple Silicon 64-bit) +and **GNU/Linux** (Intel 64-bit, Arm 32/64-bit). + +{% raw %}{% include note.html content="The main targets for the Arm binaries +are the **Raspberry Pi** class devices (armv7l and aarch64; +armv6 is not supported)." %}{% endraw %} + +## Download + +The binary files are available from GitHub [Releases]({% raw %}{{ page.download_url }}{% endraw %}). + +## Prerequisites + +- GNU/Linux Intel 64-bit: any system with **GLIBC 2.27** or higher + (like Ubuntu 18 or later, Debian 10 or later, RedHat 8 later, + Fedora 29 or later, etc) +- GNU/Linux Arm 32/64-bit: any system with **GLIBC 2.27** or higher + (like Raspberry Pi OS, Ubuntu 18 or later, Debian 10 or later, RedHat 8 later, + Fedora 29 or later, etc) +- Intel Windows 64-bit: Windows 7 with the Universal C Runtime + ([UCRT](https://support.microsoft.com/en-us/topic/update-for-universal-c-runtime-in-windows-c0514201-7fe6-95a3-b0a5-287930f3560c)), + Windows 8, Windows 10 +- Intel macOS 64-bit: 10.13 or later +- Apple Silicon macOS 64-bit: 11.6 or later + +## Install + +The full details of installing the **xPack OpenOCD** on various platforms +are presented in the separate +[Install]({% raw %}{{ site.baseurl }}{% endraw %}/dev-tools/openocd/install/) page. + +### Easy install + +The easiest way to install OpenOCD is with +[`xpm`]({% raw %}{{ site.baseurl }}{% endraw %}/xpm/) +by using the **binary xPack**, available as +[`@xpack-dev-tools/openocd`](https://www.npmjs.com/package/@xpack-dev-tools/openocd) +from the [`npmjs.com`](https://www.npmjs.com) registry. + +With the `xpm` tool available, installing +the latest version of the package and adding it as +a development dependency for a project is quite easy: + +```sh +cd my-project +xpm init # Add a package.json if not already present + +xpm install @xpack-dev-tools/openocd@latest --verbose + +ls -l xpacks/.bin +``` + +To install this specific version, use: + +```sh +xpm install @xpack-dev-tools/openocd@{% raw %}{{ page.version }}.{{ page.npm_subversion }}{% endraw %} --verbose +``` + +For xPacks aware tools, like the **Eclipse Embedded C/C++ plug-ins**, +it is also possible to install OpenOCD globally, in the user home folder. + +```sh +xpm install --global @xpack-dev-tools/openocd@latest --verbose +``` + +Eclipse will automatically +identify binaries installed with +`xpm` and provide a convenient method to manage paths. + +### Uninstall + +To remove the links created by xpm in the current project: + +```sh +cd my-project + +xpm uninstall @xpack-dev-tools/openocd +``` + +To completely remove the package from the central xPack store: + +```sh +xpm uninstall --global @xpack-dev-tools/openocd +``` + +## Compliance + +The xPack OpenOCD generally follows the official +[OpenOCD](https://openocd.org) releases. + +The current version is based on: + +- OpenOCD version {% raw %}{{ page.upstream_version }}{% endraw %}, the development commit +[{% raw %}{{ page.upstream_commit }}{% endraw %}](https://github.com/xpack-dev-tools/openocd/commit/{% raw %}{{ page.upstream_commit }}{% endraw %}/) +from {% raw %}{{ page.upstream_release_date }}{% endraw %}. + +## Changes + +There are no functional changes. + +Compared to the upstream, the following changes were applied: + +- the `src/openocd.c` file was edited to display the branding string +- the `contrib/60-openocd.rules` file was simplified to avoid protection + related issues. + +## Bug fixes + +- none + +## Enhancements + +- none + +## Known problems + +- none + +## Shared libraries + +On all platforms the packages are standalone, and expect only the standard +runtime to be present on the host. + +All dependencies that are build as shared libraries are copied locally +in the `libexec` folder (or in the same folder as the executable for Windows). + +### `DT_RPATH` and `LD_LIBRARY_PATH` + +On GNU/Linux the binaries are adjusted to use a relative path: + +```console +$ readelf -d library.so | grep runpath + 0x000000000000001d (RPATH) Library rpath: [$ORIGIN] +``` + +In the GNU ld.so search strategy, the `DT_RPATH` has +the highest priority, higher than `LD_LIBRARY_PATH`, so if this later one +is set in the environment, it should not interfere with the xPack binaries. + +Please note that previous versions, up to mid-2020, used `DT_RUNPATH`, which +has a priority lower than `LD_LIBRARY_PATH`, and does not tolerate setting +it in the environment. + +### `@rpath` and `@loader_path` + +Similarly, on macOS, the binaries are adjusted with `install_name_tool` to use a +relative path. + +## Documentation + +The original documentation is available online: + +- <https://openocd.org/doc/pdf/openocd.pdf> + +## Build + +The binaries for all supported platforms +(Windows, macOS and GNU/Linux) were built using the +[xPack Build Box (XBB)](https://xpack.github.io/xbb/), a set +of build environments based on slightly older distributions, that should be +compatible with most recent systems. + +The scripts used to build this distribution are in: + +- `distro-info/scripts` + +For the prerequisites and more details on the build procedure, please see the +[How to build](https://github.com/xpack-dev-tools/openocd-xpack/blob/xpack/README-BUILD.md) page. + +## CI tests + +Before publishing, a set of simple tests were performed on an exhaustive +set of platforms. The results are available from: + +- [GitHub Actions](https://github.com/xpack-dev-tools/openocd-xpack/actions/) +- [Travis CI](https://app.travis-ci.com/github/xpack-dev-tools/openocd-xpack/builds/) + +## Tests + +The binaries were testes on Windows 10 Pro 32/64-bit, Intel Ubuntu 18 +LTS 64-bit, Intel Xubuntu 18 LTS 32-bit and macOS 10.15. + +Install the package with xpm. + +The simple test, consists in starting the binaries +only to identify the STM32F4DISCOVERY board. + +```sh +.../xpack-openocd-{{ XBB_RELEASE_VERSION }}/bin/openocd -f board/stm32f4discovery.cfg +``` + +A more complex test consist in programming and debugging a simple blinky +application on the STM32F4DISCOVERY board. The binaries were +those generated by +[simple Eclipse projects](https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/tree/xpack/tests/eclipse) +available in the **xPack GNU Arm Embedded GCC** project. + +## Checksums + +The SHA-256 hashes for the files are: diff --git a/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-2-liquid.md b/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-2-liquid.md new file mode 100644 index 0000000..3043f54 --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-2-liquid.md @@ -0,0 +1,30 @@ + +## Deprecation notices + +### 32-bit support + +Support for 32-bit Intel Linux and Intel Windows was +dropped in 2022. Support for 32-bit Arm Linux (armv7l) will be preserved +for a while, due to the large user base of 32-bit Raspberry Pi systems. + +### Linux minimum requirements + +Support for RedHat 7 was dropped in 2022 and the +minimum requirement was raised to GLIBC 2.27, available starting +with Ubuntu 18, Debian 10 and RedHat 8. + +## Download analytics + +- GitHub [xpack-dev-tools/openocd-xpack](https://github.com/xpack-dev-tools/openocd-xpack/) + - this release [![Github All Releases](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/v{% raw %}{{ page.version }}{% endraw %}/total.svg)](https://github.com/xpack-dev-tools/openocd-xpack/releases/v{% raw %}{{ page.version }}{% endraw %}/) + - all xPack releases [![Github All Releases](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/total.svg)](https://github.com/xpack-dev-tools/openocd-xpack/releases/) + - all GNU MCU Eclipse releases [![Github All Releases](https://img.shields.io/github/downloads/gnu-mcu-eclipse/openocd/total.svg)](https://github.com/gnu-mcu-eclipse/openocd/releases/) + - [individual file counters](https://somsubhra.github.io/github-release-stats/?username=xpack-dev-tools&repository=openocd-xpack) (grouped per release) +- npmjs.com [@xpack-dev-tools/openocd](https://www.npmjs.com/package/@xpack-dev-tools/openocd) + - latest releases [![npm](https://img.shields.io/npm/dw/@xpack-dev-tools/openocd.svg)](https://www.npmjs.com/package/@xpack-dev-tools/openocd/) + - all @xpack-dev-tools releases [![npm](https://img.shields.io/npm/dt/@xpack-dev-tools/openocd.svg)](https://www.npmjs.com/package/@xpack-dev-tools/openocd/) + - all @gnu-mcu-eclipse releases [![npm](https://img.shields.io/npm/dt/@gnu-mcu-eclipse/openocd.svg)](https://www.npmjs.com/package/@gnu-mcu-eclipse/openocd/) + +Credit to [Shields IO](https://shields.io) for the badges and to +[Somsubhra/github-release-stats](https://github.com/Somsubhra/github-release-stats) +for the individual file counters. diff --git a/openocd-win/openocd/distro-info/scripts/test.sh b/openocd-win/openocd/distro-info/scripts/test.sh new file mode 100644 index 0000000..c7da71c --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/test.sh @@ -0,0 +1,95 @@ +#!/usr/bin/env bash +# ----------------------------------------------------------------------------- +# DO NOT EDIT! Generated from xpacks/@xpack-dev-tools/xbb-helper/templates/*. +# +# This file is part of the xPack distribution. +# (https://xpack.github.io) +# Copyright (c) 2020 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d). + +if [[ ! -z ${DEBUG} ]] +then + set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty. +else + DEBUG="" +fi + +set -o errexit # Exit if command failed. +set -o pipefail # Exit if pipe failed. +set -o nounset # Exit if variable not set. + +# Remove the initial space and instead use '\n'. +IFS=$'\n\t' + +# ----------------------------------------------------------------------------- +# Identify the script location, to reach, for example, the helper scripts. + +script_path="$0" +if [[ "${script_path}" != /* ]] +then + # Make relative path absolute. + script_path="$(pwd)/$0" +fi + +script_name="$(basename "${script_path}")" + +script_folder_path="$(dirname "${script_path}")" +script_folder_name="$(basename "${script_folder_path}")" + +# ============================================================================= +# Run the application tests. + +scripts_folder_path="${script_folder_path}" +project_folder_path="$(dirname ${script_folder_path})" +helper_folder_path="${project_folder_path}/xpacks/@xpack-dev-tools/xbb-helper" + +tests_folder_path="$(dirname "${scripts_folder_path}")/tests" + +# ----------------------------------------------------------------------------- + +source "${scripts_folder_path}/application.sh" + +# Common definitions. +source "${helper_folder_path}/scripts/test-common.sh" + +# Possibly override common definitions. +source "${scripts_folder_path}/tests/run.sh" +if [ -f "${scripts_folder_path}/tests/update.sh" ] +then + source "${scripts_folder_path}/tests/update.sh" +fi + +if [ ${#XBB_APPLICATION_COMMON_DEPENDENCIES[@]} -ne 0 ] +then + for dependency in ${XBB_APPLICATION_COMMON_DEPENDENCIES[@]} + do + echo "Including ${helper_folder_path}/dependencies/${dependency}.sh..." + source "${helper_folder_path}/dependencies/${dependency}.sh" + done +fi + +if [ ${#XBB_APPLICATION_DEPENDENCIES[@]} -ne 0 ] +then + for dependency in ${XBB_APPLICATION_DEPENDENCIES[@]} + do + echo "Including ${scripts_folder_path}/dependencies/${dependency}.sh..." + source "${scripts_folder_path}/dependencies/${dependency}.sh" + done +fi + +# ----------------------------------------------------------------------------- + +tests_parse_options "$@" + +tests_perform_common + +# Completed successfully. +exit 0 + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/scripts/tests/run.sh b/openocd-win/openocd/distro-info/scripts/tests/run.sh new file mode 100644 index 0000000..95abbd8 --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/tests/run.sh @@ -0,0 +1,20 @@ +# ----------------------------------------------------------------------------- +# This file is part of the xPack distribution. +# (https://xpack.github.io) +# Copyright (c) 2020 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# Included by `scrips/test.sh`. + +function tests_run_all() +{ + local test_bin_path="$1" + + openocd_test "${test_bin_path}" +} + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/distro-info/scripts/versioning.sh b/openocd-win/openocd/distro-info/scripts/versioning.sh new file mode 100644 index 0000000..95edc5c --- /dev/null +++ b/openocd-win/openocd/distro-info/scripts/versioning.sh @@ -0,0 +1,159 @@ +# ----------------------------------------------------------------------------- +# This file is part of the xPacks distribution. +# (https://xpack.github.io) +# Copyright (c) 2019 Liviu Ionescu. +# +# Permission to use, copy, modify, and/or distribute this software +# for any purpose is hereby granted, under the terms of the MIT license. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- + +function application_build_versioned_components() +{ + XBB_OPENOCD_VERSION="$(xbb_strip_version_pre_release "${XBB_RELEASE_VERSION}")" + + # Keep them in sync with the combo archive content. + if [[ "${XBB_RELEASE_VERSION}" =~ 0[.]12[.]0-.* ]] + then + XBB_OPENOCD_GIT_URL=${XBB_APPLICATION_OPENOCD_GIT_URL:-"https://github.com/openocd-org/openocd.git"} + XBB_OPENOCD_GIT_BRANCH=${XBB_APPLICATION_OPENOCD_GIT_BRANCH:-"master"} + + if [ "${XBB_RELEASE_VERSION}" == "0.12.0-1" ] + then + XBB_OPENOCD_GIT_COMMIT=${XBB_APPLICATION_OPENOCD_GIT_COMMIT:-"v0.12.0"} + elif [ "${XBB_RELEASE_VERSION}" == "0.12.0-2" ] + then + # Sep 2, 2023 + XBB_OPENOCD_GIT_COMMIT=${XBB_APPLICATION_OPENOCD_GIT_COMMIT:-"18281b0c497694d91c5608be54583172838be75c"} + else + echo "Unsupported ${XBB_APPLICATION_LOWER_CASE_NAME} version ${XBB_RELEASE_VERSION}" + exit 1 + fi + + # ------------------------------------------------------------------------- + # Build the native dependencies. + + autotools_build + + # https://ftp.gnu.org/gnu/texinfo/ + texinfo_build "7.0.3" + + # ------------------------------------------------------------------------- + # Build the target dependencies. + + xbb_reset_env + # Before set target (to possibly update CC & co variables). + xbb_activate_installed_bin + + xbb_set_target "requested" + + # ------------------------------------------------------------------------- + + # https://ftp.gnu.org/pub/gnu/libiconv/ + libiconv_build "1.17" + + # ------------------------------------------------------------------------- + + # https://sourceforge.net/projects/libusb/files/libusb-1.0/ + libusb1_build "1.0.26" + + # Starting with v0.12.0, libusb0 is no longer needed. + # if [ "${XBB_REQUESTED_HOST_PLATFORM}" == "win32" ] + # then + # # https://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/ + # libusb_w32_build "1.2.7.3" # "1.2.6.0" # ! PATCH & pkgconfig + # else + # # https://sourceforge.net/projects/libusb/files/libusb-compat-0.1/ + # # required by libjaylink + # libusb0_build "0.1.8" + # fi + + # https://www.intra2net.com/en/developer/libftdi/download.php + libftdi_build "1.5" # ! PATCH + + # https://github.com/libusb/hidapi/releases + hidapi_build "0.14.0" # "0.12.0" + + # ------------------------------------------------------------------------- + # Build the application binaries. + + xbb_set_executables_install_path "${XBB_APPLICATION_INSTALL_FOLDER_PATH}" + xbb_set_libraries_install_path "${XBB_DEPENDENCIES_INSTALL_FOLDER_PATH}" + + openocd_build "${XBB_OPENOCD_VERSION}" + + # ------------------------------------------------------------------------- + elif [[ "${XBB_RELEASE_VERSION}" =~ 0[.]11[.]0-[5] ]] + then + + XBB_OPENOCD_GIT_URL=${XBB_OPENOCD_GIT_URL:-"https://github.com/xpack-dev-tools/openocd.git"} + + XBB_OPENOCD_GIT_BRANCH=${XBB_OPENOCD_GIT_BRANCH:-"xpack"} + # XBB_OPENOCD_GIT_BRANCH=${XBB_OPENOCD_GIT_BRANCH:-"xpack-develop"} + XBB_OPENOCD_GIT_COMMIT=${XBB_OPENOCD_GIT_COMMIT:-"v${XBB_RELEASE_VERSION}-xpack"} + + # ------------------------------------------------------------------------- + # Build the native dependencies. + + autotools_build + + # https://ftp.gnu.org/gnu/texinfo/ + texinfo_build "6.8" + + # ------------------------------------------------------------------------- + # Build the target dependencies. + + xbb_reset_env + # Before set target (to possibly update CC & co variables). + xbb_activate_installed_bin + + xbb_set_target "requested" + + # ------------------------------------------------------------------------- + + if [ "${XBB_REQUESTED_HOST_PLATFORM}" != "darwin" ] + then + + # https://ftp.gnu.org/pub/gnu/libiconv/ + libiconv_build "1.17" # "1.16" + + fi + + # ------------------------------------------------------------------------- + + # https://sourceforge.net/projects/libusb/files/libusb-1.0/ + libusb1_build "1.0.26" + + if [ "${XBB_REQUESTED_HOST_PLATFORM}" == "win32" ] + then + # https://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/ + libusb_w32_build "1.2.6.0" # ! PATCH & pkgconfig + else + # https://sourceforge.net/projects/libusb/files/libusb-compat-0.1/ + # required by libjaylink + libusb0_build "0.1.5" + fi + + # https://www.intra2net.com/en/developer/libftdi/download.php + libftdi_build "1.5" # ! PATCH + + # https://github.com/libusb/hidapi/releases + hidapi_build "0.12.0" # "0.10.1" # ! pkgconfig/hidapi-*-windows.pc + + # ------------------------------------------------------------------------- + # Build the application binaries. + + xbb_set_executables_install_path "${XBB_APPLICATION_INSTALL_FOLDER_PATH}" + xbb_set_libraries_install_path "${XBB_DEPENDENCIES_INSTALL_FOLDER_PATH}" + + openocd_build "${XBB_OPENOCD_VERSION}" + + # ------------------------------------------------------------------------- + else + echo "Unsupported ${XBB_APPLICATION_LOWER_CASE_NAME} version ${XBB_RELEASE_VERSION}" + exit 1 + fi +} + +# ----------------------------------------------------------------------------- diff --git a/openocd-win/openocd/libexec/libftdi1.2.5.0.dylib b/openocd-win/openocd/libexec/libftdi1.2.5.0.dylib new file mode 100644 index 0000000..97aa0c5 Binary files /dev/null and b/openocd-win/openocd/libexec/libftdi1.2.5.0.dylib differ diff --git a/openocd-win/openocd/libexec/libftdi1.2.dylib b/openocd-win/openocd/libexec/libftdi1.2.dylib new file mode 100644 index 0000000..97aa0c5 Binary files /dev/null and b/openocd-win/openocd/libexec/libftdi1.2.dylib differ diff --git a/openocd-win/openocd/libexec/libhidapi.0.14.0.dylib b/openocd-win/openocd/libexec/libhidapi.0.14.0.dylib new file mode 100644 index 0000000..abe19d6 Binary files /dev/null and b/openocd-win/openocd/libexec/libhidapi.0.14.0.dylib differ diff --git a/openocd-win/openocd/libexec/libusb-1.0.0.dylib b/openocd-win/openocd/libexec/libusb-1.0.0.dylib new file mode 100644 index 0000000..0f0ba79 Binary files /dev/null and b/openocd-win/openocd/libexec/libusb-1.0.0.dylib differ diff --git a/openocd-win/openocd/scripts/bitsbytes.tcl b/openocd-win/openocd/scripts/bitsbytes.tcl new file mode 100644 index 0000000..03d758e --- /dev/null +++ b/openocd-win/openocd/scripts/bitsbytes.tcl @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#---------------------------------------- +# Purpose - Create some $BIT variables +# Create $K and $M variables +# and some bit field extraction variables. +# Create helper variables ... +# BIT0.. BIT31 + +for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} { + set vn [format "BIT%d" $x] + global $vn + set $vn [expr {1 << $x}] +} + +# Create K bytes values +# __1K ... to __2048K +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { + set vn [format "__%dK" $x] + global $vn + set $vn [expr {1024 * $x}] +} + +# Create M bytes values +# __1M ... to __2048K +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { + set vn [format "__%dM" $x] + global $vn + set $vn [expr {1024 * 1024 * $x}] +} + +proc create_mask { MSB LSB } { + return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}] +} + +# Cut Bits $MSB to $LSB out of this value. +# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16] +# Result: 0x02340000 + +proc extract_bitfield { VALUE MSB LSB } { + return [expr {[create_mask $MSB $LSB] & $VALUE}] +} + + +# Cut bits $MSB to $LSB out of this value +# and shift (normalize) them down to bit 0. +# +# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16] +# Result: 0x00000234 +# +proc normalize_bitfield { VALUE MSB LSB } { + return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}] +} + +proc show_normalize_bitfield { VALUE MSB LSB } { + set m [create_mask $MSB $LSB] + set mr [expr {$VALUE & $m}] + set sr [expr {$mr >> $LSB}] + echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr] + return $sr +} diff --git a/openocd-win/openocd/scripts/board/8devices-lima.cfg b/openocd-win/openocd/scripts/board/8devices-lima.cfg new file mode 100644 index 0000000..a094cae --- /dev/null +++ b/openocd-win/openocd/scripts/board/8devices-lima.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Product page: +# https://www.8devices.com/products/lima +# +# Location of JTAG pins: +# J2 GPIO0 JTAG TCK +# J2 GPIO1 JTAG TDI +# J2 GPIO2 JTAG TDO +# J2 GPIO3 JTAG TMS +# J2 RST directly connected to RESET_L of the SoC and can be used as +# JTAG SRST. Note: this pin will also reset the debug engine. +# J1 +3,3V Can be use as JTAG Vref +# J1 or J2 GND Can be used for JTAG GND +# +# This board is powered from mini USB connecter which is also used +# as USB to UART converted based on FTDI FT230XQ chip + +source [find target/qualcomm_qca4531.cfg] + +proc board_init { } { + qca4531_ddr2_550_550_init +} + +$_TARGETNAME configure -event reset-init { + board_init +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0 diff --git a/openocd-win/openocd/scripts/board/actux3.cfg b/openocd-win/openocd/scripts/board/actux3.cfg new file mode 100644 index 0000000..edb529c --- /dev/null +++ b/openocd-win/openocd/scripts/board/actux3.cfg @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# board config file for AcTux3/XBA IXP42x board +# Date: 2010-12-16 +# Author: Michael Schwingen <michael@schwingen.org> + +reset_config trst_and_srst separate + +adapter srst delay 100 +jtag_ntrst_delay 100 + +source [find target/ixp42x.cfg] + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { init_actux3 } + +proc init_actux3 { } { + ########################################################################## + # setup expansion bus CS + ########################################################################## + mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000 + mww 0xc4000004 0x94d10013 ;#CS1 + mww 0xc4000008 0x95960003 ;#CS2 + mww 0xc400000c 0x00000000 ;#CS3 + mww 0xc4000010 0x80900003 ;#CS4 + mww 0xc4000014 0x9d520003 ;#CS5 + mww 0xc4000018 0x81860001 ;#CS6 + mww 0xc400001c 0x80900003 ;#CS7 + + ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3 + + #mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000 + + ixp42x_set_bigendian + + flash probe 0 +} + +proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } { + echo "writing bootloader: $FILE" + flash write_image erase $FILE 0x50000000 bin +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME + +init +reset init + +# setup to debug u-boot in flash +proc uboot_debug {} { + gdb_breakpoint_override hard + xscale vector_catch 0xFF + + xscale vector_table low 1 0xe59ff018 + xscale vector_table low 2 0xe59ff018 + xscale vector_table low 3 0xe59ff018 + xscale vector_table low 4 0xe59ff018 + xscale vector_table low 5 0xe59ff018 + xscale vector_table low 6 0xe59ff018 + xscale vector_table low 7 0xe59ff018 + + xscale vector_table high 1 0xe59ff018 + xscale vector_table high 2 0xe59ff018 + xscale vector_table high 3 0xe59ff018 + xscale vector_table high 4 0xe59ff018 + xscale vector_table high 5 0xe59ff018 + xscale vector_table high 6 0xe59ff018 + xscale vector_table high 7 0xe59ff018 +} diff --git a/openocd-win/openocd/scripts/board/adapteva_parallella1.cfg b/openocd-win/openocd/scripts/board/adapteva_parallella1.cfg new file mode 100644 index 0000000..d6336a8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/adapteva_parallella1.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Adapteva Parallella-I board (via Porcupine-1 adapter board) +# + +reset_config srst_only + +source [find target/zynq_7000.cfg] diff --git a/openocd-win/openocd/scripts/board/adsp-sc584-ezbrd.cfg b/openocd-win/openocd/scripts/board/adsp-sc584-ezbrd.cfg new file mode 100644 index 0000000..366a24a --- /dev/null +++ b/openocd-win/openocd/scripts/board/adsp-sc584-ezbrd.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Analog Devices ADSP-SC584-EZBRD evaluation board +# +# Evaluation boards by Analog Devices (and designs derived from them) use a +# non-standard 10-pin 0.05" ARM Cortex Debug Connector. In this bastardized +# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST. +# +# As a result, a standards-compliant debug pod will force /TRST active, +# putting the processor's debug interface into reset and preventing usage. +# +# A connector adapter must be employed on these boards to isolate or remap +# /TRST so that it is only asserted when intended. + +# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all +# ADSP-SC58x designs, but this is an ARM target (and subject to the +# qualifications above) many ARM debug pods should be compatible. + +#source [find interface/cmsis-dap.cfg] +source [find interface/jlink.cfg] + +# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited +# to JTAG. (This is presumably why their connector pinout was modified.) +# SWD is chosen here, as it is more efficient and doesn't require /TRST. + +transport select swd + +# chosen speed is 'safe' choice, but your adapter may be capable of more +adapter speed 400 + +source [find target/adsp-sc58x.cfg] diff --git a/openocd-win/openocd/scripts/board/alphascale_asm9260_ek.cfg b/openocd-win/openocd/scripts/board/alphascale_asm9260_ek.cfg new file mode 100644 index 0000000..33a8354 --- /dev/null +++ b/openocd-win/openocd/scripts/board/alphascale_asm9260_ek.cfg @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/alphascale_asm9260t.cfg] + +reset_config trst_and_srst + +$_TARGETNAME configure -event reset-init { + echo "Configure clock" + # Enable SRAM clk + mww 0x80040024 0x4 + # Enable IRQ clk + mww 0x80040034 0x100 + # Enable DMA0,1 clk + mww 0x80040024 0x600 + # Make sysre syspll is enabled + mww 0x80040238 0x750 + #CPU = PLLCLK/2 + mww 0x8004017C 0x2 + #SYSAHBCLK = CPUCLK/2 + mww 0x80040180 0x2 + # Set PLL freq to 480MHz + mww 0x80040100 480 + # normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0) + sleep 100 + + # select PLL as main source + mww 0x80040120 0x1 + # disable and enable main clk to update changes? + mww 0x80040124 0x0 + mww 0x80040124 0x1 + + echo "Configure memory" + #enable EMI CLK + mww 0x80040024 0x40 + + # configure memory controller for internal SRAM + mww 0x80700000 0x1188 + # change default emi clk delay + mww 0x8004034C 0xA0503 + # make sure chip_select_register2_low has correct value (why?) + mww 0x8070001c 0x20000000 + # set type to sdram and size to 32MB + mww 0x8070005c 0xa + # configure internal SDRAM timing + mww 0x80700004 0x024996d9 + # configure Static Memory timing + mww 0x80700094 0x00542b4f + + echo "Configure uart4" + # enable pinctrl clk + mww 0x80040024 0x2000000 + # mux GPIO3_0 and GPIO3_1 to UART4 + mww 0x80044060 0x2 + mww 0x80044064 0x2 + # configure UART4CLKDIV + mww 0x800401a8 0x1 + # enable uart4 clk + mww 0x80040024 0x8000 + # clear softrst and clkgate on uart4 + mww 0x80010008 0xC0000000 + # set bandrate 115200 12M + mww 0x80010030 0x00062070 + # enable Rx&Tx + mww 0x80010024 0x301 + # clear hw control + mww 0x80010028 0xc000 +} + +$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000 +$_TARGETNAME arm7_9 fast_memory_access enable +$_TARGETNAME arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/board/altera_sockit.cfg b/openocd-win/openocd/scripts/board/altera_sockit.cfg new file mode 100644 index 0000000..bbd87d6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/altera_sockit.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Cyclone V SocKit board +# http://www.altera.com/b/arrow-sockit.html +# +# Software support page: +# http://www.rocketboards.org/ + +# openocd does not currently support the on-board USB Blaster II. +# Install the JTAG header and use a USB Blaster instead. +adapter driver usb_blaster + +source [find target/altera_fpgasoc.cfg] + +# If the USB Blaster II were supported, these settings would be needed +#usb_blaster vid_pid 0x09fb 0x6810 +#usb_blaster device_desc "USB-Blaster II" + +adapter speed 100 diff --git a/openocd-win/openocd/scripts/board/am3517evm.cfg b/openocd-win/openocd/scripts/board/am3517evm.cfg new file mode 100644 index 0000000..0b19be6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/am3517evm.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# DANGER!!!! early work in progress for this PCB/target. +# +# The most basic operations work well enough that it is +# useful to have this in the repository for cooperation +# alpha testing purposes. +# +# TI AM3517 +# +# http://focus.ti.com/docs/prod/folders/print/am3517.html +# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP) +# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x + +set CHIPTYPE "am35x" +source [find target/amdm37x.cfg] + +# The TI-14 JTAG connector does not have srst. CPU reset is handled in +# hardware. +reset_config trst_only + +# "amdm37x_dbginit am35x.cpu" needs to be run after init. diff --git a/openocd-win/openocd/scripts/board/ampere_emag8180.cfg b/openocd-win/openocd/scripts/board/ampere_emag8180.cfg new file mode 100644 index 0000000..736be12 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ampere_emag8180.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# OpenOCD Board Configuration for eMAG Development Platform +# +# Copyright (c) 2019-2021, Ampere Computing LLC +# + +# +# Configure JTAG speed +# + +adapter speed 2000 + +# +# Configure Resets +# + +jtag_ntrst_delay 100 +reset_config trst_only + +# +# Configure Targets +# + +source [find target/ampere_emag.cfg] diff --git a/openocd-win/openocd/scripts/board/ampere_qs_mq_1s.cfg b/openocd-win/openocd/scripts/board/ampere_qs_mq_1s.cfg new file mode 100644 index 0000000..bc649ed --- /dev/null +++ b/openocd-win/openocd/scripts/board/ampere_qs_mq_1s.cfg @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and +# Ampere Altra Max ("Mystique") processors +# +# Copyright (c) 2019-2021, Ampere Computing LLC + +# Argument Description +# +# JTAGFREQ +# Set the JTAG clock frequency +# Syntax: -c "set JTAGFREQ {freq_in_khz}" +# +# SYSNAME +# Set the system name +# If not specified, defaults to "qs" +# Syntax: -c "set SYSNAME {qs}" +# +# Life-Cycle State (LCS) +# If not specified, defaults to "Secure LCS" +# LCS=0, "Secure LCS" +# LCS=1, "Chip Manufacturing LCS" +# Syntax: -c "set LCS {0}" +# Syntax: -c "set LCS {1}" +# +# CORELIST_S0 +# Specify available physical cores by number +# Example syntax to connect to physical cores 16 and 17 for S0 +# Syntax: -c "set CORELIST_S0 {16 17}" +# +# COREMASK_S0_LO +# Specify available physical cores 0-63 by mask +# Example syntax to connect to physical cores 16 and 17 for S0 +# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}" +# +# COREMASK_S0_HI +# Specify available physical cores 64 and above by mask +# Example syntax to connect to physical cores 94 and 95 for S0 +# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}" +# +# PHYS_IDX +# Enable OpenOCD ARMv8 core target physical indexing +# If not specified, defaults to OpenOCD ARMv8 core target logical indexing +# Syntax: -c "set PHYS_IDX {}" + +# +# Configure JTAG speed +# + +if { [info exists JTAGFREQ] } { + adapter speed $JTAGFREQ +} else { + adapter speed 100 +} + +# +# Set the system name +# + +if { [info exists SYSNAME] } { + set _SYSNAME $SYSNAME +} else { + set _SYSNAME qs +} + +# +# Configure Resets +# + +jtag_ntrst_delay 100 +reset_config trst_only + +# +# Configure Targets +# + +if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } { + set CHIPNAME ${_SYSNAME}0 + if { [info exists CORELIST_S0] } { + set CORELIST $CORELIST_S0 + } else { + if { [info exists COREMASK_S0_LO] } { + set COREMASK_LO $COREMASK_S0_LO + } else { + set COREMASK_LO 0x0 + } + + if { [info exists COREMASK_S0_HI] } { + set COREMASK_HI $COREMASK_S0_HI + } else { + set COREMASK_HI 0x0 + } + } +} else { + set CHIPNAME ${_SYSNAME}0 + set COREMASK_LO 0x1 + set COREMASK_HI 0x0 +} + +source [find target/ampere_qs_mq.cfg] diff --git a/openocd-win/openocd/scripts/board/ampere_qs_mq_2s.cfg b/openocd-win/openocd/scripts/board/ampere_qs_mq_2s.cfg new file mode 100644 index 0000000..76d82d2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ampere_qs_mq_2s.cfg @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# OpenOCD Board Configuration for Ampere Altra ("Quicksilver") and +# Ampere Altra Max ("Mystique") processors +# +# Copyright (c) 2019-2021, Ampere Computing LLC + +# Argument Description +# +# JTAGFREQ +# Set the JTAG clock frequency +# Syntax: -c "set JTAGFREQ {freq_in_khz}" +# +# SYSNAME +# Set the system name +# If not specified, defaults to "qs" +# Syntax: -c "set SYSNAME {qs}" +# +# Life-Cycle State (LCS) +# If not specified, defaults to "Secure LCS" +# LCS=0, "Secure LCS" +# LCS=1, "Chip Manufacturing LCS" +# Syntax: -c "set LCS {0}" +# Syntax: -c "set LCS {1}" +# +# CORELIST_S0, CORELIST_S1 +# Specify available physical cores by number +# Example syntax to connect to physical cores 16 and 17 for S0 and S1 +# Syntax: -c "set CORELIST_S0 {16 17}" +# Syntax: -c "set CORELIST_S1 {16 17}" +# +# COREMASK_S0_LO, COREMASK_S1_LO +# Specify available physical cores 0-63 by mask +# Example syntax to connect to physical cores 16 and 17 for S0 and S1 +# Syntax: -c "set COREMASK_S0_LO {0x0000000000030000}" +# Syntax: -c "set COREMASK_S1_LO {0x0000000000030000}" +# +# COREMASK_S0_HI, COREMASK_S1_HI +# Specify available physical cores 64 and above by mask +# Example syntax to connect to physical cores 94 and 95 for S0 and S1 +# Syntax: -c "set COREMASK_S0_HI {0x00000000C0000000}" +# Syntax: -c "set COREMASK_S1_HI {0x00000000C0000000}" +# +# SPLITSMP +# Group all ARMv8 cores per socket into individual SMP sessions +# If not specified, group ARMv8 cores from both sockets into one SMP session +# Syntax: -c "set SPLITSMP {}" +# +# PHYS_IDX +# Enable OpenOCD ARMv8 core target physical indexing +# If not specified, defaults to OpenOCD ARMv8 core target logical indexing +# Syntax: -c "set PHYS_IDX {}" + +# +# Configure JTAG speed +# + +if { [info exists JTAGFREQ] } { + adapter speed $JTAGFREQ +} else { + adapter speed 100 +} + +# +# Set the system name +# + +if { [info exists SYSNAME] } { + set _SYSNAME $SYSNAME +} else { + set _SYSNAME qs +} + +# +# Configure Board level SMP configuration if necessary +# + +if { ![info exists SPLITSMP] } { + # Group dual chip into a single SMP configuration + set SMP_STR "target smp" + set CORE_INDEX_OFFSET 0 + set DUAL_SOCKET_SMP_ENABLED "" +} + +# +# Configure Resets +# + +jtag_ntrst_delay 100 +reset_config trst_only + +# +# Configure Targets +# + +if { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \ + [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } { + set CHIPNAME ${_SYSNAME}1 + if { [info exists CORELIST_S1] } { + set CORELIST $CORELIST_S1 + } else { + if { [info exists COREMASK_S1_LO] } { + set COREMASK_LO $COREMASK_S1_LO + } else { + set COREMASK_LO 0x0 + } + + if { [info exists COREMASK_S1_HI] } { + set COREMASK_HI $COREMASK_S1_HI + } else { + set COREMASK_HI 0x0 + } + } + source [find target/ampere_qs_mq.cfg] + + if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} { + if { [info exists MQ_ENABLE] } { + set CORE_INDEX_OFFSET 128 + } else { + set CORE_INDEX_OFFSET 80 + } + } + + set CHIPNAME ${_SYSNAME}0 + if { [info exists CORELIST_S0] } { + set CORELIST $CORELIST_S0 + } else { + if { [info exists COREMASK_S0_LO] } { + set COREMASK_LO $COREMASK_S0_LO + } else { + set COREMASK_LO 0x0 + } + + if { [info exists COREMASK_S0_HI] } { + set COREMASK_HI $COREMASK_S0_HI + } else { + set COREMASK_HI 0x0 + } + } + source [find target/ampere_qs_mq.cfg] +} else { + set CHIPNAME ${_SYSNAME}1 + set COREMASK_LO 0x0 + set COREMASK_HI 0x0 + source [find target/ampere_qs_mq.cfg] + + if { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} { + if { [info exists MQ_ENABLE] } { + set CORE_INDEX_OFFSET 128 + } else { + set CORE_INDEX_OFFSET 80 + } + } + + set CHIPNAME ${_SYSNAME}0 + set COREMASK_LO 0x1 + set COREMASK_HI 0x0 + source [find target/ampere_qs_mq.cfg] +} + +if { [info exists DUAL_SOCKET_SMP_ENABLED] } { + # For dual socket SMP configuration, evaluate the string + eval $SMP_STR +} diff --git a/openocd-win/openocd/scripts/board/arm_evaluator7t.cfg b/openocd-win/openocd/scripts/board/arm_evaluator7t.cfg new file mode 100644 index 0000000..0fb8778 --- /dev/null +++ b/openocd-win/openocd/scripts/board/arm_evaluator7t.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This board is from ARM and has an samsung s3c45101x01 chip + +source [find target/samsung_s3c4510.cfg] + +# +# FIXME: +# Add (A) sdram configuration +# Add (B) flash cfi programming configuration +# diff --git a/openocd-win/openocd/scripts/board/arm_musca_a.cfg b/openocd-win/openocd/scripts/board/arm_musca_a.cfg new file mode 100644 index 0000000..b4880d1 --- /dev/null +++ b/openocd-win/openocd/scripts/board/arm_musca_a.cfg @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration script for ARM Musca-A development board +# +# For now we do not support Musca A flash programming using OpenOCD. However, a +# work area is configured for flash programming speed up. +# +# GDB considers all memory as RAM unless target supplies a memory map. +# OpenOCD will only send memory map if flash banks are configured. Otherwise, +# configure GDB after connection by issuing following commands: +# (gdb) mem 0x10200000 0x109FFFFF ro +# (gdb) mem 0x00200000 0x009FFFFF ro +# (gdb) set mem inaccessible-by-default off + +# ARM Musca A board supports both JTAG and SWD transports. +source [find target/swj-dp.tcl] + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +global _CHIPNAME +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME MUSCA_A +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba00477 +} + +# Enable CPU1 debugging as a separate GDB target +set _ENABLE_CPU1 1 + +# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU +set WORKAREASIZE_CPU0 0x2000 +set WORKAREASIZE_CPU1 0x2000 + +# Set SRAM bank 1 to be used for work area. Override here if needed. +set WORKAREAADDR_CPU0 0x30008000 +set WORKAREAADDR_CPU1 0x3000A000 + +source [find target/arm_corelink_sse200.cfg] diff --git a/openocd-win/openocd/scripts/board/arty_s7.cfg b/openocd-win/openocd/scripts/board/arty_s7.cfg new file mode 100644 index 0000000..eaa15ab --- /dev/null +++ b/openocd-win/openocd/scripts/board/arty_s7.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists +# +# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html +# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/ + +source [find interface/ftdi/digilent-hs1.cfg] + +# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324) +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] + +adapter speed 25000 + +# Usage: +# +# Load Bitstream into FPGA: +# openocd -f board/arty_s7.cfg -c "init;\ +# pld load 0 bitstream.bit;\ +# shutdown" +# +# Write Bitstream to Flash: +# openocd -f board/arty_s7.cfg -c "init;\ +# jtagspi_init 0 bscan_spi_xc7s??.bit;\ +# jtagspi_program bitstream.bin 0;\ +# xc7_program xc7.tap;\ +# shutdown" +# +# jtagspi flash proxies can be found at: +# https://github.com/quartiq/bscan_spi_bitstreams +# +# For the Spartan 50 variant, use +# - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit +# For the Spartan 25 variant, use +# - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit diff --git a/openocd-win/openocd/scripts/board/asus-rt-n16.cfg b/openocd-win/openocd/scripts/board/asus-rt-n16.cfg new file mode 100644 index 0000000..a02bab8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/asus-rt-n16.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# http://wikidevi.com/wiki/ASUS_RT-N16 +# + +set partition_list { + CFE { Bootloader 0xbc000000 0x00040000 } + firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 } + nvram { "Config space" 0xbdfe0000 0x00020000 } +} + +source [find target/bcm4718.cfg] + +# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q) +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8 diff --git a/openocd-win/openocd/scripts/board/asus-rt-n66u.cfg b/openocd-win/openocd/scripts/board/asus-rt-n66u.cfg new file mode 100644 index 0000000..dda0f33 --- /dev/null +++ b/openocd-win/openocd/scripts/board/asus-rt-n66u.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# http://wikidevi.com/wiki/Asus_RT-N66U +# + +echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC" +echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ," +echo "there is an unpopulated footprint near U8.\n" + +set partition_list { + CFE { Bootloader 0xbc000000 0x00040000 } + firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 } + nvram { "Config space" 0xbdfe0000 0x00020000 } +} + +source [find target/bcm4706.cfg] + +# External 32MB NOR Flash (Spansion S29GL256P10TF101 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/at91cap7a-stk-sdram.cfg b/openocd-win/openocd/scripts/board/at91cap7a-stk-sdram.cfg new file mode 100644 index 0000000..6da917a --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91cap7a-stk-sdram.cfg @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394 +# +# use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cap7 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x40700f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-start { + # start off real slow when we're running off internal RC oscillator + adapter speed 32 +} + +proc peek32 {address} { + return [read_memory $address 32 1] +} + +# Wait for an expression to be true with a timeout +proc wait_state {expression} { + for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} { + if {[uplevel 1 $expression] == 0} { + return + } + } + return -code 1 "Timed out" +} + +# Use a global variable here to be able to tinker interactively with +# post reset jtag frequency. +global post_reset_khz +# Danger!!!! Even 16MHz kinda works with this target, but +# it needs to be as low as 2000kHz to be stable. +set post_reset_khz 2000 + +$_TARGETNAME configure -event reset-init { + echo "Configuring master clock" + # disable watchdog + mww 0xfffffd44 0xff008000 + # enable user reset + mww 0xfffffd08 0xa5000001 + # Enable main oscillator + mww 0xFFFFFc20 0x00000f01 + wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}} + + # Set PLLA to 96MHz + mww 0xFFFFFc28 0x20072801 + wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}} + + # Select prescaler + mww 0xFFFFFC30 0x00000004 + wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}} + + # Select master clock to 48MHz + mww 0xFFFFFC30 0x00000006 + wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}} + + echo "Master clock ok." + + # Now that we're up and running, crank up speed! + global post_reset_khz ; adapter speed $post_reset_khz + + echo "Configuring the SDRAM controller..." + + # Configure EBI Chip select for SDRAM + mww 0xFFFFEF30 0x00000102 + + # Enable clock on EBI PIOs + mww 0xFFFFFC10 0x00000004 + + # Configure PIO for SDRAM + mww 0xFFFFF470 0xFFFF0000 + mww 0xFFFFF474 0x00000000 + mww 0xFFFFF404 0xFFFF0000 + + # Configure SDRAMC CR + mww 0xFFFFEA08 0xA63392F9 + + # NOP command + mww 0xFFFFEA00 0x1 + mww 0x20000000 0 + + # Precharge All Banks command + mww 0xFFFFEA00 0x2 + mww 0x20000000 0 + + # Set 1st CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000010 0x00000001 + + # Set 2nd CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000020 0x00000002 + + # Set 3rd CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000030 0x00000003 + + # Set 4th CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000040 0x00000004 + + # Set 5th CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000050 0x00000005 + + # Set 6th CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000060 0x00000006 + + # Set 7th CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000070 0x00000007 + + # Set 8th CBR + mww 0xFFFFEA00 0x00000004 + mww 0x20000080 0x00000008 + + # Set LMR operation + mww 0xFFFFEA00 0x00000003 + + # Perform LMR burst=1, lat=2 + mww 0x20000020 0xCAFEDEDE + + # Set Refresh Timer + mww 0xFFFFEA04 0x00000203 + + # Set Normal mode + mww 0xFFFFEA00 0x00000000 + mww 0x20000000 0x00000000 + + #remap internal memory at address 0x0 + mww 0xffffef00 0x3 + + echo "SDRAM configuration ok." +} + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + +#set _FLASHNAME $_CHIPNAME.flash +#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/openocd-win/openocd/scripts/board/at91eb40a.cfg b/openocd-win/openocd/scripts/board/at91eb40a.cfg new file mode 100644 index 0000000..60c6c6e --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91eb40a.cfg @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#Script for AT91EB40a + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91eb40a +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f0f0f0f +} + + +#Atmel ties SRST & TRST together, at which point it makes +#no sense to use TRST, but use TMS instead. +# +#The annoying thing with tying SRST & TRST together is that +#there is no way to halt the CPU *before and during* the +#SRST reset, which means that the CPU will run a number +#of cycles before it can be halted(as much as milliseconds). +reset_config srst_only srst_pulls_trst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +#target configuration +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +# speed up memory downloads +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +#flash driver +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME + +# required for usable performance. Used for lots of +# other things than flash programming. +$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { + echo "Running reset init script for AT91EB40A" + # Reset script for AT91EB40a + reg cpsr 0x000000D3 + mww 0xFFE00020 0x1 + mww 0xFFE00024 0x00000000 + mww 0xFFE00000 0x01002539 + mww 0xFFFFF124 0xFFFFFFFF + mww 0xffff0010 0x100 + mww 0xffff0034 0x100 +} + +# This target is pretty snappy... +adapter speed 16000 diff --git a/openocd-win/openocd/scripts/board/at91rm9200-dk.cfg b/openocd-win/openocd/scripts/board/at91rm9200-dk.cfg new file mode 100644 index 0000000..3751103 --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91rm9200-dk.cfg @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is for the "at91rm9200-DK" (not the EK) eval board. +# +# The two are probably very simular.... I have DK... +# +# It has atmel at91rm9200 chip. +source [find target/at91rm9200.cfg] + +reset_config trst_and_srst + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { at91rm9200_dk_init } + +#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME + + +proc at91rm9200_dk_init { } { + # Try to run at 1khz... Yea, that slow! + # Chip is really running @ 32khz + adapter speed 8 + + mww 0xfffffc64 0xffffffff + ## disable all clocks but system clock + mww 0xfffffc04 0xfffffffe + ## disable all clocks to pioa and piob + mww 0xfffffc14 0xffffffc3 + ## master clock = slow cpu = slow + ## (means the CPU is running at 32khz!) + mww 0xfffffc30 0 + ## main osc enable + mww 0xfffffc20 0x0000ff01 + ## program pllA + mww 0xfffffc28 0x20263e04 + ## program pllB + mww 0xfffffc2c 0x10483e0e + ## let pll settle... sleep 100msec + sleep 100 + ## switch to fast clock + mww 0xfffffc30 0x202 + ## Sleep some - (go read) + sleep 100 + + #======================================== + # CPU now runs at 180mhz + # SYS runs at 60mhz. + adapter speed 40000 + #======================================== + + + ## set memc for all memories + mww 0xffffff60 0x02 + ## program smc controller + mww 0xffffff70 0x3284 + ## init sdram + mww 0xffffff98 0x7fffffd0 + ## all banks precharge + mww 0xffffff80 0x02 + ## touch sdram chip to make it work + mww 0x20000000 0 + ## sdram controller mode register + mww 0xffffff90 0x04 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + ## sdram controller mode register + ## Refresh, etc.... + mww 0xffffff90 0x03 + mww 0x20000080 0 + mww 0xffffff94 0x1f4 + mww 0x20000080 0 + mww 0xffffff90 0x10 + mww 0x20000000 0 + mww 0xffffff00 0x01 + +} diff --git a/openocd-win/openocd/scripts/board/at91rm9200-ek.cfg b/openocd-win/openocd/scripts/board/at91rm9200-ek.cfg new file mode 100644 index 0000000..e38914e --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91rm9200-ek.cfg @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +# +# under GPLv2 Only +# +# This is for the "at91rm9200-ek" eval board. +# +# +# It has atmel at91rm9200 chip. +source [find target/at91rm9200.cfg] + +reset_config trst_and_srst + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { at91rm9200_ek_init } + +## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME + +# The chip may run @ 32khz, so set a really low JTAG speed +adapter speed 8 + +proc at91rm9200_ek_init { } { + # Try to run at 1khz... Yea, that slow! + # Chip is really running @ 32khz + adapter speed 8 + + mww 0xfffffc64 0xffffffff + ## disable all clocks but system clock + mww 0xfffffc04 0xfffffffe + ## disable all clocks to pioa and piob + mww 0xfffffc14 0xffffffc3 + ## master clock = slow cpu = slow + ## (means the CPU is running at 32khz!) + mww 0xfffffc30 0 + ## main osc enable + mww 0xfffffc20 0x0000ff01 + ## MC_PUP + mww 0xFFFFFF50 0x00000000 + ## MC_PUER: Memory controller protection unit disable + mww 0xFFFFFF54 0x00000000 + ## EBI_CFGR + mww 0xFFFFFF64 0x00000000 + ## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS + mww 0xFFFFFF70 0x00003284 + + ## Init Clocks + ## CKGR_PLLAR + mww 0xFFFFFC28 0x2000BF05 + ## PLLAR: 179,712000 MHz for PCK + mww 0xFFFFFC28 0x20263E04 + sleep 100 + ## PMC_MCKR + mww 0xFFFFFC30 0x00000100 + sleep 100 + ## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA + mww 0xFFFFFC30 0x00000202 + sleep 100 + + #======================================== + # CPU now runs at 180mhz + # SYS runs at 60mhz. + adapter speed 40000 + #======================================== + + ## Init SDRAM + ## PIOC_ASR: Configure PIOC as peripheral (D16/D31) + mww 0xFFFFF870 0xFFFF0000 + ## PIOC_BSR: + mww 0xFFFFF874 0x00000000 + ## PIOC_PDR: + mww 0xFFFFF804 0xFFFF0000 + ## EBI_CSA : CS1=SDRAM + mww 0xFFFFFF60 0x00000002 + ## EBI_CFGR: + mww 0xFFFFFF64 0x00000000 + ## SDRC_CR : + mww 0xFFFFFF98 0x2188c155 + ## SDRC_MR : Precharge All + mww 0xFFFFFF90 0x00000002 + ## access SDRAM + mww 0x20000000 0x00000000 + ## SDRC_MR : Refresh + mww 0xFFFFFF90 0x00000004 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 + ## SDRC_MR : Load Mode Register + mww 0xFFFFFF90 0x00000003 + ## access SDRAM + mww 0x20000080 0x00000000 + ## SDRC_TR : Write refresh rate + mww 0xFFFFFF94 0x000002E0 + ## access SDRAM + mww 0x20000000 0x00000000 + ## SDRC_MR : Normal Mode + mww 0xFFFFFF90 0x00000000 + ## access SDRAM + mww 0x20000000 0x00000000 +} diff --git a/openocd-win/openocd/scripts/board/at91sam9261-ek.cfg b/openocd-win/openocd/scripts/board/at91sam9261-ek.cfg new file mode 100644 index 0000000..c2d97b0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91sam9261-ek.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Atmel AT91SAM9261-EK eval board +################################################################################ + +source [find mem_helper.tcl] +source [find target/at91sam9261.cfg] +uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]] + +# By default S1 is open and this means that NTRST is not connected. +# The reset_config in target/at91sam9261.cfg is overridden here. +# (or S1 must be populated with a 0 Ohm resistor) +reset_config srst_only + +scan_chain +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init } +$_TARGETNAME configure -event reset-start { at91sam9_reset_start } + +proc at91sam9261ek_reset_init { } { + + ;# for ppla at 199 Mhz + set config(master_pll_div) 15 + set config(master_pll_mul) 162 + + ;# for ppla at 239 Mhz + ;# set master_pll_div 1 + ;# set master_pll_mul 13 + + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt + + set config(wdt_mr_val) $val + + ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash + set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA + set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] + + ;# SDRAMC_CR - Configuration register + set val $::AT91_SDRAMC_NC_9 + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay + + set config(sdram_cr_val) $val + + set config(sdram_tr_val) 0x13c + + set config(sdram_base) $::AT91_CHIPSELECT_1 + at91sam9_reset_init $config +} diff --git a/openocd-win/openocd/scripts/board/at91sam9263-ek.cfg b/openocd-win/openocd/scripts/board/at91sam9263-ek.cfg new file mode 100644 index 0000000..328a792 --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91sam9263-ek.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Atmel AT91SAM9263-EK eval board +################################################################################ + +source [find mem_helper.tcl] +source [find target/at91sam9263.cfg] +uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]] + +# By default S1 is open and this means that NTRST is not connected. +# The reset_config in target/at91sam9263.cfg is overridden here. +# (or S1 must be populated with a 0 Ohm resistor) +reset_config srst_only + +scan_chain +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init } +$_TARGETNAME configure -event reset-start { at91sam9_reset_start } + +proc at91sam9263ek_reset_init { } { + + set config(master_pll_div) 14 + set config(master_pll_mul) 171 + + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt + + set config(wdt_mr_val) $val + + set config(sdram_piod) 1 + ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash + set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA + + set val $::AT91_MATRIX_EBI0_DBPUC + set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] + set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] + set config(matrix_ebicsa_val) $val + + ;# SDRAMC_CR - Configuration register + set val $::AT91_SDRAMC_NC_9 + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (1 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (2 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (1 << 28)}] ;# Exit Self Refresh to Active Delay + + set config(sdram_cr_val) $val + + set config(sdram_tr_val) 0x13c + + set config(sdram_base) $::AT91_CHIPSELECT_1 + at91sam9_reset_init $config +} diff --git a/openocd-win/openocd/scripts/board/at91sam9g20-ek.cfg b/openocd-win/openocd/scripts/board/at91sam9g20-ek.cfg new file mode 100644 index 0000000..4740471 --- /dev/null +++ b/openocd-win/openocd/scripts/board/at91sam9g20-ek.cfg @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################################# +# # +# Author: Gary Carlson (gcarlson@carlson-minot.com) # +# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. # +# # +################################################################################################# + +source [find target/at91sam9g20.cfg] + +set _FLASHTYPE nandflash_cs3 + +# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore +# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is +# added to the board to connect the trst signal, then this parameter may need to be changed. + +reset_config srst_only + +adapter srst delay 200 +jtag_ntrst_delay 200 + +# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the +# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has +# some powerful features, we want to have a special function that handles "reset init". To do this we declare +# an event handler where these special activities can take place. + +scan_chain +$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init} +$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start} + +# NandFlash configuration and definition + +nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800 +at91sam9 cle 0 22 +at91sam9 ale 0 21 +at91sam9 rdy_busy 0 0xfffff800 13 +at91sam9 ce 0 0xfffff800 14 + +proc read_register {register} { + return [read_memory $register 32 1] +} + +proc at91sam9g20_reset_start { } { + + # Make sure that the the jtag is running slow, since there are a number of different ways the board + # can be configured coming into this state that can cause communication problems with the jtag + # adapter. Also since this call can be made following a "reset init" where fast memory accesses + # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower + # jtag speed without causing GDB keep alive problem. + + arm7_9 fast_memory_access disable + adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. + halt ;# Make sure processor is halted, or error will result in following steps. + wait_halt 10000 + mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset. +} + +proc at91sam9g20_reset_init { } { + + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires + # a number of steps that must be carefully performed. The process outline below follows the + # recommended procedure outlined in the AT91SAM9G20 technical manual. + # + # Several key and very important things to keep in mind: + # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This + # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor + # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. + + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog. + + # Enable the main 18.432 MHz oscillator in CKGR_MOR register. + # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. + + mww 0xfffffc20 0x00004001 + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } + + # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). + # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. + + mww 0xfffffc28 0x202a3f01 + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } + + # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00000101 + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } + + # Now change PMC_MCKR register to select PLLA. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001302 + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } + + # Processor and master clocks are now operating and stable at maximum frequency possible: + # -> MCLK = 132.096 MHz + # -> PCLK = 396.288 MHz + + # Switch over to adaptive clocking. + + adapter speed 0 + + # Enable faster DCC downloads and memory accesses. + + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable + + # To be able to use external SDRAM, several peripheral configuration registers must + # be modified. The first change is made to PIO_ASR to select peripheral functions + # for D15 through D31. The second change is made to the PIO_PDR register to disable + # this for D15 through D31. + + mww 0xfffff870 0xffff0000 + mww 0xfffff804 0xffff0000 + + # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller + # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on + # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller. + + mww 0xffffef1c 0x000100a + + # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics + # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting + # a number of registers. The first step involves setting up the general I/O pins on the processor + # to be able to interface and support the external memory. + + mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock + mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS) + mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14 + mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13 + mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND + + # The exact physical timing characteristics for the memory type used on the current board + # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3, + # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers + # is a little tedious to do here. If you have questions about how to do this, Atmel has + # a decent application note #6255B that covers this process. + + mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE + mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals + mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle + mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, + + mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers + mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits) + + # Identify NandFlash bank 0. + + nand probe nandflash_cs3 + + # The AT91SAM9G20-EK evaluation board has built-in serial data flash also. + + # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations + # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference + # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted + # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock + # of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires: + # + # CAS latency = 3 cycles + # TXSR = 10 cycles + # TRAS = 6 cycles + # TRCD = 3 cycles + # TRP = 3 cycles + # TRC = 9 cycles + # TWR = 2 cycles + # 9 column, 13 row, 4 banks + # refresh equal to or less then 7.8 us for commercial/industrial rated devices + # + # Thus SDRAM_CR = 0xa6339279 + + mww 0xffffea08 0xa6339279 + + # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000001 + mww 0x20000000 0 + + # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero + # value into the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000002 + mww 0x20000000 0 + + # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing + # zero values eight times into the starting memory location for the SDRAM. + + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + + # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x3 + mww 0x20000000 0 + + # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting + # memory location for the SDRAM. + + mww 0xffffea00 0x0 + mww 0x20000000 0 + + # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles). + + mww 0xffffea04 0x0000039c +} diff --git a/openocd-win/openocd/scripts/board/atmel_at91sam7s-ek.cfg b/openocd-win/openocd/scripts/board/atmel_at91sam7s-ek.cfg new file mode 100644 index 0000000..9cf85df --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_at91sam7s-ek.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Atmel AT91SAM7S-EK +# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784 + +set CHIPNAME at91sam7s256 + +source [find target/at91sam7sx.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_at91sam9260-ek.cfg b/openocd-win/openocd/scripts/board/atmel_at91sam9260-ek.cfg new file mode 100644 index 0000000..56fce3a --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_at91sam9260-ek.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Atmel AT91SAM9260-EK eval board +# +# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933 +# +# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz +# OSCSEL configured for external 32.768 kHz crystal +# +# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks +# +################################################################################ + +# We add to the minimal configuration. +source [find target/at91sam9260.cfg] + +# By default S1 is open and this means that NTRST is not connected. +# The reset_config in target/at91sam9260.cfg is overridden here. +# (or S1 must be populated with a 0 Ohm resistor) +reset_config srst_only + +$_TARGETNAME configure -event reset-start { + # At reset CPU runs at 32.768 kHz. + # JTAG Frequency must be 6 times slower if RCLK is not supported. + jtag_rclk 5 + halt + # RSTC_MR : enable user reset, MMU may be enabled... use physical address + mww phys 0xfffffd08 0xa5000501 +} + +$_TARGETNAME configure -event reset-init { + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2) + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz) + sleep 10 ;# wait 10 ms + + # Increase JTAG Speed to 6 MHz if RCLK is not supported + jtag_rclk 6000 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 + + mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory + + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks) + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode + mww 0x20000000 0 + mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us +} diff --git a/openocd-win/openocd/scripts/board/atmel_at91sam9rl-ek.cfg b/openocd-win/openocd/scripts/board/atmel_at91sam9rl-ek.cfg new file mode 100644 index 0000000..cc3d974 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_at91sam9rl-ek.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# +# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6 +# +# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz +# OSCSEL configured for external 32.768 kHz crystal +# +# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks +# +################################################################################ + +# We add to the minimal configuration. +source [find target/at91sam9rl.cfg] + +$_TARGETNAME configure -event reset-start { + # At reset CPU runs at 32.768 kHz. + # JTAG Frequency must be 6 times slower if RCLK is not supported. + jtag_rclk 5 + halt + # RSTC_MR : enable user reset, MMU may be enabled... use physical address + mww phys 0xfffffd08 0xa5000501 +} + +$_TARGETNAME configure -event reset-init { + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2031bf03 ;# CKGR_PLLR: Set PLL Register for 200 MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2) + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLL is selected (100 MHz) + sleep 10 ;# wait 10 ms + + # Increase JTAG Speed to 6 MHz if RCLK is not supported + jtag_rclk 6000 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + mww 0xfffff670 0xffff0000 ;# PIO_ASR : Select peripheral function for D16..D31 (PIOB) + mww 0xfffff604 0xffff0000 ;# PIO_PDR : Disable PIO function for D16..D31 (PIOB) + + mww 0xffffef20 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory + + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks) + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode + mww 0x20000000 0 + mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us +} diff --git a/openocd-win/openocd/scripts/board/atmel_sam3n_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam3n_ek.cfg new file mode 100644 index 0000000..af2fd95 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam3n_ek.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Board configuration for Atmel's SAM3N-EK +# + +reset_config srst_only + +set CHIPNAME at91sam3n4c + +adapter speed 32 + +source [find target/at91sam3nXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_sam3s_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam3s_ek.cfg new file mode 100644 index 0000000..136e31d --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam3s_ek.cfg @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/at91sam3sXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_sam3u_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam3u_ek.cfg new file mode 100644 index 0000000..c308003 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam3u_ek.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/at91sam3u4e.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/atmel_sam3x_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam3x_ek.cfg new file mode 100644 index 0000000..c321cfb --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam3x_ek.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/at91sam3ax_8x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/atmel_sam4e_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam4e_ek.cfg new file mode 100644 index 0000000..61191a9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam4e_ek.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an SAM4E-EK board with a single SAM4E16 chip. +# http://www.atmel.com/tools/sam4e-ek.aspx + +# chip name +set CHIPNAME SAM4E16E + +source [find target/at91sam4sXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_sam4l8_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_sam4l8_xplained_pro.cfg new file mode 100644 index 0000000..d0c4516 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam4l8_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAM4L8 Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME ATSAM4LC8CA + +source [find target/at91sam4lXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_sam4s_ek.cfg b/openocd-win/openocd/scripts/board/atmel_sam4s_ek.cfg new file mode 100644 index 0000000..7e4bb83 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam4s_ek.cfg @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/at91sam4sXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_sam4s_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_sam4s_xplained_pro.cfg new file mode 100644 index 0000000..92191c7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_sam4s_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAM4S Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME ATSAM4SD32C + +source [find target/at91sam4sd32x.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samc20_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samc20_xplained_pro.cfg new file mode 100644 index 0000000..3ac89a5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samc20_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMC20 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samc20j18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samc21_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samc21_xplained_pro.cfg new file mode 100644 index 0000000..5ad6ccf --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samc21_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMC21 Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samc21j18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samd10_xplained_mini.cfg b/openocd-win/openocd/scripts/board/atmel_samd10_xplained_mini.cfg new file mode 100644 index 0000000..f9f1d24 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samd10_xplained_mini.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMD10 Xplained mini evaluation kit. +# http://www.atmel.com/tools/atsamd10-xmini.aspx + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd10d14 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samd11_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samd11_xplained_pro.cfg new file mode 100644 index 0000000..724c921 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samd11_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMD11 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd11d14 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samd20_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samd20_xplained_pro.cfg new file mode 100644 index 0000000..1492958 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samd20_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMD20 Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd20j18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samd21_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samd21_xplained_pro.cfg new file mode 100644 index 0000000..f55b6b9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samd21_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMD21 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd21j18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_same70_xplained.cfg b/openocd-win/openocd/scripts/board/atmel_same70_xplained.cfg new file mode 100644 index 0000000..f20e2a3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_same70_xplained.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAME70 Xplained evaluation kit. +# http://www.atmel.com/tools/ATSAME70-XPLD.aspx +# +# Connect using the EDBG chip on the dev kit over USB +source [find interface/cmsis-dap.cfg] + +set CHIPNAME atsame70q21 + +source [find target/atsamv.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/atmel_samg53_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samg53_xplained_pro.cfg new file mode 100644 index 0000000..060750c --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samg53_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMG53 Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME ATSAMG53N19 + +source [find target/at91samg5x.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samg55_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samg55_xplained_pro.cfg new file mode 100644 index 0000000..147dc73 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samg55_xplained_pro.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMG55 Xplained Pro evaluation kit. +# http://www.atmel.com/tools/ATSAMG55-XPRO.aspx +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME ATSAMG55J19 + +source [find target/at91samg5x.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_saml21_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_saml21_xplained_pro.cfg new file mode 100644 index 0000000..8e62eb2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_saml21_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAML21 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91saml21j18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samr21_xplained_pro.cfg b/openocd-win/openocd/scripts/board/atmel_samr21_xplained_pro.cfg new file mode 100644 index 0000000..cd6d28e --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samr21_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMR21 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samr21g18 + +source [find target/at91samdXX.cfg] diff --git a/openocd-win/openocd/scripts/board/atmel_samv71_xplained_ultra.cfg b/openocd-win/openocd/scripts/board/atmel_samv71_xplained_ultra.cfg new file mode 100644 index 0000000..9368f61 --- /dev/null +++ b/openocd-win/openocd/scripts/board/atmel_samv71_xplained_ultra.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Atmel SAMV71 Xplained Ultra evaluation kit. +# http://www.atmel.com/tools/ATSAMV71-XULT.aspx +# +# To connect using the EDBG chip on the dev kit over USB, you will +# first need to source [find interface/cmsis-dap.cfg] +# however, since this board also has a SWD+ETM connector, we don't +# automatically source that file here. + +set CHIPNAME samv71 + +source [find target/atsamv.cfg] diff --git a/openocd-win/openocd/scripts/board/avnet_ultrazed-eg.cfg b/openocd-win/openocd/scripts/board/avnet_ultrazed-eg.cfg new file mode 100644 index 0000000..6701fd1 --- /dev/null +++ b/openocd-win/openocd/scripts/board/avnet_ultrazed-eg.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# AVNET UltraZED EG StarterKit +# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2 +# +source [find interface/ftdi/digilent_jtag_smt2_nc.cfg] +# jtag transport only +transport select jtag +# reset lines are not wired +reset_config none + +# slow default clock +adapter speed 1000 + +set CHIPNAME uscale + +source [find target/xilinx_zynqmp.cfg] diff --git a/openocd-win/openocd/scripts/board/balloon3-cpu.cfg b/openocd-win/openocd/scripts/board/balloon3-cpu.cfg new file mode 100644 index 0000000..3ee840b --- /dev/null +++ b/openocd-win/openocd/scripts/board/balloon3-cpu.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/ +# The board has separate JTAG ports for cpu and CPLD/FPGA devices +# Chaining is done on IO interfaces if desired. + +source [find target/pxa270.cfg] + +# The board supports separate reset lines +# Override this in the interface config for parallel dongles +reset_config trst_and_srst separate + +# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> +# 29LV650 64Mbit Flash +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/bcm28155_ap.cfg b/openocd-win/openocd/scripts/board/bcm28155_ap.cfg new file mode 100644 index 0000000..99da948 --- /dev/null +++ b/openocd-win/openocd/scripts/board/bcm28155_ap.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BCM28155_AP + +adapter speed 20000 + +set CHIPNAME bcm28155 +source [find target/bcm281xx.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/bemicro_cycloneiii.cfg b/openocd-win/openocd/scripts/board/bemicro_cycloneiii.cfg new file mode 100644 index 0000000..95dd394 --- /dev/null +++ b/openocd-win/openocd/scripts/board/bemicro_cycloneiii.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BeMicro Cyclone III + + +adapter driver ftdi +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +ftdi vid_pid 0x0403 0xa4a0 +reset_config none +transport select jtag + +adapter speed 10000 + +source [find fpga/altera-cycloneiii.cfg] + +#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf + +#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load 0 cycloneiii_blinker.rbf" +# "ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555" diff --git a/openocd-win/openocd/scripts/board/bluefield.cfg b/openocd-win/openocd/scripts/board/bluefield.cfg new file mode 100644 index 0000000..e96a74e --- /dev/null +++ b/openocd-win/openocd/scripts/board/bluefield.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Board configuration for BlueField SoC. +# + +source [find interface/rshim.cfg] +source [find target/bluefield.cfg] diff --git a/openocd-win/openocd/scripts/board/bt-homehubv1.cfg b/openocd-win/openocd/scripts/board/bt-homehubv1.cfg new file mode 100644 index 0000000..bbb6fa4 --- /dev/null +++ b/openocd-win/openocd/scripts/board/bt-homehubv1.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# BT HomeHub v1 +# + +set partition_list { + CFE { Bootloader 0xbe400000 0x00020000 } + firmware { "Kernel+rootfs" 0xbe420000 0x007d0000 } + fisdir { "FIS Directory" 0xbebf0000 0x0000f000 } + nvram { "Config space" 0xbebff000 0x00001000 } +} + +source [find target/bcm6348.cfg] + +set _FLASHNAME $_CHIPNAME.norflash +flash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/calao-usb-a9260.cfg b/openocd-win/openocd/scripts/board/calao-usb-a9260.cfg new file mode 100644 index 0000000..52fede0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/calao-usb-a9260.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# CALAO Systems USB-A9260 (C01 and C02) + +adapter driver ftdi +ftdi device_desc "USB-A9260" +ftdi vid_pid 0x0403 0x6001 0x0403 0x6010 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 + +transport select jtag + +source [find target/at91sam9260.cfg] diff --git a/openocd-win/openocd/scripts/board/calao-usb-a9g20-c01.cfg b/openocd-win/openocd/scripts/board/calao-usb-a9g20-c01.cfg new file mode 100644 index 0000000..d201786 --- /dev/null +++ b/openocd-win/openocd/scripts/board/calao-usb-a9g20-c01.cfg @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# CALAO Systems USB-A9G20-C01 +# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang + +adapter driver ftdi +ftdi device_desc "USB-A9G20" +ftdi vid_pid 0x0403 0x6010 +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 + +transport select jtag + +source [find target/at91sam9g20.cfg] +source [find mem_helper.tcl] + +proc at91sam9g20_reset_start { } { + + # Make sure that the jtag is running slow, since there are a number of different ways the board + # can be configured coming into this state that can cause communication problems with the jtag + # adapter. Also since this call can be made following a "reset init" where fast memory accesses + # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower + # jtag speed without causing GDB keep alive problem. + + arm7_9 fast_memory_access disable + adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow. + halt 0 ;# Make sure processor is halted, or error will result in following steps. + wait_halt 10000 + # RSTC_MR : enable user reset, MMU may be enabled... use physical address + mww phys 0xfffffd08 0xa5000501 +} + +proc at91sam9g20_reset_init { } { + + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires + # a number of steps that must be carefully performed. The process outline below follows the + # recommended procedure outlined in the AT91SAM9G20 technical manual. + # + # Several key and very important things to keep in mind: + # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This + # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor + # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. + + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog. + + # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register. + + mww 0xfffffc20 0x00000002 + + # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132). + # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. + + mww 0xfffffc28 0x20843F02 + while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 } + + # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001300 + while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 } + + # Now change PMC_MCKR register to select PLLA. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001302 + while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 } + + # Processor and master clocks are now operating and stable at maximum frequency possible: + # -> MCLK = 133.000 MHz + # -> PCLK = 400.000 MHz + + # Switch to fast JTAG speed + + adapter speed 9500 + + # Enable faster DCC downloads. + + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable + + # To be able to use external SDRAM, several peripheral configuration registers must + # be modified. The first change is made to PIO_ASR to select peripheral functions + # for D15 through D31. The second change is made to the PIO_PDR register to disable + # this for D15 through D31. + + mww 0xfffff870 0xffff0000 + mww 0xfffff804 0xffff0000 + + # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller + # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on + # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller. + + mww 0xffffef1c 0x000000a + + # The USB-A9G20 Embedded computer has built-in NandFlash. The exact physical timing characteristics + # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting + # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. + + mww 0xffffec30 0x00020002 + mww 0xffffec34 0x04040404 + mww 0xffffec38 0x00070007 + mww 0xffffec3c 0x00030003 + + # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations + # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference + # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted + # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock + # of 133.000 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires: + # + # CAS latency = 3 cycles + # TXSR = 10 cycles + # TRAS = 6 cycles + # TRCD = 3 cycles + # TRP = 3 cycles + # TRC = 9 cycles + # TWR = 2 cycles + # 9 column, 13 row, 4 banks + # refresh equal to or less then 7.8 us for commercial/industrial rated devices + # + # Thus SDRAM_CR = 0xa6339279 + + mww 0xffffea08 0xa6339279 + + # Memory Device Type: SDRAM (low-power would be 0x1) + mww 0xffffea24 0x00000000 + + # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000001 + mww 0x20000000 0 + + # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero + # value into the starting memory location for the SDRAM. + + mww 0xffffea00 0x00000002 + mww 0x20000000 0 + + # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing + # zero values eight times into the starting memory location for the SDRAM. + + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + + # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the + # the starting memory location for the SDRAM. + + mww 0xffffea00 0x3 + mww 0x20000000 0 + + # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting + # memory location for the SDRAM. + + mww 0xffffea00 0x0 + mww 0x20000000 0 + + # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles). + + mww 0xffffea04 0x0000039c +} + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start} +$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init} diff --git a/openocd-win/openocd/scripts/board/certuspro_evaluation.cfg b/openocd-win/openocd/scripts/board/certuspro_evaluation.cfg new file mode 100644 index 0000000..5ff2a1e --- /dev/null +++ b/openocd-win/openocd/scripts/board/certuspro_evaluation.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 10000 + +source [find fpga/lattice_certuspro.cfg] diff --git a/openocd-win/openocd/scripts/board/colibri.cfg b/openocd-win/openocd/scripts/board/colibri.cfg new file mode 100644 index 0000000..b44985d --- /dev/null +++ b/openocd-win/openocd/scripts/board/colibri.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Toradex Colibri PXA270 +source [find target/pxa270.cfg] +reset_config trst_and_srst srst_push_pull +adapter srst pulse_width 40 + +# CS0 -- one bank of CFI flash, 32 MBytes +# the bank is 32-bits wide, two 16-bit chips in parallel +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/crossbow_tech_imote2.cfg b/openocd-win/openocd/scripts/board/crossbow_tech_imote2.cfg new file mode 100644 index 0000000..07ce8c7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/crossbow_tech_imote2.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Crossbow Technology iMote2 + +set CHIPNAME imote2 +source [find target/pxa270.cfg] + +# longer-than-normal reset delay +adapter srst delay 800 + +reset_config trst_and_srst separate + +# works for P30 flash +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/csb337.cfg b/openocd-win/openocd/scripts/board/csb337.cfg new file mode 100644 index 0000000..f75abbe --- /dev/null +++ b/openocd-win/openocd/scripts/board/csb337.cfg @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Cogent CSB337 +# http://cogcomp.com/csb_csb337.htm + +source [find target/at91rm9200.cfg] + +# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME + +# ETM9 trace port connector present on this board, 16 data pins. +if { [info exists ETM_DRIVER] } { + etm config $_TARGETNAME 16 normal half $ETM_DRIVER + # OpenOCD may someday support a real trace port driver... + # system config file would need to configure it. +} else { + etm config $_TARGETNAME 16 normal half dummy + etm_dummy config $_TARGETNAME +} + +proc csb337_clk_init { } { + # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock + adapter speed 8 + + # CKGR_MOR: start main oscillator (3.6864 MHz) + mww 0xfffffc20 0xff01 + sleep 10 + + # CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz) + mww 0xfffffc28 0x20313e01 + # CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2) + mww 0xfffffc2c 0x12703e18 + # let PLLs lock + sleep 10 + + # PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4 + mww 0xfffffc30 0x0302 + sleep 20 + + # CPU is in Normal Mode ... allows faster JTAG clock speed + adapter speed 40000 +} + +proc csb337_nor_init { } { + # SMC_CSR0: adjust timings (10 wait states) + mww 0xffffff70 0x1100318a + + flash probe 0 +} + +proc csb337_sdram_init { } { + # enable PIOC clock + mww 0xfffffc10 0x0010 + # PC31..PC16 are D31..D16, with internal pullups like D15..D0 + mww 0xfffff870 0xffff0000 + mww 0xfffff874 0x0 + mww 0xfffff804 0xffff0000 + + # SDRC_CR: set timings + mww 0xffffff98 0x2188b0d5 + + # SDRC_MR: issue all banks precharge to SDRAM + mww 0xffffff90 2 + mww 0x20000000 0 + + # SDRC_MR: 8 autorefresh cycles + mww 0xffffff90 4 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + mww 0x20000000 0 + + # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc) + mww 0xffffff90 3 + mww 0x20000080 0 + + # SDRC_TR: set refresh rate + mww 0xffffff94 0x200 + mww 0x20000000 0 + + # SDRC_MR: normal mode, 32 bit bus + mww 0xffffff90 0 + mww 0x20000000 0 +} + +# The rm9200 chip has just been reset. Bring it up far enough +# that we can write flash or run code from SDRAM. +proc csb337_reset_init { } { + csb337_clk_init + + # EBI_CSA: CS0 = NOR, CS1 = SDRAM + mww 0xffffff60 0x02 + + csb337_nor_init + csb337_sdram_init + + # Update CP15 control register ... we don't seem to be able to + # read/modify/write its value through a TCL variable, so just + # write it. Fields are zero unless listed here ... and note + # that OpenOCD numbers this register "2", not "1" (!). + # + # - Core to use Async Clocking mode (so it uses 184 MHz most + # of the time instead of limiting to the master clock rate): + # iA(31) = 1, nF(30) = 1 + # - Icache on (it's disabled now, slowing i-fetches) + # I(12) = 1 + # - Reserved/ones + # 6:3 = 1 + arm920t cp15 2 0xc0001078 +} + +$_TARGETNAME configure -event reset-init {csb337_reset_init} + +arm7_9 fast_memory_access enable diff --git a/openocd-win/openocd/scripts/board/csb732.cfg b/openocd-win/openocd/scripts/board/csb732.cfg new file mode 100644 index 0000000..6df1750 --- /dev/null +++ b/openocd-win/openocd/scripts/board/csb732.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Cogent CSB732 board has a single i.MX35 chip +source [find target/imx35.cfg] + +# Determined by trial and error +reset_config trst_and_srst combined +adapter srst delay 200 +jtag_ntrst_delay 200 + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { csb732_init } + +# Bare-bones initialization of core clocks and SDRAM +proc csb732_init { } { + + # Disable fast writing only for init + memwrite burst disable + + # All delay loops are omitted. + # We assume the interpreter latency is enough. + + # Allow access to all coprocessors + arm mcr 15 0 15 1 0 0x2001 + + # Disable MMU, caches, write buffer + arm mcr 15 0 1 0 0 0x78 + + # Grant manager access to all domains + arm mcr 15 0 3 0 0 0xFFFFFFFF + + # Set ARM clock to 532 MHz, AHB to 133 MHz + mww 0x53F80004 0x1000 + + # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz + mww 0x53F8001C 0xB2C01 + + set ESDMISC 0xB8001010 + set ESDCFG0 0xB8001004 + set ESDCTL0 0xB8001000 + + # Enable DDR + mww $ESDMISC 0x4 + + # Timing + mww $ESDCFG0 0x007fff3f + + # CS0 + mww $ESDCTL0 0x92120080 + + # Precharge all dummy write + mww 0x80000400 0 + + # Enable CS) auto-refresh + mww $ESDCTL0 0xA2120080 + + # Refresh twice (dummy writes) + mww 0x80000000 0 + mww 0x80000000 0 + + # Enable CS0 load mode register + mww $ESDCTL0 0xB2120080 + + # Dummy writes + mwb 0x80000033 0x01 + mwb 0x81000000 0x01 + + mww $ESDCTL0 0x82226080 + mww 0x80000000 0 + + # Re-enable fast writing + memwrite burst enable +} diff --git a/openocd-win/openocd/scripts/board/da850evm.cfg b/openocd-win/openocd/scripts/board/da850evm.cfg new file mode 100644 index 0000000..12de3a7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/da850evm.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#DA850 EVM board +# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939 +# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit + +source [find target/omapl138.cfg] + +reset_config trst_and_srst separate + +#currently any pinmux/timing must be setup by UBL before openocd can do debug +#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg diff --git a/openocd-win/openocd/scripts/board/digi_connectcore_wi-9c.cfg b/openocd-win/openocd/scripts/board/digi_connectcore_wi-9c.cfg new file mode 100644 index 0000000..0ff4742 --- /dev/null +++ b/openocd-win/openocd/scripts/board/digi_connectcore_wi-9c.cfg @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: DIGI ConnectCore Wi-9C +###################################### + +reset_config trst_and_srst + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ns9360 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN big +} + + +# What's a good fallback frequency for this board if RCLK is +# not available?? +jtag_rclk 1000 + + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926031 +} + +set _TARGETNAME $_CHIPNAME.cpu +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +adapter srst delay 200 +jtag_ntrst_delay 0 + + +###################### +# Target configuration +###################### + +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-init { + mww 0x90600104 0x33313333 + mww 0xA0700000 0x00000001 ;# Enable the memory controller. + mww 0xA0700024 0x00000006 ;# Set the refresh counter 6 + mww 0xA0700028 0x00000001 ;# + mww 0xA0700030 0x00000001 ;# Set the precharge period + mww 0xA0700034 0x00000004 ;# Active to precharge command period is 16 clock cycles + mww 0xA070003C 0x00000001 ;# tAPR + mww 0xA0700040 0x00000005 ;# tDAL + mww 0xA0700044 0x00000001 ;# tWR + mww 0xA0700048 0x00000006 ;# tRC 32 clock cycles + mww 0xA070004C 0x00000006 ;# tRFC 32 clock cycles + mww 0xA0700054 0x00000001 ;# tRRD + mww 0xA0700058 0x00000001 ;# tMRD + mww 0xA0700100 0x00004280 ;# Dynamic Config 0 (cs4) + mww 0xA0700120 0x00004280 ;# Dynamic Config 1 (cs5) + mww 0xA0700140 0x00004280 ;# Dynamic Config 2 (cs6) + mww 0xA0700160 0x00004280 ;# Dynamic Config 3 (cs7) + # + mww 0xA0700104 0x00000203 ;# CAS latency is 2 at 100 MHz + mww 0xA0700124 0x00000203 ;# CAS latency is 2 at 100 MHz + mww 0xA0700144 0x00000203 ;# CAS latency is 2 at 100 MHz + mww 0xA0700164 0x00000203 ;# CAS latency is 2 at 100 MHz + # + mww 0xA0700020 0x00000103 ;# issue SDRAM PALL command + # + mww 0xA0700024 0x00000001 ;# Set the refresh counter to be as small as possible + # + # Add some dummy writes to give the SDRAM time to settle, it needs two + # AHB clock cycles, here we poke in the debugger flag, this lets + # the software know that we are in the debugger + mww 0xA0900000 0x00000002 + mww 0xA0900000 0x00000002 + mww 0xA0900000 0x00000002 + mww 0xA0900000 0x00000002 + mww 0xA0900000 0x00000002 + # + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + mdw 0xA0900000 + # + mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30 + mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command + # + # Next we perform a read of RAM. + # mw = move word. + mdw 0x00022000 + # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3 + # + mww 0xA0700020 0x00000003 ;# issue SDRAM NORMAL command + mww 0xA0700100 0x00084280 ;# Enable buffer access + mww 0xA0700120 0x00084280 ;# Enable buffer access + mww 0xA0700140 0x00084280 ;# Enable buffer access + mww 0xA0700160 0x00084280 ;# Enable buffer access + + #Set byte lane state (static mem 1)" + mww 0xA0700220 0x00000082 + #Flash Start + mww 0xA09001F8 0x50000000 + #Flash Mask Reg + mww 0xA09001FC 0xFF000001 + mww 0xA0700028 0x00000001 + + # RAMAddr = 0x00020000 + # RAMSize = 0x00004000 + + # Set the processor mode + reg cpsr 0xd3 +} + +$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1 + +##################### +# Flash configuration +##################### + +#M29DW323DB - not working +#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/digilent_analog_discovery.cfg b/openocd-win/openocd/scripts/board/digilent_analog_discovery.cfg new file mode 100644 index 0000000..1bc239b --- /dev/null +++ b/openocd-win/openocd/scripts/board/digilent_analog_discovery.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Digilent Analog Discovery +# +# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY +# +# Config is based on data from +# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71 +# + +adapter driver ftdi +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 + +ftdi layout_init 0x8008 0x800b + +adapter speed 25000 + +source [find cpld/xilinx-xc6s.cfg] diff --git a/openocd-win/openocd/scripts/board/digilent_atlys.cfg b/openocd-win/openocd/scripts/board/digilent_atlys.cfg new file mode 100644 index 0000000..568253b --- /dev/null +++ b/openocd-win/openocd/scripts/board/digilent_atlys.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://digilentinc.com/atlys/ +# +# The Digilent Atlys normally requires proprietary tools to program and will +# enumerate as: +# ID 1443:0007 Digilent Development board JTAG +# +# However, the ixo-usb-jtag project provides an alternative open firmware for +# the on board programmer. When using this firmware the board will then +# enumerate as: +# ID 16c0:06ad Van Ooijen Technische Informatica +# (With SerialNumber == hw_nexys) +# +# See the interface/usb-jtag.cfg for more information. + +source [find interface/usb-jtag.cfg] +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] diff --git a/openocd-win/openocd/scripts/board/digilent_nexys_video.cfg b/openocd-win/openocd/scripts/board/digilent_nexys_video.cfg new file mode 100644 index 0000000..b60ec91 --- /dev/null +++ b/openocd-win/openocd/scripts/board/digilent_nexys_video.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Digilent Nexys Video with Xilinx Artix-7 FPGA +# https://reference.digilentinc.com/programmable-logic/nexys-video/start + +adapter driver ftdi +adapter speed 30000 + +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6010 + +# channel 0 is dedicated for Digilent's DPTI Interface +# channel 1 is used for JTAG +ftdi channel 1 + +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0088 0x008b +reset_config none + +# Enable sampling on falling edge for high JTAG speeds. +ftdi tdo_sample_edge falling + +transport select jtag + +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] diff --git a/openocd-win/openocd/scripts/board/digilent_zedboard.cfg b/openocd-win/openocd/scripts/board/digilent_zedboard.cfg new file mode 100644 index 0000000..010e8c6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/digilent_zedboard.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip +# +# http://zedboard.com/product/zedboard +# + +source [find interface/ftdi/digilent_jtag_smt2.cfg] + +reset_config srst_only srst_push_pull + +source [find target/zynq_7000.cfg] diff --git a/openocd-win/openocd/scripts/board/diolan_lpc4350-db1.cfg b/openocd-win/openocd/scripts/board/diolan_lpc4350-db1.cfg new file mode 100644 index 0000000..c55621d --- /dev/null +++ b/openocd-win/openocd/scripts/board/diolan_lpc4350-db1.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Diolan LPC-4350-DB1 development board +# + +set CHIPNAME lpc4350 + +source [find target/lpc4350.cfg] + +flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4 diff --git a/openocd-win/openocd/scripts/board/diolan_lpc4357-db1.cfg b/openocd-win/openocd/scripts/board/diolan_lpc4357-db1.cfg new file mode 100644 index 0000000..155328a --- /dev/null +++ b/openocd-win/openocd/scripts/board/diolan_lpc4357-db1.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Diolan LPC-4357-DB1 development board +# + +set CHIPNAME lpc4357 + +source [find target/lpc4357.cfg] + +flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4 diff --git a/openocd-win/openocd/scripts/board/dk-tm4c129.cfg b/openocd-win/openocd/scripts/board/dk-tm4c129.cfg new file mode 100644 index 0000000..27bd432 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dk-tm4c129.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg" + +source [find board/ti_dk-tm4c129.cfg] diff --git a/openocd-win/openocd/scripts/board/dm355evm.cfg b/openocd-win/openocd/scripts/board/dm355evm.cfg new file mode 100644 index 0000000..0dbffa8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dm355evm.cfg @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# DM355 EVM board +# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html +# http://c6000.spectrumdigital.com/evmdm355/ + +source [find target/ti_dm355.cfg] + +reset_config trst_and_srst separate + +# NOTE: disable or replace this call to dm355evm_init if you're +# debugging new UBL code from SRAM. +$_TARGETNAME configure -event reset-init { dm355evm_init } + +# +# This post-reset init is called when the MMU isn't active, all IRQs +# are disabled, etc. It should do most of what a UBL does, except for +# loading code (like U-Boot) into DRAM and running it. +# +proc dm355evm_init {} { + global dm355 + + echo "Initialize DM355 EVM board" + + # CLKIN = 24 MHz ... can't talk quickly to ARM yet + jtag_rclk 1500 + + ######################## + # PLL1 = 432 MHz (/8, x144) + # ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP + # ...SYSCLK2 = 108 MHz (/4) ... Peripherals + # ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC + # ...SYSCLK4 = 108 MHz (/4) ... VPSS + # pll1.{prediv,div1,div2} are fixed + # pll1.postdiv set in MISC (for *this* speed grade) + + set addr [dict get $dm355 pllc1] + set pll_divs [dict create] + dict set pll_divs div3 16 + dict set pll_divs div4 4 + pll_v02_setup $addr 144 $pll_divs + + # ARM is now running at 216 MHz, so JTAG can go faster + jtag_rclk 20000 + + ######################## + # PLL2 = 342 MHz (/8, x114) + # ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock + # pll2.{postdiv,div1} are fixed + + set addr [dict get $dm355 pllc2] + set pll_divs [dict create] + dict set pll_divs div1 1 + dict set pll_divs prediv 8 + pll_v02_setup $addr 114 $pll_divs + + ######################## + # PINMUX + + # All Video Inputs + davinci_pinmux $dm355 0 0x00007f55 + # All Video Outputs + davinci_pinmux $dm355 1 0x00145555 + # EMIFA (NOTE: more could be set up for use as GPIOs) + davinci_pinmux $dm355 2 0x00000c08 + # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs + davinci_pinmux $dm355 3 0x1bff55ff + # MMC/SD0 instead of MS; SPI0 + davinci_pinmux $dm355 4 0x00000000 + + ######################## + # PSC setup (minimal) + + # DDR EMIF/13, AEMIF/14, UART0/19 + psc_enable 13 + psc_enable 14 + psc_enable 19 + psc_go + + ######################## + # DDR2 EMIF + + # VTPIOCR impedance calibration + set addr [dict get $dm355 sysbase] + set addr [expr {$addr + 0x70}] + + # clear CLR, LOCK, PWRDN; wait a clock; set CLR + mmw $addr 0 0x20c0 + mmw $addr 0x2000 0 + + # wait for READY + while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 } + + # set IO_READY; then LOCK and PWRSAVE; then PWRDN + mmw $addr 0x4000 0 + mmw $addr 0x0180 0 + mmw $addr 0x0040 0 + + # NOTE: this DDR2 initialization sequence borrows from + # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec. + + # reset (then re-enable) DDR controller + psc_reset 13 + psc_go + psc_enable 13 + psc_go + + # now set it up for Micron MT47H64M16HR-37E @ 171 MHz + + set addr [dict get $dm355 ddr_emif] + + # DDRPHYCR1 + mww [expr {$addr + 0xe4}] 0x50006404 + + # PBBPR -- burst priority + mww [expr {$addr + 0x20}] 0xfe + + # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM* + mmw [expr {$addr + 0x08}] 0x00800000 0 + mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff + + # SDTIMR0, SDTIMR1 + mww [expr {$addr + 0x10}] 0x2a923249 + mww [expr {$addr + 0x14}] 0x4c17c763 + + # SDCR -- relock SDTIM* + mmw [expr {$addr + 0x08}] 0 0x00008000 + + # SDRCR -- refresh rate (171 MHz * 7.8usec) + mww [expr {$addr + 0x0c}] 1336 + + ######################## + # ASYNC EMIF + + set addr [dict get $dm355 a_emif] + + # slow/pessimistic timings + set nand_timings 0x40400204 + # fast (25% faster page reads) + #set nand_timings 0x0400008c + + # AWCCR + mww [expr {$addr + 0x04}] 0xff + # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte) + mww [expr {$addr + 0x10}] $nand_timings + # CS1 == dm9000 Ethernet + mww [expr {$addr + 0x14}] 0x00a00505 + # NANDFCR -- only CS0 has NAND + mww [expr {$addr + 0x60}] 0x01 + + # default: both chipselects to the NAND socket are used + nand probe 0 + nand probe 1 + + ######################## + # UART0 + + set addr [dict get $dm355 uart0] + + # PWREMU_MGNT -- rx + tx in reset + mww [expr {$addr + 0x30}] 0 + + # DLL, DLH -- 115200 baud + mwb [expr {$addr + 0x20}] 0x0d + mwb [expr {$addr + 0x24}] 0x00 + + # FCR - clear and disable FIFOs + mwb [expr {$addr + 0x08}] 0x07 + mwb [expr {$addr + 0x08}] 0x00 + + # IER - disable IRQs + mwb [expr {$addr + 0x04}] 0x00 + + # LCR - 8-N-1 + mwb [expr {$addr + 0x0c}] 0x03 + + # MCR - no flow control or loopback + mwb [expr {$addr + 0x10}] 0x00 + + # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt + mww [expr {$addr + 0x30}] 0xe001 + + + ######################## + + # turn on icache - set I bit in cp15 register c1 + arm mcr 15 0 0 1 0 0x00051078 +} + +# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one. +# +# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND +# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to +# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that +# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc. +set _FLASHNAME $_CHIPNAME.boot +nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000 +set _FLASHNAME $_CHIPNAME.flash +nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000 + +# FIXME +# - support writing UBL with its header (new layout only with new ROMs) +# - support writing ABL/U-Boot with its header (new layout) diff --git a/openocd-win/openocd/scripts/board/dm365evm.cfg b/openocd-win/openocd/scripts/board/dm365evm.cfg new file mode 100644 index 0000000..15db24c --- /dev/null +++ b/openocd-win/openocd/scripts/board/dm365evm.cfg @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# DM365 EVM board -- Beta +# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html +# http://support.spectrumdigital.com/boards/evmdm365 + +source [find target/ti_dm365.cfg] + +# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG +# connector, so it doesn't affect generation of the reset signal. +# Accordingly, resets require something else. ICEpick could do it; +# but its docs aren't generally available. +# +# At this writing, newer boards aren't available ... so assume no SRST. +# Also ICEpick docs aren't available ... so we must use watchdog reset, +# and hope the CPU isn't wedged or in a WFI loop (either of which can +# block access to CPU and thus watchdog registers). + +reset_config trst_only +$_TARGETNAME configure -event reset-assert "davinci_wdog_reset" + +# SW5.1 routes CS0: NAND vs OneNAND. +# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand) +# for boot-from-flash, those must agree with SW4.3:1 settings. + +if { [info exists CS0MODE] } { + # NAND or OneNAND + set CS0 $CS0MODE +} else { + set CS0 "" + echo "WARNING: CS0 configuration not known" + proc cs0_setup {a_emif} {} + proc flashprobe {} {} +} + +set a_emif [dict get $dm365 a_emif] + +# As shipped: boot from NAND. +if { $CS0 == "NAND" } { + echo "CS0 NAND" + + # NAND socket has two chipselects. Default MT29F16G08FAA chip + # has 1GByte on each one. + # NOTE: "hwecc4" here presumes that you're not updating anything + # that needs infix layout (e.g. UBL, old U-Boot, etc) + nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif + nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif + + proc cs0_setup {a_emif} { + global dm365 + + # 8 bit EMIF + davinci_pinmux $dm365 2 0x00000016 + + # slow/pessimistic timings + set nand_timings 0x40400204 + # fast (25% faster page reads) + #set nand_timings 0x0400008c + + # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes) + mww [expr {$a_emif + 0x10}] $nand_timings + + # NANDFCR -- CS0 has NAND + mww [expr {$a_emif + 0x60}] 0x01 + } + proc flashprobe {} { + nand probe 0 + nand probe 1 + } + +} elseif { $CS0 == "OneNAND" } { + echo "CS0 OneNAND" + + # No support for this OneNAND in OpenOCD (yet) or Linux ... + # REVISIT OneNAND timings not verified to work! + echo "WARNING -- OneNAND not yet tested!" + + proc cs0_setup {a_emif} { + global dm365 + + # 16 bit EMIF + davinci_pinmux $dm365 2 0x00000055 + + # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes) + mww [expr {$a_emif + 0x10}] 0x00000001 + + # ONENANDCTRL -- CS0 has OneNAND, enable sync reads + mww [expr {$a_emif + 0x5c}] 0x0441 + } + proc flashprobe {} { } +} + +# NOTE: disable or replace this call to dm365evm_init if you're +# debugging new UBL/NANDboot code from SRAM. +$_TARGETNAME configure -event reset-init { dm365evm_init } + +# +# This post-reset init is called when the MMU isn't active, all IRQs +# are disabled, etc. It should do most of what a UBL does, except for +# loading code (like U-Boot) into DRAM and running it. +# +proc dm365evm_init {} { + global dm365 + + echo "Initialize DM365 EVM board" + + # CLKIN = 24 MHz ... can't talk quickly to ARM yet + adapter speed 1500 + + # FIXME -- PLL init + + ######################## + # PINMUX setup + + davinci_pinmux $dm365 0 0x00fd0000 + davinci_pinmux $dm365 1 0x00145555 + # mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand + davinci_pinmux $dm365 3 0x375affff + davinci_pinmux $dm365 4 0x55556555 + + ######################## + # PSC setup (minimal) + + # DDR EMIF/13, AEMIF/14, UART0/19 + psc_enable 13 + psc_enable 14 + psc_enable 19 + psc_go + + # FIXME setup DDR2 (needs PLL) + + ######################## + # ASYNC EMIF + + set a_emif [dict get $dm365 a_emif] + + # AWCCR + mww [expr {$a_emif + 0x04}] 0xff + # CS0 == NAND or OneNAND + cs0_setup $a_emif + # CS1 == CPLD + mww [expr {$a_emif + 0x14}] 0x00a00505 + + # FIXME setup UART0 + + flashprobe +} diff --git a/openocd-win/openocd/scripts/board/dm6446evm.cfg b/openocd-win/openocd/scripts/board/dm6446evm.cfg new file mode 100644 index 0000000..1236b86 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dm6446evm.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# DM6446 EVM board +# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html +# http://c6000.spectrumdigital.com/davincievm/ +# EVM is just the board; buy that at Spectrum. +# The "kit" from TI also has: video camera, LCD video monitor, more. + +source [find target/ti_dm6446.cfg] + +# J4 controls what CS2 hooks up to, usually NOR or NAND flash. +# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings. +# S3.3 controls AEMIF bus width. + +if { [info exists J4_OPTION] } { + # NOR, NAND, SRAM, ... + set CS2_MODE $J4_OPTION +} else { + set CS2_MODE "" +} + +# ARM boot: +# S3.1 = 0, S3.2 = 0 ==> ROM/UBL boot via NAND (J4 == NAND) +# S3.1 = 1, S3.2 = 0 ==> AEMIF boot (J4 == NOR or SRAM) +# S3.1 = 0, S3.2 = 1 ==> ROM/UBL boot via HPI +# S3.1 = 1, S3.2 = 1 ==> ROM/UBL boot via UART (J4 == don't care) +# AEMIF bus width: +# S3.3 = 0 ==> 8 bit bus width +# S3.3 = 1 ==> 16 bit bus width +# DSP boot: +# S3.4 = 0 ==> controlled by ARM + +if { $CS2_MODE == "NOR" } { + # 16 Mbytes address space; 16 bit bus width + # (older boards used 32MB parts, with upper 16 MB unusable) + set _FLASHNAME $_CHIPNAME.flash + flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME + proc flashprobe {} { flash probe 0 } +} elseif { $CS2_MODE == "NAND" } { + # 64 Mbyte small page; 8 bit bus width + nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000 + proc flashprobe {} { nand probe 0 } +} elseif { $CS2_MODE == "SRAM" } { + # 4 Mbyte address space; 16 bit bus width + # loaded via JTAG or HPI + proc flashprobe {} {} +} else { + # maybe it's HPI boot? can't tell... + echo "WARNING: CS2/flash configuration not recognized" + proc flashprobe {} {} +} + +# NOTE: disable or replace this call to dm6446evm_init if you're +# debugging new UBL code from SRAM (for NAND boot). +$_TARGETNAME configure -event reset-init { dm6446evm_init } + +# +# This post-reset init is called when the MMU isn't active, all IRQs +# are disabled, etc. It should do most of what a UBL does, except for +# loading code (like U-Boot) into DRAM and running it. +# +proc dm6446evm_init {} { + + echo "Initialize DM6446 EVM board" + + # FIXME initialize everything: + # - PLL1 + # - PLL2 + # - PINMUX + # - PSC + # - DDR + # - AEMIF + # - UART0 + # - icache + + flashprobe +} diff --git a/openocd-win/openocd/scripts/board/dp_busblaster_v3.cfg b/openocd-win/openocd/scripts/board/dp_busblaster_v3.cfg new file mode 100644 index 0000000..5599617 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dp_busblaster_v3.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Dangerous Prototypes - Bus Blaster +# +# http://dangerousprototypes.com/docs/Bus_Blaster +# +# To reprogram the on-board CPLD do: +# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown" +# + +source [find interface/ftdi/dp_busblaster.cfg] +ftdi channel 1 + +jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8 diff --git a/openocd-win/openocd/scripts/board/dp_busblaster_v4.cfg b/openocd-win/openocd/scripts/board/dp_busblaster_v4.cfg new file mode 100644 index 0000000..2c2f0e9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dp_busblaster_v4.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Dangerous Prototypes - Bus Blaster +# +# http://dangerousprototypes.com/docs/Bus_Blaster +# +# The Bus Blaster has a configurable buffer between the FTDI FT2232H +# and the JTAG header which allows it to emulate various debugger +# types. This config works with KT-Link compatible implementation from +# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf +# +# To reprogram the on-board CPLD do: +# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown" +# + +source [find interface/ftdi/dp_busblaster.cfg] +ftdi channel 1 + +jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8 diff --git a/openocd-win/openocd/scripts/board/dptechnics_dpt-board-v1.cfg b/openocd-win/openocd/scripts/board/dptechnics_dpt-board-v1.cfg new file mode 100644 index 0000000..3ab2c68 --- /dev/null +++ b/openocd-win/openocd/scripts/board/dptechnics_dpt-board-v1.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Product page: +# https://www.dptechnics.com/en/products/dpt-board-v1.html +# +# JTAG is a 5 pin array located close to main module in following order: +# 1. JTAG TCK +# 2. JTAG TDO +# 3. JTAG TDI +# 4. JTAG TMS +# 5. GND The GND is located near letter G of word JTAG on board. +# +# Two RST pins are connected to: +# 1. GND +# 2. GPIO11 this pin is located near letter R of word RST. +# +# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example +# with 10K resistor connected to V3.3 pin. +# +# This board is powered from micro USB connector. No real reset pin or button, for +# example RESET_L is available. + +source [find target/atheros_ar9331.cfg] + +$_TARGETNAME configure -event reset-init { + ar9331_25mhz_pll_init + sleep 1 + ar9331_ddr2_init +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0 diff --git a/openocd-win/openocd/scripts/board/ecp5_evaluation.cfg b/openocd-win/openocd/scripts/board/ecp5_evaluation.cfg new file mode 100644 index 0000000..427037b --- /dev/null +++ b/openocd-win/openocd/scripts/board/ecp5_evaluation.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Lattice ECP5 evaluation Kit +# https://www.latticesemi.com/view_document?document_id=52479 +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/lattice_ecp5.cfg] + +#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load 0 shared_folder/ecp5_blinker_impl1.bit" +#ipdbg -start -tap ecp5.tap -hub 0x32 -port 5555 -tool 0 diff --git a/openocd-win/openocd/scripts/board/efikamx.cfg b/openocd-win/openocd/scripts/board/efikamx.cfg new file mode 100644 index 0000000..9083543 --- /dev/null +++ b/openocd-win/openocd/scripts/board/efikamx.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Genesi USA EfikaMX +# http://www.genesi-usa.com/products/efika + +# Fall back to 6MHz if RTCK is not supported +jtag_rclk 6000 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 6000 } + +source [find target/imx51.cfg] + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/efm32.cfg b/openocd-win/openocd/scripts/board/efm32.cfg new file mode 100644 index 0000000..0ffab04 --- /dev/null +++ b/openocd-win/openocd/scripts/board/efm32.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for EFM32 boards with on-board SEGGER J-Link +# +# Tested with Tiny, Giant and Zero Gecko Starter Kit. +# + +source [find interface/jlink.cfg] +transport select swd +adapter speed 1000 + +set CHIPNAME efm32 +source [find target/efm32.cfg] diff --git a/openocd-win/openocd/scripts/board/eir.cfg b/openocd-win/openocd/scripts/board/eir.cfg new file mode 100644 index 0000000..d634249 --- /dev/null +++ b/openocd-win/openocd/scripts/board/eir.cfg @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Elector Internet Radio board +# http://www.ethernut.de/en/hardware/eir/index.html + +source [find target/at91sam7se512.cfg] + +$_TARGETNAME configure -event reset-init { + # WDT_MR, disable watchdog + mww 0xFFFFFD44 0x00008000 + + # RSTC_MR, enable user reset + mww 0xfffffd08 0xa5000001 + + # CKGR_MOR + mww 0xFFFFFC20 0x00000601 + sleep 10 + + # CKGR_PLLR + mww 0xFFFFFC2C 0x00481c0e + sleep 10 + + # PMC_MCKR + mww 0xFFFFFC30 0x00000007 + sleep 10 + + # PMC_IER + mww 0xFFFFFF60 0x00480100 + + # + # Enable SDRAM interface. + # + + # Enable SDRAM control at PIO A. + mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF + mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF + + # Enable address bus (A0, A2-A11, A13-A17) at PIO B + mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF + mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF + + # Enable 16 bit data bus at PIO C + mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF + mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF + + # Enable SDRAM chip select + mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF + + # Set SDRAM characteristics in configuration register. + # Hard coded values for MT48LC32M16A2 with 48MHz CPU. + mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF + sleep 10 + + # Issue 16 bit SDRAM command: NOP + mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + + # Issue 16 bit SDRAM command: Precharge all + mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + + # Issue 8 auto-refresh cycles + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000000 + + # Issue 16 bit SDRAM command: Set mode register + mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF + mww 0x20000014 0xcafedede + + # Set refresh rate count ??? + mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF + + # Issue 16 bit SDRAM command: Normal mode + mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF + mww 0x20000000 0x00000180 + + # + # Enable external reset key. + # + mww 0xfffffd08 0xa5000001 +} diff --git a/openocd-win/openocd/scripts/board/ek-lm3s1968.cfg b/openocd-win/openocd/scripts/board/ek-lm3s1968.cfg new file mode 100644 index 0000000..c794a17 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s1968.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S1968 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s1968 +# + +# NOTE: to use J-Link instead of the on-board interface, +# you may also need to reduce adapter speed to be about 1200. +# source [find interface/jlink.cfg] + +# include the FT2232 interface config for on-board JTAG interface +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using in JTAG mode, as done here. +source [find interface/ftdi/luminary.cfg] + +# include the target config +set WORKAREASIZE 0x2000 +set CHIPNAME lm3s1968 +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s3748.cfg b/openocd-win/openocd/scripts/board/ek-lm3s3748.cfg new file mode 100644 index 0000000..705cb64 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s3748.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris lm3s3748 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s3748 +# + +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using it in JTAG mode, as done here. +source [find interface/ftdi/luminary.cfg] + +# 20k working area +set WORKAREASIZE 0x4000 +set CHIPNAME lm3s3748 +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s6965.cfg b/openocd-win/openocd/scripts/board/ek-lm3s6965.cfg new file mode 100644 index 0000000..ee4e15f --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s6965.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S6965 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s6965 +# + +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using it in JTAG mode, as done here. +source [find interface/ftdi/luminary.cfg] + +# 20k working area +set WORKAREASIZE 0x5000 +set CHIPNAME lm3s6965 +# include the target config +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s811-revb.cfg b/openocd-win/openocd/scripts/board/ek-lm3s811-revb.cfg new file mode 100644 index 0000000..f968eec --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s811-revb.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier) +# +# http://www.ti.com/tool/ek-lm3s811 +# + +# NOTE: newer 811-EK boards (rev C and above) shouldn't use this. +# use board/ek-lm3s811.cfg +source [find interface/ftdi/luminary-lm3s811.cfg] + +# include the target config +set WORKAREASIZE 0x2000 +set CHIPNAME lm3s811 +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s811.cfg b/openocd-win/openocd/scripts/board/ek-lm3s811.cfg new file mode 100644 index 0000000..0cf36c2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s811.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S811 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s811 +# + +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using it in JTAG mode, as done here. +# NOTE: older '811-EK boards (before rev C) shouldn't use this. +source [find interface/ftdi/luminary.cfg] + +# include the target config +set WORKAREASIZE 0x2000 +set CHIPNAME lm3s811 +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s8962.cfg b/openocd-win/openocd/scripts/board/ek-lm3s8962.cfg new file mode 100644 index 0000000..71a1b10 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s8962.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S8962 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s8962 +# + +# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional! +# so is using it in JTAG mode, as done here. +source [find interface/ftdi/luminary.cfg] + +# 64k working area +set WORKAREASIZE 0x10000 +set CHIPNAME lm3s8962 +# include the target config +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s9b9x.cfg b/openocd-win/openocd/scripts/board/ek-lm3s9b9x.cfg new file mode 100644 index 0000000..289a2cc --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s9b9x.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S9B9x Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s9b90 +# http://www.ti.com/tool/ek-lm3s9b92 +# + +# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional! +# so is using in JTAG mode, as done here. +source [find interface/ftdi/luminary-icdi.cfg] + +set WORKAREASIZE 0x4000 +set CHIPNAME lm3s9b9x +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm3s9d92.cfg b/openocd-win/openocd/scripts/board/ek-lm3s9d92.cfg new file mode 100644 index 0000000..08bbbdb --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm3s9d92.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI/Luminary Stellaris LM3S9D92 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm3s9d92 +# + +# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional! +# so is using in JTAG mode, as done here. +source [find interface/ftdi/luminary-icdi.cfg] + +# 64k working area +set WORKAREASIZE 0x10000 +set CHIPNAME lm3s9d92 +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm4f120xl.cfg b/openocd-win/openocd/scripts/board/ek-lm4f120xl.cfg new file mode 100644 index 0000000..db8b201 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm4f120xl.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits +# +# http://www.ti.com/tool/ek-lm4f120xl +# + +# +# NOTE: using the bundled ICDI interface is optional! +# This interface is not ftdi based as previous boards were +# +source [find interface/ti-icdi.cfg] + +transport select hla_jtag + +set WORKAREASIZE 0x8000 +set CHIPNAME lm4f120h5qr +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-lm4f232.cfg b/openocd-win/openocd/scripts/board/ek-lm4f232.cfg new file mode 100644 index 0000000..89b2c3c --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-lm4f232.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Stellaris LM4F232 Evaluation Kits +# +# http://www.ti.com/tool/ek-lm4f232 +# + +# +# NOTE: using the bundled ICDI interface is optional! +# This interface is not ftdi based as previous boards were +# +source [find interface/ti-icdi.cfg] + +transport select hla_jtag + +set WORKAREASIZE 0x8000 +set CHIPNAME lm4f23x +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-tm4c123gxl.cfg b/openocd-win/openocd/scripts/board/ek-tm4c123gxl.cfg new file mode 100644 index 0000000..d569e58 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-tm4c123gxl.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg" + +source [find board/ti_ek-tm4c123gxl.cfg] diff --git a/openocd-win/openocd/scripts/board/ek-tm4c1294xl.cfg b/openocd-win/openocd/scripts/board/ek-tm4c1294xl.cfg new file mode 100644 index 0000000..5c11674 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ek-tm4c1294xl.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg" + +source [find board/ti_ek-tm4c1294xl.cfg] diff --git a/openocd-win/openocd/scripts/board/embedded-artists_lpc2478-32.cfg b/openocd-win/openocd/scripts/board/embedded-artists_lpc2478-32.cfg new file mode 100644 index 0000000..ef61060 --- /dev/null +++ b/openocd-win/openocd/scripts/board/embedded-artists_lpc2478-32.cfg @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Embedded Artists eval board for LPC2478 +# http://www.embeddedartists.com/ + +# Target device: LPC2478 +set CCLK 72000 +source [find target/lpc2478.cfg] + +# Helper +# +proc read_register {register} { + return [read_memory $register 32 1] +} + +proc init_board {} { + # Delays on reset lines + adapter srst delay 500 + jtag_ntrst_delay 1 + + # Adaptive JTAG clocking through RTCK. + # + jtag_rclk 20 + + global _TARGETNAME + global _CHIPNAME + + # A working area will help speeding the flash programming + $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0 + + # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB) + flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe + + # Event handlers + # + $_TARGETNAME configure -event reset-start { + # Back to the slow JTAG clock + jtag_rclk 20 + } + + $_TARGETNAME configure -event reset-init { + arm core_state arm + arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer + arm7_9 fast_memory_access enable + + # Peripheral clocks + mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value) + + # Map the user flash to the vector table area (0x00...0x3F) + mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash + + # Memory accelerator module + mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles + mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled + + # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0) + mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0, + # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0, + # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3 + mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15 + mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31 + mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15 + mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE, + # P4.25=WE, P4.30=CS0, P4.31=CS1 + mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC + + # Start PLL, then use faster JTAG clock + enable_pll + jtag_rclk 3000 + + # 16-bit flash @ CS0 (SST39VF3201-70) + mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on + mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0 + mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0 + mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0 + mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0 + mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0 + mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0 + + # 8-bit NAND @ CS1 + # TODO + + # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75) + mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig + mww 0xFFE08030 0x00000001 ;# EMCDynamicRP + mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS + mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX + mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR + mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL + mww 0xFFE08044 0x00000001 ;# EMCDynamicWR + mww 0xFFE08048 0x00000005 ;# EMCDynamicRC + mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC + mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR + mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD + mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD + # + mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0 + mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0 + sleep 100 + mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP + sleep 10 + mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL + mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh + sleep 100 + mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE + mdw 0xA0011000 1 ;# Set SDRAM mode register + mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL + mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers + } + + $_TARGETNAME configure -event gdb-attach { + # Without this gdb-attach will first time as probe will fail + reset init + } +} + +# Enable the PLL. +# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator. +# Note: The PLL output runs at a frequency N times the desired CPU clock. +# It in unavoidable that the CPU clock drops down to (4 MHz/N) during +# the initialization! +# Here: N=4 +# Note that if the PLL is already active at the time this script is +# called, the effective value of N is the value of CCLKCFG at that time! +# +proc enable_pll {} { + # Disconnect PLL in case it is already connected + if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} { + # Disconnect it, but leave it enabled + # (This MUST be done in two steps) + mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL + mww 0xE01FC08C 0x000000AA ;# PLLFEED + mww 0xE01FC08C 0x00000055 ;# PLLFEED + } + # Disable PLL (as it might already be enabled at this time!) + mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL + mww 0xE01FC08C 0x000000AA ;# PLLFEED + mww 0xE01FC08C 0x00000055 ;# PLLFEED + + # Setup PLL to generate 288 MHz from internal RC oscillator + mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC + mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36 + mww 0xE01FC08C 0x000000AA ;# PLLFEED + mww 0xE01FC08C 0x00000055 ;# PLLFEED + mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL + mww 0xE01FC08C 0x000000AA ;# PLLFEED + mww 0xE01FC08C 0x00000055 ;# PLLFEED + sleep 100 + mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz) + mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL + mww 0xE01FC08C 0x000000AA ;# PLLFEED + mww 0xE01FC08C 0x00000055 ;# PLLFEED +} diff --git a/openocd-win/openocd/scripts/board/emcraft_imx8m-som-bsb.cfg b/openocd-win/openocd/scripts/board/emcraft_imx8m-som-bsb.cfg new file mode 100644 index 0000000..7b9f7b1 --- /dev/null +++ b/openocd-win/openocd/scripts/board/emcraft_imx8m-som-bsb.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for Emcraft IMX8M-SOM-BSB +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# SRST and TRST are wired up +reset_config trst_and_srst + +# delay after SRST goes inactive +adapter srst delay 70 + +# board has an i.MX8MQ with 4 Cortex-A53 cores +set CHIPNAME imx8mq +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8m.cfg] diff --git a/openocd-win/openocd/scripts/board/emcraft_twr-vf6-som-bsb.cfg b/openocd-win/openocd/scripts/board/emcraft_twr-vf6-som-bsb.cfg new file mode 100644 index 0000000..57efa8f --- /dev/null +++ b/openocd-win/openocd/scripts/board/emcraft_twr-vf6-som-bsb.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# EmCraft Systems TWR-VF6-SOM-BSB +# +# http://www.emcraft.com/products/259#twr-kit +# + +source [find board/emcraft_vf6-som.cfg] + +reset_config srst_only srst_nogate diff --git a/openocd-win/openocd/scripts/board/emcraft_vf6-som.cfg b/openocd-win/openocd/scripts/board/emcraft_vf6-som.cfg new file mode 100644 index 0000000..0a6f0f8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/emcraft_vf6-som.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# EmCraft Systems Vybrid VF6 SOM +# +# http://www.emcraft.com/products/259#som +# + +set CHIPNAME vf610 +source [find target/vybrid_vf6xx.cfg] diff --git a/openocd-win/openocd/scripts/board/esp32-bridge.cfg b/openocd-win/openocd/scripts/board/esp32-bridge.cfg new file mode 100644 index 0000000..17146e5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32-bridge.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32 connected via ESP USB Bridge board +# +# For example, OpenOCD can be started for ESP32 debugging on +# +# openocd -f board/esp32-bridge.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_bridge.cfg] +# ESP32 chip id defined in the idf esp_chip_model_t +espusbjtag chip_id 1 +# Source the ESP32 configuration file +source [find target/esp32.cfg] diff --git a/openocd-win/openocd/scripts/board/esp32-ethernet-kit-3.3v.cfg b/openocd-win/openocd/scripts/board/esp32-ethernet-kit-3.3v.cfg new file mode 100644 index 0000000..3bfe84b --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32-ethernet-kit-3.3v.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-ETHERNET-KIT board. +# +# For example, OpenOCD can be started for ESP32 debugging on +# +# openocd -f board/esp32-ethernet-kit-3.3v.cfg +# + +# Source the JTAG interface configuration file +source [find interface/ftdi/esp32_devkitj_v1.cfg] +set ESP32_FLASH_VOLTAGE 3.3 +# Source the ESP32 configuration file +source [find target/esp32.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# +# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/openocd-win/openocd/scripts/board/esp32-wrover-kit-1.8v.cfg b/openocd-win/openocd/scripts/board/esp32-wrover-kit-1.8v.cfg new file mode 100644 index 0000000..9aa3954 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32-wrover-kit-1.8v.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-WROVER-KIT board. +# +# For example, OpenOCD can be started for ESP32 debugging on +# +# openocd -f board/esp32-wrover-kit-1.8v.cfg +# + +# Source the JTAG interface configuration file +source [find interface/ftdi/esp32_devkitj_v1.cfg] +set ESP32_FLASH_VOLTAGE 1.8 +# Source the ESP32 configuration file +source [find target/esp32.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# +# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/openocd-win/openocd/scripts/board/esp32-wrover-kit-3.3v.cfg b/openocd-win/openocd/scripts/board/esp32-wrover-kit-3.3v.cfg new file mode 100644 index 0000000..ce62436 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32-wrover-kit-3.3v.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-WROVER-KIT board. +# +# For example, OpenOCD can be started for ESP32 debugging on +# +# openocd -f board/esp32-wrover-kit-3.3v.cfg +# + +# Source the JTAG interface configuration file +source [find interface/ftdi/esp32_devkitj_v1.cfg] +set ESP32_FLASH_VOLTAGE 3.3 +# Source the ESP32 configuration file +source [find target/esp32.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# +# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/openocd-win/openocd/scripts/board/esp32s2-bridge.cfg b/openocd-win/openocd/scripts/board/esp32s2-bridge.cfg new file mode 100644 index 0000000..b87be8b --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32s2-bridge.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S2 connected via ESP USB Bridge board +# +# For example, OpenOCD can be started for ESP32-S2 debugging on +# +# openocd -f board/esp32s2-bridge.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_bridge.cfg] +# ESP32S2 chip id defined in the idf esp_chip_model_t +espusbjtag chip_id 2 +# Source the ESP32-S2 configuration file +source [find target/esp32s2.cfg] diff --git a/openocd-win/openocd/scripts/board/esp32s2-kaluga-1.cfg b/openocd-win/openocd/scripts/board/esp32s2-kaluga-1.cfg new file mode 100644 index 0000000..783ea21 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32s2-kaluga-1.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S2 Kaluga board. +# +# For example, OpenOCD can be started for ESP32-S2 debugging on +# +# openocd -f board/esp32s2-kaluga-1.cfg +# + +source [find interface/ftdi/esp32s2_kaluga_v1.cfg] +source [find target/esp32s2.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# On ESP32-S2, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/openocd-win/openocd/scripts/board/esp32s3-bridge.cfg b/openocd-win/openocd/scripts/board/esp32s3-bridge.cfg new file mode 100644 index 0000000..a42e257 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32s3-bridge.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S3 connected via ESP USB Bridge board +# +# For example, OpenOCD can be started for ESP32-S3 debugging on +# +# openocd -f board/esp32s3-bridge.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_bridge.cfg] +# ESP32S3 chip id defined in the idf esp_chip_model_t +espusbjtag chip_id 9 +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/openocd-win/openocd/scripts/board/esp32s3-builtin.cfg b/openocd-win/openocd/scripts/board/esp32s3-builtin.cfg new file mode 100644 index 0000000..353099c --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32s3-builtin.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter. +# +# For example, OpenOCD can be started for ESP32-S3 debugging on +# +# openocd -f board/esp32s3-builtin.cfg +# + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] + +adapter speed 40000 diff --git a/openocd-win/openocd/scripts/board/esp32s3-ftdi.cfg b/openocd-win/openocd/scripts/board/esp32s3-ftdi.cfg new file mode 100644 index 0000000..6070664 --- /dev/null +++ b/openocd-win/openocd/scripts/board/esp32s3-ftdi.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog. +# +# For example, OpenOCD can be started for ESP32-S3 debugging on +# +# openocd -f board/esp32s3-ftdi.cfg +# + +# Source the JTAG interface configuration file +source [find interface/ftdi/esp32_devkitj_v1.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# +# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/openocd-win/openocd/scripts/board/ethernut3.cfg b/openocd-win/openocd/scripts/board/ethernut3.cfg new file mode 100644 index 0000000..384db1d --- /dev/null +++ b/openocd-win/openocd/scripts/board/ethernut3.cfg @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Ethernut 3 board configuration file +# +# http://www.ethernut.de/en/hardware/enut3/ + + +# AT91R40008-66AU ARM7TDMI Microcontroller +# 256kB internal RAM +source [find target/at91r40008.cfg] + + +# AT49BV322A-70TU NOR Flash +# 2M x 16 mode at address 0x10000000 +# Common flash interface supported +# +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME + + +# Micrel MIC2775-29YM5 Supervisor +# Reset output will remain active for 280ms (maximum) +# +adapter srst delay 300 +jtag_ntrst_delay 300 + + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable +adapter speed 16000 + + +# Target events +# +$_TARGETNAME configure -event reset-init { board_init } + +# Initialize board hardware +# +proc board_init { } { + board_remap + flash probe 0 +} + +# Memory remap +# +proc board_remap {{VERBOSE 0}} { + # CS0: NOR flash + # 16MB @ 0x10000000 + # 16-bit data bus + # 4 wait states + # + mww 0xffe00000 0x1000212d + + # CS1: Ethernet controller + # 1MB @ 0x20000000 + # 16-bit data bus + # 2 wait states + # Byte select access + # + mww 0xffe00004 0x20003025 + + # CS2: CPLD registers + # 1MB @ 0x21000000 + # 8-bit data bus + # 2 wait states + # + mww 0xffe00008 0x21002026 + + # CS3: Expansion bus + # 1MB @ 0x22000000 + # 8-bit data bus + # 8 wait states + # + mww 0xffe00010 0x22002e3e + + # Remap command + # + mww 0xffe00020 0x00000001 + + if {$VERBOSE != 0} { + echo "0x00000000 RAM" + echo "0x10000000 Flash" + echo "0x20000000 Ethernet" + echo "0x21000000 CPLD" + echo "0x22000000 Expansion" + } +} diff --git a/openocd-win/openocd/scripts/board/evb-lan9255.cfg b/openocd-win/openocd/scripts/board/evb-lan9255.cfg new file mode 100644 index 0000000..3fd6f60 --- /dev/null +++ b/openocd-win/openocd/scripts/board/evb-lan9255.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Microchip LAN9255 evaluation board +# https://www.microchip.com/en-us/development-tool/EV25Y25A +# + +set CHIPNAME same53 + +source [find target/atsame5x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/frdm-kl25z.cfg b/openocd-win/openocd/scripts/board/frdm-kl25z.cfg new file mode 100644 index 0000000..68dc48d --- /dev/null +++ b/openocd-win/openocd/scripts/board/frdm-kl25z.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip. +# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z +# + +source [find interface/cmsis-dap.cfg] + +# increase working area to 16KB +set WORKAREASIZE 0x4000 + +# chip name +set CHIPNAME MKL25Z128VLK4 + +reset_config srst_only + +source [find target/kl25.cfg] diff --git a/openocd-win/openocd/scripts/board/frdm-kl46z.cfg b/openocd-win/openocd/scripts/board/frdm-kl46z.cfg new file mode 100644 index 0000000..3fb7205 --- /dev/null +++ b/openocd-win/openocd/scripts/board/frdm-kl46z.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip. +# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z +# + +source [find interface/cmsis-dap.cfg] + +# increase working area to 16KB +set WORKAREASIZE 0x4000 + +# chip name +set CHIPNAME MKL46Z256VLL4 + +reset_config srst_only + +source [find target/kl46.cfg] diff --git a/openocd-win/openocd/scripts/board/fsl_imx6q_sabresd.cfg b/openocd-win/openocd/scripts/board/fsl_imx6q_sabresd.cfg new file mode 100644 index 0000000..faeeafb --- /dev/null +++ b/openocd-win/openocd/scripts/board/fsl_imx6q_sabresd.cfg @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Board configuration file for the Freescale IMX6Q Sabre SD EVM +# +# This board does not have an embedded JTAG adapter, you must source +# a suitable adapter configuration before sourcing this file. + +# Sabre SD has a standard ARM-20 JTAG connector with +# nTRST and nSRST available. +reset_config trst_and_srst + +# the only possible transport is JTAG +transport select jtag + +# iMX6Q POR gates JTAG and the chip is completely incommunicado +# over JTAG for at least 10ms after nSRST is deasserted +adapter srst delay 11 + +# Source generic iMX6Q target configuration +set CHIPNAME imx6q +source [find target/imx6.cfg] + +# function to apply initial configuration after a reset. It +# provides a basic pad configuration and also DDR memory and clocks +# sufficient to load and execute a boot loader (e.g. barebox) from +# DDR memory. This list is extracted from the barebox flash image +# header. +proc apply_dcd { } { + mww 0x020e05a8 0x00000030 + mww 0x020e05b0 0x00000030 + mww 0x020e0524 0x00000030 + mww 0x020e051c 0x00000030 + mww 0x020e0518 0x00000030 + mww 0x020e050c 0x00000030 + mww 0x020e05b8 0x00000030 + mww 0x020e05c0 0x00000030 + mww 0x020e05ac 0x00020030 + mww 0x020e05b4 0x00020030 + mww 0x020e0528 0x00020030 + mww 0x020e0520 0x00020030 + mww 0x020e0514 0x00020030 + mww 0x020e0510 0x00020030 + mww 0x020e05bc 0x00020030 + mww 0x020e05c4 0x00020030 + mww 0x020e056c 0x00020030 + mww 0x020e0578 0x00020030 + mww 0x020e0588 0x00020030 + mww 0x020e0594 0x00020030 + mww 0x020e057c 0x00020030 + mww 0x020e0590 0x00003000 + mww 0x020e0598 0x00003000 + mww 0x020e058c 0x00000000 + mww 0x020e059c 0x00003030 + mww 0x020e05a0 0x00003030 + mww 0x020e0784 0x00000030 + mww 0x020e0788 0x00000030 + mww 0x020e0794 0x00000030 + mww 0x020e079c 0x00000030 + mww 0x020e07a0 0x00000030 + mww 0x020e07a4 0x00000030 + mww 0x020e07a8 0x00000030 + mww 0x020e0748 0x00000030 + mww 0x020e074c 0x00000030 + mww 0x020e0750 0x00020000 + mww 0x020e0758 0x00000000 + mww 0x020e0774 0x00020000 + mww 0x020e078c 0x00000030 + mww 0x020e0798 0x000c0000 + mww 0x021b081c 0x33333333 + mww 0x021b0820 0x33333333 + mww 0x021b0824 0x33333333 + mww 0x021b0828 0x33333333 + mww 0x021b481c 0x33333333 + mww 0x021b4820 0x33333333 + mww 0x021b4824 0x33333333 + mww 0x021b4828 0x33333333 + mww 0x021b0018 0x00081740 + mww 0x021b001c 0x00008000 + mww 0x021b000c 0x555a7975 + mww 0x021b0010 0xff538e64 + mww 0x021b0014 0x01ff00db + mww 0x021b002c 0x000026d2 + mww 0x021b0030 0x005b0e21 + mww 0x021b0008 0x09444040 + mww 0x021b0004 0x00025576 + mww 0x021b0040 0x00000027 + mww 0x021b0000 0x831a0000 + mww 0x021b001c 0x04088032 + mww 0x021b001c 0x0408803a + mww 0x021b001c 0x00008033 + mww 0x021b001c 0x0000803b + mww 0x021b001c 0x00428031 + mww 0x021b001c 0x00428039 + mww 0x021b001c 0x09408030 + mww 0x021b001c 0x09408038 + mww 0x021b001c 0x04008040 + mww 0x021b001c 0x04008048 + mww 0x021b0800 0xa1380003 + mww 0x021b4800 0xa1380003 + mww 0x021b0020 0x00005800 + mww 0x021b0818 0x00022227 + mww 0x021b4818 0x00022227 + mww 0x021b083c 0x434b0350 + mww 0x021b0840 0x034c0359 + mww 0x021b483c 0x434b0350 + mww 0x021b4840 0x03650348 + mww 0x021b0848 0x4436383b + mww 0x021b4848 0x39393341 + mww 0x021b0850 0x35373933 + mww 0x021b4850 0x48254A36 + mww 0x021b080c 0x001f001f + mww 0x021b0810 0x001f001f + mww 0x021b480c 0x00440044 + mww 0x021b4810 0x00440044 + mww 0x021b08b8 0x00000800 + mww 0x021b48b8 0x00000800 + mww 0x021b001c 0x00000000 + mww 0x021b0404 0x00011006 + mww 0x020c4068 0x00c03f3f + mww 0x020c406c 0x0030fc03 + mww 0x020c4070 0x0fffc000 + mww 0x020c4074 0x3ff00000 + mww 0x020c4078 0x00fff300 + mww 0x020c407c 0x0f0000c3 + mww 0x020c4080 0x000003ff + mww 0x020e0010 0xf00000cf + mww 0x020e0018 0x007f007f + mww 0x020e001c 0x007f007f +} + +# disable watchdog +proc disable_wdog { } { + mwh 0x020bc000 0x30 +} + +# This function applies the initial configuration after a "reset init" +# command +proc imx6q_sabresd_init { } { + disable_wdog + apply_dcd +} + +# prevent cortex-a code from asserting SRST again +$_TARGETNAME.0 configure -event reset-assert { } +# hook the init function into the reset-init event +$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init } +# set a slow default JTAG clock, can be overridden later +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/board/gatemate_eval.cfg b/openocd-win/openocd/scripts/board/gatemate_eval.cfg new file mode 100644 index 0000000..cc078a0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/gatemate_eval.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# GateMateTM FPGA Evaluation Board +# https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/ +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0014 0x011b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/gatemate.cfg] diff --git a/openocd-win/openocd/scripts/board/glyn_tonga2.cfg b/openocd-win/openocd/scripts/board/glyn_tonga2.cfg new file mode 100644 index 0000000..d847bec --- /dev/null +++ b/openocd-win/openocd/scripts/board/glyn_tonga2.cfg @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9) +# +# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm +# +# Hardware on the S0-DIMM module: +# - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz) +# - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2) +# - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V) +# - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface) +# + +source [find target/tmpa900.cfg] + +######################## +# Target configuration # +######################## + +# Initial JTAG speed should not exceed 1/6 of the initial CPU clock +# frequency (24MHz). Be conservative and use 1/8 of the frequency. +# (24MHz / 8 = 3MHz) +adapter speed 3000 + +$_TARGETNAME configure -event reset-start { + # Upon reset, set the JTAG frequency to 3MHz again, see above. + echo "Setting JTAG speed to 3MHz until clocks are initialized." + adapter speed 3000 + + # Halt the CPU. + halt + + # Disable faster memory access for now. + arm7_9 fast_memory_access disable +} + +$_TARGETNAME configure -event reset-init { + # Setup clocks, and initialize SRAM and DDR SDRAM. + tonga2_init + + # At this point the CPU is running at 192MHz, increase JTAG speed. + # Tests showed that 15MHz works OK, higher speeds can cause problems, + # though. Not sure if this is a CPU issue or JTAG adapter issue. + echo "Increasing JTAG speed to 15MHz." + adapter speed 15000 + + # Enable faster memory access. + arm7_9 fast_memory_access enable +} + +proc tonga2_init { } { + ###################### + # PLL initialization # + ###################### + + # Clock overview (see datasheet chapter 3.5.2, page 57): + # - fs: Low-frequency oscillator + # - fOSCH: High-frequency oscillator (24MHz on this board) + # - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8) + # - fFCLK = fPLL / gear (where gear can be 1/2/4/8) + # - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2. + # + # We select multiplier = 8 and gear = 1, so + # fFCLK = fOSCH * 8 / 1 = 192MHz. + + # SYSCR3 (System Control Register 3): Disable and configure PLL. + # - PLL operation control: off + # - PLL constant value setting 1: always 0, as per datasheet + # - PLL constant value setting 2: x8 (multiplier = 8) + mww 0xf005000c 0x00000007 + + # SYSCR4 (System Control Register 4): Configure PLL. + # - PLL constant value setting 3: 140MHz or more + # - PLL constant value setting 4: always 1, as per datasheet + # - PLL constant value setting 5: 140MHz or more + mww 0xf0050010 0x00000065 + + # SYSCR3 (System Control Register 3): Enable PLL. + # - PLL operation control: on + # - All other bits remain set as above. + mww 0xf005000c 0x00000087 + + # Wait for PLL to stabilize. + sleep 10 + + # SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL. + # - Selection of the PLL output clock: fPLL + mww 0xf0050008 0x00000002 + + # SYSCR1 (System Control Register 1): + # - Clock gear programming: fc/1 (i.e., gear = 1, don't divide). + mww 0xf0050004 0x00000000 + + # CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet + # says the bits are reserved, but also recommends "Write as one". + mww 0xf0050054 0x00000048 + + + ############################################################## + # Dynamic Memory Controller (DMC) / DDR SDRAM initialization # + ############################################################## + + # PMC (Power Management Controller): + # PMCDRV (External Port "Driverbility" control register): + # Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power): + mww 0xf0020260 0x00000003 ;# Select 1.8V +/- 0.1V + + # Setup DDR SDRAM timing parameters for our specific chip. + mww 0xf4310014 0x00000004 ;# cas_latency = 2 + mww 0xf4310018 0x00000001 ;# t_dqss = 1 + mww 0xf431001c 0x00000002 ;# t_mrd = 2 + mww 0xf4310020 0x0000000a ;# t_ras = 10 + mww 0xf4310024 0x0000000a ;# t_rc = 10 + mww 0xf4310028 0x00000013 ;# t_rcd = 3, schedule_rcd = 2 + mww 0xf431002c 0x0000010a ;# t_rfc = 10, schedule_rfc = 8 + mww 0xf4310030 0x00000013 ;# t_rp = 3, schedule_rp = 2 + mww 0xf4310034 0x00000002 ;# t_rrd = 2 + mww 0xf4310038 0x00000002 ;# t_wr = 2 + mww 0xf431003c 0x00000001 ;# t_wtr = 1 + mww 0xf4310040 0x0000000a ;# t_xp = 10 + mww 0xf4310044 0x0000000c ;# t_xsr = 12 + mww 0xf4310048 0x00000014 ;# t_esr = 20 + + # dmc_memory_cfg_5 (DMC Memory Configuration register): + # Set memory configuration: + # column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0, + # auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4 + mww 0xf431000c 0x00010012 + + # dmc_user_config_5 (DMC user_config register): + # Data bus width of DDR SDRAM: 16 bit + mww 0xf4310304 0x00000058 + + # dmc_refresh_prd_5 (DMC Refresh Period register): + # Auto refresh: every 2656 (0xa60) DMCSCLK periods. + mww 0xf4310010 0x00000a60 + + # dmc_chip_0_cfg_5 (DMC chip_0_cfg registers): + # - SDRAM address structure: bank, row, column + # - address_match = 01000000 (start address [31:24]) + # - address_mask = 11111100 (start address [31:24] mask value) + mww 0xf4310200 0x000140fc + + # Initialize the DDR SDRAM chip. + # dmc_direct_cmd_5 (DMC Direct Command register). + # See datasheet chapter 3.10.5.1, page 268. + mww 0xf4310008 0x000c0000 ;# RAM init: NOP + mww 0xf4310008 0x00000000 ;# RAM init: Precharge all + mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh + mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh + mww 0xf4310008 0x00080032 ;# RAM init: addr_13_to_0 = 0x32 + mww 0xf4310008 0x000c0000 ;# RAM init: NOP + mww 0xf4310008 0x000a0000 ;# RAM init: bank_addr = bank 2 + + # dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers): + # Set min./max. QoS values. + # - 0x5: Enable QoS, max. QoS = 1 + # - 0xb: Enable QoS, min. QoS = 2 + mww 0xf4310100 0x00000005 ;# AHB0: CPU Data + mww 0xf4310104 0x00000005 ;# AHB1: CPU Inst + mww 0xf4310108 0x0000000b ;# AHB2: LCDC + mww 0xf431010c 0x00000005 ;# AHB3: LCDDA, USB + mww 0xf4310110 0x00000005 ;# AHB4: DMA1 + mww 0xf4310114 0x00000005 ;# AHB5: DMA2 + + # dmc_memc_cmd_5 (DMC Memory Controller Command register): + # Change DMC state to ready. + mww 0xf4310004 0x00000000 ;# memc_cmd = "Go" + + # EBI: SMC Timeout register + mww 0xf00a0050 0x00000001 ;# smc_timeout = 1 + + + ######################################################## + # Static Memory Controller (SMC) / SRAM initialization # + ######################################################## + + # smc_set_cycles_5 (SMC Set Cycles register): + # tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2 + mww 0xf4311014 0x0004afaa + + # smc_set_opmode_5 (SMC Set Opmode register): + # Memory data bus width = 16 bits, async read mode, read burst + # length = 1 beat, async write mode, write burst length = 1 beat, + # byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary + # split setting = burst can cross any address boundary + mww 0xf4311018 0x00000001 + + # smc_direct_cmd_5 (SMC Direct Command register): + # cmd_type = UpdateRegs, chip_select = CS1 + mww 0xf4311010 0x00c00000 + + echo "Clocks, SRAM, and DDR SDRAM are now initialized." +} + +####################### +# Flash configuration # +####################### + +# TODO: Implement NAND support. diff --git a/openocd-win/openocd/scripts/board/gowin_runber.cfg b/openocd-win/openocd/scripts/board/gowin_runber.cfg new file mode 100644 index 0000000..9496c6f --- /dev/null +++ b/openocd-win/openocd/scripts/board/gowin_runber.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Gowin RUNBER FPGA Development Board +# https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/gowin_gw1n.cfg] + + +#openocd -f board/gowin_runber.cfg -c "init" -c "pld load 0 impl/pnr/gw1n_blinker.fs" +#ipdbg -start -tap gw1n.tap -hub 0x42 -port 5555 -tool 0 diff --git a/openocd-win/openocd/scripts/board/gti/espressobin.cfg b/openocd-win/openocd/scripts/board/gti/espressobin.cfg new file mode 100644 index 0000000..d1492df --- /dev/null +++ b/openocd-win/openocd/scripts/board/gti/espressobin.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# config for ESPRESSObin from +# Globalscale Technologies Inc. + +# srst is isolated through missing resistor +reset_config trst_only + +source [find target/marvell/88f3720.cfg] diff --git a/openocd-win/openocd/scripts/board/gumstix-aerocore.cfg b/openocd-win/openocd/scripts/board/gumstix-aerocore.cfg new file mode 100644 index 0000000..ddadc88 --- /dev/null +++ b/openocd-win/openocd/scripts/board/gumstix-aerocore.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on +# the first interface of a Quad FTDI chip. nTRST is bit 4. +adapter driver ftdi +ftdi vid_pid 0x0403 0x6011 + +ftdi layout_init 0x0000 0x001b +ftdi layout_signal nTRST -data 0x0010 + +source [find target/stm32f4x.cfg] +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/hammer.cfg b/openocd-win/openocd/scripts/board/hammer.cfg new file mode 100644 index 0000000..79d58ae --- /dev/null +++ b/openocd-win/openocd/scripts/board/hammer.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target Configuration for the TinCanTools S3C2410 Based Hammer Module +# http://www.tincantools.com + +source [find target/samsung_s3c2410.cfg] + +$_TARGETNAME configure -event reset-init { + # Reset Script for the TinCanTools S3C2410 Based Hammer Module + # http://www.tincantools.com + # + # Setup primary clocks and initialize the SDRAM + mww 0x53000000 0x00000000 + mww 0x4a000008 0xffffffff + mww 0x4a00000c 0x000007ff + mww 0x4c000000 0x00ffffff + mww 0x4c000014 0x00000003 + mww 0x4c000004 0x000a1031 + mww 0x48000000 0x11111122 + mww 0x48000004 0x00000700 + mww 0x48000008 0x00000700 + mww 0x4800000c 0x00000700 + mww 0x48000010 0x00000700 + mww 0x48000014 0x00000700 + mww 0x48000018 0x00000700 + mww 0x4800001c 0x00018005 + mww 0x48000020 0x00018005 + mww 0x48000024 0x009c0459 + mww 0x48000028 0x000000b2 + mww 0x4800002c 0x00000030 + mww 0x48000030 0x00000030 + flash probe 0 +} + + +#flash configuration +#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> [driver_options ...] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/hilscher_nxdb500sys.cfg b/openocd-win/openocd/scripts/board/hilscher_nxdb500sys.cfg new file mode 100644 index 0000000..68e1cda --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxdb500sys.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for paired K4S561632C (64MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C13261 + mww 0x00100140 0x030D0121 + + puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)" + mww 0x00100100 0x0201000E + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#> +flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hilscher_nxeb500hmi.cfg b/openocd-win/openocd/scripts/board/hilscher_nxeb500hmi.cfg new file mode 100644 index 0000000..a814365 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxeb500hmi.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads disable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC8M32 (32MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0111 + + puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)" + mww 0x00100100 0x0101000E + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#> +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hilscher_nxhx10.cfg b/openocd-win/openocd/scripts/board/hilscher_nxhx10.cfg new file mode 100644 index 0000000..e116a6c --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxhx10.cfg @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx10.cfg] + +# Usually it is not needed to set srst_pulls_trst +# but sometimes it does not work without it. If you encounter +# problems try to line below +# reset_config trst_and_srst srst_pulls_trst +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1 + +# Par. Flash can only be accessed if DIP switch on the board is set in proper +# position and init_sdrambus was called. Don't call these functions if the DIP +# switch is in invalid position, as some outputs may collide. This is why this +# function is not called automatically +proc flash_init { } { + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x101C0100 0x01010008 + + flash probe 0 +} + +proc mread32 {addr} { + return [read_memory $addr 32 1] +} + +proc init_clocks { } { + puts "Enabling all clocks " + set accesskey [mread32 0x101c0070] + mww 0x101c0070 $accesskey + + mww 0x101c0028 0x00007511 +} + +proc init_sdrambus { } { + puts "Initializing external SDRAM Bus 16 Bit " + set accesskey [mread32 0x101c0070] + mww 0x101c0070 $accesskey + mww 0x101c0C40 0x00000050 + + puts "Configuring SDRAM controller for K4S561632E (32MB) " + mww 0x101C0140 0 + sleep 100 + #mww 0x101C0144 0x00a13262 + mww 0x101C0144 0x00a13251 + mww 0x101C0148 0x00000033 + mww 0x101C0140 0x030d0121 +} + +$_TARGETNAME configure -event reset-init { + halt + wait_halt 1000 + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + init_clocks +# init_sdrambus + + puts "" + puts "-------------------------------------------------" + puts "Call 'init_clocks' to enable all clocks" + puts "Call 'init_sdrambus' to enable external SDRAM bus" + puts "-------------------------------------------------" +} + +##################### +# Flash configuration +##################### + +#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#> +#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hilscher_nxhx50.cfg b/openocd-win/openocd/scripts/board/hilscher_nxhx50.cfg new file mode 100644 index 0000000..8aef6ca --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxhx50.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx50.cfg] + +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x1C000140 0 + mww 0x1C000144 0x00A12151 + mww 0x1C000140 0x030D0001 + + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x1C000100 0x01010008 + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#> +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hilscher_nxhx500.cfg b/openocd-win/openocd/scripts/board/hilscher_nxhx500.cfg new file mode 100644 index 0000000..9ddf657 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxhx500.cfg @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sleep 100 + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0001 + + puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)" + mww 0x00100100 0x01010008 + + flash probe 0 +} + +##################### +# Flash configuration +##################### + +#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#> +flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hilscher_nxsb100.cfg b/openocd-win/openocd/scripts/board/hilscher_nxsb100.cfg new file mode 100644 index 0000000..b59ea17 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hilscher_nxsb100.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +source [find target/hilscher_netx500.cfg] + +reset_config trst_and_srst +adapter srst delay 500 +jtag_ntrst_delay 500 + +$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + halt + + arm7_9 fast_memory_access enable + arm7_9 dcc_downloads enable + + sdram_fix + + puts "Configuring SDRAM controller for MT48LC2M32 (8MB) " + mww 0x00100140 0 + mww 0x00100144 0x03C23251 + mww 0x00100140 0x030D0001 + +} + +init +reset init diff --git a/openocd-win/openocd/scripts/board/hitex_lpc1768stick.cfg b/openocd-win/openocd/scripts/board/hitex_lpc1768stick.cfg new file mode 100644 index 0000000..52cf370 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hitex_lpc1768stick.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hitex LPC1768 Stick +# +# http://www.hitex.com/?id=1602 +# + +reset_config trst_and_srst + +source [find interface/ftdi/hitex_lpc1768stick.cfg] + +source [find target/lpc17xx.cfg] + + +# startup @ 500kHz +adapter speed 500 diff --git a/openocd-win/openocd/scripts/board/hitex_lpc2929.cfg b/openocd-win/openocd/scripts/board/hitex_lpc2929.cfg new file mode 100644 index 0000000..35007c0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hitex_lpc2929.cfg @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hitex eval board for LPC2929/LPC2939 +# http://www.hitex.com/ + +# Delays on reset lines +adapter srst delay 50 +jtag_ntrst_delay 1 + +# Maximum of 1/8 of clock frequency (XTAL = 16 MHz). +# Adaptive clocking through RTCK is not supported. +adapter speed 2000 + +# Target device: LPC29xx with ETB +# The following variables are used by the LPC2900 script: +# HAS_ETB Must be set to 1. The CPU on this board has ETB. +# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz) +set HAS_ETB 1 +set FLASH_CLOCK 112000 +source [find target/lpc2900.cfg] + +# A working area will help speeding the flash programming +#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0 +$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0 + +# Event handlers +$_TARGETNAME configure -event reset-start { + # Back to the slow JTAG clock + adapter speed 2000 +} + +# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB) +set _FLASHNAME $_CHIPNAME.extflash +flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe + + +$_TARGETNAME configure -event reset-init { + # Flash + mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached + + # Use PLL + mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz + mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal + mww 0xFFFF8028 0x00000005 ;# PLL: (power down) + mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up) + # --> f=112 MHz, fcco=224 MHz + sleep 100 + mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL + + # Increase JTAG speed + adapter speed 6000 + + # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7) + mww 0xE0001138 0x0000001F ;# P1.14 = D0 + mww 0xE000113C 0x0000001F ;# P1.15 = D1 + mww 0xE0001140 0x0000001F ;# P1.16 = D2 + mww 0xE0001144 0x0000001F ;# P1.17 = D3 + mww 0xE0001148 0x0000001F ;# P1.18 = D4 + mww 0xE000114C 0x0000001F ;# P1.19 = D5 + mww 0xE0001150 0x0000001F ;# P1.20 = D6 + mww 0xE0001154 0x0000001F ;# P1.21 = D7 + mww 0xE0001200 0x0000001F ;# P2.0 = D8 + mww 0xE0001204 0x0000001F ;# P2.1 = D9 + mww 0xE0001208 0x0000001F ;# P2.2 = D10 + mww 0xE000120C 0x0000001F ;# P2.3 = D11 + mww 0xE0001210 0x0000001F ;# P2.4 = D12 + mww 0xE0001214 0x0000001F ;# P2.5 = D13 + mww 0xE0001218 0x0000001F ;# P2.6 = D14 + mww 0xE000121C 0x0000001F ;# P2.7 = D15 + mww 0xE0001104 0x00000007 ;# P1.1 = A1 + mww 0xE0001108 0x00000007 ;# P1.2 = A2 + mww 0xE000110C 0x00000007 ;# P1.3 = A3 + mww 0xE0001110 0x00000007 ;# P1.4 = A4 + mww 0xE0001114 0x00000007 ;# P1.5 = A5 + mww 0xE0001118 0x00000007 ;# P1.6 = A6 + mww 0xE000111C 0x00000007 ;# P1.7 = A7 + mww 0xE0001028 0x00000007 ;# P0.10 = A8 + mww 0xE000102C 0x00000007 ;# P0.11 = A9 + mww 0xE0001030 0x00000007 ;# P0.12 = A10 + mww 0xE0001034 0x00000007 ;# P0.13 = A11 + mww 0xE0001038 0x00000007 ;# P0.14 = A12 + mww 0xE000103C 0x00000007 ;# P0.15 = A13 + mww 0xE0001048 0x00000007 ;# P0.18 = A14 + mww 0xE000104C 0x00000007 ;# P0.19 = A15 + mww 0xE0001050 0x00000007 ;# P0.20 = A16 + mww 0xE0001054 0x00000007 ;# P0.21 = A17 + mww 0xE0001058 0x00000007 ;# P0.22 = A18 + mww 0xE000105C 0x00000007 ;# P0.23 = A19 + mww 0xE0001238 0x00000007 ;# P2.14 = BLS0 + mww 0xE000123C 0x00000007 ;# P2.15 = BLS1 + mww 0xE0001300 0x00000007 ;# P3.0 = CS6 + mww 0xE0001304 0x00000007 ;# P3.1 = CS7 + mww 0xE0001130 0x00000007 ;# P1.12 = OE_N + mww 0xE0001134 0x00000007 ;# P1.13 = WE_N + mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1 + mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0 + mww 0x600000AC 0x00000005 ;# Bank6 WST1=5 + mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1 + mww 0x600000B0 0x00000006 ;# Bank6 WST2=6 + mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2 + mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1 + mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0 + mww 0x600000C8 0x0000000A ;# Bank7 WST1=10 + mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1 + mww 0x600000CC 0x0000000C ;# Bank7 WST2=8 + mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2 +} diff --git a/openocd-win/openocd/scripts/board/hitex_stm32-performancestick.cfg b/openocd-win/openocd/scripts/board/hitex_stm32-performancestick.cfg new file mode 100644 index 0000000..bab5964 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hitex_stm32-performancestick.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hitex stm32 performance stick + +reset_config trst_and_srst + +source [find interface/ftdi/stm32-stick.cfg] + +set CHIPNAME stm32_hitex +source [find target/stm32f1x.cfg] + +# configure str750 connected to jtag chain +# FIXME -- source [find target/str750.cfg] after cleaning that up +jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041 + +# for some reason this board like to startup @ 500kHz +adapter speed 500 diff --git a/openocd-win/openocd/scripts/board/hitex_str9-comstick.cfg b/openocd-win/openocd/scripts/board/hitex_str9-comstick.cfg new file mode 100644 index 0000000..a508046 --- /dev/null +++ b/openocd-win/openocd/scripts/board/hitex_str9-comstick.cfg @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hitex STR9-comStick +# http://www.hitex.com/index.php?id=383 +# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2. + +source [find interface/ftdi/hitex_str9-comstick.cfg] + +# set jtag speed +adapter speed 3000 + +adapter srst delay 100 +jtag_ntrst_delay 100 +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +# +# FIXME use the standard str912 target config; that script might need +# updating to "-ignore-version" for the boundary scan TAP +# +# source [find target/str912.cfg] +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists FLASHTAPID] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0x04570041 +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # Found on STR9-comStick, revision STR912CS-A1 + set _BSTAPID1 0x1457f041 + # Found on STR9-comStick, revision STR912CS-A2 + set _BSTAPID2 0x2457f041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-init { + # We can increase speed now that we know the target is halted. + #jtag_rclk 3000 + + # -- Enable 96K RAM + # PFQBC enabled / DTCM & AHB wait-states disabled + mww 0x5C002034 0x0191 + + str9x flash_config 0 4 2 0 0x80000 + flash protect 0 0 7 off +} + +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 + +#flash bank <driver> <base> <size> <chip_width> <bus_width> +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0 +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0 diff --git a/openocd-win/openocd/scripts/board/iar_lpc1768.cfg b/openocd-win/openocd/scripts/board/iar_lpc1768.cfg new file mode 100644 index 0000000..d8d669e --- /dev/null +++ b/openocd-win/openocd/scripts/board/iar_lpc1768.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Board from IAR KickStart Kit for LPC1768 +# See www.iar.com and also +# http://www.olimex.com/dev/lpc-1766stk.html +# + +source [find target/lpc17xx.cfg] + +# The chip has just been reset. +# +$_TARGETNAME configure -event reset-init { + # FIXME update the core clock to run at 100 MHz; + # and update JTAG clocking similarly; then + # make CCLK match, + + flash probe 0 +} diff --git a/openocd-win/openocd/scripts/board/iar_str912_sk.cfg b/openocd-win/openocd/scripts/board/iar_str912_sk.cfg new file mode 100644 index 0000000..d94c0ce --- /dev/null +++ b/openocd-win/openocd/scripts/board/iar_str912_sk.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The IAR str912-sk evaluation kick start board has an str912 + +source [find target/str912.cfg] diff --git a/openocd-win/openocd/scripts/board/icnova_imx53_sodimm.cfg b/openocd-win/openocd/scripts/board/icnova_imx53_sodimm.cfg new file mode 100644 index 0000000..c4e8bde --- /dev/null +++ b/openocd-win/openocd/scripts/board/icnova_imx53_sodimm.cfg @@ -0,0 +1,450 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################################# +# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;# +# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;# +# Kiwigrid GmbH ;# +# Generated for In-Circuit i.MX53 SO-Dimm ;# +################################################################################################# + +# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip +source [find target/imx53.cfg] +# Helper for common memory read/modify/write procedures +source [find mem_helper.tcl] + +echo "i.MX53 SO-Dimm board lodaded." + +# Set reset type +#reset_config srst_only + +adapter speed 3000 + +# Slow speed to be sure it will work +jtag_rclk 1000 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } + +$_TARGETNAME configure -event "reset-assert" { + echo "Resetting ...." + #cortex_a dbginit +} + +$_TARGETNAME configure -event reset-init { sodimm_init } + +global AIPS1_BASE_ADDR +set AIPS1_BASE_ADDR 0x53F00000 +global AIPS2_BASE_ADDR +set AIPS2_BASE_ADDR 0x63F00000 + +proc sodimm_init { } { + echo "Reset-init..." + ; # halt the CPU + halt + + echo "HW version [format %x [mrw 0x48]]" + + dap apsel 1 + DCD + + ; # ARM errata ID #468414 + set tR [arm mrc 15 0 1 0 1] + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit + + init_l2cc + init_aips + init_clock + + dap apsel 0 + + ; # Force ARM state + ; #reg cpsr 0x000001D3 + arm core_state arm + + jtag_rclk 3000 +# adapter speed 3000 +} + + +# L2CC Cache setup/invalidation/disable +proc init_l2cc { } { + ; #/* explicitly disable L2 cache */ + ; #mrc 15, 0, r0, c1, c0, 1 + set tR [arm mrc 15 0 1 0 1] + ; #bic r0, r0, #0x2 + ; #mcr 15, 0, r0, c1, c0, 1 + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] + + ; #/* reconfigure L2 cache aux control reg */ + ; #mov r0, #0xC0 /* tag RAM */ + ; #add r0, r0, #0x4 /* data RAM */ + ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */ + ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */ + ; #orr r0, r0, #(1 << 22) /* disable write allocate */ + + ; #mcr 15, 1, r0, c9, c0, 2 + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] +} + + +# AIPS setup - Only setup MPROTx registers. +# The PACR default values are good. +proc init_aips { } { + ; # Set all MPROTx to be non-bufferable, trusted for R/W, + ; # not forced to user-mode. + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set VAL 0x77777777 + +# dap apsel 1 + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL +# dap apsel 0 +} + + +proc init_clock { } { + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] + set CLKCTL_CCSR 0x0C + set CLKCTL_CBCDR 0x14 + set CLKCTL_CBCMR 0x18 + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] + set CLKCTL_CSCMR1 0x1C + set CLKCTL_CDHIPR 0x48 + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] + set CLKCTL_CSCDR1 0x24 + set CLKCTL_CCDR 0x04 + + ; # Switch ARM to step clock + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 + + return + echo "not returned" + setup_pll $PLL1_BASE_ADDR 800 + setup_pll $PLL3_BASE_ADDR 400 + + ; # Switch peripheral to PLL3 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL2_BASE_ADDR 400 + + ; # Switch peripheral to PLL2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 + + ; # change uart clk parent to pll2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] + + ; # make sure change is effective + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL3_BASE_ADDR 216 + + setup_pll $PLL4_BASE_ADDR 455 + + ; # Set the platform clock dividers + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 + + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 + + ; # Switch ARM back to PLL 1. + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 + + ; # make uart div=6 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] + + ; # Restore the default values in the Gate registers + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 + + ; # for cko - for ARM div by 8 + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] +} + + +proc setup_pll { PLL_ADDR CLK } { + set PLL_DP_CTL 0x00 + set PLL_DP_CONFIG 0x04 + set PLL_DP_OP 0x08 + set PLL_DP_HFS_OP 0x1C + set PLL_DP_MFD 0x0C + set PLL_DP_HFS_MFD 0x20 + set PLL_DP_MFN 0x10 + set PLL_DP_HFS_MFN 0x24 + + if {$CLK == 1000} { + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] + set DP_MFN 5 + } elseif {$CLK == 850} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 41 + } elseif {$CLK == 800} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 700} { + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 7 + } elseif {$CLK == 600} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 1 + } elseif {$CLK == 665} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] + set DP_MFN 89 + } elseif {$CLK == 532} { + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 13 + } elseif {$CLK == 455} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 71 + } elseif {$CLK == 400} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 216} { + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 3 + } else { + error "Error (setup_dll): clock not found!" + } + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 + + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP + + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD + + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } +} + + +proc CPU_2_BE_32 { L } { + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] +} + + +# Device Configuration Data +proc DCD { } { +# dap apsel 1 +#*========================================================================================== ====== +# Initialization script for 32 bit DDR3 (CS0+CS1) +#*========================================================================================== ====== +# Remux D24/D25 to perform Flash-access + mww 0x53fa818C 0x00000000 ; #EIM_RW + mww 0x53fa8180 0x00000000 ; #EIM_CS0 + mww 0x53fa8188 0x00000000 ; #EIM_OE + mww 0x53fa817C 0x00000000 ; #A16 + mww 0x53fa8178 0x00000000 ; #A17 + mww 0x53fa8174 0x00000000 ; #A18 + mww 0x53fa8170 0x00000000 ; #A19 + mww 0x53fa816C 0x00000000 ; #A20 + mww 0x53fa8168 0x00000000 ; #A21 + mww 0x53fa819C 0x00000000 ; #DA0 + mww 0x53fa81A0 0x00000000 ; #DA1 + mww 0x53fa81A4 0x00000000 ; #DA2 + mww 0x53fa81A8 0x00000000 ; #DA3 + mww 0x53fa81AC 0x00000000 ; #DA4 + mww 0x53fa81B0 0x00000000 ; #DA5 + mww 0x53fa81B4 0x00000000 ; #DA6 + mww 0x53fa81B8 0x00000000 ; #DA7 + mww 0x53fa81BC 0x00000000 ; #DA8 + mww 0x53fa81C0 0x00000000 ; #DA9 + mww 0x53fa81C4 0x00000000 ; #DA10 + mww 0x53fa81C8 0x00000000 ; #DA11 + mww 0x53fa81CC 0x00000000 ; #DA12 + mww 0x53fa81D0 0x00000000 ; #DA13 + mww 0x53fa81D4 0x00000000 ; #DA14 + mww 0x53fa81D8 0x00000000 ; #DA15 + mww 0x53fa8118 0x00000000 ; #D16 + mww 0x53fa811C 0x00000000 ; #D17 + mww 0x53fa8120 0x00000000 ; #D18 + mww 0x53fa8124 0x00000000 ; #D19 + mww 0x53fa8128 0x00000000 ; #D20 + mww 0x53fa812C 0x00000000 ; #D21 + mww 0x53fa8130 0x00000000 ; #D22 + mww 0x53fa8134 0x00000000 ; #D23 + mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24 + mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25 + mww 0x53fa8144 0x00000000 ; #D26 + mww 0x53fa8148 0x00000000 ; #D27 + mww 0x53fa814C 0x00000000 ; #D28 + mww 0x53fa8150 0x00000000 ; #D29 + mww 0x53fa8154 0x00000000 ; #D30 + mww 0x53fa8158 0x00000000 ; #D31 + +# DDR3 IOMUX configuration +#* Global pad control options */ + mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 + mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 + mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 + mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 + mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 + mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency + mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS + mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency + mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 + mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 + mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 + mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS + mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 + mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 + mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS + mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL + mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE +# mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX + mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX + mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS + mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS + mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS + mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX + mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS + mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS +# mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode +# mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode +# mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE +# mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00 + +#* Data bus byte lane pad drive strength control options */ +# mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS +# mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 +# mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 +# mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS +# mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 +# mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 +# mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS +# mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 +# mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 +# mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS +# mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +# mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 + +#* SDCLK pad drive strength control options */ +# mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 +# mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + +#* Control and addr bus pad drive strength control options */ +# mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS +# mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS +# mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus +# mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE + +# mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 +# mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 + +# Initialize DDR3 memory - Micron MT41J128M16-187Er +#** Keep for now, same setting as CPU3 board **# + mww 0x63fd901c 0x00008000 +# mww 0x63fd904c 0x01680172 ; #write leveling reg 0 +# mww 0x63fd9050 0x0021017f ; #write leveling reg 1 + mww 0x63fd9088 0x32383535 ; #read delay lines + mww 0x63fd9090 0x40383538 ; #write delay lines +# mww 0x63fd90F8 0x00000800 ; #Measure unit + mww 0x63fd907c 0x0136014d ; #DQS gating 0 + mww 0x63fd9080 0x01510141 ; #DQS gating 1 +#* CPU3 Board settingr +# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0 +# mww 0x63fd9018 0x00091740 ; #Misc register: +#* Quick Silver board setting +# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0 + mww 0x63fd9018 0x00011740 ; #Misc register + +# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit +# mww 0x63fd9000 0xc3190000 ; #Main control register +# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit + mww 0x63fd9000 0x83190000 ; #Main control register +# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck + mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0 +# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck + mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1 +# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4 + mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2 + mww 0x63fd902c 0x000026d2 ; #command delay (default) + mww 0x63fd9030 0x009f0e21 ; #out of reset delays +# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values + mww 0x63fd9008 0x12273030 ; #ODT timings +# tCKE=3; tCKSRX=5; tCKSRE=5 + mww 0x63fd9004 0x0002002d +#Power down control +#********************************** +#DDR device configuration: +#********************************** +#********************************** +# CS0: +#********************************** + mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings) +# Full array self refresh +# Rtt_WR disabled (no ODT at IO CMOS operation) +# Manual self refresh +# CWS=5 + mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0. + mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings) +# out impedance = RZQ/7 +# Rtt_nom disabled (no ODT at IO CMOS operation) +# Aditive latency off +# write leveling disabled +# tdqs (differential?) disabled + + mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0 + mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL) +#********************************** +# CS1: +#********************************** +# mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1. +# mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1. +# mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7 +# mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1. +# mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL) +#********************************** + + + mww 0x63fd9020 0x00001800 ; # Refresh control register + mww 0x63fd9040 0x04b80003 ; # ZQ HW control + mww 0x63fd9058 0x00022227 ; # ODT control register + + mww 0x63fd901c 0x00000000 + +# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals) +# mww 0x53FA8314 = 0 +# mww 0x53FA8320 0x4 +# mww 0x53FD4060 0x01e900f0 + +# dap apsel 0 +} + +# IRAM +$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1 + +flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME + +# vim:filetype=tcl diff --git a/openocd-win/openocd/scripts/board/icnova_sam9g45_sodimm.cfg b/openocd-win/openocd/scripts/board/icnova_sam9g45_sodimm.cfg new file mode 100644 index 0000000..7efa8c2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/icnova_sam9g45_sodimm.cfg @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################################# +# # +# Author: Lars Poeschel (larsi@wh2.tu-dresden.de) # +# Generated for In-Circuit ICnova SAM9G45 SODIMM # +# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova # +# # +################################################################################################# + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + +source [find target/at91sam9g45.cfg] + +# Set reset type. +# reset_config trst_and_srst + +# adapter srst delay 200 +# jtag_ntrst_delay 200 + + +# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the +# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has +# some powerful features, we want to have a special function that handles "reset init". To do this we declare +# an event handler where these special activities can take place. + +scan_chain +$_TARGETNAME configure -event reset-init {at91sam9g45_init} + +# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). +# Slow-speed oscillator enabled at reset, so run jtag speed slow. +$_TARGETNAME configure -event reset-start {at91sam9g45_start} + + +# NandFlash configuration and definition +# Future TBD +# Flash configuration +# flash bank cfi <base> <size> <chip width> <bus width> <target#> +set _FLASHNAME $_CHIPNAME.flash +# set _NANDNAME $_CHIPNAME.nand +flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME +# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800 + + +proc read_register {register} { + return [read_memory $register 32 1] +} + +proc at91sam9g45_start { } { + + # Make sure that the the jtag is running slow, since there are a number of different ways the board + # can be configured coming into this state that can cause communication problems with the jtag + # adapter. Also since this call can be made following a "reset init" where fast memory accesses + # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower + # jtag speed without causing GDB keep alive problem. + + arm7_9 fast_memory_access disable + # Slow-speed oscillator enabled at reset, so run jtag speed slow. + adapter speed 4 + # Make sure processor is halted, or error will result in following steps. + halt + wait_halt 10000 + # RSTC_MR : enable user reset. + mww 0xfffffd08 0xa5000501 +} + + +proc at91sam9g45_init { } { + + # At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires + # a number of steps that must be carefully performed. The process outline below follows the + # recommended procedure outlined in the AT91SAM9G45 technical manual. + # + # Several key and very important things to keep in mind: + # The SDRAM parts used currently on the board are -75 grade parts. This + # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor + # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly. + + # Make sure processor is halted, or error will result in following steps. + halt + # RSTC_MR : enable user reset. + mww 0xfffffd08 0xa5000501 + # WDT_MR : disable watchdog. + mww 0xfffffd44 0x00008000 + + # Enable the main 15.000 MHz oscillator in CKGR_MOR register. + # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. + + mww 0xfffffc20 0x00004001 + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } + + # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). + # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. + + #mww 0xfffffc28 0x202a3f01 + mww 0xfffffc28 0x20c73f03 + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } + + # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. + # Wait for MCKRDY signal from PMC_SR to assert. + + #mww 0xfffffc30 0x00000101 + mww 0xfffffc30 0x00001301 + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } + + # Now change PMC_MCKR register to select PLLA. + # Wait for MCKRDY signal from PMC_SR to assert. + + mww 0xfffffc30 0x00001302 + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } + + # Processor and master clocks are now operating and stable at maximum frequency possible: + # -> MCLK = 132.096 MHz + # -> PCLK = 396.288 MHz + + # Switch over to adaptive clocking. + + adapter speed 6000 + + # Enable faster DCC downloads. + + arm7_9 dcc_downloads enable + + # To be able to use external SDRAM, several peripheral configuration registers must + # be modified. The first change is made to PIO_ASR to select peripheral functions + # for D15 through D31. The second change is made to the PIO_PDR register to disable + # this for D15 through D31. + +# mww 0xfffff870 0xffff0000 +# mww 0xfffff804 0xffff0000 + + # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller + # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on + # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller. + + # mww 0xffffef1c 0x000100a + + # The ICnova SAM9G45 SODIMM has built-in NandFlash. The exact physical timing characteristics + # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting + # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. + + # mww 0xffffec30 0x00020002 + # mww 0xffffec34 0x04040404 + # mww 0xffffec38 0x00070007 + # mww 0xffffec3c 0x00030003 + + # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete. + +# nand probe 0 + + # SMC_SETUP0 : Setup SMC for NOR Flash + mww 0xffffe800 0x0012000a + # SMC_PULSE0 + mww 0xffffe804 0x3b38343b + # SMC_CYCLE0 + mww 0xffffe808 0x003f003f + # SMC_MODE0 + mww 0xffffe80c 0x00001000 + # Identify flash bank 0 + flash probe 0 + + # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations + # are based on 2 x Samsung K4T51083QG memory. + + # 0. Enable DDR2 Clock + mww 0xfffffc00 0x4 + # 1. Program memory device type + # 1.1 configure the DDR controller + mww 0xffffe620 0x16 + # 1.2 program the DDR controller + mww 0xffffe608 0x3d + + # 2. program memory device features + # 2.1 assume timings for 7.5ns min clock period + mww 0xffffe60c 0x21128226 + # 2.2 pSDDRC->HDDRSDRC2_T1PR + mww 0xffffe610 0x02c8100e + # 2.3 pSDDRC->HDDRSDRC2_T2PR + mww 0xffffe614 0x01000702 + # 3. NOP + mww 0xffffe600 0x1 + mww 0x70000000 0x1 + # 3.1 delay 200us + sleep 1 + # jim tcl alternative: after ms + # after 0.2 + + # 4. NOP + mww 0xffffe600 0x1 + mww 0x70000000 0x1 + # 4.1 delay 400ns + + # 5. set all bank precharge + mww 0xffffe600 0x2 + mww 0x70000000 0x1 + # 5.1 delay 400ns + + # 6. set EMR operation (EMRS2) + mww 0xffffe600 0x5 + mww 0x74000000 0x1 + # 6.1 delay 2 cycles + + # 7. set EMR operation (EMRS3) + mww 0xffffe600 0x5 + mww 0x76000000 0x1 + # 7.1 delay 2 cycles + + # 8. set EMR operation (EMRS1) + mww 0xffffe600 0x5 + mww 0x72000000 0x1 + # 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s) + sleep 1 + + # 9. Enable DLL Reset (set DLL bit) + set CR [expr {[read_register 0xffffe608] | 0x80}] + mww 0xffffe608 $CR + + # 10. mode register cycle to reset the DLL + mww 0xffffe600 0x5 + mww 0x70000000 0x1 + # 10.1 delay 2 cycles + + # 11. set all bank precharge + mww 0xffffe600 0x2 + mww 0x70000000 0x1 + # 11.1 delay 400 ns + + # 12. two auto-refresh (CBR) cycles are provided. + mww 0xffffe600 0x4 + mww 0x70000000 0x1 + # 12.1 delay 10 cycles + # 12.2 2nd cycle (schreiben des Mode Register sparen wir uns) + mww 0x70000000 0x1 + # 12.3 delay 10 cycles + + # 13. disable DLL reset (clear DLL bit) + set CR [expr {[read_register 0xffffe608] & 0xffffff7f}] + mww 0xffffe608 $CR + + # 14. mode register set cycle + mww 0xffffe600 0x3 + mww 0x70000000 0x1 + + # 15. program OCD field (set OCD bits) + set CR [expr {[read_register 0xffffe608] | 0x7000}] + mww 0xffffe608 $CR + + # 16. (EMRS1) + mww 0xffffe600 0x5 + mww 0x72000000 0x1 + # 16.1 delay 2 cycles + + # 17. disable OCD field (clear OCD bits) + set CR [expr {[read_register 0xffffe608] & 0xffff8fff}] + mww 0xffffe608 $CR + + # 18. (EMRS1) + mww 0xffffe600 0x5 + mww 0x76000000 0x1 + # 18.1 delay 2 cycles + + # 19. normal mode command + mww 0xffffe600 0x0 + mww 0x70000000 0x1 + + # 20. perform write to any address + #mww 0x70000000 0x1 + + # 21. write refresh rate into the count field of the refresh rate register + mww 0xffffe604 0x24b + # 21.1 delay (500 * 6 cycles) + + arm7_9 fast_memory_access enable +} diff --git a/openocd-win/openocd/scripts/board/imx27ads.cfg b/openocd-win/openocd/scripts/board/imx27ads.cfg new file mode 100644 index 0000000..79d3c51 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx27ads.cfg @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The IMX27 ADS eval board has a single IMX27 chip +# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8 +source [find target/imx27.cfg] +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { imx27ads_init } + +# The IMX27 ADS board has a NOR flash on CS0 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME + +proc imx27ads_init { } { + # This setup puts RAM at 0xA0000000 + + # reset the board correctly + reset run + reset halt + + mww 0x10000000 0x20040304 + mww 0x10020000 0x00000000 + mww 0x10000004 0xDFFBFCFB + mww 0x10020004 0xFFFFFFFF + + sleep 100 + + # ======================================== + # Configure DDR on CSD0 -- initial reset + # ======================================== + mww 0xD8001010 0x00000008 + + # ======================================== + # Configure PSRAM on CS5 + # ======================================== + mww 0xd8002050 0x0000dcf6 + mww 0xd8002054 0x444a4541 + mww 0xd8002058 0x44443302 + + # ======================================== + # Configure16 bit NorFlash on CS0 + # ======================================== + mww 0xd8002000 0x0000CC03 + mww 0xd8002004 0xa0330D01 + mww 0xd8002008 0x00220800 + + # ======================================== + # Configure CPLD on CS4 + # ======================================== + mww 0xd8002040 0x0000DCF6 + mww 0xd8002044 0x444A4541 + mww 0xd8002048 0x44443302 + + # ======================================== + # Configure DDR on CSD0 -- wait 5000 cycle + # ======================================== + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 + + mww 0xD8001010 0x00000004 + + mww 0xD8001004 0x00795729 + + mww 0xD8001000 0x92200000 + mww 0xA0000F00 0x0 + + mww 0xD8001000 0xA2200000 + mww 0xA0000F00 0x0 + mww 0xA0000F00 0x0 + + mww 0xD8001000 0xB2200000 + mwb 0xA0000033 0xFF + mwb 0xA1000000 0xAA + + mww 0xD8001000 0x82228085 +} diff --git a/openocd-win/openocd/scripts/board/imx27lnst.cfg b/openocd-win/openocd/scripts/board/imx27lnst.cfg new file mode 100644 index 0000000..24f6ed8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx27lnst.cfg @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Linuxstamp-mx27 is board has a single IMX27 chip +# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD +source [find target/imx27.cfg] +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { imx27lnst_init } + +proc imx27lnst_init { } { + # This setup puts RAM at 0xA0000000 + + # reset the board correctly + adapter speed 500 + reset run + reset halt + + mww 0x10000000 0x20040304 + mww 0x10020000 0x00000000 + mww 0x10000004 0xDFFBFCFB + mww 0x10020004 0xFFFFFFFF + + sleep 100 + + # ======================================== + # Configure DDR on CSD0 -- initial reset + # ======================================== + mww 0xD8001010 0x00000008 + + sleep 100 + + # ======================================== + # Configure DDR on CSD0 -- wait 5000 cycle + # ======================================== + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 + + mww 0xD8001010 0x00000004 + + mww 0xD8001004 0x00795729 + + #mww 0xD8001000 0x92200000 + mww 0xD8001000 0x91120000 + mww 0xA0000F00 0x0 + + #mww 0xD8001000 0xA2200000 + mww 0xD8001000 0xA1120000 + mww 0xA0000F00 0x0 + mww 0xA0000F00 0x0 + + #mww 0xD8001000 0xB2200000 + mww 0xD8001000 0xB1120000 + mwb 0xA0000033 0xFF + mwb 0xA1000000 0xAA + + #mww 0xD8001000 0x82228085 + mww 0xD8001000 0x81128080 + +} diff --git a/openocd-win/openocd/scripts/board/imx28evk.cfg b/openocd-win/openocd/scripts/board/imx28evk.cfg new file mode 100644 index 0000000..cc13c51 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx28evk.cfg @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The IMX28EVK eval board has a IMX28 chip +# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD +# Date: 201-02-01 +# Authors: James Robinson & Fabio Estevam + +source [find target/imx28.cfg] +$_TARGETNAME configure -event gdb-attach { imx28evk_init } +$_TARGETNAME configure -event reset-init { imx28evk_init } + +proc imx28evk_init { } { + + halt + + #**************************** + # VDDD setting + #**************************** + # set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e + mww 0x80044010 0x0003F503 + mww 0x80044040 0x0002041E + + #**************************** + # CLOCK set up + #**************************** + # Power up PLL0 HW_CLKCTRL_PLL0CTRL0 + mww 0x80040000 0x00020000 + # Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0 + # EMI - first set DIV_EMI to div-by-2 before programming frac divider + mww 0x800400F0 0x80000002 + + + # CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz + mww 0x800401B0 0x92921613 + # Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR + mww 0x800401D8 0x00040080 + # HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2 + mww 0x80040060 0x00000002 + + #**************************** + # POWER up DCDD_VDDA (DDR2) + #**************************** + # Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC + mww 0x80044050 0x0000270C + + #**************************** + # DDR2 DCDD_VDDA + #**************************** + # First set up pin muxing and drive strength + # Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR + mww 0x80018008 0xC0000000 + + #**************************** + # EMI PAD setting + #**************************** + # Set up drive strength for EMI pins + mww 0x80019B80 0x00030000 + #IOMUXC_SW_PAD_CTL_GRP_CTLDS + + # Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13 + mww 0x800181A8 0xFFFFFFFF + mww 0x800181B8 0xFFFFFFFF + mww 0x800181C8 0xFFFFFFFF + mww 0x800181D8 0xFFFFFFFF + + #** Ungate EMI clock in CCM + mww 0x800400F0 0x00000002 + + #============================================================================ + # DDR Controller Registers + #============================================================================ + # Manufacturer: Elpida + # Device Part Number: EDE1116AEBG + # Clock Freq.: 200MHz + # Density: 1Gb + # Chip Selects: 1 + # Number of Banks: 8 + # Row address: 13 + # Column address: 10 + #============================================================================ + mww 0x800E0000 0x00000000 + mww 0x800E0040 0x00000000 + mww 0x800E0054 0x00000000 + mww 0x800E0058 0x00000000 + mww 0x800E005C 0x00000000 + mww 0x800E0060 0x00000000 + mww 0x800E0064 0x00000000 + mww 0x800E0068 0x00010101 + mww 0x800E006C 0x01010101 + mww 0x800E0070 0x000f0f01 + mww 0x800E0074 0x0102020A + mww 0x800E007C 0x00010101 + mww 0x800E0080 0x00000100 + mww 0x800E0084 0x00000100 + mww 0x800E0088 0x00000000 + mww 0x800E008C 0x00000002 + mww 0x800E0090 0x01010000 + mww 0x800E0094 0x07080403 + mww 0x800E0098 0x06005003 + mww 0x800E009C 0x0A0000C8 + mww 0x800E00A0 0x02009C40 + mww 0x800E00A4 0x0002030C + mww 0x800E00A8 0x0036B009 + mww 0x800E00AC 0x031A0612 + mww 0x800E00B0 0x02030202 + mww 0x800E00B4 0x00C8001C + mww 0x800E00C0 0x00011900 + mww 0x800E00C4 0xffff0303 + mww 0x800E00C8 0x00012100 + mww 0x800E00CC 0xffff0303 + mww 0x800E00D0 0x00012100 + mww 0x800E00D4 0xffff0303 + mww 0x800E00D8 0x00012100 + mww 0x800E00DC 0xffff0303 + mww 0x800E00E0 0x00000003 + mww 0x800E00E8 0x00000000 + mww 0x800E0108 0x00000612 + mww 0x800E010C 0x01000f02 + mww 0x800E0114 0x00000200 + mww 0x800E0118 0x00020007 + mww 0x800E011C 0xf4004a27 + mww 0x800E0120 0xf4004a27 + mww 0x800E012C 0x07400300 + mww 0x800E0130 0x07400300 + mww 0x800E013C 0x00000005 + mww 0x800E0140 0x00000000 + mww 0x800E0144 0x00000000 + mww 0x800E0148 0x01000000 + mww 0x800E014C 0x01020408 + mww 0x800E0150 0x08040201 + mww 0x800E0154 0x000f1133 + mww 0x800E015C 0x00001f04 + mww 0x800E0160 0x00001f04 + mww 0x800E016C 0x00001f04 + mww 0x800E0170 0x00001f04 + mww 0x800E0288 0x00010000 + mww 0x800E028C 0x00030404 + mww 0x800E0290 0x00000003 + mww 0x800E02AC 0x01010000 + mww 0x800E02B0 0x01000000 + mww 0x800E02B4 0x03030000 + mww 0x800E02B8 0x00010303 + mww 0x800E02BC 0x01020202 + mww 0x800E02C0 0x00000000 + mww 0x800E02C4 0x02030303 + mww 0x800E02C8 0x21002103 + mww 0x800E02CC 0x00061200 + mww 0x800E02D0 0x06120612 + mww 0x800E02D4 0x04420442 + # Mode register 0 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02D8 0x00000000 + # Mode register 0 for CS2 and CS3, not supported in this processor + mww 0x800E02DC 0x00040004 + # Mode register 1 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02E0 0x00000000 + # Mode register 1 for CS2 and CS3, not supported in this processor + mww 0x800E02E4 0x00000000 + # Mode register 2 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02E8 0x00000000 + # Mode register 2 for CS2 and CS3, not supported in this processor + mww 0x800E02EC 0x00000000 + # Mode register 3 for CS1 and CS0, ok to program CS1 even if not used + mww 0x800E02F0 0x00000000 + # Mode register 3 for CS2 and CS3, not supported in this processor + mww 0x800E02F4 0xffffffff + + #** start controller **# + mww 0x800E0040 0x00000001 + # bit[0]: start +} diff --git a/openocd-win/openocd/scripts/board/imx31pdk.cfg b/openocd-win/openocd/scripts/board/imx31pdk.cfg new file mode 100644 index 0000000..65fa520 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx31pdk.cfg @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The IMX31PDK eval board has a single IMX31 chip +source [find target/imx31.cfg] +source [find target/imx.cfg] +$_TARGETNAME configure -event reset-init { imx31pdk_init } + +proc self_test {} { + echo "Running 100 iterations of test." + dump_image /ram/test 0x80000000 0x40000 + for {set i 0} {$i < 100} {set i [expr {$i+1}]} { + echo "Iteration $i" + reset init + mww 0x80000000 0x12345678 0x10000 + load_image /ram/test 0x80000000 bin + verify_image /ram/test 0x80000000 bin + } +} + + +# Slow fallback frequency +# measure_clk indicates ca. 3-4MHz. +jtag_rclk 1000 + +proc imx31pdk_init { } { + + imx3x_reset + + # This setup puts RAM at 0x80000000 + + mww 0x53FC0000 0x040 + mww 0x53F80000 0x074B0B7D + + # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40 + #mww 0x53F80004 0xFF871D50 + #mww 0x53F80010 0x00271C1B + + # Start 16 bit NorFlash Initialization on CS0 + mww 0xb8002000 0x0000CC03 + mww 0xb8002004 0xa0330D01 + mww 0xb8002008 0x00220800 + + # Configure CPLD on CS4 + mww 0xb8002040 0x0000DCF6 + mww 0xb8002044 0x444A4541 + mww 0xb8002048 0x44443302 + + # SDCLK + mww 0x43FAC26C 0 + + # CAS + mww 0x43FAC270 0 + + # RAS + mww 0x43FAC274 0 + + # CS2 (CSD0) + mww 0x43FAC27C 0x1000 + + # DQM3 + mww 0x43FAC284 0 + + # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) + mww 0x43FAC288 0 + mww 0x43FAC28C 0 + mww 0x43FAC290 0 + mww 0x43FAC294 0 + mww 0x43FAC298 0 + mww 0x43FAC29C 0 + mww 0x43FAC2A0 0 + mww 0x43FAC2A4 0 + mww 0x43FAC2A8 0 + mww 0x43FAC2AC 0 + mww 0x43FAC2B0 0 + mww 0x43FAC2B4 0 + mww 0x43FAC2B8 0 + mww 0x43FAC2BC 0 + mww 0x43FAC2C0 0 + mww 0x43FAC2C4 0 + mww 0x43FAC2C8 0 + mww 0x43FAC2CC 0 + mww 0x43FAC2D0 0 + mww 0x43FAC2D4 0 + mww 0x43FAC2D8 0 + mww 0x43FAC2DC 0 + + # Initialization script for 32 bit DDR on MX31 ADS + mww 0xB8001010 0x00000004 + mww 0xB8001004 0x006ac73a + mww 0xB8001000 0x92100000 + mww 0x80000f00 0x12344321 + mww 0xB8001000 0xa2100000 + mww 0x80000000 0x12344321 + mww 0x80000000 0x12344321 + mww 0xB8001000 0xb2100000 + mwb 0x80000033 0xda + mwb 0x81000000 0xff + mww 0xB8001000 0x82226080 + mww 0x80000000 0xDEADBEEF + mww 0xB8001010 0x0000000c +} diff --git a/openocd-win/openocd/scripts/board/imx35pdk.cfg b/openocd-win/openocd/scripts/board/imx35pdk.cfg new file mode 100644 index 0000000..41206c6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx35pdk.cfg @@ -0,0 +1,254 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The IMX35PDK eval board has a single IMX35 chip +source [find target/imx35.cfg] +source [find target/imx.cfg] +$_TARGETNAME configure -event reset-init { imx35pdk_init } + +# Stick to *really* low clock rate or reset will fail +# without RTCK / RCLK +jtag_rclk 10 + +proc imx35pdk_init { } { + + imx3x_reset + + mww 0x43f00040 0x00000000 + mww 0x43f00044 0x00000000 + mww 0x43f00048 0x00000000 + mww 0x43f0004C 0x00000000 + mww 0x43f00050 0x00000000 + mww 0x43f00000 0x77777777 + mww 0x43f00004 0x77777777 + mww 0x53f00040 0x00000000 + mww 0x53f00044 0x00000000 + mww 0x53f00048 0x00000000 + mww 0x53f0004C 0x00000000 + mww 0x53f00050 0x00000000 + mww 0x53f00000 0x77777777 + mww 0x53f00004 0x77777777 + + # clock setup + mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP + mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz. + + #================================================= + # WEIM config + #================================================= + # CS0U + mww 0xB8002000 0x0000CC03 + # CS0L + mww 0xB8002004 0xA0330D01 + # CS0A + mww 0xB8002008 0x00220800 + # CS5U + mww 0xB8002050 0x0000dcf6 + # CS5L + mww 0xB8002054 0x444a4541 + # CS5A + mww 0xB8002058 0x44443302 + + # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR + mww 0x43FAC368 0x00000006 + mww 0x43FAC36C 0x00000006 + mww 0x43FAC370 0x00000006 + mww 0x43FAC374 0x00000006 + mww 0x43FAC378 0x00000006 + mww 0x43FAC37C 0x00000006 + mww 0x43FAC380 0x00000006 + mww 0x43FAC384 0x00000006 + mww 0x43FAC388 0x00000006 + mww 0x43FAC38C 0x00000006 + mww 0x43FAC390 0x00000006 + mww 0x43FAC394 0x00000006 + mww 0x43FAC398 0x00000006 + mww 0x43FAC39C 0x00000006 + mww 0x43FAC3A0 0x00000006 + mww 0x43FAC3A4 0x00000006 + mww 0x43FAC3A8 0x00000006 + mww 0x43FAC3AC 0x00000006 + mww 0x43FAC3B0 0x00000006 + mww 0x43FAC3B4 0x00000006 + mww 0x43FAC3B8 0x00000006 + mww 0x43FAC3BC 0x00000006 + mww 0x43FAC3C0 0x00000006 + mww 0x43FAC3C4 0x00000006 + mww 0x43FAC3C8 0x00000006 + mww 0x43FAC3CC 0x00000006 + mww 0x43FAC3D0 0x00000006 + mww 0x43FAC3D4 0x00000006 + mww 0x43FAC3D8 0x00000006 + + # DDR data bus SD 0 through 31 + mww 0x43FAC3DC 0x00000082 + mww 0x43FAC3E0 0x00000082 + mww 0x43FAC3E4 0x00000082 + mww 0x43FAC3E8 0x00000082 + mww 0x43FAC3EC 0x00000082 + mww 0x43FAC3F0 0x00000082 + mww 0x43FAC3F4 0x00000082 + mww 0x43FAC3F8 0x00000082 + mww 0x43FAC3FC 0x00000082 + mww 0x43FAC400 0x00000082 + mww 0x43FAC404 0x00000082 + mww 0x43FAC408 0x00000082 + mww 0x43FAC40C 0x00000082 + mww 0x43FAC410 0x00000082 + mww 0x43FAC414 0x00000082 + mww 0x43FAC418 0x00000082 + mww 0x43FAC41c 0x00000082 + mww 0x43FAC420 0x00000082 + mww 0x43FAC424 0x00000082 + mww 0x43FAC428 0x00000082 + mww 0x43FAC42c 0x00000082 + mww 0x43FAC430 0x00000082 + mww 0x43FAC434 0x00000082 + mww 0x43FAC438 0x00000082 + mww 0x43FAC43c 0x00000082 + mww 0x43FAC440 0x00000082 + mww 0x43FAC444 0x00000082 + mww 0x43FAC448 0x00000082 + mww 0x43FAC44c 0x00000082 + mww 0x43FAC450 0x00000082 + mww 0x43FAC454 0x00000082 + mww 0x43FAC458 0x00000082 + + # DQM setup + mww 0x43FAC45c 0x00000082 + mww 0x43FAC460 0x00000082 + mww 0x43FAC464 0x00000082 + mww 0x43FAC468 0x00000082 + + mww 0x43FAC46c 0x00000006 + mww 0x43FAC470 0x00000006 + mww 0x43FAC474 0x00000006 + mww 0x43FAC478 0x00000006 + mww 0x43FAC47c 0x00000006 + mww 0x43FAC480 0x00000006 ;# CSD0 + mww 0x43FAC484 0x00000006 ;# CSD1 + mww 0x43FAC488 0x00000006 + mww 0x43FAC48c 0x00000006 + mww 0x43FAC490 0x00000006 + mww 0x43FAC494 0x00000006 + mww 0x43FAC498 0x00000006 + mww 0x43FAC49c 0x00000006 + mww 0x43FAC4A0 0x00000006 + mww 0x43FAC4A4 0x00000006 ;# RAS + mww 0x43FAC4A8 0x00000006 ;# CAS + mww 0x43FAC4Ac 0x00000006 ;# SDWE + mww 0x43FAC4B0 0x00000006 ;# SDCKE0 + mww 0x43FAC4B4 0x00000006 ;# SDCKE1 + mww 0x43FAC4B8 0x00000002 ;# SDCLK + + # SDQS0 through SDQS3 + mww 0x43FAC4Bc 0x00000082 + mww 0x43FAC4C0 0x00000082 + mww 0x43FAC4C4 0x00000082 + mww 0x43FAC4C8 0x00000082 + + + # *================================================== + # Initialization script for 32 bit DDR2 on RINGO 3DS + # *================================================== + + #-------------------------------------------- + # Init CCM + #-------------------------------------------- + mww 0x53F80028 0x7D000028 + + #-------------------------------------------- + # Init IOMUX for JTAG + #-------------------------------------------- + mww 0x43FAC5EC 0x000000C3 + mww 0x43FAC5F0 0x000000C3 + mww 0x43FAC5F4 0x000000F3 + mww 0x43FAC5F8 0x000000F3 + mww 0x43FAC5FC 0x000000F3 + mww 0x43FAC600 0x000000F3 + mww 0x43FAC604 0x000000F3 + + + # ESD_MISC : enable DDR2 + mww 0xB8001010 0x00000304 + + #-------------------------------------------- + # Init 32-bit DDR2 memory on CSD0 + # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25] + #-------------------------------------------- + + # ESD_ESDCFG0 : set timing parameters + mww 0xB8001004 0x007ffC2f + + # ESD_ESDCTL0 : select Prechare-All mode + mww 0xB8001000 0x92220000 + # DDR2 : Prechare-All + mww 0x80000400 0x12345678 + + # ESD_ESDCTL0 : select Load-Mode-Register mode + mww 0xB8001000 0xB2220000 + # DDR2 : Load reg EMR2 + mwb 0x84000000 0xda + # DDR2 : Load reg EMR3 + mwb 0x86000000 0xda + # DDR2 : Load reg EMR1 -- enable DLL + mwb 0x82000400 0xda + # DDR2 : Load reg MR -- reset DLL + mwb 0x80000333 0xda + + # ESD_ESDCTL0 : select Prechare-All mode + mww 0xB8001000 0x92220000 + # DDR2 : Prechare-All + mwb 0x80000400 0x12345678 + + # ESD_ESDCTL0 : select Manual-Refresh mode + mww 0xB8001000 0xA2220000 + # DDR2 : Manual-Refresh 2 times + mww 0x80000000 0x87654321 + mww 0x80000000 0x87654321 + + # ESD_ESDCTL0 : select Load-Mode-Register mode + mww 0xB8001000 0xB2220000 + # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset + mwb 0x80000233 0xda + # DDR2 : Load reg EMR1 -- OCD default + mwb 0x82000780 0xda + # DDR2 : Load reg EMR1 -- OCD exit + mwb 0x82000400 0xda ;# ODT disabled + + # ESD_ESDCTL0 : select normal-operation mode + # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit + # disable PWT & PRCT + # disable Auto-Refresh + mww 0xB8001000 0x82220080 + + ## ESD_ESDCTL0 : enable Auto-Refresh + mww 0xB8001000 0x82228080 + ## ESD_ESDCTL1 : enable Auto-Refresh + mww 0xB8001008 0x00002000 + + + #*********************************************** + # Adjust the ESDCDLY5 register + #*********************************************** + # Vary DQS_ABS_OFFSET5 for writes + mww 0xB8001020 0x00F48000 ;# this is the default value + mww 0xB8001024 0x00F48000 ;# this is the default value + mww 0xB8001028 0x00F48000 ;# this is the default value + mww 0xB800102c 0x00F48000 ;# this is the default value + + + #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC) + mww 0xB8001010 0x00000384 + # wait a while + sleep 1000 + # now clear the force measurement bit + mww 0xB8001010 0x00000304 + + # dummy write to DDR memory to set DQS low + mww 0x80000000 0x00000000 + + mww 0x30000100 0x0 + mww 0x30000104 0x31024 + + +} diff --git a/openocd-win/openocd/scripts/board/imx53-m53evk.cfg b/openocd-win/openocd/scripts/board/imx53-m53evk.cfg new file mode 100644 index 0000000..6f9210a --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx53-m53evk.cfg @@ -0,0 +1,320 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +####################################### +# DENX M53EVK # +# http://www.denx-cs.de/?q=M53EVK # +# Author: Marek Vasut <marex@denx.de> # +# Based on imx53loco.cfg # +####################################### + +# The DENX M53EVK has on-board JTAG adapter +source [find interface/ftdi/m53evk.cfg] +# The DENX M53EVK board has a single i.MX53 chip +source [find target/imx53.cfg] +# Helper for common memory read/modify/write procedures +source [find mem_helper.tcl] + +echo "iMX53 M53EVK board lodaded." + +# Set reset type +reset_config trst_and_srst separate trst_open_drain srst_open_drain + +# Run at 6 MHz +adapter speed 6000 + +$_TARGETNAME configure -event "reset-assert" { + echo "Resetting ...." + #cortex_a dbginit +} + +$_TARGETNAME configure -event reset-init { m53evk_init } + +global AIPS1_BASE_ADDR +set AIPS1_BASE_ADDR 0x53F00000 +global AIPS2_BASE_ADDR +set AIPS2_BASE_ADDR 0x63F00000 + +proc m53evk_init { } { + echo "Reset-init..." + ; # halt the CPU + halt + + echo "HW version [format %x [mrw 0x48]]" + + dap apsel 1 + DCD + + ; # ARM errata ID #468414 + set tR [arm mrc 15 0 1 0 1] + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit + + init_l2cc + init_aips + init_clock + + dap apsel 0 + + ; # Force ARM state + ; #reg cpsr 0x000001D3 + arm core_state arm +} + + +# L2CC Cache setup/invalidation/disable +proc init_l2cc { } { + ; #/* explicitly disable L2 cache */ + ; #mrc 15, 0, r0, c1, c0, 1 + set tR [arm mrc 15 0 1 0 1] + ; #bic r0, r0, #0x2 + ; #mcr 15, 0, r0, c1, c0, 1 + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] + + ; #/* reconfigure L2 cache aux control reg */ + ; #mov r0, #0xC0 /* tag RAM */ + ; #add r0, r0, #0x4 /* data RAM */ + ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */ + ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */ + ; #orr r0, r0, #(1 << 22) /* disable write allocate */ + + ; #mcr 15, 1, r0, c9, c0, 2 + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] +} + + +# AIPS setup - Only setup MPROTx registers. +# The PACR default values are good. +proc init_aips { } { + ; # Set all MPROTx to be non-bufferable, trusted for R/W, + ; # not forced to user-mode. + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set VAL 0x77777777 + +# dap apsel 1 + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL +# dap apsel 0 +} + + +proc init_clock { } { + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] + set CLKCTL_CCSR 0x0C + set CLKCTL_CBCDR 0x14 + set CLKCTL_CBCMR 0x18 + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] + set CLKCTL_CSCMR1 0x1C + set CLKCTL_CDHIPR 0x48 + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] + set CLKCTL_CSCDR1 0x24 + set CLKCTL_CCDR 0x04 + + ; # Switch ARM to step clock + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 + + return + echo "not returned" + setup_pll $PLL1_BASE_ADDR 800 + setup_pll $PLL3_BASE_ADDR 400 + + ; # Switch peripheral to PLL3 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL2_BASE_ADDR 400 + + ; # Switch peripheral to PLL2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 + + ; # change uart clk parent to pll2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] + + ; # make sure change is effective + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL3_BASE_ADDR 216 + + setup_pll $PLL4_BASE_ADDR 455 + + ; # Set the platform clock dividers + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 + + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 + + ; # Switch ARM back to PLL 1. + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 + + ; # make uart div=6 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] + + ; # Restore the default values in the Gate registers + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 + + ; # for cko - for ARM div by 8 + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] +} + + +proc setup_pll { PLL_ADDR CLK } { + set PLL_DP_CTL 0x00 + set PLL_DP_CONFIG 0x04 + set PLL_DP_OP 0x08 + set PLL_DP_HFS_OP 0x1C + set PLL_DP_MFD 0x0C + set PLL_DP_HFS_MFD 0x20 + set PLL_DP_MFN 0x10 + set PLL_DP_HFS_MFN 0x24 + + if {$CLK == 1000} { + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] + set DP_MFN 5 + } elseif {$CLK == 850} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 41 + } elseif {$CLK == 800} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 700} { + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 7 + } elseif {$CLK == 600} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 1 + } elseif {$CLK == 665} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] + set DP_MFN 89 + } elseif {$CLK == 532} { + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 13 + } elseif {$CLK == 455} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 71 + } elseif {$CLK == 400} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 216} { + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 3 + } else { + error "Error (setup_dll): clock not found!" + } + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 + + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP + + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD + + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } +} + + +proc CPU_2_BE_32 { L } { + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] +} + + +# Device Configuration Data +proc DCD { } { +# dap apsel 1 + mww 0x53fa86f4 0x00000000 ;# GRP_DDRMODE_CTL + mww 0x53fa8714 0x00000000 ;# GRP_DDRMODE + mww 0x53fa86fc 0x00000000 ;# GRP_DDRPKE + mww 0x53fa8724 0x04000000 ;# GRP_DDR_TYPE + + mww 0x53fa872c 0x00300000 ;# GRP_B3DS + mww 0x53fa8554 0x00300000 ;# DRAM_DQM3 + mww 0x53fa8558 0x00300040 ;# DRAM_SDQS3 + + mww 0x53fa8728 0x00300000 ;# GRP_B2DS + mww 0x53fa8560 0x00300000 ;# DRAM_DQM2 + mww 0x53fa8568 0x00300040 ;# DRAM_SDQS2 + + mww 0x53fa871c 0x00300000 ;# GRP_B1DS + mww 0x53fa8594 0x00300000 ;# DRAM_DQM1 + mww 0x53fa8590 0x00300040 ;# DRAM_SDQS1 + + mww 0x53fa8718 0x00300000 ;# GRP_B0DS + mww 0x53fa8584 0x00300000 ;# DRAM_DQM0 + mww 0x53fa857c 0x00300040 ;# DRAM_SDQS0 + + mww 0x53fa8578 0x00300000 ;# DRAM_SDCLK_0 + mww 0x53fa8570 0x00300000 ;# DRAM_SDCLK_1 + + mww 0x53fa8574 0x00300000 ;# DRAM_CAS + mww 0x53fa8588 0x00300000 ;# DRAM_RAS + mww 0x53fa86f0 0x00300000 ;# GRP_ADDDS + mww 0x53fa8720 0x00300000 ;# GRP_CTLDS + + mww 0x53fa8564 0x00300040 ;# DRAM_SDODT1 + mww 0x53fa8580 0x00300040 ;# DRAM_SDODT0 + + # Initialize DDR2 memory + mww 0x63fd9088 0x32383535 + mww 0x63fd9090 0x40383538 + mww 0x63fd907c 0x0136014d + mww 0x63fd9080 0x01510141 + + mww 0x63fd9018 0x00011740 + mww 0x63fd9000 0xc3190000 + mww 0x63fd900c 0x555952e3 + mww 0x63fd9010 0xb68e8b63 + mww 0x63fd9014 0x01ff00db + mww 0x63fd902c 0x000026d2 + mww 0x63fd9030 0x009f0e21 + mww 0x63fd9008 0x12273030 + mww 0x63fd9004 0x0002002d + mww 0x63fd901c 0x00008032 + mww 0x63fd901c 0x00008033 + mww 0x63fd901c 0x00028031 + mww 0x63fd901c 0x092080b0 + mww 0x63fd901c 0x04008040 + mww 0x63fd901c 0x0000803a + mww 0x63fd901c 0x0000803b + mww 0x63fd901c 0x00028039 + mww 0x63fd901c 0x09208138 + mww 0x63fd901c 0x04008048 + mww 0x63fd9020 0x00001800 + mww 0x63fd9040 0x04b80003 + mww 0x63fd9058 0x00022227 + mww 0x63fd901c 0x00000000 +# dap apsel 0 +} + +# vim:filetype=tcl diff --git a/openocd-win/openocd/scripts/board/imx53loco.cfg b/openocd-win/openocd/scripts/board/imx53loco.cfg new file mode 100644 index 0000000..fcc2f4d --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx53loco.cfg @@ -0,0 +1,317 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################## +# Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> # +# Kiwigrid GmbH # +################################################################################## + +# The IMX53LOCO (QSB) board has a single IMX53 chip +source [find target/imx53.cfg] +# Helper for common memory read/modify/write procedures +source [find mem_helper.tcl] + +echo "iMX53 Loco board lodaded." + +# Set reset type +#reset_config srst_only + +adapter speed 3000 + +# Slow speed to be sure it will work +jtag_rclk 1000 +$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } + +#adapter srst delay 200 +#jtag_ntrst_delay 200 + +$_TARGETNAME configure -event "reset-assert" { + echo "Resetting ...." + #cortex_a dbginit +} + +$_TARGETNAME configure -event reset-init { loco_init } + +global AIPS1_BASE_ADDR +set AIPS1_BASE_ADDR 0x53F00000 +global AIPS2_BASE_ADDR +set AIPS2_BASE_ADDR 0x63F00000 + +proc loco_init { } { + echo "Reset-init..." + ; # halt the CPU + halt + + echo "HW version [format %x [mrw 0x48]]" + + dap apsel 1 + DCD + + ; # ARM errata ID #468414 + set tR [arm mrc 15 0 1 0 1] + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit + + init_l2cc + init_aips + init_clock + + dap apsel 0 + + ; # Force ARM state + ; #reg cpsr 0x000001D3 + arm core_state arm + + jtag_rclk 3000 +# adapter speed 3000 +} + + +# L2CC Cache setup/invalidation/disable +proc init_l2cc { } { + ; #/* explicitly disable L2 cache */ + ; #mrc 15, 0, r0, c1, c0, 1 + set tR [arm mrc 15 0 1 0 1] + ; #bic r0, r0, #0x2 + ; #mcr 15, 0, r0, c1, c0, 1 + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] + + ; #/* reconfigure L2 cache aux control reg */ + ; #mov r0, #0xC0 /* tag RAM */ + ; #add r0, r0, #0x4 /* data RAM */ + ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */ + ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */ + ; #orr r0, r0, #(1 << 22) /* disable write allocate */ + + ; #mcr 15, 1, r0, c9, c0, 2 + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] +} + + +# AIPS setup - Only setup MPROTx registers. +# The PACR default values are good. +proc init_aips { } { + ; # Set all MPROTx to be non-bufferable, trusted for R/W, + ; # not forced to user-mode. + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set VAL 0x77777777 + +# dap apsel 1 + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL +# dap apsel 0 +} + + +proc init_clock { } { + global AIPS1_BASE_ADDR + global AIPS2_BASE_ADDR + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] + set CLKCTL_CCSR 0x0C + set CLKCTL_CBCDR 0x14 + set CLKCTL_CBCMR 0x18 + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] + set CLKCTL_CSCMR1 0x1C + set CLKCTL_CDHIPR 0x48 + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] + set CLKCTL_CSCDR1 0x24 + set CLKCTL_CCDR 0x04 + + ; # Switch ARM to step clock + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 + + return + echo "not returned" + setup_pll $PLL1_BASE_ADDR 800 + setup_pll $PLL3_BASE_ADDR 400 + + ; # Switch peripheral to PLL3 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL2_BASE_ADDR 400 + + ; # Switch peripheral to PLL2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 + + ; # change uart clk parent to pll2 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] + + ; # make sure change is effective + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } + + setup_pll $PLL3_BASE_ADDR 216 + + setup_pll $PLL4_BASE_ADDR 455 + + ; # Set the platform clock dividers + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 + + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 + + ; # Switch ARM back to PLL 1. + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 + + ; # make uart div=6 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] + + ; # Restore the default values in the Gate registers + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF + + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 + + ; # for cko - for ARM div by 8 + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] +} + + +proc setup_pll { PLL_ADDR CLK } { + set PLL_DP_CTL 0x00 + set PLL_DP_CONFIG 0x04 + set PLL_DP_OP 0x08 + set PLL_DP_HFS_OP 0x1C + set PLL_DP_MFD 0x0C + set PLL_DP_HFS_MFD 0x20 + set PLL_DP_MFN 0x10 + set PLL_DP_HFS_MFN 0x24 + + if {$CLK == 1000} { + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] + set DP_MFN 5 + } elseif {$CLK == 850} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 41 + } elseif {$CLK == 800} { + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 700} { + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 7 + } elseif {$CLK == 600} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 1 + } elseif {$CLK == 665} { + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] + set DP_MFN 89 + } elseif {$CLK == 532} { + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] + set DP_MFN 13 + } elseif {$CLK == 455} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] + set DP_MFN 71 + } elseif {$CLK == 400} { + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] + set DP_MFN 1 + } elseif {$CLK == 216} { + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] + set DP_MFN 3 + } else { + error "Error (setup_dll): clock not found!" + } + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 + + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP + + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD + + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN + + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } +} + + +proc CPU_2_BE_32 { L } { + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] +} + + +# Device Configuration Data +proc DCD { } { +# dap apsel 1 + mww 0x53FA8554 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 + mww 0x53FA8558 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 + mww 0x53FA8560 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 + mww 0x53FA8564 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT + mww 0x53FA8568 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 + mww 0x53FA8570 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + mww 0x53FA8574 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS + mww 0x53FA8578 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 + mww 0x53FA857c 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 + mww 0x53FA8580 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 + mww 0x53FA8584 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 + mww 0x53FA8588 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS + mww 0x53FA8590 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 + mww 0x53FA8594 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 + mww 0x53FA86f0 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS + mww 0x53FA86f4 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL + mww 0x53FA86fc 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE + mww 0x53FA8714 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode + mww 0x53FA8718 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B0DS + mww 0x53FA871c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B1DS + mww 0x53FA8720 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS + mww 0x53FA8724 0x04000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0= + mww 0x53FA8728 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B2DS + mww 0x53FA872c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B3DS + + # Initialize DDR2 memory + mww 0x63FD9088 0x35343535 ;# ESDCTL_RDDLCTL + mww 0x63FD9090 0x4d444c44 ;# ESDCTL_WRDLCTL + mww 0x63FD907c 0x01370138 ;# ESDCTL_DGCTRL0 + mww 0x63FD9080 0x013b013c ;# ESDCTL_DGCTRL1 + mww 0x63FD9018 0x00011740 ;# ESDCTL_ESDMISC + mww 0x63FD9000 0xc3190000 ;# ESDCTL_ESDCTL + mww 0x63FD900c 0x9f5152e3 ;# ESDCTL_ESDCFG0 + mww 0x63FD9010 0xb68e8a63 ;# ESDCTL_ESDCFG1 + mww 0x63FD9014 0x01ff00db ;# ESDCTL_ESDCFG2 + mww 0x63FD902c 0x000026d2 ;# ESDCTL_ESDRWD + mww 0x63FD9030 0x009f0e21 ;# ESDCTL_ESDOR + mww 0x63FD9008 0x12273030 ;# ESDCTL_ESDOTC + mww 0x63FD9004 0x0002002d ;# ESDCTL_ESDPDC + mww 0x63FD901c 0x00008032 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x00008033 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x00028031 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x052080b0 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x04008040 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x0000803a ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x0000803b ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x00028039 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x05208138 ;# ESDCTL_ESDSCR + mww 0x63FD901c 0x04008048 ;# ESDCTL_ESDSCR + mww 0x63FD9020 0x00005800 ;# ESDCTL_ESDREF + mww 0x63FD9040 0x04b80003 ;# ESDCTL_ZQHWCTRL + mww 0x63FD9058 0x00022227 ;# ESDCTL_ODTCTRL + mww 0x63FD901C 0x00000000 ;# ESDCTL_ESDSCR +# dap apsel 0 +} + +# vim:filetype=tcl diff --git a/openocd-win/openocd/scripts/board/imx8mp-evk.cfg b/openocd-win/openocd/scripts/board/imx8mp-evk.cfg new file mode 100644 index 0000000..898f3b7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/imx8mp-evk.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for NXP MC-IMX8MP-EVK +# +# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg +# + +transport select jtag +adapter speed 1000 +reset_config srst_only +adapter srst delay 100 + +set CHIPNAME imx8mp +set CHIPCORES 4 + +source [find target/imx8m.cfg] diff --git a/openocd-win/openocd/scripts/board/insignal_arndale.cfg b/openocd-win/openocd/scripts/board/insignal_arndale.cfg new file mode 100644 index 0000000..c7c28b3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/insignal_arndale.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# InSignal Arndale board +# + +source [find target/exynos5250.cfg] + +# Experimentally determined highest working speed +adapter speed 200 diff --git a/openocd-win/openocd/scripts/board/kasli.cfg b/openocd-win/openocd/scripts/board/kasli.cfg new file mode 100644 index 0000000..d85e1ca --- /dev/null +++ b/openocd-win/openocd/scripts/board/kasli.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter driver ftdi +ftdi device_desc "Quad RS232-HS" +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 +ftdi layout_init 0x0008 0x000b +# adapter usb location 1:8 + +reset_config none +transport select jtag +adapter speed 25000 + +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] +source [find fpga/xilinx-xadc.cfg] +source [find fpga/xilinx-dna.cfg] diff --git a/openocd-win/openocd/scripts/board/kc100.cfg b/openocd-win/openocd/scripts/board/kc100.cfg new file mode 100644 index 0000000..2fd6965 --- /dev/null +++ b/openocd-win/openocd/scripts/board/kc100.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Knovative KC-100 cable modem + +# TNETC4401PYP, 208-QFP U3 +source [find target/tnetc4401.cfg] + +# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND. +# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back. +reset_config trst_and_srst separate + +# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot. +# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys. +# That is remapped to 0xB0000000 uncached, 0x90000000 cached. +flash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME + +# Perform this after a clean reboot, halt, and reset init (which should also leave it halted). +proc kc100_dump_flash {} { + echo "Probing 48 TSOP Intel CFI flash chip (2MB)..." + flash probe intel + echo "Dumping 2MB flash chip to flashdump.bin. + flash read_bank 0 flashdump.bin 0 0x200000 +} + +#TODO figure out memory init sequence to be able to dump from cached segment instead + +# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1. + +# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX. + +# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com. +# The firmware/OS is also susceptible to many of the same procedures in "Hacking the Cable Modem" +# by DerEngel (Ryan Harris), available from No Starch Press. diff --git a/openocd-win/openocd/scripts/board/kc705.cfg b/openocd-win/openocd/scripts/board/kc705.cfg new file mode 100644 index 0000000..fad9fff --- /dev/null +++ b/openocd-win/openocd/scripts/board/kc705.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html + +source [find interface/ftdi/digilent-hs1.cfg] +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] +source [find fpga/xilinx-xadc.cfg] +source [find fpga/xilinx-dna.cfg] +adapter speed 25000 + +# example command to write bitstream, soft-cpu bios and runtime: +# openocd -f board/kc705.cfg -c "init;\ +# jtagspi_init 0 bscan_spi_xc7k325t.bit;\ +# jtagspi_program bitstream-kc705.bin 0;\ +# jtagspi_program bios.bin 0xaf0000;\ +# jtagspi_program runtime.fbi 0xb00000;\ +# xc7_program xc7.tap;\ +# exit" diff --git a/openocd-win/openocd/scripts/board/kcu105.cfg b/openocd-win/openocd/scripts/board/kcu105.cfg new file mode 100644 index 0000000..1510a06 --- /dev/null +++ b/openocd-win/openocd/scripts/board/kcu105.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx ultrascale +# http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf + +source [find interface/ftdi/digilent_jtag_smt2_nc.cfg] + +set CHIP XCKU040 +source [find cpld/xilinx-xcu.cfg] + +source [find cpld/jtagspi.cfg] + +adapter speed 25000 diff --git a/openocd-win/openocd/scripts/board/keil_mcb1700.cfg b/openocd-win/openocd/scripts/board/keil_mcb1700.cfg new file mode 100644 index 0000000..6efbd63 --- /dev/null +++ b/openocd-win/openocd/scripts/board/keil_mcb1700.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Keil MCB1700 eval board +# +# http://www.keil.com/mcb1700/picture.asp +# + +source [find target/lpc17xx.cfg] diff --git a/openocd-win/openocd/scripts/board/keil_mcb2140.cfg b/openocd-win/openocd/scripts/board/keil_mcb2140.cfg new file mode 100644 index 0000000..bb1d10b --- /dev/null +++ b/openocd-win/openocd/scripts/board/keil_mcb2140.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Keil MCB2140 eval board +# +# http://www.keil.com/mcb2140/picture.asp +# + +source [find target/lpc2148.cfg] diff --git a/openocd-win/openocd/scripts/board/kindle2.cfg b/openocd-win/openocd/scripts/board/kindle2.cfg new file mode 100644 index 0000000..8c032cb --- /dev/null +++ b/openocd-win/openocd/scripts/board/kindle2.cfg @@ -0,0 +1,183 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Board configuration file for Amazon Kindle Model No. D00701 and D00801 +# AKA Kindle 2nd generation and Kindle DX +# using a Freescale MCIMX31LDVKN5D i.MX31 processor +# +# Pins at J9 40-Pin FFC-A: +# 1 - GND +# 16 - TRSTB +# 17 - TDI +# 18 - TMS +# 19 - TCK +# 20 - RTCK +# 21 - TDO +# 22 - DE +# 25 - BOOT_MODE4 +# 27 - BOOT_MODE2 + +source [find target/imx31.cfg] +source [find target/imx.cfg] + +$_TARGETNAME configure -event reset-init { kindle2_init } +$_TARGETNAME configure -event reset-start { adapter speed 1000 } + +# 8MiB NOR Flash +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xa0000000 0x800000 2 2 $_TARGETNAME + +# 16kiB internal SRAM +$_TARGETNAME configure -work-area-phys 0x1fffc000 \ + -work-area-size 0x4000 -work-area-backup 0 + +# FIXME: currently SRST is not wired to the system +reset_config trst_only +jtag_ntrst_assert_width 10 +jtag_ntrst_delay 30 + +# this is broken but enabled by default +arm11 memwrite burst disable + +adapter speed 1000 +ftdi tdo_sample_edge falling + +proc kindle2_init {} { + imx3x_reset + kindle2_clock_setup + disable_mmu_and_cache + kindle2_misc_init + kindle2_sdram_init + arm core_state arm +} + +proc kindle2_clock_setup {} { + # CCMR: clock from FPM/CKIL + mww 0x53f80000 0x074b0b7b + # IPU_CONF + mww 0x53fc0000 0x040 + # 398MHz + mww 0x53f80004 0xff871650 + mww 0x53f80010 0x00331c23 +} + +proc kindle2_misc_init { } { + # AIPS1 + mww 0x43f00040 0x0 + mww 0x43f00044 0x0 + mww 0x43f00048 0x0 + mww 0x43f0004c 0x0 + mww 0x43f00050 0x0 + mww 0x43f00000 0x77777777 + mww 0x43f00004 0x77777777 + + # AIPS2 + mww 0x53f00040 0x0 + mww 0x53f00044 0x0 + mww 0x53f00048 0x0 + mww 0x53f0004c 0x0 + mww 0x53f00050 0x0 + mww 0x53f00000 0x77777777 + mww 0x53f00004 0x77777777 + + # Start 16 bit NorFlash Initialization on CS0 + mww 0xb8002000 0x0000cc03 + mww 0xb8002004 0xa0330d01 + mww 0xb8002008 0x00220800 +} + +proc disable_mmu_and_cache {} { + # Mode Supervisor, disable FIQ, IRQ and imprecise data aborts + reg cpsr 0x1d3 + + # flush entire BTAC + arm mcr 15 0 7 5 6 0 + # invalidate instruction and data cache + # MCR CP15, 0, R1, C7, C7, 0 + arm mcr 15 0 7 7 0 + + # clean and invalidate cache + arm mcr 15 0 7 15 0 + + # disable MMU and caches + arm mcr 15 0 1 0 0 0 + + arm mcr 15 0 15 2 4 0 + + # invalidate TLBs + arm mcr 15 0 8 7 0 0 + + # Drain the write buffer + arm mcr 15 0 7 10 4 0 + + # start from AIPS 2GB region + arm mcr 15 0 15 2 4 0x40000015 +} + +proc kindle2_sdram_init {} { + #-------------------------------------------- + # Samsung K4X1G323PC-8GC3 32Mx32 Mobile DDR SDRAM + #-------------------------------------------- + # SDCLK + mww 0x43fac26c 0 + + # CAS + mww 0x43fac270 0 + + # RAS + mww 0x43fac274 0 + + # CS2 (CSD0) + mww 0x43fac27c 0x1000 + + # DQM3 + mww 0x43fac284 0 + + # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2dc) + mww 0x43fac288 0 + mww 0x43fac28c 0 + mww 0x43fac290 0 + mww 0x43fac294 0 + mww 0x43fac298 0 + mww 0x43fac29c 0 + mww 0x43fac2a0 0 + mww 0x43fac2a4 0 + mww 0x43fac2a8 0 + mww 0x43fac2ac 0 + mww 0x43fac2b0 0 + mww 0x43fac2b4 0 + mww 0x43fac2b8 0 + mww 0x43fac2bc 0 + mww 0x43fac2c0 0 + mww 0x43fac2c4 0 + mww 0x43fac2c8 0 + mww 0x43fac2cc 0 + mww 0x43fac2d0 0 + mww 0x43fac2d4 0 + mww 0x43fac2d8 0 + mww 0x43fac2dc 0 + + # ? + mww 0xb8002000 0x00006602 + mww 0xb8002004 0x00000501 + mww 0xb8002008 0x00000000 + + # LPDDR1 Initialization script + mww 0xb8001010 0x00000002 + mww 0xb8001010 0x00000004 + # ESDCFG0: set timing parameters + mww 0xb8001004 0x007fff7f + # ESDCTL0: select Prechare-All mode + mww 0xb8001000 0x92100000 + mww 0x80000f00 0x12344321 + # ESDCTL0: Auto Refresh + mww 0xb8001000 0xa2100000 + mww 0x80000000 0x12344321 + mww 0x80000000 0x12344321 + # ESDCTL0: Load Mode Register + mww 0xb8001000 0xb2100000 + mwb 0x80000033 0xda + mwb 0x81000000 0xff + # ESDCTL0: enable Auto-Refresh + mww 0xb8001000 0x82226080 + mww 0x80000000 0xdeadbeef +} diff --git a/openocd-win/openocd/scripts/board/kontron_sl28.cfg b/openocd-win/openocd/scripts/board/kontron_sl28.cfg new file mode 100644 index 0000000..9816f38 --- /dev/null +++ b/openocd-win/openocd/scripts/board/kontron_sl28.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Kontron SMARC-sAL28 + +transport select jtag +reset_config srst_only srst_nogate + +jtag newtap unknown0 tap -irlen 12 + +set _CPUS 2 +source [find target/ls1028a.cfg] + +source [find tcl/cpld/altera-epm240.cfg] + +adapter speed 2000 diff --git a/openocd-win/openocd/scripts/board/kwikstik.cfg b/openocd-win/openocd/scripts/board/kwikstik.cfg new file mode 100644 index 0000000..ade0c91 --- /dev/null +++ b/openocd-win/openocd/scripts/board/kwikstik.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale KwikStik development board +# + +# +# JLINK interface is onboard +# +source [find interface/jlink.cfg] + +source [find target/k40.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/la_fonera-fon2200.cfg b/openocd-win/openocd/scripts/board/la_fonera-fon2200.cfg new file mode 100644 index 0000000..b0b2966 --- /dev/null +++ b/openocd-win/openocd/scripts/board/la_fonera-fon2200.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/atheros_ar2315.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/lambdaconcept_ecpix-5.cfg b/openocd-win/openocd/scripts/board/lambdaconcept_ecpix-5.cfg new file mode 100644 index 0000000..19b9c1c --- /dev/null +++ b/openocd-win/openocd/scripts/board/lambdaconcept_ecpix-5.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# LambdaConcept ECPIX-5 +# http://docs.lambdaconcept.com/ecpix-5/ +# Currently there are following board variants: +# ECPIX-5 45F - LFE5UM5G-45F +# ECPIX-5 85F - LFE5UM5G-85F +# +# This boards have two JTAG interfaces: +# - CN4, micro USB port connected to FT2232HQ chip: +# ADBUS0 TCK +# ADBUS1 TDI +# ADBUS2 TDO +# ADBUS3 TMS +# BDBUS0 UART_TXD +# BDBUS1 UART_RXD +# This interface should be used with following config: +# interface/ftdi/lambdaconcept_ecpix-5.cfg +# - CN3, 6 pin connector +# See schematics for more details: +# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF +# +# No reset lines are implemented. So it is not possible to remote reset the FPGA +# by using any of this interfaces + +source [find interface/ftdi/lambdaconcept_ecpix-5.cfg] +source [find fpga/lattice_ecp5.cfg] diff --git a/openocd-win/openocd/scripts/board/lemaker_hikey.cfg b/openocd-win/openocd/scripts/board/lemaker_hikey.cfg new file mode 100644 index 0000000..fc04435 --- /dev/null +++ b/openocd-win/openocd/scripts/board/lemaker_hikey.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# board configuration for LeMaker Hikey +# + +# board does not feature anything but JTAG +transport select jtag + +# SRST-only reset configuration +reset_config srst_only srst_push_pull + +source [find target/hi6220.cfg] + +# make sure the default target is the boot core +targets ${_TARGETNAME}0 + +proc core_up { args } { + global _TARGETNAME + + # examine remaining cores + foreach _core $args { + ${_TARGETNAME}$_core arp_examine + } +} diff --git a/openocd-win/openocd/scripts/board/linksys-wag200g.cfg b/openocd-win/openocd/scripts/board/linksys-wag200g.cfg new file mode 100644 index 0000000..26900a7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/linksys-wag200g.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Linksys WAG200G Router +# +# The stock firmware Flash layout is organized as follow: +# +# Start End Device +# 0x90000000 0x90020000 /dev/mtdblock/2 +# 0x90020000 0x900d0000 /dev/mtdblock/1 +# 0x900d0000 0x903a0000 /dev/mtdblock/0 +# 0x903a0000 0x903e0000 /dev/mtdblock/5 +# 0x903e0000 0x903f0000 /dev/mtdblock/3 +# 0x903f0000 0x90400000 /dev/mtdblock/4 + +set partition_list { + adam2 { "Adam2 bootloader" 0x90000000 0x00020000 } + kernel { "Kernel" 0x90020000 0x000b0000 } + rootfs { "Root FS" 0x900d0000 0x002d0000 } + lang { "Minix language part" 0x903a0000 0x00040000 } + config { "Firmware config" 0x903e0000 0x00010000 } + adam2env { "Adam2 environment" 0x903f0000 0x00010000 } +} + +source [find target/ti-ar7.cfg] + +# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e) +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/linksys-wrt54gl.cfg b/openocd-win/openocd/scripts/board/linksys-wrt54gl.cfg new file mode 100644 index 0000000..58dfec3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/linksys-wrt54gl.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Linksys WRT54GL v1.1 +# + +source [find target/bcm5352e.cfg] + +set partition_list { + CFE { Bootloader 0x1c000000 0x00040000 } + firmware { "Kernel+rootfs" 0x1c040000 0x003b0000 } + nvram { "Config space" 0x1c3f0000 0x00010000 } +} + +# External 4MB NOR Flash (Intel TE28F320C3BD90 or similar) +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x1c000000 0x00400000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/linksys_nslu2.cfg b/openocd-win/openocd/scripts/board/linksys_nslu2.cfg new file mode 100644 index 0000000..536f97e --- /dev/null +++ b/openocd-win/openocd/scripts/board/linksys_nslu2.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for the LinkSys (CISCO) NSLU2 board +# It is an Intel XSCALE IXP420 CPU. + +source [find target/ixp42x.cfg] +# The _TARGETNAME is set by the above. + +$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/board/lisa-l.cfg b/openocd-win/openocd/scripts/board/lisa-l.cfg new file mode 100644 index 0000000..1607fb8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/lisa-l.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# the Lost Illusions Serendipitous Autopilot +# http://paparazzi.enac.fr/wiki/Lisa + +# Work-area size (RAM size) = 20kB for STM32F103RB device +set WORKAREASIZE 0x5000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/logicpd_imx27.cfg b/openocd-win/openocd/scripts/board/logicpd_imx27.cfg new file mode 100644 index 0000000..8365d4f --- /dev/null +++ b/openocd-win/openocd/scripts/board/logicpd_imx27.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The LogicPD Eval IMX27 eval board has a single IMX27 chip +source [find target/imx27.cfg] + +# The Logic PD board has a NOR flash on CS0 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME + +# +# FIX ME, Add support to +# +# (A) hard reset the board. +# (B) Initialize the SDRAM on the board +# diff --git a/openocd-win/openocd/scripts/board/lpc1850_spifi_generic.cfg b/openocd-win/openocd/scripts/board/lpc1850_spifi_generic.cfg new file mode 100644 index 0000000..167b624 --- /dev/null +++ b/openocd-win/openocd/scripts/board/lpc1850_spifi_generic.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Generic LPC1850 board w/ SPIFI flash. +# This config file is intended as an example of how to +# use the lpcspifi flash driver, but it should be functional +# for most LPC1850 boards utilizing SPIFI flash. + +set CHIPNAME lpc1850 + +source [find target/lpc1850.cfg] + +#A large working area greatly reduces flash write times +set _WORKAREASIZE 0x4000 + +$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE + +#Configure the flash bank; 0x14000000 is the base address for +#lpc43xx/lpc18xx family micros. +flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3 diff --git a/openocd-win/openocd/scripts/board/lpc4350_spifi_generic.cfg b/openocd-win/openocd/scripts/board/lpc4350_spifi_generic.cfg new file mode 100644 index 0000000..8a017ec --- /dev/null +++ b/openocd-win/openocd/scripts/board/lpc4350_spifi_generic.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Generic LPC4350 board w/ SPIFI flash. +# This config file is intended as an example of how to +# use the lpcspifi flash driver, but it should be functional +# for most LPC4350 boards utilizing SPIFI flash. + +set CHIPNAME lpc4350 + +source [find target/lpc4350.cfg] + +#Configure the flash bank; 0x14000000 is the base address for +#lpc43xx/lpc18xx family micros. +flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4 diff --git a/openocd-win/openocd/scripts/board/lubbock.cfg b/openocd-win/openocd/scripts/board/lubbock.cfg new file mode 100644 index 0000000..e4de385 --- /dev/null +++ b/openocd-win/openocd/scripts/board/lubbock.cfg @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel "Lubbock" Development Board with PXA255 (dbpxa255) +# Obsolete; this was Intel's original PXA255 development system +# Board also had CPU cards for SA1100, PXA210, PXA250, and more. + +source [find target/pxa255.cfg] + +adapter srst delay 250 +jtag_ntrst_delay 250 + +# NOTE: until after pinmux and such are set up, only CS0 is +# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc. + +# CS0, CS1 -- two banks of CFI flash, 32 MBytes each +# each bank is 32-bits wide, two 16-bit chips in parallel +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME + +# CS2 low -- FPGA registers +# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch +$_TARGETNAME configure -work-area-phys 0x0a0f0000 + +$_TARGETNAME configure -event reset-assert-pre \ + "$_TARGETNAME configure -work-area-size 0" + +# Make the hex led display a number, assuming CS2 is set up +# and all digits have been enabled through the FPGA. +proc hexled {u32} { + mww 0x08000010 $u32 +} + +# CS3 -- Ethernet +# CS4 -- SA1111 +# CS5 -- PCMCIA + +# NOTE: system console normally uses the FF UART connector + +proc lubbock_init {target} { + + echo "Initialize PXA255 Lubbock board" + + # (1) pinmux + + # GPSR0..GPSR2 + mww 0x40e00018 0x00008000 + mww 0x40e0001c 0x00FC0382 + mww 0x40e00020 0x0001FFFF + # GPDR0..GPDR2 + mww 0x40e0000c 0x0060A800 + mww 0x40e00010 0x00FF0382 + mww 0x40e00014 0x0001C000 + # GAFR0_[LU]..GAFR2_[LU] + mww 0x40e00054 0x98400000 + mww 0x40e00058 0x00002950 + mww 0x40e0005c 0x000A9558 + mww 0x40e00060 0x0005AAAA + mww 0x40e00064 0xA0000000 + mww 0x40e00068 0x00000002 + + # write PSSR, enable GPIOs + mww 0x40f00000 0x00000020 + + # write LED ctrl register ... ones disable + # high byte, 8 hex leds; low byte, 8 discretes + mwh 0x08000040 0xf0ff + + hexled 0x0000 + + # (2) Address space setup + + # MSC0/MSC1/MSC2 + mww 0x48000008 0x23f223f2 + mww 0x4800000c 0x3ff1a441 + mww 0x48000010 0x7ff97ff1 + # pcmcia/cf + mww 0x48000014 0x00000000 + mww 0x48000028 0x00010504 + mww 0x4800002c 0x00010504 + mww 0x48000030 0x00010504 + mww 0x48000034 0x00010504 + mww 0x48000038 0x00004715 + mww 0x4800003c 0x00004715 + + hexled 0x1111 + + # (3) SDRAM setup + # REVISIT this looks dubious ... no refresh cycles + mww 0x48000004 0x03CA4018 + mww 0x48000004 0x004B4018 + mww 0x48000004 0x000B4018 + mww 0x48000004 0x000BC018 + mww 0x48000000 0x00001AC8 + mww 0x48000000 0x00001AC9 + + mww 0x48000040 0x00000000 + + # FIXME -- setup: + # CLOCKS (and faster JTAG) + # enable icache + + # FIXME SRAM isn't working + # $target configure -work-area-size 0x10000 + + hexled 0x2222 + + flash probe 0 + flash probe 1 + + hexled 0xcafe +} +$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/board/marsohod.cfg b/openocd-win/openocd/scripts/board/marsohod.cfg new file mode 100644 index 0000000..2be8391 --- /dev/null +++ b/openocd-win/openocd/scripts/board/marsohod.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Marsohod CPLD Development and Education board +# +# http://marsohod.org/howtostart/plata +# + +# Recommended MBFTDI programmer +source [find interface/ftdi/mbftdi.cfg] +adapter speed 2000 +transport select jtag + +# Altera MAXII EPM240T100C CPLD +source [find cpld/altera-epm240.cfg] diff --git a/openocd-win/openocd/scripts/board/marsohod2.cfg b/openocd-win/openocd/scripts/board/marsohod2.cfg new file mode 100644 index 0000000..9575100 --- /dev/null +++ b/openocd-win/openocd/scripts/board/marsohod2.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Marsohod2 FPGA Development and Education board +# +# http://www.marsohod.org/prodmarsohod2 +# + +# Built-in MBFTDI programmer +source [find interface/ftdi/mbftdi.cfg] +adapter speed 2000 +transport select jtag + +# Cyclone III EP3C10E144 FPGA +source [find fpga/altera-ep3c10.cfg] diff --git a/openocd-win/openocd/scripts/board/marsohod3.cfg b/openocd-win/openocd/scripts/board/marsohod3.cfg new file mode 100644 index 0000000..b4f2d30 --- /dev/null +++ b/openocd-win/openocd/scripts/board/marsohod3.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Marsohod3 FPGA Development and Education board +# +# http://www.marsohod.org/plata-marsokhod3 +# + +# Built-in MBFTDI programmer +source [find interface/ftdi/mbftdi.cfg] +adapter speed 2000 +transport select jtag + +# MAX10 10M50SAE144C8GES FPGA +source [find fpga/altera-10m50.cfg] diff --git a/openocd-win/openocd/scripts/board/mbed-lpc11u24.cfg b/openocd-win/openocd/scripts/board/mbed-lpc11u24.cfg new file mode 100644 index 0000000..9f5be88 --- /dev/null +++ b/openocd-win/openocd/scripts/board/mbed-lpc11u24.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an mbed eval board with a single NXP LPC11U24 chip. +# http://mbed.org/handbook/mbed-NXP-LPC11U24 +# + +source [find interface/cmsis-dap.cfg] + +# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM +set WORKAREASIZE 0x2000 + +source [find target/lpc11xx.cfg] diff --git a/openocd-win/openocd/scripts/board/mbed-lpc1768.cfg b/openocd-win/openocd/scripts/board/mbed-lpc1768.cfg new file mode 100644 index 0000000..62b0911 --- /dev/null +++ b/openocd-win/openocd/scripts/board/mbed-lpc1768.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an mbed eval board with a single NXP LPC1768 chip. +# http://mbed.org/handbook/mbed-NXP-LPC1768 +# + +source [find interface/cmsis-dap.cfg] + +source [find target/lpc17xx.cfg] diff --git a/openocd-win/openocd/scripts/board/mcb1700.cfg b/openocd-win/openocd/scripts/board/mcb1700.cfg new file mode 100644 index 0000000..8ab6e88 --- /dev/null +++ b/openocd-win/openocd/scripts/board/mcb1700.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Keil MCB1700 PCB with 1768 +# +# Reset init script sets it to 100MHz +set CCLK 100000 + +source [find target/lpc17xx.cfg] + +global MCB1700_CCLK +set MCB1700_CCLK $CCLK + +$_TARGETNAME configure -event reset-start { + # Start *real slow* as we do not know the + # state the boot rom left the clock in + adapter speed 10 +} + +# Set up 100MHz clock to CPU +$_TARGETNAME configure -event reset-init { + # PLL0CON: Disable PLL + mww 0x400FC080 0x00000000 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # CCLK=PLL/4 (=100 MHz) + mww 0x400FC104 0x00000003 + # CLKSRCSEL: Clock source = internal RC oscillator + mww 0x400FC10C 0x00000000 + + # PLL0CFG: M=50,N=1 -> PLL=400 MHz + mww 0x400FC084 0x00000031 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # PLL0CON: Enable PLL + mww 0x400FC080 0x00000001 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + sleep 50 + + # PLL0CON: Connect PLL + mww 0x400FC080 0x00000003 + # PLLFEED + mww 0x400FC08C 0x000000AA + # PLLFEED + mww 0x400FC08C 0x00000055 + + # Dividing CPU clock by 8 should be pretty conservative + # + # + global MCB1700_CCLK + adapter speed [expr {$MCB1700_CCLK / 8}] + + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + + mww 0x400FC040 0x01 +} diff --git a/openocd-win/openocd/scripts/board/microchip_explorer16.cfg b/openocd-win/openocd/scripts/board/microchip_explorer16.cfg new file mode 100644 index 0000000..6b528d6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/microchip_explorer16.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Microchip Explorer 16 with PIC32MX360F512L PIM module. +# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858 + +# TAPID for PIC32MX360F512L +set CPUTAPID 0x30938053 + +# use 32k working area +set WORKAREASIZE 32768 + +source [find target/pic32mx.cfg] diff --git a/openocd-win/openocd/scripts/board/microchip_sama5d27_som1_kit1.cfg b/openocd-win/openocd/scripts/board/microchip_sama5d27_som1_kit1.cfg new file mode 100644 index 0000000..8e92040 --- /dev/null +++ b/openocd-win/openocd/scripts/board/microchip_sama5d27_som1_kit1.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Microchip SAMA5D27-SOM1-EK1 +# https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMA5D27-SOM1-EK1 +# This board provide two jtag interfaces: +# J11 - 10 pin interface +# J10 - USB interface connected to the J-Link-OB. +# This functionality is implemented with an ATSAM3U4C microcontroller and +# provides JTAG functions and a bridge USB/Serial debug port (CDC). +# +# Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality. +# - Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional. +# - Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG +# controller can be used through the 10-pin JTAG port J11. + +source [find interface/jlink.cfg] +reset_config srst_only + +source [find target/at91sama5d2.cfg] diff --git a/openocd-win/openocd/scripts/board/microchip_same51_curiosity_nano.cfg b/openocd-win/openocd/scripts/board/microchip_same51_curiosity_nano.cfg new file mode 100644 index 0000000..32e2885 --- /dev/null +++ b/openocd-win/openocd/scripts/board/microchip_same51_curiosity_nano.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Microchip SAME51 Curiosity Nano evaluation kit. +# +# https://www.microchip.com/en-us/development-tool/EV76S68A +# + +source [find interface/cmsis-dap.cfg] + +set CHIPNAME same51 + +source [find target/atsame5x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/microchip_same54_xplained_pro.cfg b/openocd-win/openocd/scripts/board/microchip_same54_xplained_pro.cfg new file mode 100644 index 0000000..3588165 --- /dev/null +++ b/openocd-win/openocd/scripts/board/microchip_same54_xplained_pro.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Microchip (former Atmel) SAM E54 Xplained Pro evaluation kit. +# http://www.microchip.com/developmenttools/productdetails.aspx?partno=atsame54-xpro +# + +source [find interface/cmsis-dap.cfg] + +set CHIPNAME same54 + +source [find target/atsame5x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/microchip_saml11_xplained_pro.cfg b/openocd-win/openocd/scripts/board/microchip_saml11_xplained_pro.cfg new file mode 100644 index 0000000..c2fcd65 --- /dev/null +++ b/openocd-win/openocd/scripts/board/microchip_saml11_xplained_pro.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Microchip (formerly Atmel) SAM L11 Xplained Pro Evaluation Kit. +# https://www.microchip.com/DevelopmentTools/ProductDetails/dm320205 +# + +source [find interface/cmsis-dap.cfg] +adapter speed 1000 + +set CHIPNAME saml11 +source [find target/atsaml1x.cfg] diff --git a/openocd-win/openocd/scripts/board/mini2440.cfg b/openocd-win/openocd/scripts/board/mini2440.cfg new file mode 100644 index 0000000..85d9a35 --- /dev/null +++ b/openocd-win/openocd/scripts/board/mini2440.cfg @@ -0,0 +1,321 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#------------------------------------------------------------------------- +# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R +# NOTE: Configured for NAND boot (switch S2 in NANDBOOT) +# 64 MB NAND (Samsung K9D1208V0M) +# B Findlay 08/09 +# +# ----------- Important notes to help you on your way ---------- +# README: +# NOR/NAND Boot Switch - I have not read the vivi source, but from +# what I could tell from reading the registers it appears that vivi +# loads itself into DRAM and then flips NFCONT (0x4E000004) bits +# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND +# FLASH at the bottom 64MB of memory. This essentially takes the +# NOR Flash out of the circuit so you can't trash it. +# +# I adapted the samsung_s3c2440.cfg file which is why I did not +# include "source [find target/samsung_s3c2440.cfg]". I believe +# the -work-area-phys 0x200000 is incorrect, but also had to pad +# some additional resets. I didn't modify it as if it is working +# for someone, the work-area-phys is not used by most. +# +# JTAG ADAPTER SPECIFIC +# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely +# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist. +# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is +# necessary to FORCE setting the clock. Normally this should be configured +# in the openocd.cfg file, but was placed here as it can be a tough +# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified +# the openOCD driver jlink.c and posted it here. It may eventually end +# up changed in openOCD, but its a hack in the driver and really should +# be in the jtag layer (core.c me thinks), but haven't done it yet. My +# hack for jlink.c may be found here. +# +# http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135 +# +# Note: Also if you have a USB JTAG, you will need the USB library installed +# on your system "libusb-dev" or the make of openocd will fail. I *think* +# it's apt-get install libusb-dev. When I made my config I only included +# --enable-jlink and --enable-usbdevs +# +# I HAVE NOT Tested this thoroughly, so there could still be problems. +# But it should get you way ahead of the game from where I started. +# If you find problems (and fixes) please post them to +# openocd-development@lists.berlios.de and join the developers and +# check in fixes to this and anything else you find. I do not +# provide support, but if you ask really nice and I see anything +# obvious I will tell you.. mostly just dig, fix, and submit to openocd. +# +# best! brfindla@yahoo.com Nashua, NH USA +# +# Recommended resources: +# - first two are the best Mini2440 resources anywhere +# - maintained by buserror... thanks guy! +# +# http://bliterness.blogspot.com/ +# http://code.google.com/p/mini2440/ +# +# others.... +# +# http://forum.sparkfun.com/viewforum.php?f=18 +# http://labs.kernelconcepts.de/Publications/Micro24401/ +# http://www.friendlyarm.net/home +# http://www.amontec.com/jtag_pinout.shtml +# +#------------------------------------------------------------------------- +# +# +# Your openocd.cfg file should contain: +# source [find interface/<yourjtag>.cfg] +# source [find board/mini2440.cfg] +# +# +# + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + +#------------------------------------------------------------------------- +# Target configuration for the Samsung 2440 system on chip +# Tested on a S3C2440 Evaluation board by keesj +# Processor : ARM920Tid(wb) rev 0 (v4l) +# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d +# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) +#------------------------------------------------------------------------- + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2440 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0032409d +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1 + +#reset configuration +adapter srst delay 100 +jtag_ntrst_delay 100 +reset_config trst_and_srst + +#------------------------------------------------------------------------- +# JTAG ADAPTER SPECIFIC +# IMPORTANT! See README at top of this file. +#------------------------------------------------------------------------- + + adapter speed 12000 + +#------------------------------------------------------------------------- +# GDB Setup +#------------------------------------------------------------------------- + + gdb_breakpoint_override hard + +#------------------------------------------------ +# ARM SPECIFIC +#------------------------------------------------ + + targets + # arm7_9 dcc_downloads enable + # arm7_9 fast_memory_access enable + + + nand device s3c2440 0 + + adapter srst delay 100 + jtag_ntrst_delay 100 + reset_config trst_and_srst + init + + echo " " + echo "-------------------------------------------" + echo "--- login with - telnet localhost 4444 ---" + echo "--- then type help_2440 ---" + echo "-------------------------------------------" + echo " " + + + +#------------------------------------------------ +# Processor Initialialization +# Note: Processor writes can only occur when +# the state is in SYSTEM. When you call init_2440 +# one of the first lines will tell you what state +# you are in. If a linux image is booting +# when you run this, it will not work +# a vivi boot loader will run with this just +# fine. The reg values were obtained by a combination +# of figuring them out fromt the manual, and looking +# at post vivi values with the debugger. Don't +# place too much faith in them, but seem to work. +#------------------------------------------------ + +proc init_2440 { } { + + halt + s3c2440.cpu curstate + + #----------------------------------------------- + # Set Processor Clocks - mini2440 xtal=12mHz + # we set main clock for 405mHZ + # we set the USB Clock for 48mHz + # OM2 OM3 pulled to ground so main clock and + # usb clock are off 12mHz xtal + #----------------------------------------------- + + mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg + mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register + mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg + mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg + + #----------------------------------------------- + # Configure Memory controller + # BWSCON configures all banks, NAND, NOR, DRAM + # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 + #----------------------------------------------- + + mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width + mww phys 0x48000010 0x00001112 ;# BANKCON4 - ? + mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM + mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM + mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM + mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM + mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM + mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM + + #----------------------------------------------- + # Now port configuration for enables for memory + # and other stuff. + #----------------------------------------------- + + mww phys 0x56000000 0x007FFFFF ;# GPACON + + mww phys 0x56000010 0x00295559 ;# GPBCON + mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE) + mww phys 0x56000014 0x000007C2 ;# GPBDAT + + mww phys 0x56000020 0xAAAAA6AA ;# GPCCON + mww phys 0x56000028 0x0000FFFF ;# GPCUP + mww phys 0x56000024 0x00000020 ;# GPCDAT + + mww phys 0x56000030 0xAAAAAAAA ;# GPDCON + mww phys 0x56000038 0x0000FFFF ;# GPDUP + + mww phys 0x56000040 0xAAAAAAAA ;# GPECON + mww phys 0x56000048 0x0000FFFF ;# GPEUP + + mww phys 0x56000050 0x00001555 ;# GPFCON + mww phys 0x56000058 0x0000007F ;# GPFUP + mww phys 0x56000054 0x00000000 ;# GPFDAT + + mww phys 0x56000060 0x00150114 ;# GPGCON + mww phys 0x56000068 0x0000007F ;# GPGUP + + mww phys 0x56000070 0x0015AAAA ;# GPHCON + mww phys 0x56000078 0x000003FF ;# GPGUP + +} + + + +proc flash_config { } { + + #----------------------------------------- + # Finish Flash Configuration + #----------------------------------------- + + halt + + #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen) + nand probe 0 + nand list +} + +proc flash_uboot { } { + + # flash the u-Boot binary and reboot into it + init_2440 + flash_config + nand erase 0 0x0 0x40000 + nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw + resume +} + + +proc load_uboot { } { + echo " " + echo " " + echo "----------------------------------------------------------" + echo "---- Load U-Boot into RAM and execute it. ---" + echo "---- NOTE: loads, partially runs, and hangs ---" + echo "---- U-Boot is fine, this image runs from vivi. ---" + echo "---- I burned u-boot into NAND so I didn't finish ---" + echo "---- debugging it. I am leaving this here as it is ---" + echo "---- part of the way there if you want to fix it. ---" + echo "---- ---" + echo "---- mini2440 U-boot here: ---" + echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---" + echo "---- Also this: ---" + echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --" + echo "----------------------------------------------------------" + + init_2440 + echo "Loading /tftpboot/u-boot-nand512.bin" + load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin + echo "Verifying image...." + verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin + echo "jumping to u-boot" + #bp 0x33f80068 4 hw + reg 0 0 + reg 1 0 + reg 2 0 + reg 3 0 + reg 4 0x33f80000 + resume 0x33f80000 +} + + # this may help a little bit debugging the load_uboot +proc s {} { + step + reg + arm disassemble 0x33F80068 0x10 +} + +proc help_2440 {} { + echo " " + echo " " + echo "-----------------------------------------------------------" + echo "---- The following mini2440 funcs are supported ----" + echo "---- init_2440 - initialize clocks, DRAM, IO ----" + echo "---- flash_config - configures nand flash ----" + echo "---- load_uboot - loads uboot into ram ----" + echo "---- flash_uboot - flashes uboot to nand (untested) ----" + echo "---- help_2440 - this help display ----" + echo "-----------------------------------------------------------" + echo " " + echo " " +} + + +#---------------------------------------------------------------------------- +#----------------------------------- END ------------------------------------ +#---------------------------------------------------------------------------- diff --git a/openocd-win/openocd/scripts/board/mini6410.cfg b/openocd-win/openocd/scripts/board/mini6410.cfg new file mode 100644 index 0000000..18f9e8d --- /dev/null +++ b/openocd-win/openocd/scripts/board/mini6410.cfg @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the Samsung s3c6410 system on chip +# Tested on a tiny6410 +# Processor : ARM1176 +# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2) +# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0) + +source [find target/samsung_s3c6410.cfg] + +proc init_6410 {} { + halt + reg cpsr 0x1D3 + arm mcr 15 0 15 2 4 0x70000013 + + #----------------------------------------------- + # Clock and Timer Setting + #----------------------------------------------- + mww 0x7e004000 0 ;# WATCHDOG - Disable + mww 0x7E00F120 0x0003 ;# MEM_SYS_CFG - CS0:8 bit, Mem1:32bit, CS2=NAND + #mww 0x7E00F120 0x1000 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=SROMC + #mww 0x7E00F120 0x1002 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=OND + mww 0x7E00F900 0x805e ;# OTHERS - Change SYNCMUX[6] to “1” + sleep 1000 + mww 0x7E00F900 0x80de ;# OTHERS - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify) + sleep 1000 ;# - Others[11:8] to 0xF + mww 0x7E00F000 0xffff ;# APLL_LOCK - APLL LockTime + mww 0x7E00F004 0xffff ;# MPLL_LOCK - MPLL LockTime + mww 0x7E00F020 0x1047310 ;# CLK_DIV0 - ARMCLK:HCLK:PCLK = 1:4:16 + mww 0x7E00F00c 0x81900302 ;# APLL_CON - A:400, P:3, S:2 => 400MHz + mww 0x7E00F010 0x81900303 ;# MPLL_CON - M:400, P:3, S:3 => 200MHz + mww 0x7E00F01c 0x3 ;# CLK_SRC - APLL,MPLL Clock Select + + #----------------------------------------------- + # DRAM initialization + #----------------------------------------------- + mww 0x7e001004 0x4 ;# P1MEMCCMD - Enter the config state + mww 0x7e001010 0x30C ;# P1REFRESH - Refresh Period register (7800ns), 100MHz +# mww 0x7e001010 0x40e ;# P1REFRESH - Refresh Period register (7800ns), 133MHz + mww 0x7e001014 0x6 ;# P1CASLAT - CAS Latency = 3 + mww 0x7e001018 0x1 ;# P1T_DQSS + mww 0x7e00101c 0x2 ;# P1T_MRD + mww 0x7e001020 0x7 ;# P1T_RAS - 45 ns + mww 0x7e001024 0xA ;# P1T_RC - 67.5 ns + mww 0x7e001028 0xC ;# P1T_RCD - 22.5 ns + mww 0x7e00102C 0x10B ;# P1T_RFC - 80 ns + mww 0x7e001030 0xC ;# P1T_RP - 22.5 ns + mww 0x7e001034 0x3 ;# P1T_RRD - 15 ns + mww 0x7e001038 0x3 ;# P1T_WR - 15 ns + mww 0x7e00103C 0x2 ;# P1T_WTR + mww 0x7e001040 0x2 ;# P1T_XP + mww 0x7e001044 0x11 ;# P1T_XSR - 120 ns + mww 0x7e001048 0x11 ;# P1T_ESR + + #----------------------------------------------- + # Memory Configuration Registers + #----------------------------------------------- + mww 0x7e00100C 0x00010012 ;# P1MEMCFG - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit + mww 0x7e00104C 0x0B41 ;# P1MEMCFG2 - Read delay 1 Cycle, mDDR, 32bit, Sync. + mww 0x7e001200 0x150F0 ;# CHIP_N_CFG - 0x150F0 for 256M, 0x150F8 for 128M + + #----------------------------------------------- + # Memory Direct Commands + #----------------------------------------------- + mww 0x7e001008 0xc0000 ;# Chip0 Direct Command :NOP5 + mww 0x7e001008 0x0 ;# Chip0 Direct Command :PreCharge al + mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh + mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh + mww 0x7e001008 0xA0000 ;# EMRS, DS:Full, PASR:Full + mww 0x7e001008 0x80032 ;# MRS, CAS3, BL4 + mww 0x7e001004 0x0 ;# Enable DMC1 +} + +proc install_6410_uboot {} { + # write U-boot magic number + mww 0x50000000 0x24564236 + mww 0x50000004 0x20764316 + load_image u-boot_nand-ram256.bin 0x50008000 bin + load_image u-boot_nand-ram256.bin 0x57E00000 bin + + #Kick in + reg pc 0x57E00000 + resume +} + +proc init_6410_flash {} { + halt + nand probe 0 + nand list +} + + +adapter speed 1000 +adapter srst delay 100 +jtag_ntrst_delay 100 +reset_config trst_and_srst + +gdb_breakpoint_override hard + +targets +nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu + +init +echo " " +echo " " +echo "-------------------------------------------------------------------" +echo "---- The following mini6410/tiny6410 functions are available: ----" +echo "---- init_6410 - initialize clock, timer, DRAM ----" +echo "---- init_6410_flash - initializes NAND flash support ----" +echo "---- install_6410_uboot - copies u-boot image into RAM and ----" +echo "---- runs it ----" +echo "-------------------------------------------------------------------" +echo " " +echo " " diff --git a/openocd-win/openocd/scripts/board/minispartan6.cfg b/openocd-win/openocd/scripts/board/minispartan6.cfg new file mode 100644 index 0000000..011cc54 --- /dev/null +++ b/openocd-win/openocd/scripts/board/minispartan6.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://www.scarabhardware.com/minispartan6/ + +source [find interface/ftdi/minispartan6.cfg] +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] + +# example command to read the device dna of the FPGA on the board; +# openocd -f board/minispartan6.cfg -c "init;xc6s_print_dna xc6s.tap;shutdown" + +# example command to write bitstream +# openocd -f board/minispartan6.cfg -c "init;\ +# jtagspi_init 0 bscan_spi_xc6slx??.bit;\ +# jtagspi_program bitstream.bin 0;\ +# xc6s_program xc6s.tap;\ +# shutdown" +# +# jtagspi flash procies can be found in the contrib/loaders/flash/fpga/ +# directory, with prebuilt versions available at +# https://github.com/jordens/bscan_spi_bitstreams +# +# For the SLX25 variant, use +# - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx25.bit +# For the SLX9 variant, use +# - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx9.bit diff --git a/openocd-win/openocd/scripts/board/nds32_corvettef1.cfg b/openocd-win/openocd/scripts/board/nds32_corvettef1.cfg new file mode 100644 index 0000000..7300ce0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nds32_corvettef1.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# ADP-Corvette-F1 R1.0 +# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r1/ +# ADP-Corvette-F1 R2.0 +# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/ + +adapter speed 10000 + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +reset_config srst_only + +source [find target/nds32v5.cfg] diff --git a/openocd-win/openocd/scripts/board/nds32_xc7.cfg b/openocd-win/openocd/scripts/board/nds32_xc7.cfg new file mode 100644 index 0000000..82c00ac --- /dev/null +++ b/openocd-win/openocd/scripts/board/nds32_xc7.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# ADP-XC7K160/410 +# http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ + +source [find target/nds32v5.cfg] diff --git a/openocd-win/openocd/scripts/board/netgear-dg834v3.cfg b/openocd-win/openocd/scripts/board/netgear-dg834v3.cfg new file mode 100644 index 0000000..a993888 --- /dev/null +++ b/openocd-win/openocd/scripts/board/netgear-dg834v3.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Netgear DG834v3 Router +# Internal 4Kb RAM (@0x80000000) +# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1) +# + +set partition_list { + loader { "Bootloader (ADAM2)" 0x90000000 0x00020000 } + firmware { "Kernel+rootfs" 0x90020000 0x003d0000 } + config { "Bootloader config space" 0x903f0000 0x00010000 } +} + +source [find target/ti-ar7.cfg] + +# External 16MB SDRAM - disabled as we use internal sram +#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000 + +# External 4MB NOR Flash +set _FLASHNAME $_CHIPNAME.norflash +flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/netgear-wg102.cfg b/openocd-win/openocd/scripts/board/netgear-wg102.cfg new file mode 100644 index 0000000..15f9c11 --- /dev/null +++ b/openocd-win/openocd/scripts/board/netgear-wg102.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/atheros_ar2313.cfg] + +reset_config trst_and_srst + +$_TARGETNAME configure -event reset-init { + mips32 cp0 12 0 0x10400000 + + # configure sdram controller + mww 0xb8300004 0x0e03 + sleep 100 + mww 0xb8300004 0x0e01 + mww 0xb8300008 0x10 + sleep 500 + mww 0xb8300004 0x0e02 + + mww 0xb8300000 0x6c0088 + mww 0xb8300008 0x57e + mww 0xb8300004 0x0e00 + mww 0xb8300004 0xb00 + + # configure flash + # 0x00000001 - 0x01 << FLASHCTL_IDCY_S + # 0x000000e0 - 0x07 << FLASHCTL_WST1_S + # FLASHCTL_RBLE 0x00000400 - Read byte lane enable + # 0x00003800 - 0x07 << FLASHCTL_WST2_S + # FLASHCTL_AC_8M 0x00060000 - Size of flash + # FLASHCTL_E 0x00080000 - Flash bank enable (added) + # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode wont work!! + # FLASHCTL_MWx16 0x10000000 - 16bit mode. Do not use it!! + # FLASHCTL_MWx8 0x00000000 - 8bit mode. + mww 0xb8400000 0x000d3ce1 +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xbe000000 0x00400000 1 1 $_TARGETNAME x16_as_x8 diff --git a/openocd-win/openocd/scripts/board/nordic_nrf51822_mkit.cfg b/openocd-win/openocd/scripts/board/nordic_nrf51822_mkit.cfg new file mode 100644 index 0000000..266d710 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nordic_nrf51822_mkit.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT) +# + +source [find interface/cmsis-dap.cfg] +source [find target/nrf51.cfg] diff --git a/openocd-win/openocd/scripts/board/nordic_nrf51_dk.cfg b/openocd-win/openocd/scripts/board/nordic_nrf51_dk.cfg new file mode 100644 index 0000000..7ddae2d --- /dev/null +++ b/openocd-win/openocd/scripts/board/nordic_nrf51_dk.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor NRF51 Development Kit (nRF6824) +# + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/nrf51.cfg] diff --git a/openocd-win/openocd/scripts/board/nordic_nrf52_dk.cfg b/openocd-win/openocd/scripts/board/nordic_nrf52_dk.cfg new file mode 100644 index 0000000..7366bf9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nordic_nrf52_dk.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic Semiconductor NRF52 Development Kit (nRF52832) +# + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/nrf52.cfg] diff --git a/openocd-win/openocd/scripts/board/nordic_nrf52_ftx232.cfg b/openocd-win/openocd/scripts/board/nordic_nrf52_ftx232.cfg new file mode 100644 index 0000000..c3c69a8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nordic_nrf52_ftx232.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# nordic module NRF52 (nRF52832/52840) attached to an adafruit ft232h module +# or any FT232H/FT2232H/FT4232H based board/module +# + +source [find interface/ftdi/ft232h-module-swd.cfg] +#source [find interface/ftdi/minimodule-swd.cfg] + +transport select swd + +source [find target/nrf52.cfg] diff --git a/openocd-win/openocd/scripts/board/novena-internal-fpga.cfg b/openocd-win/openocd/scripts/board/novena-internal-fpga.cfg new file mode 100644 index 0000000..c36938c --- /dev/null +++ b/openocd-win/openocd/scripts/board/novena-internal-fpga.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Novena open hardware and F/OSS-friendly computing platform +# +# Design documentation: +# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source +# +# +-------------+--------------+------+-------+---------+ +# | Pad name | Schematic | GPIO | sysfs | JTAG | +# +-------------+--------------+------+-------+---------+ +# | DISP0_DAT13 | FPGA_RESET_N | 5-07 | 135 | RESET_N | +# | DISP0_DAT14 | FPGA_TCK | 5-08 | 136 | TCK | +# | DISP0_DAT15 | FPGA_TDI | 5-09 | 137 | TDI | +# | DISP0_DAT16 | FPGA_TDO | 5-10 | 138 | TDO | +# | DISP0_DAT17 | FPGA_TMS | 5-11 | 139 | TMS | +# +-------------+--------------+------+-------+---------+ + +adapter driver sysfsgpio + +transport select jtag + +# TCK TMS TDI TDO +sysfsgpio jtag_nums 136 139 137 138 + +source [find cpld/xilinx-xc6s.cfg] diff --git a/openocd-win/openocd/scripts/board/npcx_evb.cfg b/openocd-win/openocd/scripts/board/npcx_evb.cfg new file mode 100644 index 0000000..4f28bc9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/npcx_evb.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Nuvoton NPCX Evaluation Board + +source [find interface/jlink.cfg] +transport select swd + +source [find target/npcx.cfg] diff --git a/openocd-win/openocd/scripts/board/numato_mimas_a7.cfg b/openocd-win/openocd/scripts/board/numato_mimas_a7.cfg new file mode 100644 index 0000000..82d6a56 --- /dev/null +++ b/openocd-win/openocd/scripts/board/numato_mimas_a7.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Numato Mimas A7 - Artix 7 FPGA Board +# +# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet +# +# Note: Connect external DC power supply if programming a heavy design onto FPGA. +# Programming while powering via USB may lead to programming failure. +# Therefore, prefer external power supply. + +adapter driver ftdi +ftdi device_desc "Mimas Artix 7 FPGA Module" +ftdi vid_pid 0x2a19 0x1009 + +# channel 0 is for custom purpose by users (like uart, fifo etc) +# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers) +ftdi channel 1 +ftdi tdo_sample_edge falling + + +# FTDI Pin Layout +# +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# | DBUS7 | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 | +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# | PROG_B | OE_N | NC | NC | TMS | TDO | TDI | TCK | +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# +# OE_N is JTAG buffer output enable signal (active-low) +# PROG_B is not used, so left as input to FTDI. +# +ftdi layout_init 0x0008 0x004b +reset_config none +adapter speed 30000 + +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] diff --git a/openocd-win/openocd/scripts/board/numato_opsis.cfg b/openocd-win/openocd/scripts/board/numato_opsis.cfg new file mode 100644 index 0000000..ea07ff3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/numato_opsis.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://opsis.hdmi2usb.tv +# +# The Numato Opsis is an FPGA based, open video platform. +# +# The board is supported via ixo-usb-jtag project. See the +# interface/usb-jtag.cfg for more information. + +source [find interface/usb-jtag.cfg] +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] diff --git a/openocd-win/openocd/scripts/board/nxp_frdm-k64f.cfg b/openocd-win/openocd/scripts/board/nxp_frdm-k64f.cfg new file mode 100644 index 0000000..1581c95 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_frdm-k64f.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an NXP Freedom eval board with a single MK64FN1M0VLL12 chip. +# https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F +# + +source [find interface/cmsis-dap.cfg] + +# Set working area to 16 KiB +set WORKAREASIZE 0x4000 + +set CHIPNAME k64f +reset_config srst_only + +source [find target/kx.cfg] diff --git a/openocd-win/openocd/scripts/board/nxp_frdm-ls1012a.cfg b/openocd-win/openocd/scripts/board/nxp_frdm-ls1012a.cfg new file mode 100644 index 0000000..17a50c9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_frdm-ls1012a.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP FRDM-LS1012A (Freedom) +# + +# +# NXP Kinetis K20 +# +source [find interface/cmsis-dap.cfg] +transport select jtag + +# Also offers a 10-pin 0.05" CoreSight JTAG connector. + +source [find target/ls1012a.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/nxp_imx7sabre.cfg b/openocd-win/openocd/scripts/board/nxp_imx7sabre.cfg new file mode 100644 index 0000000..9b0c743 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_imx7sabre.cfg @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP IMX7SABRE board +# use on-board JTAG header +transport select jtag + +# set a safe speed, can be overridden +adapter speed 1000 + +# reset configuration has TRST and SRST support +reset_config trst_and_srst srst_push_pull +# need at least 100ms delay after SRST release for JTAG +adapter srst delay 100 + +# source the target file +source [find target/imx7.cfg] +# import mrw proc +source [find mem_helper.tcl] + +# function to disable the on-chip watchdog +proc imx7_disable_wdog { } { + # echo "disable watchdog power-down counter" + mwh phys 0x30280008 0x00 +} + +proc imx7_uart_dbgconf { } { + # disable response to debug_req signal for uart1 + mww phys 0x308600b4 0x0a60 +} + +proc check_bits_set_32 { addr mask } { + while { [expr {[mrw $addr] & $mask} == 0] } { } +} + +proc apply_dcd { } { + # echo "apply dcd" + + mww phys 0x30340004 0x4F400005 + # Clear then set bit30 to ensure exit from DDR retention + mww phys 0x30360388 0x40000000 + mww phys 0x30360384 0x40000000 + + mww phys 0x30391000 0x00000002 + mww phys 0x307a0000 0x01040001 + mww phys 0x307a01a0 0x80400003 + mww phys 0x307a01a4 0x00100020 + mww phys 0x307a01a8 0x80100004 + mww phys 0x307a0064 0x00400046 + mww phys 0x307a0490 0x00000001 + mww phys 0x307a00d0 0x00020083 + mww phys 0x307a00d4 0x00690000 + mww phys 0x307a00dc 0x09300004 + mww phys 0x307a00e0 0x04080000 + mww phys 0x307a00e4 0x00100004 + mww phys 0x307a00f4 0x0000033f + mww phys 0x307a0100 0x09081109 + mww phys 0x307a0104 0x0007020d + mww phys 0x307a0108 0x03040407 + mww phys 0x307a010c 0x00002006 + mww phys 0x307a0110 0x04020205 + mww phys 0x307a0114 0x03030202 + mww phys 0x307a0120 0x00000803 + mww phys 0x307a0180 0x00800020 + mww phys 0x307a0184 0x02000100 + mww phys 0x307a0190 0x02098204 + mww phys 0x307a0194 0x00030303 + mww phys 0x307a0200 0x00000016 + mww phys 0x307a0204 0x00171717 + mww phys 0x307a0214 0x04040404 + mww phys 0x307a0218 0x0f040404 + mww phys 0x307a0240 0x06000604 + mww phys 0x307a0244 0x00000001 + mww phys 0x30391000 0x00000000 + mww phys 0x30790000 0x17420f40 + mww phys 0x30790004 0x10210100 + mww phys 0x30790010 0x00060807 + mww phys 0x307900b0 0x1010007e + mww phys 0x3079009c 0x00000d6e + mww phys 0x30790020 0x08080808 + mww phys 0x30790030 0x08080808 + mww phys 0x30790050 0x01000010 + mww phys 0x30790050 0x00000010 + + mww phys 0x307900c0 0x0e407304 + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e447306 + + check_bits_set_32 0x307900c4 0x1 + + mww phys 0x307900c0 0x0e447304 + mww phys 0x307900c0 0x0e407304 + + + mww phys 0x30384130 0x00000000 + mww phys 0x30340020 0x00000178 + mww phys 0x30384130 0x00000002 + mww phys 0x30790018 0x0000000f + + check_bits_set_32 0x307a0004 0x1 +} + +# disable internal reset-assert handling to +# allow reset-init to work +$_TARGETNAME.0 configure -event reset-assert "" +$_TARGETNAME.1 configure -event reset-assert "" +$_TARGETNAME_2 configure -event reset-assert "" + +$_TARGETNAME.0 configure -event reset-init { + global _CHIPNAME + imx7_disable_wdog + imx7_uart_dbgconf + apply_dcd + $_CHIPNAME.dap memaccess 0 +} + +target smp $_TARGETNAME.0 $_TARGETNAME.1 diff --git a/openocd-win/openocd/scripts/board/nxp_lpc-link2.cfg b/openocd-win/openocd/scripts/board/nxp_lpc-link2.cfg new file mode 100644 index 0000000..52f13fa --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_lpc-link2.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP LPC-Link2 +# +# http://www.nxp.com/board/OM13054.html +# https://www.lpcware.com/lpclink2 +# http://embeddedartists.com/products/lpcxpresso/lpclink2.php +# + +source [find target/lpc4370.cfg] + +# W25Q80BVSSIG w/ 1 MB flash +flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4 diff --git a/openocd-win/openocd/scripts/board/nxp_mcimx8m-evk.cfg b/openocd-win/openocd/scripts/board/nxp_mcimx8m-evk.cfg new file mode 100644 index 0000000..bcd0f67 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_mcimx8m-evk.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for NXP MC-IMX8M-EVK +# + +# only JTAG supported +transport select jtag + +# set a safe JTAG clock speed, can be overridden +adapter speed 1000 + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + +# board has an i.MX8MQ with 4 Cortex-A53 cores +set CHIPNAME imx8mq +set CHIPCORES 4 + +# source SoC configuration +source [find target/imx8m.cfg] diff --git a/openocd-win/openocd/scripts/board/nxp_rdb-ls1046a.cfg b/openocd-win/openocd/scripts/board/nxp_rdb-ls1046a.cfg new file mode 100644 index 0000000..fde1829 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_rdb-ls1046a.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP LS1046ARDB (Reference Design Board) +# This is for the "console" USB port on the front panel +# You must ensure that SW4-7 is in the "off" position + +# NXP K20 +# The firmware implements the old CMSIS-DAP v1 USB HID interface +# You must pass --enable-cmsis-dap to ./configure to enable it +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only + +source [find target/ls1046a.cfg] + +# The adapter can't handle 10MHz +adapter speed 5000 diff --git a/openocd-win/openocd/scripts/board/nxp_rdb-ls1088a.cfg b/openocd-win/openocd/scripts/board/nxp_rdb-ls1088a.cfg new file mode 100644 index 0000000..40483f2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/nxp_rdb-ls1088a.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP LS1088ARDB (Reference Design Board) +# This is for the "main" JTAG connector J55 + +transport select jtag +reset_config srst_only + +# To access the CPLD, populate J48 and add `-c 'set CWTAP 1'` to your command +# line. At the time of this writing, programming is unsupported. +if { [info exists CWTAP] } { + source [find cpld/altera-epm240.cfg] +} else { + source [find target/ls1088a.cfg] +} diff --git a/openocd-win/openocd/scripts/board/olimex_LPC2378STK.cfg b/openocd-win/openocd/scripts/board/olimex_LPC2378STK.cfg new file mode 100644 index 0000000..23588ae --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_LPC2378STK.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +##################################################### +# Olimex LPC2378STK eval board +# +# http://olimex.com/dev/lpc-2378stk.html +# +# Author: Sten, debian@sansys-electronic.com +##################################################### +# + +source [find target/lpc2378.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_lpc_h2148.cfg b/openocd-win/openocd/scripts/board/olimex_lpc_h2148.cfg new file mode 100644 index 0000000..96ae405 --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_lpc_h2148.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex LPC-H2148 eval board +# +# http://www.olimex.com/dev/lpc-h2148.html +# + +source [find target/lpc2148.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_sam7_ex256.cfg b/openocd-win/openocd/scripts/board/olimex_sam7_ex256.cfg new file mode 100644 index 0000000..9924f27 --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_sam7_ex256.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it. + +source [find target/at91sam7x256.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_sam7_la2.cfg b/openocd-win/openocd/scripts/board/olimex_sam7_la2.cfg new file mode 100644 index 0000000..d91432b --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_sam7_la2.cfg @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/at91sam7a2.cfg] + +# delays needed to get stable reads of cpu state +jtag_ntrst_delay 10 +adapter srst delay 200 + +# board uses pullup and connects only srst +reset_config srst_open_drain + +# srst is connected to NRESET of CPU and fully resets everything... +reset_config srst_only srst_pulls_trst + +adapter speed 1 +$_TARGETNAME configure -event reset-start { + adapter speed 1 +} + +$_TARGETNAME configure -event reset-init { + # init script from http://www.mikrocontroller.net/topic/107462 + # AT91SAM7A2 + # AMC (advanced memory controller) + + echo "setting up AMC" + # AMC_CS0 - FLASH 1MB (0x40000000-0x400FFFFF) + DM9000E (0x40100000) + mww 0xFFE00000 0x40003EBD + + # AMC_CS1 - RAM low 2MB (0x40400000-0x405FFFFF) + mww 0xFFE00004 0x404030A9 + + # AMC_CS2 - RAM high 2MB (0x40800000-0x405FFFFF) + #mww 0xFFE00008 0x404030A9 + # changed to 0x40_8_ + mww 0xFFE00008 0x408030A9 + + # AMC_MCR + mww 0xFFE00024 0x00000004 + + # AMC_RCR force remap + mww 0xFFE00020 0x00000001 + + echo "set up AMC" + sleep 100 + + # the following base addresses from the original script did not correspond to those from datasheet + # changed bases from 0xFF000000 to 0xFFF00000 + + # disable watchdog, to prevent unwanted resets + mww 0xFFFA0068 0x00000000 + echo "disabled watchdog" + + sleep 50 + + # disable PLL + mww 0xFFFEC004 0x18070004 + + # PLL = 10 ==> Coreclock = 6Mhz*10/2 = 30 Mhz + mww 0xFFFEC010 0x762D800A + + # enable PLL + mww 0xFFFEC000 0x23050004 + echo "set up pll" + + sleep 100 + adapter speed 5000 +} + +$_TARGETNAME arm7_9 dcc_downloads enable +$_TARGETNAME arm7_9 fast_memory_access enable + +# remap: ram at 0, flash at 0x40000000, like reset-init above does +$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1 +flash bank onboard.flash cfi 0x40000000 0x00100000 2 2 at91sam7a2.cpu + +# boot: ram at 0x300000, flash at 0x0, useful if board is in funny configuration +#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 +#flash bank onboard1.flash cfi 0x00000000 0x00100000 2 2 at91sam7a2.cpu diff --git a/openocd-win/openocd/scripts/board/olimex_sam9_l9260.cfg b/openocd-win/openocd/scripts/board/olimex_sam9_l9260.cfg new file mode 100644 index 0000000..7491a0e --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_sam9_l9260.cfg @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Olimex SAM9-L9260 Development Board +# +# http://www.olimex.com/dev/sam9-L9260.html +# +# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz +# PMC configured for external 18.432 MHz crystal +# +# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks +# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit +# Dataflash : 1 x Atmel AT45DB161D, 16Mbit +# +################################################################################ + +source [find target/at91sam9260.cfg] + +# NTRST_E jumper is enabled by default, so we don't need to override the reset +# config. +#reset_config srst_only + +$_TARGETNAME configure -event reset-start { + # At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if + # RCLK is not supported. + jtag_rclk 5 + halt + + # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may + # be enabled... use physical address. + mww phys 0xfffffd08 0xa5000501 +} + +$_TARGETNAME configure -event reset-init { + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + ## + # Clock configuration for 99.328 MHz main clock. + ## + echo "Setting up clock" + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup + sleep 20 ;# wait 20 ms (need 15.6 ms for startup) + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz) + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup + sleep 20 ;# wait 20 ms (need 1.9 ms for startup) + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2 + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz) + + # Increase JTAG speed to 6 MHz if RCLK is not supported. + jtag_rclk 6000 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads. + + ## + # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks. + ## + echo "Configuring SDRAM" + mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31 + + mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory + + mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode + mww 0x20000000 0 + + mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us + + ## + # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit. + ## + echo "Configuring NAND flash" + mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock + mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS) + mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14 + mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13 + mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND + mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13 + + mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before + + mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE + mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals + mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle + mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, + # 3 TDF cycles, no optimization + + mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers + mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits) + + nand probe at91sam9260.flash + + ## + # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit + ## + echo "Setting up dataflash" + mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), + # 2(SPI0_SPCK), and 11(SPI0_NPCS1) + mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2 + mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11 + mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock + + mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0 + mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure + mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected + + mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, + # 250ns delay before SPCK, 250ns b/n tx + + mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1 + mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0 +} + +nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800 +at91sam9 cle 0 22 +at91sam9 ale 0 21 +at91sam9 rdy_busy 0 0xfffff800 13 +at91sam9 ce 0 0xfffff800 14 diff --git a/openocd-win/openocd/scripts/board/olimex_stm32_h103.cfg b/openocd-win/openocd/scripts/board/olimex_stm32_h103.cfg new file mode 100644 index 0000000..92ca7ae --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_stm32_h103.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Olimex STM32-H103 eval board +# http://olimex.com/dev/stm32-h103.html + +# Work-area size (RAM size) = 20kB for STM32F103RB device +set WORKAREASIZE 0x5000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_stm32_h107.cfg b/openocd-win/openocd/scripts/board/olimex_stm32_h107.cfg new file mode 100644 index 0000000..c199cdc --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_stm32_h107.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex STM32-H107 +# +# http://olimex.com/dev/stm32-h107.html +# + +# Work-area size (RAM size) = 64kB for STM32F107VC device +set WORKAREASIZE 0x10000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_stm32_h405.cfg b/openocd-win/openocd/scripts/board/olimex_stm32_h405.cfg new file mode 100644 index 0000000..f2f1d7f --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_stm32_h405.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Olimex STM32-H405 eval board +# https://www.olimex.com/Products/ARM/ST/STM32-H405/ + +# Work-area size (RAM size) = 128kB for STM32F405RG device +set WORKAREASIZE 0x20000 + +source [find target/stm32f4x.cfg] diff --git a/openocd-win/openocd/scripts/board/olimex_stm32_p107.cfg b/openocd-win/openocd/scripts/board/olimex_stm32_p107.cfg new file mode 100644 index 0000000..9511030 --- /dev/null +++ b/openocd-win/openocd/scripts/board/olimex_stm32_p107.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex STM32-P107 +# +# http://olimex.com/dev/stm32-p107.html +# + +# Work-area size (RAM size) = 64kB for STM32F107VC device +set WORKAREASIZE 0x10000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/omap2420_h4.cfg b/openocd-win/openocd/scripts/board/omap2420_h4.cfg new file mode 100644 index 0000000..ec16965 --- /dev/null +++ b/openocd-win/openocd/scripts/board/omap2420_h4.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OMAP2420 SDP board ("H4") + +source [find target/omap2420.cfg] + +# NOTE: this assumes you're *NOT* using a TI-14 connector. +reset_config trst_and_srst separate + +# Board configs can vary a *LOT* ... parts, jumpers, etc. +# This GP board boots from cs0 using NOR (2x32M), and also +# has 64M NAND on cs6. +flash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME +flash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/openrd.cfg b/openocd-win/openocd/scripts/board/openrd.cfg new file mode 100644 index 0000000..f6c8317 --- /dev/null +++ b/openocd-win/openocd/scripts/board/openrd.cfg @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Marvell OpenRD + +source [find interface/ftdi/openrd.cfg] +source [find target/feroceon.cfg] + +adapter speed 2000 + +$_TARGETNAME configure \ + -work-area-phys 0x10000000 \ + -work-area-size 65536 \ + -work-area-backup 0 + +arm7_9 dcc_downloads enable + +# this assumes the hardware default peripherals location before u-Boot moves it +set _FLASHNAME $_CHIPNAME.flash +nand device $_FLASHNAME orion 0 0xd8000000 + +proc openrd_init { } { + + # We need to assert DBGRQ while holding nSRST down. + # However DBGACK will be set only when nSRST is released. + # Furthermore, the JTAG interface doesn't respond at all when + # the CPU is in the WFI (wait for interrupts) state, so it is + # possible that initial tap examination failed. So let's + # re-examine the target again here when nSRST is asserted which + # should then succeed. + adapter assert srst + feroceon.cpu arp_examine + halt 0 + adapter deassert srst + wait_halt + + arm mcr 15 0 0 1 0 0x00052078 + + mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register + mww 0xD0001404 0x37543000 ;# Dunit Control Low Register + mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register + mww 0xD000140C 0x00000A33 ;# DDR SDRAM Timing (High) Register + mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register + mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register + mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register + mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register + mww 0xD0001420 0x00000004 ;# DDR SDRAM Extended Mode Register + mww 0xD0001424 0x0000F17F ;# Dunit Control High Register + mww 0xD0001428 0x00085520 ;# Dunit Control High Register + mww 0xD000147c 0x00008552 ;# Dunit Control High Register + mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register + mww 0xD0001508 0x10000000 ;# CS1n Base Register + mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register + mww 0xD0001514 0x00000000 ;# CS2n Size Register + mww 0xD000151C 0x00000000 ;# CS3n Size Register + mww 0xD0001494 0x00120012 ;# DDR2 SDRAM ODT Control (Low) Register + mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister + mww 0xD000149C 0x0000E40F ;# DDR2 Dunit ODT Control Register + mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register + mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + + mww 0xD0010000 0x01111111 ;# MPP 0 to 7 + mww 0xD0010004 0x11113322 ;# MPP 8 to 15 + mww 0xD0010008 0x00001111 ;# MPP 16 to 23 + + mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister + mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register + mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register + +} + +proc openrd_reflash_uboot { } { + + # reflash the u-Boot binary and reboot into it + openrd_init + nand probe 0 + nand erase 0 0x0 0xa0000 + nand write 0 uboot.bin 0 oob_softecc_kw + resume + +} + +proc openrd_load_uboot { } { + + # load u-Boot into RAM and execute it + openrd_init + load_image uboot.elf + verify_image uboot.elf + resume 0x00600000 + +} diff --git a/openocd-win/openocd/scripts/board/or1k_generic.cfg b/openocd-win/openocd/scripts/board/or1k_generic.cfg new file mode 100644 index 0000000..915a0de --- /dev/null +++ b/openocd-win/openocd/scripts/board/or1k_generic.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# If you want to use the VJTAG TAP or the XILINX BSCAN, +# you must set your FPGA TAP ID here + +set FPGATAPID 0x020b30dd + +# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN) +if { [info exists TAP_TYPE] == 0} { + set TAP_TYPE VJTAG +} + +# Set your chip name +set CHIPNAME or1200 + +source [find target/or1k.cfg] + +# Set the servers polling period to 1ms (needed to JSP Server) +poll_period 1 + +# Set the adapter speed +adapter speed 3000 + +# Enable the target description feature +gdb_target_description enable + +# Add a new register in the cpu register list. This register will be +# included in the generated target descriptor file. +# format is addreg [name] [address] [feature] [reg_group] +addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system + +# Override default init_reset +proc init_reset {mode} { + soft_reset_halt + resume +} + +# Target initialization +init +echo "Halting processor" +halt + +foreach name [target names] { + set y [$name cget -endian] + set z [$name cget -type] + puts [format "Chip is %s, Endian: %s, type: %s" \ + $name $y $z] +} + +set c_blue "\033\[01;34m" +set c_reset "\033\[0m" + +puts [format "%sTarget ready...%s" $c_blue $c_reset] diff --git a/openocd-win/openocd/scripts/board/osk5912.cfg b/openocd-win/openocd/scripts/board/osk5912.cfg new file mode 100644 index 0000000..0759a27 --- /dev/null +++ b/openocd-win/openocd/scripts/board/osk5912.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://omap.spectrumdigital.com/osk5912/ + +source [find target/omap5912.cfg] + +# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE") +# JTAG connector, and accordingly have J1 connecting pins 1 & 2. +# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3. +reset_config trst_and_srst separate + +# NOTE: boards with XOMAP parts wire nSRST to nPWRON_RESET. +# That resets everything -- including JTAG and EmbeddedICE. +# So they must use "reset_config srst_pulls_trst". + +# NOTE: an expansion board could add a trace connector ... if +# it does, change this appropriately. And reset_config too, +# assuming JTAG_DIS reroutes JTAG to that connector. +etm config $_TARGETNAME 8 demultiplexed full dummy +etm_dummy config $_TARGETNAME + +# standard boards populate two 16 MB chips, but manufacturing +# options or an expansion board could change this config. +flash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME +flash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME + +proc osk5912_init {} { + omap5912_reset + + # detect flash + flash probe 0 + flash probe 1 +} +$_TARGETNAME configure -event reset-init { osk5912_init } + +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/board/phone_se_j100i.cfg b/openocd-win/openocd/scripts/board/phone_se_j100i.cfg new file mode 100644 index 0000000..70387ee --- /dev/null +++ b/openocd-win/openocd/scripts/board/phone_se_j100i.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Sony Ericsson J100I Phone +# +# more information can be found on +# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i +# +source [find target/ti_calypso.cfg] + +# external flash + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/phytec_lpc3250.cfg b/openocd-win/openocd/scripts/board/phytec_lpc3250.cfg new file mode 100644 index 0000000..036b16f --- /dev/null +++ b/openocd-win/openocd/scripts/board/phytec_lpc3250.cfg @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/lpc3250.cfg] + +adapter srst delay 200 +jtag_ntrst_delay 1 +adapter speed 200 +reset_config trst_and_srst separate + +arm7_9 dcc_downloads enable + +$_TARGETNAME configure -event gdb-attach { reset init } + +$_TARGETNAME configure -event reset-start { + arm7_9 fast_memory_access disable + adapter speed 200 +} + +$_TARGETNAME configure -event reset-end { + adapter speed 6000 + arm7_9 fast_memory_access enable +} + +$_TARGETNAME configure -event reset-init { phytec_lpc3250_init } + +# Bare-bones initialization of core clocks and SDRAM +proc phytec_lpc3250_init { } { + # Set clock dividers + # ARMCLK = 266.5 MHz + # HCLK = 133.25 MHz + # PERIPHCLK = 13.325 MHz + mww 0x400040BC 0 + mww 0x40004050 0x140 + mww 0x40004040 0x4D + mww 0x40004058 0x16250 + + # Init PLLs + mww 0x40004044 0x006 + sleep 1 busy + mww 0x40004044 0x106 + sleep 1 busy + mww 0x40004044 0x006 + sleep 1 busy + mww 0x40004048 0x2 + + # Init SDRAM with 133 MHz timings + mww 0x40028134 0x00FFFFFF + mww 0x4002802C 0x00000008 + + mww 0x31080000 1 + mww 0x31080008 0 + mww 0x40004068 0x1C000 + mww 0x31080028 0x11 + + mww 0x31080400 0 + mww 0x31080440 0 + mww 0x31080460 0 + mww 0x31080480 0 + + # Delays + mww 0x31080030 1 + mww 0x31080034 6 + mww 0x31080038 10 + mww 0x31080044 1 + mww 0x31080048 9 + mww 0x3108004C 12 + mww 0x31080050 10 + mww 0x31080054 1 + mww 0x31080058 1 + mww 0x3108005C 0 + + mww 0x31080100 0x5680 + mww 0x31080104 0x302 + + # Init sequence + mww 0x31080020 0x193 + sleep 1 busy + mww 0x31080024 1 + mww 0x31080020 0x113 + sleep 1 busy + mww 0x31080020 0x013 + sleep 1 busy + mww 0x31080024 65 + mww 0x31080020 0x093 + mdw 0x80020000 + mww 0x31080020 0x013 + + # SYS_CTRL remapping + mww 0x40004014 1 +} diff --git a/openocd-win/openocd/scripts/board/pic-p32mx.cfg b/openocd-win/openocd/scripts/board/pic-p32mx.cfg new file mode 100644 index 0000000..0703220 --- /dev/null +++ b/openocd-win/openocd/scripts/board/pic-p32mx.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Olimex PIC-P32MX has a PIC32MX + +set CPUTAPID 0x40916053 +source [find target/pic32mx.cfg] diff --git a/openocd-win/openocd/scripts/board/pico-debug.cfg b/openocd-win/openocd/scripts/board/pico-debug.cfg new file mode 100644 index 0000000..ba59f86 --- /dev/null +++ b/openocd-win/openocd/scripts/board/pico-debug.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# pico-debug is a virtual CMSIS-DAP debug adapter +# it runs on the very same RP2040 target being debugged without additional hardware +# https://github.com/majbthrd/pico-debug + +source [find interface/cmsis-dap.cfg] +adapter speed 4000 + +set CHIPNAME rp2040 +source [find target/rp2040-core0.cfg] diff --git a/openocd-win/openocd/scripts/board/pipistrello.cfg b/openocd-win/openocd/scripts/board/pipistrello.cfg new file mode 100644 index 0000000..17584a0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/pipistrello.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://pipistrello.saanlima.com/ + +source [find interface/ftdi/pipistrello.cfg] +source [find cpld/xilinx-xc6s.cfg] +source [find cpld/jtagspi.cfg] + +# example command to write bitstream, soft-cpu bios and runtime: +# openocd -f board/pipistrello.cfg -c "init;\ +# jtagspi_init 0 bscan_spi_xc6slx45.bit;\ +# jtagspi_program bitstream-pistrello.bin 0;\ +# jtagspi_program bios.bin 0x170000;\ +# jtagspi_program runtime.fbi 0x180000;\ +# xc6s_program xc6s.tap;\ +# exit" diff --git a/openocd-win/openocd/scripts/board/propox_mmnet1001.cfg b/openocd-win/openocd/scripts/board/propox_mmnet1001.cfg new file mode 100644 index 0000000..0e12604 --- /dev/null +++ b/openocd-win/openocd/scripts/board/propox_mmnet1001.cfg @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +## Chip: +set CHIPNAME at91sam9260 +set CPUTAPID 0x0792603f +set ENDIAN little +source [find target/at91sam9260.cfg] + +$_TARGETNAME configure -event reset-init {at91sam_init} + + +proc at91sam_init { } { + + # at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz + jtag_rclk 4 + + # Enable user reset and disable watchdog + mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + # Oscillator setup + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator (18.432 MHz) + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + + # now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz + jtag_rclk 2000 + + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc2c 0x207c3f0c ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz) + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected + sleep 10 ;# wait 10 ms + + # now we are running at 198.656 MHz kHz => full speed jtag + jtag_rclk 30000 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + # Configure PIO Controller for SDRAM data-lines D16-D31 + # PC16-PC31 = Peripheral A: D16-D32 + mww 0xfffff844 0xffff0000 ;# Interrupt Disable + mww 0xfffff854 0xffff0000 ;# Multi-Drive Disable + mww 0xfffff860 0xffff0000 ;# Pull-Up Disable + mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral A function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable) + mww 0xfffffc10 0x00000010 ;# Enable PIO-C Clock in PMC (PID=4) + + # SD-Ram setup + mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit)) + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th) + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th) + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : Normal Mode + mww 0x20000000 0 + mww 0xFFFFEA04 0x30d ;# SDRAM Refresh Time Register + # datasheet: 8k refresh cycles / 64 ms + # MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d + +} diff --git a/openocd-win/openocd/scripts/board/pxa255_sst.cfg b/openocd-win/openocd/scripts/board/pxa255_sst.cfg new file mode 100644 index 0000000..8d00dfe --- /dev/null +++ b/openocd-win/openocd/scripts/board/pxa255_sst.cfg @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# A PXA255 test board with SST 39LF400A flash +# +# At reset the memory map is as follows. Note that +# the memory map changes later on as the application +# starts... +# +# RAM at 0x4000000 +# Flash at 0x00000000 +# +source [find target/pxa255.cfg] + +# Target name is set by above +$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0 + +# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe + +proc pxa255_sst_init {} { + xscale cp15 15 0x00002001 ;#Enable CP0 and CP13 access + # + # setup GPIO + # + mww 0x40E00018 0x00008000 ;#CPSR0 + sleep 20 + mww 0x40E0001C 0x00000002 ;#GPSR1 + sleep 20 + mww 0x40E00020 0x00000008 ;#GPSR2 + sleep 20 + mww 0x40E0000C 0x00008000 ;#GPDR0 + sleep 20 + mww 0x40E00054 0x80000000 ;#GAFR0_L + sleep 20 + mww 0x40E00058 0x00188010 ;#GAFR0_H + sleep 20 + mww 0x40E0005C 0x60908018 ;#GAFR1_L + sleep 20 + mww 0x40E0000C 0x0280E000 ;#GPDR0 + sleep 20 + mww 0x40E00010 0x821C88B2 ;#GPDR1 + sleep 20 + mww 0x40E00014 0x000F03DB ;#GPDR2 + sleep 20 + mww 0x40E00000 0x000F03DB ;#GPLR0 + sleep 20 + + + mww 0x40F00004 0x00000020 ;#PSSR + sleep 20 + + # + # setup memory controller + # + mww 0x48000008 0x01111998 ;#MSC0 + sleep 20 + mww 0x48000010 0x00047ff0 ;#MSC2 + sleep 20 + mww 0x48000014 0x00000000 ;#MECR + sleep 20 + mww 0x48000028 0x00010504 ;#MCMEM0 + sleep 20 + mww 0x4800002C 0x00010504 ;#MCMEM1 + sleep 20 + mww 0x48000030 0x00010504 ;#MCATT0 + sleep 20 + mww 0x48000034 0x00010504 ;#MCATT1 + sleep 20 + mww 0x48000038 0x00004715 ;#MCIO0 + sleep 20 + mww 0x4800003C 0x00004715 ;#MCIO1 + sleep 20 + # + mww 0x48000004 0x03CA4018 ;#MDREF + sleep 20 + mww 0x48000004 0x004B4018 ;#MDREF + sleep 20 + mww 0x48000004 0x000B4018 ;#MDREF + sleep 20 + mww 0x48000004 0x000BC018 ;#MDREF + sleep 20 + mww 0x48000000 0x00001AC8 ;#MDCNFG + sleep 20 + + sleep 20 + + mww 0x48000000 0x00001AC9 ;#MDCNFG + sleep 20 + mww 0x48000040 0x00000000 ;#MDMRS + sleep 20 +} + +$_TARGETNAME configure -event reset-init {pxa255_sst_init} + +reset_config trst_and_srst + +adapter srst delay 200 +jtag_ntrst_delay 200 + +#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address diff --git a/openocd-win/openocd/scripts/board/quark_d2000_refboard.cfg b/openocd-win/openocd/scripts/board/quark_d2000_refboard.cfg new file mode 100644 index 0000000..3af5735 --- /dev/null +++ b/openocd-win/openocd/scripts/board/quark_d2000_refboard.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582) + +# the board has an onboard FTDI FT232H chip +adapter driver ftdi +ftdi vid_pid 0x0403 0x6014 +ftdi channel 0 + +ftdi layout_init 0x0000 0x030b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0100 + +source [find target/quark_d20xx.cfg] + +adapter speed 1000 + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/quark_x10xx_board.cfg b/openocd-win/openocd/scripts/board/quark_x10xx_board.cfg new file mode 100644 index 0000000..aa6adaf --- /dev/null +++ b/openocd-win/openocd/scripts/board/quark_x10xx_board.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# There are many Quark boards that can host the quark_x10xx SoC +# Galileo is an example board + +source [find target/quark_x10xx.cfg] + +#default frequency but this can be adjusted at runtime +adapter speed 4000 + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/quicklogic_quickfeather.cfg b/openocd-win/openocd/scripts/board/quicklogic_quickfeather.cfg new file mode 100644 index 0000000..b522eff --- /dev/null +++ b/openocd-win/openocd/scripts/board/quicklogic_quickfeather.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# QuickLogic EOS S3 QuickFeather +# https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/ + +source [find target/eos_s3.cfg] + +reset_config srst_only + +transport select swd diff --git a/openocd-win/openocd/scripts/board/radiona_ulx3s.cfg b/openocd-win/openocd/scripts/board/radiona_ulx3s.cfg new file mode 100644 index 0000000..eb9b027 --- /dev/null +++ b/openocd-win/openocd/scripts/board/radiona_ulx3s.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Radiona ULX3S +# https://radiona.org/ulx3s/ +# Currently there are following board variants: +# CS-ULX3S-01 - LFE5U 12F +# CS-ULX3S-02 - LFE5U 45F +# CS-ULX3S-03 - LFE5U 85F +# +# two JTAG interfaces: +# - US1, micro USB port connected to FT231XQ +# This interface should be used with following config: +# interface/ft232r/radiona_ulx3s.cfg +# - J4, 6 pin connector +# +# Both of this interfaces share the JTAG lines (TDI, TMS, TCK, TDO) between +# Lattice ECP5 FPGA chip and ESP32 WiFi controller. +# Note: TRST_N of the ESP32 is pulled up by default and can be pulled down over +# J3 interface. +# See schematics for more information: +# https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf +# https://github.com/emard/ulx3s/blob/master/doc/schematics_v314.pdf +# https://github.com/emard/ulx3s/blob/master/doc/schematics_v315.pdf +# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf + +source [find interface/ft232r/radiona_ulx3s.cfg] +source [find fpga/lattice_ecp5.cfg] diff --git a/openocd-win/openocd/scripts/board/redbee.cfg b/openocd-win/openocd/scripts/board/redbee.cfg new file mode 100644 index 0000000..714dfdc --- /dev/null +++ b/openocd-win/openocd/scripts/board/redbee.cfg @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/mc13224v.cfg] diff --git a/openocd-win/openocd/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg b/openocd-win/openocd/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg new file mode 100644 index 0000000..2d98cc5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Achilles Instant-Development Kit Arria 10 SoC SoM +# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som +# + +if { [info exists USE_EXTERNAL_DEBUGGER] } { + echo "Using external debugger" +} else { + source [find interface/altera-usb-blaster2.cfg] + usb_blaster device_desc "Arria10 IDK" +} + +source [find fpga/altera-10m50.cfg] +source [find target/altera_fpgasoc_arria10.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_dk-s7g2.cfg b/openocd-win/openocd/scripts/board/renesas_dk-s7g2.cfg new file mode 100644 index 0000000..e310112 --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_dk-s7g2.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Renesas Synergy DK-S7G2 +# + +source [find interface/jlink.cfg] +transport select swd + +# XXX 19-pin SWD+TRACE connector also available + +# Synergy R7FS7G27H2A01CBD +source [find target/renesas_s7g2.cfg] + +# 32 MB QSPI flash (Micron N25Q256A13EF840E) diff --git a/openocd-win/openocd/scripts/board/renesas_falcon.cfg b/openocd-win/openocd/scripts/board/renesas_falcon.cfg new file mode 100644 index 0000000..c796f85 --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_falcon.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Renesas R-Car V3U Falcon Board Config + +# The Falcon board comes with either an V3U SOC. + +echo "\nFalcon:" +if { ![info exists SOC] } { + set SOC V3U +} +source [find target/renesas_rcar_gen3.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_gr_peach.cfg b/openocd-win/openocd/scripts/board/renesas_gr_peach.cfg new file mode 100644 index 0000000..b3823ca --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_gr_peach.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/A1H GR-Peach board + +reset_config srst_only + +source [find target/renesas_r7s72100.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_porter.cfg b/openocd-win/openocd/scripts/board/renesas_porter.cfg new file mode 100644 index 0000000..134e9ba --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_porter.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car M2 Evaluation Board + +set SOC M2 +source [find target/renesas_rcar_gen2.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_salvator-xs.cfg b/openocd-win/openocd/scripts/board/renesas_salvator-xs.cfg new file mode 100644 index 0000000..1323c13 --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_salvator-xs.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car Gen3 Salvator-X(S) Board Config + +# The Salvator-X(S) boards come with either an H3, M3W, or M3N SOC. + +echo "\nSalvator-X(S):" +if { ![info exists SOC] } { + set SOC H3 +} +source [find target/renesas_rcar_gen3.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_silk.cfg b/openocd-win/openocd/scripts/board/renesas_silk.cfg new file mode 100644 index 0000000..dd61e1d --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_silk.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car E2 Evaluation Board + +set SOC E2 +source [find target/renesas_rcar_gen2.cfg] diff --git a/openocd-win/openocd/scripts/board/renesas_stout.cfg b/openocd-win/openocd/scripts/board/renesas_stout.cfg new file mode 100644 index 0000000..69a524b --- /dev/null +++ b/openocd-win/openocd/scripts/board/renesas_stout.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car H2 Evaluation Board + +set SOC H2 +source [find target/renesas_rcar_gen2.cfg] diff --git a/openocd-win/openocd/scripts/board/rigado_bmd300_ek.cfg b/openocd-win/openocd/scripts/board/rigado_bmd300_ek.cfg new file mode 100644 index 0000000..601041d --- /dev/null +++ b/openocd-win/openocd/scripts/board/rigado_bmd300_ek.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Rigado BMD-300 Evaluation Kit +# +# https://www.rigado.com/products/modules/bmd-300/ +# + +source [find interface/jlink.cfg] +transport select swd +adapter speed 1000 + +source [find target/nrf52.cfg] diff --git a/openocd-win/openocd/scripts/board/rpi3.cfg b/openocd-win/openocd/scripts/board/rpi3.cfg new file mode 100644 index 0000000..fd93a9d --- /dev/null +++ b/openocd-win/openocd/scripts/board/rpi3.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Raspberry Pi 3 board with BCM2837 chip +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md +# +# Enable JTAG GPIO on Raspberry Pi boards +# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md + +source [find target/bcm2837.cfg] +transport select jtag + +# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST) +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/rpi4b.cfg b/openocd-win/openocd/scripts/board/rpi4b.cfg new file mode 100644 index 0000000..5b046af --- /dev/null +++ b/openocd-win/openocd/scripts/board/rpi4b.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Raspberry Pi 4 model B board with BCM2711 chip +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md +# +# Enable JTAG GPIO on Raspberry Pi boards +# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md + +source [find target/bcm2711.cfg] +transport select jtag + +# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST) +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/rsc-w910.cfg b/openocd-win/openocd/scripts/board/rsc-w910.cfg new file mode 100644 index 0000000..b07f940 --- /dev/null +++ b/openocd-win/openocd/scripts/board/rsc-w910.cfg @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Avalue RSC-W8910 sbc +# http://www.avalue.com.tw/products/RSC-W910.cfm +# 2MB NOR Flash +# 64MB SDRAM +# 128MB NAND Flash + +# Based on Nuvoton nuc910 +source [find target/nuc910.cfg] + +# +# reset only behaves correctly if we use srst_pulls_trst +# +reset_config trst_and_srst srst_pulls_trst + +adapter speed 1000 +adapter srst delay 100 +jtag_ntrst_delay 100 + +$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME + +set _NANDNAME $_CHIPNAME.nand +nand device $_NANDNAME nuc910 $_TARGETNAME + +# +# Target events +# + +$_TARGETNAME configure -event reset-start {adapter speed 1000} + +$_TARGETNAME configure -event reset-init { + # switch on PLL for 200MHz operation + # running from 15MHz input clock + + mww 0xB0000200 0x00000030 ;# CLKEN + mww 0xB0000204 0x00000f3c ;# CLKSEL + mww 0xB0000208 0x05007000 ;# CLKDIV + mww 0xB000020C 0x00004f24 ;# PLLCON0 + mww 0xB0000210 0x00002b63 ;# PLLCON1 + mww 0xB000000C 0x08817fa6 ;# MFSEL + sleep 10 + + # we are now running @ 200MHz + # enable all openocd speed tweaks + + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable + adapter speed 15000 + + # map nor flash to 0x20000000 + # map sdram to 0x00000000 + + mww 0xb0001000 0x000530c1 ;# EBICON + mww 0xb0001004 0x40030084 ;# ROMCON + mww 0xb0001008 0x000010ee ;# SDCONF0 + mww 0xb000100C 0x00000000 ;# SDCONF1 + mww 0xb0001010 0x0000015b ;# SDTIME0 + mww 0xb0001014 0x0000015b ;# SDTIME1 + mww 0xb0001018 0x00000000 ;# EXT0CON + mww 0xb000101C 0x00000000 ;# EXT1CON + mww 0xb0001020 0x00000000 ;# EXT2CON + mww 0xb0001024 0x00000000 ;# EXT3CON + mww 0xb000102c 0x00ff0048 ;# CKSKEW +} diff --git a/openocd-win/openocd/scripts/board/sayma_amc.cfg b/openocd-win/openocd/scripts/board/sayma_amc.cfg new file mode 100644 index 0000000..b714609 --- /dev/null +++ b/openocd-win/openocd/scripts/board/sayma_amc.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Sayma AMC is an FPGA board for the µTCA AMC format +# The board is open hardware (CERN OHL) and the gateware and software +# running on it are open source (ARTIQ, LGPLv3+). +# +# https://github.com/m-labs/sinara/wiki/Sayma +# +# It contains a Xilinx Kintex Ultrascale 040 FPGA (xcku040). +# There is a SCANSTA112SM JTAG router on the board which is configured to +# automatically add devices to the JTAG svcan chain when they are added. +# Sayma AMC is usually combined with Sayma RTM (rear transition module) +# which features an Artix 7 FPGA. + +adapter driver ftdi +ftdi device_desc "Quad RS232-HS" +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 +# Use this to distinguish multiple boards by topology +#adapter usb location 5:1 +# sampling on falling edge generally seems to work and accelerates things but +# is not fully tested +#ftdi tdo_sample_edge falling +# EN_USB_JTAG on ADBUS7: out, high +# USB_nTRST on ADBUS4: out, high, but R46 is DNP +ftdi layout_init 0x0098 0x008b +#ftdi layout_signal EN_USB -data 0x0080 +#ftdi layout_signal nTRST -data 0x0010 +reset_config none + +adapter speed 5000 + +transport select jtag + +# Add the RTM Artix to the chain. Note that this changes the PLD numbering. +# Unfortunately openocd TAPs can't be disabled after they have been added and +# before `init`. +#source [find cpld/xilinx-xc7.cfg] + +set CHIP XCKU040 +source [find cpld/xilinx-xcu.cfg] + +set XILINX_USER1 0x02 +set XILINX_USER2 0x03 +set JTAGSPI_IR $XILINX_USER1 +source [find cpld/jtagspi.cfg] +flash bank xcu.spi1 jtagspi 0 0 0 0 xcu.proxy $XILINX_USER2 diff --git a/openocd-win/openocd/scripts/board/sheevaplug.cfg b/openocd-win/openocd/scripts/board/sheevaplug.cfg new file mode 100644 index 0000000..734fab6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/sheevaplug.cfg @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Marvell SheevaPlug + +source [find interface/ftdi/sheevaplug.cfg] +source [find target/feroceon.cfg] + +adapter speed 2000 + +$_TARGETNAME configure \ + -work-area-phys 0x10000000 \ + -work-area-size 65536 \ + -work-area-backup 0 + +arm7_9 dcc_downloads enable + +# this assumes the hardware default peripherals location before u-Boot moves it +set _FLASHNAME $_CHIPNAME.flash +nand device $_FLASHNAME orion 0 0xd8000000 + +proc sheevaplug_init { } { + + # We need to assert DBGRQ while holding nSRST down. + # However DBGACK will be set only when nSRST is released. + # Furthermore, the JTAG interface doesn't respond at all when + # the CPU is in the WFI (wait for interrupts) state, so it is + # possible that initial tap examination failed. So let's + # re-examine the target again here when nSRST is asserted which + # should then succeed. + adapter assert srst + feroceon.cpu arp_examine + halt 0 + adapter deassert srst + wait_halt + + arm mcr 15 0 0 1 0 0x00052078 + + mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register + mww 0xD0001404 0x39543000 ;# Dunit Control Low Register + mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register + mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register + mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register + mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register + mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register + mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register + mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register + mww 0xD0001424 0x0000F17F ;# Dunit Control High Register + mww 0xD0001428 0x00085520 ;# Dunit Control High Register + mww 0xD000147c 0x00008552 ;# Dunit Control High Register + mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register + mww 0xD0001508 0x10000000 ;# CS1n Base Register + mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register + mww 0xD0001514 0x00000000 ;# CS2n Size Register + mww 0xD000151C 0x00000000 ;# CS3n Size Register + mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register + mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister + mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register + mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register + mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + + mww 0xD0010000 0x01111111 ;# MPP 0 to 7 + mww 0xD0010004 0x11113322 ;# MPP 8 to 15 + mww 0xD0010008 0x00001111 ;# MPP 16 to 23 + + mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister + mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register + mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register + +} + +proc sheevaplug_reflash_uboot { } { + + # reflash the u-Boot binary and reboot into it + sheevaplug_init + nand probe 0 + nand erase 0 0x0 0xa0000 + nand write 0 uboot.bin 0 oob_softecc_kw + resume + +} + +proc sheevaplug_reflash_uboot_env { } { + + # reflash the u-Boot environment variables area + sheevaplug_init + nand probe 0 + nand erase 0 0xa0000 0x40000 + nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw + resume + +} + +proc sheevaplug_load_uboot { } { + + # load u-Boot into RAM and execute it + sheevaplug_init + load_image uboot.elf + verify_image uboot.elf + resume 0x00600000 + +} diff --git a/openocd-win/openocd/scripts/board/sifive-e31arty.cfg b/openocd-win/openocd/scripts/board/sifive-e31arty.cfg new file mode 100644 index 0000000..b3e980f --- /dev/null +++ b/openocd-win/openocd/scripts/board/sifive-e31arty.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Be sure you include the speed and interface before this file +# Example: +# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg" + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/openocd-win/openocd/scripts/board/sifive-e51arty.cfg b/openocd-win/openocd/scripts/board/sifive-e51arty.cfg new file mode 100644 index 0000000..3133c39 --- /dev/null +++ b/openocd-win/openocd/scripts/board/sifive-e51arty.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Be sure you include the speed and interface before this file +# Example: +# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg" + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/openocd-win/openocd/scripts/board/sifive-hifive1-revb.cfg b/openocd-win/openocd/scripts/board/sifive-hifive1-revb.cfg new file mode 100644 index 0000000..e5fe104 --- /dev/null +++ b/openocd-win/openocd/scripts/board/sifive-hifive1-revb.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter speed 4000 + +adapter driver jlink +transport select jtag + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 0 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME.0 + +init + +jlink jtag 3 + +halt +flash protect 0 1 last off +echo "Ready for Remote Connections" diff --git a/openocd-win/openocd/scripts/board/sifive-hifive1.cfg b/openocd-win/openocd/scripts/board/sifive-hifive1.cfg new file mode 100644 index 0000000..f69dc4f --- /dev/null +++ b/openocd-win/openocd/scripts/board/sifive-hifive1.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter speed 10000 + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi set_signal, but still good to document +#adapter srst delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi set_signal nSRST 0 + ftdi set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off diff --git a/openocd-win/openocd/scripts/board/smdk6410.cfg b/openocd-win/openocd/scripts/board/smdk6410.cfg new file mode 100644 index 0000000..be61ae9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/smdk6410.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the Samsung s3c6410 system on chip +# Tested on a SMDK6410 +# Processor : ARM1176 +# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) + +source [find target/samsung_s3c6410.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe diff --git a/openocd-win/openocd/scripts/board/snps_em_sk.cfg b/openocd-win/openocd/scripts/board/snps_em_sk.cfg new file mode 100644 index 0000000..56eed93 --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_em_sk.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2014-2016,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys DesignWare ARC EM Starter Kit v2.x +# + +# Configure JTAG cable +# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1. +source [find interface/ftdi/digilent-hs1.cfg] + +# 5MHz seems to work good with all cores that might happen in 2.x +adapter speed 5000 + +# ARCs support only JTAG. +transport select jtag + +# Configure FPGA. This script supports both LX45 and LX150. +source [find target/snps_em_sk_fpga.cfg] diff --git a/openocd-win/openocd/scripts/board/snps_em_sk_v1.cfg b/openocd-win/openocd/scripts/board/snps_em_sk_v1.cfg new file mode 100644 index 0000000..94aab14 --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_em_sk_v1.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2014-2016,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1 +# + +# Configure JTAG cable +# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1. +source [find interface/ftdi/digilent-hs1.cfg] +adapter speed 10000 + +# ARCs support only JTAG. +transport select jtag + +# Configure FPGA. This script supports both LX45 and LX150. +source [find target/snps_em_sk_fpga.cfg] diff --git a/openocd-win/openocd/scripts/board/snps_em_sk_v2.1.cfg b/openocd-win/openocd/scripts/board/snps_em_sk_v2.1.cfg new file mode 100644 index 0000000..96391df --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_em_sk_v2.1.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2014-2016,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys DesignWare ARC EM Starter Kit v2.1 +# + +# Configure JTAG cable +# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1. +source [find interface/ftdi/digilent-hs1.cfg] + +# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency +# 20MHz. 7.5 MHz seems to work fine. +adapter speed 7500 + +# ARCs support only JTAG. +transport select jtag + +# Configure FPGA. This script supports both LX45 and LX150. +source [find target/snps_em_sk_fpga.cfg] diff --git a/openocd-win/openocd/scripts/board/snps_em_sk_v2.2.cfg b/openocd-win/openocd/scripts/board/snps_em_sk_v2.2.cfg new file mode 100644 index 0000000..c1f6a72 --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_em_sk_v2.2.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2016,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys DesignWare ARC EM Starter Kit v2.2 +# + +# Configure JTAG cable +# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1. +source [find interface/ftdi/digilent-hs1.cfg] + +# EM11D reportedly requires 5 MHz. Other cores and board can work faster. +adapter speed 5000 + +# ARCs support only JTAG. +transport select jtag + +# Configure FPGA. This script supports both LX45 and LX150. +source [find target/snps_em_sk_fpga.cfg] diff --git a/openocd-win/openocd/scripts/board/snps_hsdk.cfg b/openocd-win/openocd/scripts/board/snps_hsdk.cfg new file mode 100644 index 0000000..24022e5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_hsdk.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2019, 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores) +# + +source [find interface/ftdi/snps_sdp.cfg] +adapter speed 10000 + +# ARCs supports only JTAG. +transport select jtag + +# Configure SoC +source [find target/snps_hsdk.cfg] diff --git a/openocd-win/openocd/scripts/board/snps_hsdk_4xd.cfg b/openocd-win/openocd/scripts/board/snps_hsdk_4xd.cfg new file mode 100644 index 0000000..5901533 --- /dev/null +++ b/openocd-win/openocd/scripts/board/snps_hsdk_4xd.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2023 Synopsys, Inc. +# Artemiy Volkov <artemiy@synopsys.com> + +# Adapted from tcl/board/snps_hsdk.cfg. + +# +# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores) +# + +source [find interface/ftdi/snps_sdp.cfg] +adapter speed 10000 + +# ARCs supports only JTAG. +transport select jtag + +# Configure SoC +source [find target/snps_hsdk_4xd.cfg] diff --git a/openocd-win/openocd/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg b/openocd-win/openocd/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg new file mode 100644 index 0000000..c22ace8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Spansion SK-FM4-176L-S6E2CC +# + +# +# FM3 MB9AF312K +# +source [find interface/cmsis-dap.cfg] + +# There's also an unpopulated 10-pin 0.05" pinout. + +# +# FM4 S6E2CCAJ0A w/ 192 KB SRAM0 +# +set CHIPNAME s6e2cc +set CHIPSERIES S6E2CCAJ0A +set WORKAREASIZE 0x30000 +source [find target/fm4_s6e2cc.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/spansion_sk-fm4-u120-9b560.cfg b/openocd-win/openocd/scripts/board/spansion_sk-fm4-u120-9b560.cfg new file mode 100644 index 0000000..15477a2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/spansion_sk-fm4-u120-9b560.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Spansion SK-FM4-U120-9B560 +# + +# +# FM3 MB9AF312K +# +# source [find interface/cmsis-dap.cfg] + +# +# FM4 MB9BF568R w/ 64 KB SRAM0 +# +set CHIPNAME mb9bf568 +set CHIPSERIES MB9BF568R +set WORKAREASIZE 0x10000 +source [find target/fm4_mb9bf.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/spear300evb.cfg b/openocd-win/openocd/scripts/board/spear300evb.cfg new file mode 100644 index 0000000..f2cf596 --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear300evb.cfg @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr300 Evaluation board +# EVALSPEAr300 Rev. 1.0 +# http://www.st.com/spear +# +# Date: 2010-11-27 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + +# The standard board has JTAG SRST not connected. +# This script targets such boards using quirky code to bypass the issue. + + +source [find mem_helper.tcl] +source [find target/spear3xx.cfg] +source [find chip/st/spear/spear3xx_ddr.tcl] +source [find chip/st/spear/spear3xx.tcl] + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + + +# Serial NOR on SMI CS0. 8Mbyte. +set _FLASHNAME1 $_CHIPNAME.snor +flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME + +if { [info exists BOARD_HAS_SRST] } { + # Modified board has SRST on JTAG connector + reset_config trst_and_srst separate srst_gates_jtag \ + trst_push_pull srst_open_drain +} else { + # Standard board has no SRST on JTAG connector + reset_config trst_only separate srst_gates_jtag trst_push_pull + source [find chip/st/spear/quirk_no_srst.tcl] +} + +$_TARGETNAME configure -event reset-init { spear300evb_init } + +proc spear300evb_init {} { + reg pc 0xffff0020; # loop forever + + sp3xx_clock_default + sp3xx_common_init + sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" + sp300_init +} diff --git a/openocd-win/openocd/scripts/board/spear300evb_mod.cfg b/openocd-win/openocd/scripts/board/spear300evb_mod.cfg new file mode 100644 index 0000000..4b1d578 --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear300evb_mod.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr300 Evaluation board +# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector +# http://www.st.com/spear +# +# List of board modifications to enable SRST, as reported in +# ST Application Note (FIXME: add reference). +# - Modifications on the top layer: +# 1. replace reset chip U4 with a STM6315SDW13F; +# - Modifications on the bottom layer: +# 2. add 0 ohm resistor R10. It is located close to JTAG connector. +# 3. add a 10K ohm pull-up resistor on the reset wire named as +# POWERGOOD in the schematic. +# +# The easier way to do modification 3, is to use a resistor in package +# 0603 and solder it between R10 and R54: +# - one pad soldered with the pad of R54 connected to 3.3V (this +# is the pad of R54 far from JTAG connector J4) +# - the other pad soldered with the nearest pad of R10. +# +# Date: 2011-11-18 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + + +# Modified boards has SRST on JTAG connector +set BOARD_HAS_SRST 1 +source [find board/spear300evb.cfg] diff --git a/openocd-win/openocd/scripts/board/spear310evb20.cfg b/openocd-win/openocd/scripts/board/spear310evb20.cfg new file mode 100644 index 0000000..c37bd1d --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear310evb20.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr310 Evaluation board +# EVALSPEAr310 Rev. 2.0 +# http://www.st.com/spear +# +# Date: 2010-08-17 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + +# The standard board has JTAG SRST not connected. +# This script targets such boards using quirky code to bypass the issue. +# +# Check ST Application Note AN3321 on how to fix SRST on +# the board, then use the script board/spear310evb20_mod.cfg + + +source [find mem_helper.tcl] +source [find target/spear3xx.cfg] +source [find chip/st/spear/spear3xx_ddr.tcl] +source [find chip/st/spear/spear3xx.tcl] + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + +# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte. +set _FLASHNAME0 $_CHIPNAME.pnor +flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME + +# Serial NOR on SMI CS0. 8Mbyte. +set _FLASHNAME1 $_CHIPNAME.snor +flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME + +if { [info exists BOARD_HAS_SRST] } { + # Modified board has SRST on JTAG connector + reset_config trst_and_srst separate srst_gates_jtag \ + trst_push_pull srst_open_drain +} else { + # Standard board has no SRST on JTAG connector + reset_config trst_only separate srst_gates_jtag trst_push_pull + source [find chip/st/spear/quirk_no_srst.tcl] +} + +$_TARGETNAME configure -event reset-init { spear310evb20_init } + +proc spear310evb20_init {} { + reg pc 0xffff0020 ;# loop forever + + sp3xx_clock_default + sp3xx_common_init + sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" + sp310_init + sp310_emi_init +} diff --git a/openocd-win/openocd/scripts/board/spear310evb20_mod.cfg b/openocd-win/openocd/scripts/board/spear310evb20_mod.cfg new file mode 100644 index 0000000..2c56254 --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear310evb20_mod.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr310 Evaluation board +# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector +# http://www.st.com/spear +# +# List of board modifications to enable SRST, as reported in +# ST Application Note AN3321. +# - Modifications on the top layer: +# 1. remove R137 and C57, located near the SMII PHY U18; +# 2. remove R172 and C75, located near the SMII PHY U19; +# 3. remove R207 and C90, located near the SMII PHY U20; +# 4. remove C236, located near the SMII PHY U21; +# 5. remove U12, located near the JTAG connector; +# 6. solder together pins 7, 8 and 9 of U12; +# 7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12. +# - Modifications on the bottom layer: +# 8. replace reset chip U11 with a STM6315SDW13F; +# 9. add 0 ohm resistor R329. It is located close to JTAG connector. +# +# Date: 2009-10-31 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + + +# Modified boards has SRST on JTAG connector +set BOARD_HAS_SRST 1 +source [find board/spear310evb20.cfg] diff --git a/openocd-win/openocd/scripts/board/spear320cpu.cfg b/openocd-win/openocd/scripts/board/spear320cpu.cfg new file mode 100644 index 0000000..df713ea --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear320cpu.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr320 CPU board +# EVAL_SPEAr320CPU Rev. 2.0 +# http://www.st.com/spear +# +# Date: 2011-11-18 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + +# The standard board has JTAG SRST not connected. +# This script targets such boards using quirky code to bypass the issue. + + +source [find mem_helper.tcl] +source [find target/spear3xx.cfg] +source [find chip/st/spear/spear3xx_ddr.tcl] +source [find chip/st/spear/spear3xx.tcl] + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + + +# Serial NOR on SMI CS0. 8Mbyte. +set _FLASHNAME1 $_CHIPNAME.snor +flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME + +if { [info exists BOARD_HAS_SRST] } { + # Modified board has SRST on JTAG connector + reset_config trst_and_srst separate srst_gates_jtag \ + trst_push_pull srst_open_drain +} else { + # Standard board has no SRST on JTAG connector + reset_config trst_only separate srst_gates_jtag trst_push_pull + source [find chip/st/spear/quirk_no_srst.tcl] +} + +$_TARGETNAME configure -event reset-init { spear320cpu_init } + +if { [info exists DDR_CHIPS] } { + set _DDR_CHIPS $DDR_CHIPS +} else { + set _DDR_CHIPS 1 +} + +proc spear320cpu_init {} { + global _DDR_CHIPS + reg pc 0xffff0020; # loop forever + + sp3xx_clock_default + sp3xx_common_init + sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $_DDR_CHIPS + sp320_init +} diff --git a/openocd-win/openocd/scripts/board/spear320cpu_mod.cfg b/openocd-win/openocd/scripts/board/spear320cpu_mod.cfg new file mode 100644 index 0000000..d12607d --- /dev/null +++ b/openocd-win/openocd/scripts/board/spear320cpu_mod.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Configuration for the ST SPEAr320 Evaluation board +# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector +# http://www.st.com/spear +# +# List of board modifications to enable SRST, as reported in +# ST Application Note (FIXME: add reference). +# - Modifications on the bottom layer: +# 1. replace reset chip U7 with a STM6315SDW13F; +# 2. add 0 ohm resistor R45. It is located close to JTAG connector. +# 3. add a 10K ohm pull-up resistor on the reset wire named as +# POWERGOOD in the schematic. +# +# The easier way to do modification 3, is to use a resistor in package +# 0603 or 0402 and solder it between R15 and R45: +# - one pad soldered with the pad of R15 connected to 3.3V (this +# is the pad of R15 closer to R45) +# - the other pad soldered with the nearest pad of R45. +# +# Date: 2011-11-18 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + + +# Modified boards has SRST on JTAG connector +set BOARD_HAS_SRST 1 +source [find board/spear320cpu.cfg] diff --git a/openocd-win/openocd/scripts/board/st_b-l475e-iot01a.cfg b/openocd-win/openocd/scripts/board/st_b-l475e-iot01a.cfg new file mode 100644 index 0000000..e75c99d --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_b-l475e-iot01a.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip. +# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 96KB +set WORKAREASIZE 0x18000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32l4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x4002104C 0x000001FF 0 ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks) + mmw 0x40021050 0x00000100 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0 + + # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V + + # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V + mmw 0x48001000 0xAAA00000 0x55500000 ;# MODER + mmw 0x48001008 0xFFF00000 0x00000000 ;# OSPEEDR + mmw 0x48001024 0xAAAAAA00 0x55555500 ;# AFRH + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x01500008 ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00160100 ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mmw 0x40022000 0x00000004 0x00000003 ;# 4 WS for 72 MHz HCLK + sleep 1 + mmw 0x40021000 0x00000100 0x00000000 ;# HSI on + mww 0x4002100C 0x01002432 ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI + mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1 + mmw 0x40021000 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/st_nucleo_8l152r8.cfg b/openocd-win/openocd/scripts/board/st_nucleo_8l152r8.cfg new file mode 100644 index 0000000..7cb8bce --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_8l152r8.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip. +# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html + +source [find interface/stlink-dap.cfg] + +transport select swim + +source [find target/stm8l15xx8.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_8s208rb.cfg b/openocd-win/openocd/scripts/board/st_nucleo_8s208rb.cfg new file mode 100644 index 0000000..0d3c0c9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_8s208rb.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip. +# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html + +source [find interface/stlink-dap.cfg] + +transport select swim + +# 128 KiB flash and 2 KiB EEPROM +set FLASHEND 0x27fff +set EEPROMEND 0x47ff + +source [find target/stm8s.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_f0.cfg b/openocd-win/openocd/scripts/board/st_nucleo_f0.cfg new file mode 100644 index 0000000..31a95f5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_f0.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for all ST NUCLEO with any STM32F0. Known boards at the moment: +# STM32F030R8 +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997 +# NUCLEO-F072RB +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997 +# STM32F091RC +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944 + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f0x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_f103rb.cfg b/openocd-win/openocd/scripts/board/st_nucleo_f103rb.cfg new file mode 100644 index 0000000..9815d45 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_f103rb.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875 + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f1x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_f3.cfg b/openocd-win/openocd/scripts/board/st_nucleo_f3.cfg new file mode 100644 index 0000000..8833724 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_f3.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004 + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f3x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_f4.cfg b/openocd-win/openocd/scripts/board/st_nucleo_f4.cfg new file mode 100644 index 0000000..a1908e4 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_f4.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for all ST NUCLEO with any STM32F4. Known boards at the moment: +# STM32F401RET6 +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000 +# STM32F411RET6 +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320 + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_f7.cfg b/openocd-win/openocd/scripts/board/st_nucleo_f7.cfg new file mode 100644 index 0000000..9c5b36e --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_f7.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32F7 Nucleo development board +# Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f7x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_g0.cfg b/openocd-win/openocd/scripts/board/st_nucleo_g0.cfg new file mode 100644 index 0000000..f8e67a0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_g0.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for all ST NUCLEO with any STM32G0. Known boards at the moment: +# NUCLEO-G031K8 +# https://www.st.com/en/evaluation-tools/nucleo-g031k8.html +# NUCLEO-G070RB +# https://www.st.com/en/evaluation-tools/nucleo-g070rb.html +# NUCLEO-G071RB +# https://www.st.com/en/evaluation-tools/nucleo-g071rb.html +# NUCLEO-G0B1RE +# https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32g0x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_g4.cfg b/openocd-win/openocd/scripts/board/st_nucleo_g4.cfg new file mode 100644 index 0000000..8e583e7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_g4.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for all ST NUCLEO with any STM32G4. Known boards at the moment: +# NUCLEO-G431KB +# https://www.st.com/en/evaluation-tools/nucleo-g431kb.html +# NUCLEO-G431RB +# https://www.st.com/en/evaluation-tools/nucleo-g431rb.html +# NUCLEO-G474RE +# https://www.st.com/en/evaluation-tools/nucleo-g474re.html +# NUCLEO-G491RE +# https://www.st.com/en/evaluation-tools/nucleo-g491re.html + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32g4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_h743zi.cfg b/openocd-win/openocd/scripts/board/st_nucleo_h743zi.cfg new file mode 100644 index 0000000..b857b00 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_h743zi.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip. +# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_h745zi.cfg b/openocd-win/openocd/scripts/board/st_nucleo_h745zi.cfg new file mode 100644 index 0000000..ad563b7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_h745zi.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip. + +source [find interface/stlink-dap.cfg] +transport select dapdirect_swd + +# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4) +set DUAL_CORE 1 + +# enable CTI for cross halting both cores +set USE_CTI 1 + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_l073rz.cfg b/openocd-win/openocd/scripts/board/st_nucleo_l073rz.cfg new file mode 100644 index 0000000..10fac5e --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_l073rz.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip. +# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 + +source [find target/stm32l0_dual_bank.cfg] + +# There is only system reset line and JTAG/SWD command can be issued when SRST +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_l1.cfg b/openocd-win/openocd/scripts/board/st_nucleo_l1.cfg new file mode 100644 index 0000000..50688d2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_l1.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002 + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l1x_dual_bank.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/st_nucleo_l4.cfg b/openocd-win/openocd/scripts/board/st_nucleo_l4.cfg new file mode 100644 index 0000000..8c63d8c --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_l4.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Should work with all STM32L4 Nucleo Dev Boards. +# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l4x.cfg] + +# use hardware reset +reset_config srst_only srst_nogate diff --git a/openocd-win/openocd/scripts/board/st_nucleo_l5.cfg b/openocd-win/openocd/scripts/board/st_nucleo_l5.cfg new file mode 100644 index 0000000..6450f08 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_l5.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for STM32L5 Nucleo Dev Boards. +# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html + +source [find interface/stlink-dap.cfg] + +transport select dapdirect_swd + +source [find target/stm32l5x.cfg] + +# use hardware reset +reset_config srst_only srst_nogate diff --git a/openocd-win/openocd/scripts/board/st_nucleo_wb55.cfg b/openocd-win/openocd/scripts/board/st_nucleo_wb55.cfg new file mode 100644 index 0000000..29b7ec9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/st_nucleo_wb55.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6) +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32wbx.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/steval-idb007v1.cfg b/openocd-win/openocd/scripts/board/steval-idb007v1.cfg new file mode 100644 index 0000000..69d4585 --- /dev/null +++ b/openocd-win/openocd/scripts/board/steval-idb007v1.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an evaluation board with a single BlueNRG-1 chip. +# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb008v1.html +set CHIPNAME bluenrg-1 +source [find target/bluenrg-x.cfg] diff --git a/openocd-win/openocd/scripts/board/steval-idb008v1.cfg b/openocd-win/openocd/scripts/board/steval-idb008v1.cfg new file mode 100644 index 0000000..057c0dd --- /dev/null +++ b/openocd-win/openocd/scripts/board/steval-idb008v1.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an evaluation board with a single BlueNRG-2 chip. +# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb007v1.html +set CHIPNAME bluenrg-2 +source [find target/bluenrg-x.cfg] diff --git a/openocd-win/openocd/scripts/board/steval-idb011v1.cfg b/openocd-win/openocd/scripts/board/steval-idb011v1.cfg new file mode 100644 index 0000000..1163508 --- /dev/null +++ b/openocd-win/openocd/scripts/board/steval-idb011v1.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an evaluation board with a single BlueNRG-LP chip. +set CHIPNAME bluenrg-lp +source [find target/bluenrg-x.cfg] diff --git a/openocd-win/openocd/scripts/board/steval-idb012v1.cfg b/openocd-win/openocd/scripts/board/steval-idb012v1.cfg new file mode 100644 index 0000000..288cbb2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/steval-idb012v1.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an evaluation board with a single BlueNRG-LPS chip. +set CHIPNAME bluenrg-lps +source [find interface/cmsis-dap.cfg] +source [find target/bluenrg-x.cfg] diff --git a/openocd-win/openocd/scripts/board/steval_pcc010.cfg b/openocd-win/openocd/scripts/board/steval_pcc010.cfg new file mode 100644 index 0000000..6e006ba --- /dev/null +++ b/openocd-win/openocd/scripts/board/steval_pcc010.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram +# coming with the STEVAL-PCC010 board +# http://www.st.com/internet/evalboard/product/251530.jsp +# or any other board with only a STM32F2x in the JTAG chain + +# increase working area to 32KB for faster flash programming +set WORKAREASIZE 0x8000 + +source [find target/stm32f2x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm320518_eval.cfg b/openocd-win/openocd/scripts/board/stm320518_eval.cfg new file mode 100644 index 0000000..04486fc --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm320518_eval.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6 +# (64KB) chip. +# http://www.st.com/internet/evalboard/product/252994.jsp +# + +# increase working area to 8KB +set WORKAREASIZE 0x2000 + +# chip name +set CHIPNAME STM32F051R8T6 + +source [find target/stm32f0x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm320518_eval_stlink.cfg b/openocd-win/openocd/scripts/board/stm320518_eval_stlink.cfg new file mode 100644 index 0000000..153f7e5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm320518_eval_stlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6 +# (64KB) chip. +# http://www.st.com/internet/evalboard/product/252994.jsp +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 8KB +set WORKAREASIZE 0x2000 + +# chip name +set CHIPNAME STM32F051R8T6 + +source [find target/stm32f0x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32100b_eval.cfg b/openocd-win/openocd/scripts/board/stm32100b_eval.cfg new file mode 100644 index 0000000..ebb5681 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32100b_eval.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32 eval board with a single STM32F100VBT6 chip. +# http://www.st.com/internet/evalboard/product/247099.jsp + +# The chip has only 8KB sram +set WORKAREASIZE 0x2000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm3210b_eval.cfg b/openocd-win/openocd/scripts/board/stm3210b_eval.cfg new file mode 100644 index 0000000..072f542 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3210b_eval.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32 eval board with a single STM32F10x (128KB) chip. +# http://www.st.com/internet/evalboard/product/176090.jsp + +# increase working area to 32KB for faster flash programming +set WORKAREASIZE 0x8000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm3210c_eval.cfg b/openocd-win/openocd/scripts/board/stm3210c_eval.cfg new file mode 100644 index 0000000..ec56f63 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3210c_eval.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32 eval board with a single STM32F107VCT chip. +# http://www.st.com/internet/evalboard/product/217965.jsp + +# increase working area to 32KB for faster flash programming +set WORKAREASIZE 0x8000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm3210e_eval.cfg b/openocd-win/openocd/scripts/board/stm3210e_eval.cfg new file mode 100644 index 0000000..f08e04b --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3210e_eval.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32 eval board with a single STM32F103ZET6 chip. +# http://www.st.com/internet/evalboard/product/204176.jsp + +# increase working area to 32KB for faster flash programming +set WORKAREASIZE 0x8000 + +source [find target/stm32f1x.cfg] + +# +# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash +# M29W128GL70ZA6E +# + +set _FLASHNAME $_CHIPNAME.norflash +flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME + +proc stm32_enable_fsmc {} { + + echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)" + + # enable gpio (defg) clocks for fsmc + # RCC_APB2ENR + mww 0x40021018 0x000001E0 + + # enable fsmc clock + # RCC_AHBENR + mww 0x40021014 0x00000114 + + # configure gpio to alternate function + # GPIOD_CRL + mww 0x40011400 0x44BB44BB + # GPIOD_CRH + mww 0x40011404 0xBBBBBBBB + + # GPIOE_CRL + mww 0x40011800 0xBBBBB444 + # GPIOE_CRH + mww 0x40011804 0xBBBBBBBB + + # GPIOF_CRL + mww 0x40011C00 0x44BBBBBB + # GPIOF_CRH + mww 0x40011C04 0xBBBB4444 + + # GPIOG_CRL + mww 0x40012000 0x44BBBBBB + # GPIOG_CRH + mww 0x40012004 0x444444B4 + + # setup fsmc timings + # FSMC_BCR1 + mww 0xA0000008 0x00001058 + + # FSMC_BTR1 + mww 0xA000000C 0x10000502 + + # FSMC_BCR1 - enable fsmc + mww 0xA0000008 0x00001059 +} + +$_TARGETNAME configure -event reset-init { + stm32_enable_fsmc +} diff --git a/openocd-win/openocd/scripts/board/stm3220g_eval.cfg b/openocd-win/openocd/scripts/board/stm3220g_eval.cfg new file mode 100644 index 0000000..9782a07 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3220g_eval.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6 +# (128KB) chip. +# http://www.st.com/internet/evalboard/product/250374.jsp + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F207IGH6 + +source [find target/stm32f2x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm3220g_eval_stlink.cfg b/openocd-win/openocd/scripts/board/stm3220g_eval_stlink.cfg new file mode 100644 index 0000000..d529672 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3220g_eval_stlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6 +# (128KB) chip. +# http://www.st.com/internet/evalboard/product/250374.jsp +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F207IGH6 + +source [find target/stm32f2x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm3241g_eval.cfg b/openocd-win/openocd/scripts/board/stm3241g_eval.cfg new file mode 100644 index 0000000..7df373f --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3241g_eval.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6 +# (1024KB) chip. +# http://www.st.com/internet/evalboard/product/252216.jsp + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F417IGH6 + +source [find target/stm32f4x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm3241g_eval_stlink.cfg b/openocd-win/openocd/scripts/board/stm3241g_eval_stlink.cfg new file mode 100644 index 0000000..d2d5790 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm3241g_eval_stlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6 +# (1024KB) chip. +# http://www.st.com/internet/evalboard/product/252216.jsp +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F417IGH6 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32429i_eval.cfg b/openocd-win/openocd/scripts/board/stm32429i_eval.cfg new file mode 100644 index 0000000..3304ef6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32429i_eval.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6 +# (2048KB) chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093 + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F429NIH6 + +source [find target/stm32f4x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm32429i_eval_stlink.cfg b/openocd-win/openocd/scripts/board/stm32429i_eval_stlink.cfg new file mode 100644 index 0000000..be3c482 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32429i_eval_stlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6 +# (2048KB) chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093 +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F429NIH6 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32439i_eval.cfg b/openocd-win/openocd/scripts/board/stm32439i_eval.cfg new file mode 100644 index 0000000..c29d4de --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32439i_eval.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6 +# (2048KB) chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094 + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F439NIH6 + +source [find target/stm32f4x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm32439i_eval_stlink.cfg b/openocd-win/openocd/scripts/board/stm32439i_eval_stlink.cfg new file mode 100644 index 0000000..7a1a396 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32439i_eval_stlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6 +# (2048KB) chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094 +# +# This is for using the onboard STLINK/V2 + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# chip name +set CHIPNAME STM32F439NIH6 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm327x6g_eval.cfg b/openocd-win/openocd/scripts/board/stm327x6g_eval.cfg new file mode 100644 index 0000000..03fe949 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm327x6g_eval.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards. +# STM32746G-EVAL +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639 +# STM32756G-EVAL +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640 + +# increase working area to 256KB +set WORKAREASIZE 0x40000 + +source [find target/stm32f7x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f0discovery.cfg b/openocd-win/openocd/scripts/board/stm32f0discovery.cfg new file mode 100644 index 0000000..60fb4a6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f0discovery.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F0 discovery board with a single STM32F051R8T6 chip. +# http://www.st.com/internet/evalboard/product/253215.jsp + +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 +source [find target/stm32f0x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f103c8_blue_pill.cfg b/openocd-win/openocd/scripts/board/stm32f103c8_blue_pill.cfg new file mode 100644 index 0000000..0b84f72 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f103c8_blue_pill.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32F103C8 "Blue Pill" + +# NOTE: +# There is a fair bit of confusion about whether the "Blue Pill" has 128kB or 64kB flash size. +# The most likely cause is that there exist a -C8 and a -CB variant of the STM32F103, where +# the C8 has 64kB, the CB has 128kB as per specification. "Blue Pill" boards are manufactured +# by a lot of different vendors, some may actually use the CB variant but from a cursory look +# it very hard to tell them apart ("C8" and "CB" look very similar). Nevertheless, people have +# tried using the full 128kB of flash on the C8 and found it to be working. Hence this board file +# overrides the internal size detection. Be aware though that you may be using you particular +# board outside of its specification. If in doubt, comment the following line. +set FLASH_SIZE 0x20000 + +source [find target/stm32f1x.cfg] diff --git a/openocd-win/openocd/scripts/board/stm32f334discovery.cfg b/openocd-win/openocd/scripts/board/stm32f334discovery.cfg new file mode 100644 index 0000000..3ff2968 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f334discovery.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F334 discovery board with a single STM32F334C8T6 chip. +# As it is one of the few boards with stlink V.2-1, we source the corresponding +# nucleo file. +# http://www.st.com/web/en/catalog/tools/FM116/SC959/SS1532/LN1848/PF260318 + +source [find board/st_nucleo_f3.cfg] diff --git a/openocd-win/openocd/scripts/board/stm32f3discovery.cfg b/openocd-win/openocd/scripts/board/stm32f3discovery.cfg new file mode 100644 index 0000000..f28e11f --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f3discovery.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F3 discovery board with a single STM32F303VCT6 chip. +# http://www.st.com/internet/evalboard/product/254044.jsp + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f3x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f412g-disco.cfg b/openocd-win/openocd/scripts/board/stm32f412g-disco.cfg new file mode 100644 index 0000000..757b25d --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f412g-disco.cfg @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip. +# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000000FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0 + + # PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V + + # Port B: PB02:AF09:V + mmw 0x40020400 0x00000020 0x00000010 ;# MODER + mmw 0x40020408 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x00000900 0x00000600 ;# AFRL + + # Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V + mmw 0x40021400 0x000AA000 0x00055000 ;# MODER + mmw 0x40021408 0x000FF000 0x00000000 ;# OSPEEDR + mmw 0x40021420 0x99000000 0x66000000 ;# AFRL + mmw 0x40021424 0x000000AA 0x00000055 ;# AFRH + + # Port G: PG06:AF10:V + mmw 0x40021800 0x00002000 0x00001000 ;# MODER + mmw 0x40021808 0x00003000 0x00000000 ;# OSPEEDR + mmw 0x40021820 0x0A000000 0x05000000 ;# AFRL + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000003 ;# 3 WS for 96 MHz HCLK + sleep 1 + mww 0x40023804 0x24001808 ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2 + mww 0x40023808 0x00001000 ;# APB1: /2, APB2: /1 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f413h-disco.cfg b/openocd-win/openocd/scripts/board/stm32f413h-disco.cfg new file mode 100644 index 0000000..6abf495 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f413h-disco.cfg @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip. +# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html + +# +# Untested!!! +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000000FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0 + + # PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V + + # Port B: PB02:AF09:V + mmw 0x40020400 0x00000020 0x00000010 ;# MODER + mmw 0x40020408 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x00000900 0x00000600 ;# AFRL + + # Port D: PD13:AF09:V + mmw 0x40020C00 0x08000000 0x04000000 ;# MODER + mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR + mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH + + # Port E: PE02:AF09:V + mmw 0x40021000 0x00000020 0x00000010 ;# MODER + mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40021020 0x00000900 0x00000600 ;# AFRL + + # Port F: PF09:AF10:V, PF08:AF10:V + mmw 0x40021400 0x000A0000 0x00050000 ;# MODER + mmw 0x40021408 0x000F0000 0x00000000 ;# OSPEEDR + mmw 0x40021424 0x000000AA 0x00000055 ;# AFRH + + # Port G: PG06:AF10:V + mmw 0x40021800 0x00002000 0x00001000 ;# MODER + mmw 0x40021808 0x00003000 0x00000000 ;# OSPEEDR + mmw 0x40021820 0x0A000000 0x05000000 ;# AFRL + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000003 ;# 3 WS for 96 MHz HCLK + sleep 1 + mww 0x40023804 0x24001808 ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2 + mww 0x40023808 0x00001000 ;# APB1: /2, APB2: /1 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f429disc1.cfg b/openocd-win/openocd/scripts/board/stm32f429disc1.cfg new file mode 100644 index 0000000..657aa19 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f429disc1.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is an STM32F429 discovery board with a single STM32F429ZI chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f429discovery.cfg b/openocd-win/openocd/scripts/board/stm32f429discovery.cfg new file mode 100644 index 0000000..d1b5f5a --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f429discovery.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is an STM32F429 discovery board with a single STM32F429ZI chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f469discovery.cfg b/openocd-win/openocd/scripts/board/stm32f469discovery.cfg new file mode 100644 index 0000000..cca25b7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f469discovery.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is an STM32F469 discovery board with a single STM32F469NI chip. +# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f469i-disco.cfg b/openocd-win/openocd/scripts/board/stm32f469i-disco.cfg new file mode 100644 index 0000000..7ce57f6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f469i-disco.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F469I discovery board with a single STM32F469NIH6 chip. +# http://www.st.com/en/evaluation-tools/32f469idiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PF10: CLK, PB06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0 + + # PB06:AF10:V, PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V + + # Port B: PB06:AF10:V + mmw 0x40020400 0x00002000 0x00001000 ;# MODER + mmw 0x40020408 0x00003000 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x0A000000 0x05000000 ;# AFRL + + # Port F: PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V + mmw 0x40021400 0x002AA000 0x00155000 ;# MODER + mmw 0x40021408 0x003FF000 0x00000000 ;# OSPEEDR + mmw 0x40021420 0x99000000 0x66000000 ;# AFRL + mmw 0x40021424 0x000009AA 0x00000655 ;# AFRH + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000005 ;# 5 WS for 160 MHz HCLK + sleep 1 + mww 0x40023804 0x24002808 ;# 160 MHz: HSI, PLLM=8, PLLN=160, PLLP=2 + mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f4discovery.cfg b/openocd-win/openocd/scripts/board/stm32f4discovery.cfg new file mode 100644 index 0000000..714f1e9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f4discovery.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F4 discovery board with a single STM32F407VGT6 chip. +# http://www.st.com/internet/evalboard/product/252419.jsp + +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 64KB +set WORKAREASIZE 0x10000 + +source [find target/stm32f4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32f723e-disco.cfg b/openocd-win/openocd/scripts/board/stm32f723e-disco.cfg new file mode 100644 index 0000000..2dee2f9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f723e-disco.cfg @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F723E discovery board with a single STM32F723IEK6 chip. +# http://www.st.com/en/evaluation-tools/32f723ediscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 128KB +set WORKAREASIZE 0x20000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f7x.cfg] + +reset_config srst_only + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0 + + # PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V + + # Port B: PB06:AF10:V, PB02:AF09:V + mmw 0x40020400 0x00002020 0x00001010 ;# MODER + mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL + + # Port C: PC10:AF09:V, PC09:AF09:V + mmw 0x40020800 0x00280000 0x00140000 ;# MODER + mmw 0x40020808 0x003C0000 0x00000000 ;# OSPEEDR + mmw 0x40020824 0x00000990 0x00000660 ;# AFRH + + # Port D: PD13:AF09:V + mmw 0x40020C00 0x08000000 0x04000000 ;# MODER + mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR + mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH + + # Port E: PE02:AF09:V + mmw 0x40021000 0x00000020 0x00000010 ;# MODER + mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40021020 0x00000900 0x00000600 ;# AFRL + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00190100 ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 4-byte addresses + mww 0xA0001014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK + sleep 1 + mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2 + mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f746g-disco.cfg b/openocd-win/openocd/scripts/board/stm32f746g-disco.cfg new file mode 100644 index 0000000..fed1d8e --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f746g-disco.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F746G discovery board with a single STM32F746NGH6 chip. +# http://www.st.com/en/evaluation-tools/32f746gdiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 256KB +set WORKAREASIZE 0x40000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f7x.cfg] + +reset_config srst_only + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0 + + # PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V + + # Port B: PB06:AF10:V, PB02:AF09:V + mmw 0x40020400 0x00002020 0x00001010 ;# MODER + mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL + + # Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V + mmw 0x40020C00 0x0A800000 0x05400000 ;# MODER + mmw 0x40020C08 0x0FC00000 0x00000000 ;# OSPEEDR + mmw 0x40020C24 0x00999000 0x00666000 ;# AFRH + + # Port E: PE02:AF09:V + mmw 0x40021000 0x00000020 0x00000010 ;# MODER + mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40021020 0x00000900 0x00000600 ;# AFRL + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK + sleep 1 + mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2 + mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f769i-disco.cfg b/openocd-win/openocd/scripts/board/stm32f769i-disco.cfg new file mode 100644 index 0000000..2969bb9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f769i-disco.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F769I discovery board with a single STM32F769NIH6 chip. +# http://www.st.com/en/evaluation-tools/32f769idiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 256KB +set WORKAREASIZE 0x40000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32f7x.cfg] + +reset_config srst_only + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0 + + # PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V + + # Port B: PB06:AF10:V, PB02:AF09:V + mmw 0x40020400 0x00002020 0x00001010 ;# MODER + mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR + mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL + + # Port C: PC10:AF09:V, PC09:AF09:V + mmw 0x40020800 0x00280000 0x00140000 ;# MODER + mmw 0x40020808 0x003C0000 0x00000000 ;# OSPEEDR + mmw 0x40020824 0x00000990 0x00000660 ;# AFRH + + # Port D: PD13:AF09:V + mmw 0x40020C00 0x08000000 0x04000000 ;# MODER + mmw 0x40020C08 0x0C000000 0x00000000 ;# OSPEEDR + mmw 0x40020C24 0x00900000 0x00600000 ;# AFRH + + # Port E: PE02:AF09:V + mmw 0x40021000 0x00000020 0x00000010 ;# MODER + mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x40021020 0x00000900 0x00000600 ;# AFRL + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00190100 ;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # exit qpi mode + mww 0xA0001014 0x000033f5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + + # 1-line memory-mapped read mode with 4-byte addresses + mww 0xA0001014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ + + # 4-line qpi mode + mww 0xA0001014 0x00003135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=EQIO + + # 4-line memory-mapped read mode with 4-byte addresses + mww 0xA0001014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0xA, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=4READ4B +} + +$_TARGETNAME configure -event reset-init { + mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK + sleep 1 + mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2 + mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2 + mmw 0x40023800 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32f7discovery.cfg b/openocd-win/openocd/scripts/board/stm32f7discovery.cfg new file mode 100644 index 0000000..4cc22ea --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32f7discovery.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32F7 discovery board with a single STM32F756NGH6 chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641 + +# This is for using the onboard STLINK/V2-1 +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 256KB +set WORKAREASIZE 0x40000 + +source [find target/stm32f7x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32h735g-disco.cfg b/openocd-win/openocd/scripts/board/stm32h735g-disco.cfg new file mode 100644 index 0000000..4097ae2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h735g-disco.cfg @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a stm32h735g-dk with a single STM32H735IGK6 chip. +# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +set CHIPNAME stm32h735igk6 + +# enable stmqspi +if {![info exists OCTOSPI1]} { + set OCTOSPI1 1 + set OCTOSPI2 0 +} + +source [find target/stm32h7x.cfg] + +reset_config srst_only + +# OCTOSPI initialization +# octo: 8-line mode +proc octospi_init { octo } { + global a b + mmw 0x58024540 0x000006FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x58024534 0x00284000 0 ;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks) + sleep 1 ;# Wait for clock startup + + mww 0x5200B404 0x03010111 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1 + mww 0x5200B408 0x00000000 ;# OCTOSPIM_P2CR: disable Port 2 + + # PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5, + # PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0 + + # PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V + # PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V + # Port B: PB02:AF10:V + mmw 0x58020400 0x00000020 0x00000010 ;# MODER + mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x5802040C 0x00000000 0x00000030 ;# PUPDR + mmw 0x58020420 0x00000A00 0x00000500 ;# AFRL + # Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V + mmw 0x58020C00 0x0A808A00 0x05404500 ;# MODER + mmw 0x58020C08 0x0FC0CF00 0x00000000 ;# OSPEEDR + mmw 0x58020C0C 0x00000000 0x0FC0CF00 ;# PUPDR + mmw 0x58020C20 0xA0AA0000 0x50550000 ;# AFRL + mmw 0x58020C24 0x00999000 0x00666000 ;# AFRH + # Port E: PE02:AF09:V + mmw 0x58021000 0x00000020 0x00000010 ;# MODER + mmw 0x58021008 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x5802100C 0x00000000 0x00000030 ;# PUPDR + mmw 0x58021020 0x00000900 0x00000600 ;# AFRL + # Port F: PF10:AF09:V + mmw 0x58021400 0x00200000 0x00100000 ;# MODER + mmw 0x58021408 0x00300000 0x00000000 ;# OSPEEDR + mmw 0x5802140C 0x00000000 0x00300000 ;# PUPDR + mmw 0x58021424 0x00000900 0x00000600 ;# AFRH + # Port G: PG09:AF09:V, PG06:AF10:V + mmw 0x58021800 0x00082000 0x00041000 ;# MODER + mmw 0x58021808 0x000C3000 0x00000000 ;# OSPEEDR + mmw 0x5802180C 0x00000000 0x000C3000 ;# PUPDR + mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL + mmw 0x58021824 0x00000090 0x00000060 ;# AFRH + + # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses + mww 0x52005130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0 + mww 0x52005008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0 + mww 0x5200500C 0x00000005 ;# OCTOSPI_DCR2: PRESCALER=5 + + mww 0x52005108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0 + mww 0x52005100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1 + mww 0x52005110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B + + flash probe $a ;# load configuration from CR, TCR, CCR, IR register values + + if { $octo == 1 } { + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 ;# Read Status Register + stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable + + # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses + mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1 + mww 0x52005108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6 + mww 0x52005100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4 + mww 0x52005110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read + + flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values + + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 0 0x04 ;# Write Disable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + } +} + +$_CHIPNAME.cpu0 configure -event reset-init { + global OCTOSPI1 + global OCTOSPI2 + + mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK + + mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on + mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock + mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1 + mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2 + mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2 + mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI + mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide + mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24 + mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1 + sleep 1 + mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock + sleep 1 + + adapter speed 24000 + + if { $OCTOSPI1 } { + octospi_init 1 + } +} diff --git a/openocd-win/openocd/scripts/board/stm32h745i-disco.cfg b/openocd-win/openocd/scripts/board/stm32h745i-disco.cfg new file mode 100644 index 0000000..1c0bc67 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h745i-disco.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a stm32h745i-disco with a single STM32H745XIH6 chip. +# www.st.com/en/product/stm32h745i-disco.html +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +set CHIPNAME stm32h745xih6 + +# enable stmqspi +if {![info exists QUADSPI]} { + set QUADSPI 1 +} + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only + +source [find board/stm32h7x_dual_qspi.cfg] + +$_CHIPNAME.cpu0 configure -event reset-init { + global QUADSPI + + mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK + + mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on + mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock + mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1 + mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2 + mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2 + mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI + mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide + mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24 + mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1 + sleep 1 + mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock + sleep 1 + + adapter speed 24000 + + if { $QUADSPI } { + qspi_init 1 + } +} + diff --git a/openocd-win/openocd/scripts/board/stm32h747i-disco.cfg b/openocd-win/openocd/scripts/board/stm32h747i-disco.cfg new file mode 100644 index 0000000..e0a348e --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h747i-disco.cfg @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a stm32h747i-disco with a single STM32H747XIH6 chip. +# www.st.com/en/product/stm32h747i-disco.html +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +set CHIPNAME stm32h747xih6 + +# enable stmqspi +if {![info exists QUADSPI]} { + set QUADSPI 1 +} + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only + +# QUADSPI initialization +# qpi: 4-line mode +proc qspi_init { qpi } { + global a + mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0, + # PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0 + + # PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H + # PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V + + # Port B: PB02:AF09:V + mmw 0x58020400 0x00000020 0x00000010 ;# MODER + mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x58020420 0x00000900 0x00000600 ;# AFRL + # Port D: PD11:AF09:V + mmw 0x58020C00 0x00800000 0x00400000 ;# MODER + mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR + mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH + # Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V + mmw 0x58021400 0x0008A000 0x00045000 ;# MODER + mmw 0x58021408 0x000CF000 0x00000000 ;# OSPEEDR + mmw 0x58021420 0x99000000 0x66000000 ;# AFRL + mmw 0x58021424 0x000000A0 0x00000050 ;# AFRH + # Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H + mmw 0x58021800 0x20082000 0x10041000 ;# MODER + mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR + mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL + mmw 0x58021824 0x09000090 0x06000060 ;# AFRH + # Port H: PH03:AF09:V, PH02:AF09:V + mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER + mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR + mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL + + # correct FSIZE is 0x1A, however, this causes trouble when + # reading the last bytes at end of bank in *memory mapped* mode + + # for dual flash mode 2 * mt25ql512 + mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1 + mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0 + + mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1 + mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # Exit QPI mode + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI + sleep 1 + + if { $qpi == 1 } { + # Write Enable + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable + sleep 1 + + # Configure dummy clocks via volatile configuration register + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes + mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg. + mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks + sleep 1 + + # Write Enable + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable + sleep 1 + + # Enable QPI mode via enhanced volatile configuration register + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes + mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg. + mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode + sleep 1 + + # Enter QPI mode + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI + sleep 1 + + # memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only) + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ + } else { + # memory-mapped read mode with 4-byte addresses + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ + } +} + +$_CHIPNAME.cpu0 configure -event reset-init { + global QUADSPI + + mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK + + mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on + mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock + mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1 + mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2 + mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2 + mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI + mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide + mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24 + mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1 + sleep 1 + mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock + sleep 1 + + adapter speed 24000 + + if { $QUADSPI } { + qspi_init 1 + } +} + diff --git a/openocd-win/openocd/scripts/board/stm32h750b-disco.cfg b/openocd-win/openocd/scripts/board/stm32h750b-disco.cfg new file mode 100644 index 0000000..efb32b1 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h750b-disco.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a stm32h750b-dk with a single STM32H750XBH6 chip. +# www.st.com/en/product/stm32h750b-dk.html +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +set CHIPNAME stm32h750xbh6 + +# enable stmqspi +if {![info exists QUADSPI]} { + set QUADSPI 1 +} + +source [find target/stm32h7x.cfg] + +reset_config srst_only + +source [find board/stm32h7x_dual_qspi.cfg] + +$_CHIPNAME.cpu0 configure -event reset-init { + global QUADSPI + + mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK + + mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on + mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock + mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1 + mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2 + mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2 + mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI + mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide + mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24 + mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1 + sleep 1 + mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock + sleep 1 + + adapter speed 24000 + + if { $QUADSPI } { + qspi_init 1 + } +} + diff --git a/openocd-win/openocd/scripts/board/stm32h7b3i-disco.cfg b/openocd-win/openocd/scripts/board/stm32h7b3i-disco.cfg new file mode 100644 index 0000000..58ad9f7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h7b3i-disco.cfg @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip. +# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html +# + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +set CHIPNAME stm32h7b3lih6q + +# enable stmqspi +if {![info exists OCTOSPI1]} { + set OCTOSPI1 1 + set OCTOSPI2 0 +} + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only + +# OCTOSPI initialization +# octo: 8-line mode +proc octospi_init { octo } { + global a b + mmw 0x58024540 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x58024534 0x00284000 0 ;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks) + sleep 1 ;# Wait for clock startup + + mww 0x5200B404 0x03010111 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1 + mww 0x5200B408 0x00000000 ;# OCTOSPIM_P2CR: disable Port 2 + + # PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5, + # PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0 + + # PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V + # PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V + # Port B: PB02:AF09:V + mmw 0x58020400 0x00000020 0x00000010 ;# MODER + mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR + mmw 0x5802040C 0x00000000 0x00000030 ;# PUPDR + mmw 0x58020420 0x00000900 0x00000600 ;# AFRL + # Port C: PC05:AF10:V, PC01:AF10:V + mmw 0x58020800 0x00000808 0x00000404 ;# MODER + mmw 0x58020808 0x00000C0C 0x00000000 ;# OSPEEDR + mmw 0x5802080C 0x00000000 0x00000C0C ;# PUPDR + mmw 0x58020820 0x00A000A0 0x00500050 ;# AFRL + # Port D: PD11:AF09:V, PD07:AF10:V + mmw 0x58020C00 0x00808000 0x00404000 ;# MODER + mmw 0x58020C08 0x00C0C000 0x00000000 ;# OSPEEDR + mmw 0x58020C0C 0x00000000 0x00C0C000 ;# PUPDR + mmw 0x58020C20 0xA0000000 0x50000000 ;# AFRL + mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH + # Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V + mmw 0x58021400 0x0008A000 0x00045000 ;# MODER + mmw 0x58021408 0x000CF000 0x00000000 ;# OSPEEDR + mmw 0x5802140C 0x00000000 0x000CF000 ;# PUPDR + mmw 0x58021420 0xAA000000 0x55000000 ;# AFRL + mmw 0x58021424 0x000000A0 0x00000050 ;# AFRH + # Port G: PG09:AF09:V, PG06:AF10:V + mmw 0x58021800 0x00082000 0x00041000 ;# MODER + mmw 0x58021808 0x000C3000 0x00000000 ;# OSPEEDR + mmw 0x5802180C 0x00000000 0x000C3000 ;# PUPDR + mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL + mmw 0x58021824 0x00000090 0x00000060 ;# AFRH + # Port H: PH03:AF09:V + mmw 0x58021C00 0x00000080 0x00000040 ;# MODER + mmw 0x58021C08 0x000000C0 0x00000000 ;# OSPEEDR + mmw 0x58021C0C 0x00000000 0x000000C0 ;# PUPDR + mmw 0x58021C20 0x00009000 0x00006000 ;# AFRL + + # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses + mww 0x52005130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0 + mww 0x52005008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0 + mww 0x5200500C 0x00000005 ;# OCTOSPI_DCR2: PRESCALER=5 + + mww 0x52005108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0 + mww 0x52005100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1 + mww 0x52005110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B + + flash probe $a ;# load configuration from CR, TCR, CCR, IR register values + + if { $octo == 1 } { + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 ;# Read Status Register + stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable + + # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses + mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1 + mww 0x52005108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6 + mww 0x52005100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4 + mww 0x52005110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read + + flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values + + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 0 0x04 ;# Write Disable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + } +} + +$_CHIPNAME.cpu0 configure -event reset-init { + global OCTOSPI1 + global OCTOSPI2 + + mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK + + mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on + mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock + mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1 + mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2 + mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2 + mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI + mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide + mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24 + mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1 + sleep 1 + mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock + sleep 1 + + adapter speed 24000 + + if { $OCTOSPI1 } { + octospi_init 1 + } +} diff --git a/openocd-win/openocd/scripts/board/stm32h7x3i_eval.cfg b/openocd-win/openocd/scripts/board/stm32h7x3i_eval.cfg new file mode 100644 index 0000000..b9c4c74 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h7x3i_eval.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards. +# This is an ST EVAL-H743XI board with single STM32H743XI chip. +# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html +# This is an ST EVAL-H753XI board with single STM32H753XI chip. +# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32h7x_dual_qspi.cfg b/openocd-win/openocd/scripts/board/stm32h7x_dual_qspi.cfg new file mode 100644 index 0000000..0349fad --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32h7x_dual_qspi.cfg @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# stm32h754i-disco and stm32h750b-dk dual quad qspi. + +# QUADSPI initialization +# qpi: 4-line mode +proc qspi_init { qpi } { + global a + mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks) + mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0, + # PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0 + + # PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H + # PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V + + # Port D: PD11:AF09:V + mmw 0x58020C00 0x00800000 0x00400000 ;# MODER + mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR + mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH + # Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V + mmw 0x58021400 0x0028A000 0x00145000 ;# MODER + mmw 0x58021408 0x003CF000 0x00000000 ;# OSPEEDR + mmw 0x58021420 0x99000000 0x66000000 ;# AFRL + mmw 0x58021424 0x000009A0 0x00000650 ;# AFRH + # Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H + mmw 0x58021800 0x20082000 0x10041000 ;# MODER + mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR + mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL + mmw 0x58021824 0x09000090 0x06000060 ;# AFRH + # Port H: PH03:AF09:V, PH02:AF09:V + mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER + mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR + mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL + + # correct FSIZE is 0x1A, however, this causes trouble when + # reading the last bytes at end of bank in *memory mapped* mode + + # for dual flash mode 2 * mt25ql512 + mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1 + mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0 + + mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1 + mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # Exit QPI mode + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI + sleep 1 + + if { $qpi == 1 } { + # Write Enable + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable + sleep 1 + + # Configure dummy clocks via volatile configuration register + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes + mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg. + mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks + sleep 1 + + # Write Enable + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable + sleep 1 + + # Enable QPI mode via enhanced volatile configuration register + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes + mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg. + mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode + sleep 1 + + # Enter QPI mode + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI + sleep 1 + + # memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only) + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ + } else { + # memory-mapped read mode with 4-byte addresses + mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1 + mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ + } +} diff --git a/openocd-win/openocd/scripts/board/stm32l0discovery.cfg b/openocd-win/openocd/scripts/board/stm32l0discovery.cfg new file mode 100644 index 0000000..c711d9c --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l0discovery.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32L053 discovery board with a single STM32L053 chip. +# http://www.st.com/web/en/catalog/tools/PF260319 + +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 +source [find target/stm32l0.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32l476g-disco.cfg b/openocd-win/openocd/scripts/board/stm32l476g-disco.cfg new file mode 100644 index 0000000..a32d20f --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l476g-disco.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32L476G discovery board with a single STM32L476VGT6 chip. +# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 96KB +set WORKAREASIZE 0x18000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32l4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x4002104C 0x000001FF 0 ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks) + mmw 0x40021050 0x00000100 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0 + + # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V + + # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V + mmw 0x48001000 0xAAA00000 0x55500000 ;# MODER + mmw 0x48001008 0xFFF00000 0x00000000 ;# OSPEEDR + mmw 0x48001024 0xAAAAAA00 0x55555500 ;# AFRH + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x01500008 ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mmw 0x40022000 0x00000004 0x00000003 ;# 4 WS for 72 MHz HCLK + sleep 1 + mmw 0x40021000 0x00000100 0x00000000 ;# HSI on + mww 0x4002100C 0x01002432 ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI + mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1 + mmw 0x40021000 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32l496g-disco.cfg b/openocd-win/openocd/scripts/board/stm32l496g-disco.cfg new file mode 100644 index 0000000..1ba2299 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l496g-disco.cfg @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32L496G discovery board with a single STM32L496AGI6 chip. +# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 96KB +set WORKAREASIZE 0x18000 + +# enable stmqspi +set QUADSPI 1 + +source [find target/stm32l4x.cfg] + +# QUADSPI initialization +proc qspi_init { } { + global a + mmw 0x4002104C 0x000001FF 0 ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks) + mmw 0x40021050 0x00000100 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock) + sleep 1 ;# Wait for clock startup + + # PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0 + + # PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V + + # Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V + mmw 0x48000000 0x0000A080 0x00005040 ;# MODER + mmw 0x48000008 0x0000F0C0 0x00000000 ;# OSPEEDR + mmw 0x48000020 0xAA00A000 0x55005000 ;# AFRL + + # Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V + mmw 0x48000400 0x0080000A 0x00400005 ;# MODER + mmw 0x48000408 0x00C0000F 0x00000000 ;# OSPEEDR + mmw 0x48000420 0x000000AA 0x00000055 ;# AFRL + mmw 0x48000424 0x0000A000 0x00005000 ;# AFRH + + mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x01500008 ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1 + mww 0xA0001004 0x00160100 ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0 + mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1 + + # 1-line spi mode + mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO + sleep 1 + + # memory-mapped read mode with 3-byte addresses + mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ +} + +$_TARGETNAME configure -event reset-init { + mmw 0x40022000 0x00000004 0x00000003 ;# 4 WS for 72 MHz HCLK + sleep 1 + mmw 0x40021000 0x00000100 0x00000000 ;# HSI on + mww 0x4002100C 0x01002432 ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI + mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1 + mmw 0x40021000 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + qspi_init +} diff --git a/openocd-win/openocd/scripts/board/stm32l4discovery.cfg b/openocd-win/openocd/scripts/board/stm32l4discovery.cfg new file mode 100644 index 0000000..f089550 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l4discovery.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Explicitly for the STM32L476 discovery board: +# http://www.st.com/web/en/catalog/tools/PF261635 +# but perfectly functional for any other STM32L4 board connected via +# an stlink-v2-1 interface. +# This is for STM32L4 boards that are connected via stlink-v2-1. + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l4x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32l4p5g-disco.cfg b/openocd-win/openocd/scripts/board/stm32l4p5g-disco.cfg new file mode 100644 index 0000000..20d781a --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l4p5g-disco.cfg @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip. +# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 96KB +set WORKAREASIZE 0x18000 + +# enable stmqspi +set OCTOSPI1 1 +set OCTOSPI2 0 + +source [find target/stm32l4x.cfg] + +# OCTOSPI initialization +# octo: 8-line mode +proc octospi_init { octo } { + global a b + mmw 0x4002104C 0x001001FF 0 ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks) + mmw 0x40021050 0x00000300 0 ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks) + mmw 0x40021058 0x10000000 0 ;# RCC_APB1ENR1 |= PWREN (enable clock) + sleep 1 ;# Wait for clock startup + + mmw 0x40007004 0x00000200 0 ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432) + + mww 0x50061C04 0x07050333 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2 + mww 0x50061C08 0x03010111 ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1 + + # PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5 + # PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0 + + # PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V + # PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V + + # Port A: PA07:AF10:V, PA06:AF10:V + mmw 0x48000000 0x0000A000 0x00005000 ;# MODER + mmw 0x48000008 0x0000F000 0x00000000 ;# OSPEEDR + mmw 0x4800000C 0x00000000 0x0000F000 ;# PUPDR + mmw 0x48000020 0xAA000000 0x55000000 ;# AFRL + # Port C: PC03:AF10:V + mmw 0x48000800 0x00000080 0x00000040 ;# MODER + mmw 0x48000808 0x000000C0 0x00000000 ;# OSPEEDR + mmw 0x4800080C 0x00000000 0x000000C0 ;# PUPDR + mmw 0x48000820 0x0000A000 0x00005000 ;# AFRL + # Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V + mmw 0x48000C00 0x00008A00 0x00004500 ;# MODER + mmw 0x48000C08 0x0000CF00 0x00000000 ;# OSPEEDR + mmw 0x48000C0C 0x00000000 0x0000CF00 ;# PUPDR + mmw 0x48000C20 0xA0AA0000 0x50550000 ;# AFRL + # Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V + mmw 0x48001000 0x0AA00000 0x05500000 ;# MODER + mmw 0x48001008 0x0FF00000 0x00000000 ;# OSPEEDR + mmw 0x4800100C 0x00000000 0x0FF00000 ;# PUPDR + mmw 0x48001024 0x00AAAA00 0x00555500 ;# AFRH + # Port G: PG06:AF03:V + mmw 0x48001800 0x00002000 0x00001000 ;# MODER + mmw 0x48001808 0x00003000 0x00000000 ;# OSPEEDR + mmw 0x4800180C 0x00000000 0x00003000 ;# PUPDR + mmw 0x48001820 0x03000000 0x0C000000 ;# AFRL + + # PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5 + # PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0 + + # PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V + # PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V + + # Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V + mmw 0x48001400 0x020002AA 0x01000155 ;# MODER + mmw 0x48001408 0x030003FF 0x00000000 ;# OSPEEDR + mmw 0x4800140C 0x00000000 0x030003FF ;# PUPDR + mmw 0x48001420 0x00055555 0x000AAAAA ;# AFRL + mmw 0x48001424 0x00050000 0x000A0000 ;# AFRH + # Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V + mmw 0x48001800 0x0228000A 0x01140005 ;# MODER + mmw 0x48001808 0x033C000F 0x00000000 ;# OSPEEDR + mmw 0x4800180C 0x00000000 0x033C000F ;# PUPDR + mmw 0x48001820 0x00000055 0x000000AA ;# AFRL + mmw 0x48001824 0x00050550 0x000A0AA0 ;# AFRH + + # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses + mww 0xA0001130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0 + mww 0xA0001008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0 + mww 0xA000100C 0x00000001 ;# OCTOSPI_DCR2: PRESCALER=1 + + mww 0xA0001108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0 + mww 0xA0001100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1 + mww 0xA0001110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B + + if { $octo == 1 } { + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 ;# Read Status Register + stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable + + # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses + mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1 + mww 0xA0001108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6 + mww 0xA0001100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4 + mww 0xA0001110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read + + flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values + + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 0 0x04 ;# Write Disable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + } +} + +$_TARGETNAME configure -event reset-init { + mmw 0x40022000 0x00000003 0x0000000C ;# 3 WS for 72 MHz HCLK + sleep 1 + mmw 0x40021000 0x00000100 0x00000000 ;# HSI on + mww 0x4002100C 0x01002432 ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI + mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1 + mmw 0x40021000 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 24000 + + octospi_init 1 +} + diff --git a/openocd-win/openocd/scripts/board/stm32l4r9i-disco.cfg b/openocd-win/openocd/scripts/board/stm32l4r9i-disco.cfg new file mode 100644 index 0000000..f364ad3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32l4r9i-disco.cfg @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip. +# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html + +# This is for using the onboard STLINK +source [find interface/stlink.cfg] + +transport select hla_swd + +# increase working area to 96KB +set WORKAREASIZE 0x18000 + +# enable stmqspi +set OCTOSPI1 1 +set OCTOSPI2 0 + +source [find target/stm32l4x.cfg] + +# OCTOSPI initialization +# octo: 8-line mode +proc octospi_init { octo } { + global a b + mmw 0x4002104C 0x001001FF 0 ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks) + mmw 0x40021050 0x00000300 0 ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks) + mmw 0x40021058 0x10000000 0 ;# RCC_APB1ENR1 |= PWREN (enable clock) + sleep 1 ;# Wait for clock startup + + mmw 0x40007004 0x00000200 0 ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432) + + mww 0x50061C04 0x00000000 ;# OCTOSPIM_P1CR: disable Port 1 + mww 0x50061C08 0x03010111 ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1 + + # PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5, + # PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0 + + # PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V + # PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V + + # Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V + mmw 0x48001800 0x82280000 0x41140000 ;# MODER + mmw 0x48001808 0xC33C0000 0x00000000 ;# OSPEEDR + mmw 0x48001824 0x50050550 0xA00A0AA0 ;# AFRH + + # Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V + mmw 0x48001C00 0x002A0000 0x00150000 ;# MODER + mmw 0x48001C08 0x003F0000 0x00000000 ;# OSPEEDR + mmw 0x48001C24 0x00000555 0x00000AAA ;# AFRH + + # Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V + mmw 0x48002000 0x00A82000 0x00541000 ;# MODER + mmw 0x48002008 0x00FC3000 0x00000000 ;# OSPEEDR + mmw 0x48002020 0x05000000 0x0A000000 ;# AFRL + mmw 0x48002024 0x00005550 0x0000AAA0 ;# AFRH + + # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses + mww 0xA0001130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full + mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0 + mww 0xA0001008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0 + mww 0xA000100C 0x00000001 ;# OCTOSPI_DCR2: PRESCALER=1 + + mww 0xA0001108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0 + mww 0xA0001100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1 + mww 0xA0001110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B + + if { $octo == 1 } { + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 ;# Read Status Register + stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable + + # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses + mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1 + mww 0xA0001108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6 + mww 0xA0001100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4 + mww 0xA0001110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read + + flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values + + stmqspi cmd $a 0 0x06 ;# Write Enable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 0 0x04 ;# Write Disable + stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode) + stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits + } +} + +$_TARGETNAME configure -event reset-init { + mmw 0x40022000 0x00000003 0x0000000C ;# 3 WS for 72 MHz HCLK + sleep 1 + mmw 0x40021000 0x00000100 0x00000000 ;# HSI on + mww 0x4002100C 0x01002432 ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI + mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1 + mmw 0x40021000 0x01000000 0x00000000 ;# PLL on + sleep 1 + mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL + sleep 1 + + adapter speed 4000 + + octospi_init 1 +} diff --git a/openocd-win/openocd/scripts/board/stm32ldiscovery.cfg b/openocd-win/openocd/scripts/board/stm32ldiscovery.cfg new file mode 100644 index 0000000..d760eda --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32ldiscovery.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32L discovery board with a single STM32L152RBT6 chip. +# http://www.st.com/internet/evalboard/product/250990.jsp + +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x4000 +source [find target/stm32l1.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32mp13x_dk.cfg b/openocd-win/openocd/scripts/board/stm32mp13x_dk.cfg new file mode 100644 index 0000000..6328ddb --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32mp13x_dk.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# board MB1635x +# http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html + +source [find interface/stlink-dap.cfg] + +transport select dapdirect_swd + +source [find target/stm32mp13x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32mp15x_dk2.cfg b/openocd-win/openocd/scripts/board/stm32mp15x_dk2.cfg new file mode 100644 index 0000000..9503428 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32mp15x_dk2.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# board MB1272B +# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html +# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html + +source [find interface/stlink-dap.cfg] + +transport select dapdirect_swd + +source [find target/stm32mp15x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/stm32vldiscovery.cfg b/openocd-win/openocd/scripts/board/stm32vldiscovery.cfg new file mode 100644 index 0000000..30e35b9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/stm32vldiscovery.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is an STM32VL discovery board with a single STM32F100RB chip. +# http://www.st.com/internet/evalboard/product/250863.jsp + +source [find interface/stlink.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 +source [find target/stm32f1x.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/str910-eval.cfg b/openocd-win/openocd/scripts/board/str910-eval.cfg new file mode 100644 index 0000000..b6e9837 --- /dev/null +++ b/openocd-win/openocd/scripts/board/str910-eval.cfg @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# str910-eval eval board +# +# Need reset scripts +reset_config trst_and_srst + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists FLASHTAPID] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0x04570041 +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID + + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x1457f041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1 + +$_TARGETNAME configure -event reset-init { + # We can increase speed now that we know the target is halted. + #jtag_rclk 3000 + + # -- Enable 96K RAM + # PFQBC enabled / DTCM & AHB wait-states disabled + mww 0x5C002034 0x0191 + + str9x flash_config 0 4 2 0 0x80000 + flash protect 0 0 7 off +} + +#flash bank str9x <base> <size> 0 0 <target#> <variant> +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0 +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0 diff --git a/openocd-win/openocd/scripts/board/telo.cfg b/openocd-win/openocd/scripts/board/telo.cfg new file mode 100644 index 0000000..721c019 --- /dev/null +++ b/openocd-win/openocd/scripts/board/telo.cfg @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/c100.cfg] +# basic register definition for C100 +source [find target/c100regs.tcl] +# board-config info +source [find target/c100config.tcl] +# C100 helper functions +source [find target/c100helper.tcl] + + +# Telo board & C100 support trst and srst +# make the reset asserted to +# allow RC circuit to discharge for: [ms] +adapter srst pulse_width 100 +jtag_ntrst_assert_width 100 +# don't talk to JTAG after reset for: [ms] +adapter srst delay 100 +jtag_ntrst_delay 100 +reset_config trst_and_srst separate + + + + +# issue telnet: reset init +# issue gdb: monitor reset init +$_TARGETNAME configure -event reset-init { + adapter speed 100 + # this will setup Telo board + setupTelo + #turn up the JTAG speed + adapter speed 3000 + echo "JTAG speek now 3MHz" + echo "type helpC100 to get help on C100" +} + +$_TARGETNAME configure -event reset-deassert-post { + # Force target into ARM state. +# soft_reset_halt ;# not implemented on ARM11 + echo "Detected SRSRT asserted on C100.CPU" + +} + +$_TARGETNAME configure -event reset-assert-post { + echo "Assering reset" + #sleep 10 +} + +proc power_restore {} { echo "Sensed power restore. No action." } +proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } + + +# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus +# it's really 16MB but the upper 8mb is controller via gpio +# openocd does not support 'complex reads/writes' to NOR +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME + +# writing data to memory does not work without this +arm11 memwrite burst disable diff --git a/openocd-win/openocd/scripts/board/ti_am335xevm.cfg b/openocd-win/openocd/scripts/board/ti_am335xevm.cfg new file mode 100644 index 0000000..af058ec --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am335xevm.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI AM335x Evaluation Module +# +# For more information please see http://www.ti.com/tool/tmdxevm3358 +# +jtag_rclk 6000 + +source [find target/am335x.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/ti_am437x_idk.cfg b/openocd-win/openocd/scripts/board/ti_am437x_idk.cfg new file mode 100644 index 0000000..b427762 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am437x_idk.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Texas Instruments AM437x Industrial Development Kit + +# The JTAG interface is built directly on the board. +source [find interface/ftdi/xds100v2.cfg] + +transport select jtag +adapter speed 30000 + +source [find target/am437x.cfg] +$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 } + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/ti_am43xx_evm.cfg b/openocd-win/openocd/scripts/board/ti_am43xx_evm.cfg new file mode 100644 index 0000000..005421f --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am43xx_evm.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Works on both AM437x GP EVM and AM438x ePOS EVM +transport select jtag +adapter speed 16000 + +source [find target/am437x.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/ti_am625_swd_native.cfg b/openocd-win/openocd/scripts/board/ti_am625_swd_native.cfg new file mode 100644 index 0000000..dc4b205 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am625_swd_native.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am625 +# Link: https://www.ti.com/product/AM625 +# +# This configuration file is used as a self hosted debug configuration that +# works on every AM625 platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside AM625 and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem + +if { ![info exists SOC] } { + set SOC am625 +} + +source [find target/ti_k3.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_am625evm.cfg b/openocd-win/openocd/scripts/board/ti_am625evm.cfg new file mode 100644 index 0000000..4906fd0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am625evm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am625 EVM/SK +# Link: https://www.ti.com/lit/zip/sprr448 +# + +# AM625 EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am625 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_am62a7evm.cfg b/openocd-win/openocd/scripts/board/ti_am62a7evm.cfg new file mode 100644 index 0000000..e407909 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am62a7evm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments am62a7 EVM/SK +# Link: https://www.ti.com/tool/SK-AM62A-LP +# + +# AM62a7 EVM/SK has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am62a7 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_am642evm.cfg b/openocd-win/openocd/scripts/board/ti_am642evm.cfg new file mode 100644 index 0000000..e97fdcf --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am642evm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM642 EVM +# + +# AM642 EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC am642 +} + +source [find target/ti_k3.cfg] + +adapter speed 250 diff --git a/openocd-win/openocd/scripts/board/ti_am654evm.cfg b/openocd-win/openocd/scripts/board/ti_am654evm.cfg new file mode 100644 index 0000000..a661f60 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_am654evm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments AM654 EVM/IDK Base Board +# + +# AM654 EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 70 + +if { ![info exists SOC] } { + set SOC am654 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_beagleboard.cfg b/openocd-win/openocd/scripts/board/ti_beagleboard.cfg new file mode 100644 index 0000000..6767bd6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_beagleboard.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OMAP3 BeagleBoard +# http://beagleboard.org + +# Fall back to 6MHz if RTCK is not supported +jtag_rclk 6000 + +source [find target/omap3530.cfg] + +# TI-14 JTAG connector +reset_config trst_only + +# Later run: omap3_dbginit diff --git a/openocd-win/openocd/scripts/board/ti_beagleboard_xm.cfg b/openocd-win/openocd/scripts/board/ti_beagleboard_xm.cfg new file mode 100644 index 0000000..fd176a0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_beagleboard_xm.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BeagleBoard xM (DM37x) +# http://beagleboard.org + +set CHIPTYPE "dm37x" +source [find target/amdm37x.cfg] + +# The TI-14 JTAG connector does not have srst. CPU reset is handled in +# hardware. +reset_config trst_only + +# "amdm37x_dbginit dm37x.cpu" needs to be run after init. diff --git a/openocd-win/openocd/scripts/board/ti_beaglebone-base.cfg b/openocd-win/openocd/scripts/board/ti_beaglebone-base.cfg new file mode 100644 index 0000000..566f0a4 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_beaglebone-base.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# AM335x Beaglebone family base configuration +# http://beagleboard.org/bone + +source [find target/am335x.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_beaglebone.cfg b/openocd-win/openocd/scripts/board/ti_beaglebone.cfg new file mode 100644 index 0000000..d96e45f --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_beaglebone.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# AM335x Beaglebone +# http://beagleboard.org/bone + +# The JTAG interface is built directly on the board. +source [find interface/ftdi/xds100v2.cfg] + +adapter speed 16000 + +reset_config trst_and_srst + +source [find board/ti_beaglebone-base.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_beaglebone_black.cfg b/openocd-win/openocd/scripts/board/ti_beaglebone_black.cfg new file mode 100644 index 0000000..d72bf09 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_beaglebone_black.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# AM335x Beaglebone Black +# http://beagleboard.org/bone + +adapter speed 1000 + +reset_config trst_and_srst + +source [find board/ti_beaglebone-base.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_blaze.cfg b/openocd-win/openocd/scripts/board/ti_blaze.cfg new file mode 100644 index 0000000..e28b05b --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_blaze.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +jtag_rclk 6000 + +source [find target/omap4430.cfg] + +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/board/ti_cc13x0_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc13x0_launchpad.cfg new file mode 100644 index 0000000..f6dfbcd --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc13x0_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC13x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +transport select jtag +adapter speed 5500 +source [find target/ti_cc13x0.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_cc13x2_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc13x2_launchpad.cfg new file mode 100644 index 0000000..900842a --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc13x2_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC13x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 5500 +transport select jtag +source [find target/ti_cc13x2.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_cc26x0_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc26x0_launchpad.cfg new file mode 100644 index 0000000..431383d --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc26x0_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC26x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 5500 +transport select jtag +source [find target/ti_cc26x0.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_cc26x2_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc26x2_launchpad.cfg new file mode 100644 index 0000000..133f57e --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc26x2_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC26x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 5500 +transport select jtag +source [find target/ti_cc26x2.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_cc3200_launchxl.cfg b/openocd-win/openocd/scripts/board/ti_cc3200_launchxl.cfg new file mode 100644 index 0000000..5f39b8a --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc3200_launchxl.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI SimpleLink Wi-Fi CC3200 LaunchPad +# +# http://www.ti.com/tool/cc3200-launchxl +# + +source [find interface/ftdi/ti-icdi.cfg] + +if { [info exists TRANSPORT] } { + transport select $TRANSPORT +} else { + transport select jtag +} + +adapter speed 2500 + +set WORKAREASIZE 0x40000 +source [find target/ti_cc32xx.cfg] + +reset_config srst_only +adapter srst delay 1100 diff --git a/openocd-win/openocd/scripts/board/ti_cc3220sf_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc3220sf_launchpad.cfg new file mode 100644 index 0000000..fe34554 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc3220sf_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 8500 +transport select swd +source [find target/ti_cc3220sf.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_cc32xx_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_cc32xx_launchpad.cfg new file mode 100644 index 0000000..343da48 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_cc32xx_launchpad.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI CC32xx-LaunchXL LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 8500 +transport select swd +source [find target/ti_cc32xx.cfg] + +reset_config srst_only +adapter srst delay 1100 diff --git a/openocd-win/openocd/scripts/board/ti_dk-tm4c129.cfg b/openocd-win/openocd/scripts/board/ti_dk-tm4c129.cfg new file mode 100644 index 0000000..d8210e3 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_dk-tm4c129.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Tiva C DK-TM4C129X Connected Development Kit +# +# http://www.ti.com/tool/dk-tm4c129x +# + +source [find interface/ti-icdi.cfg] + +transport select hla_jtag + +set WORKAREASIZE 0x8000 +set CHIPNAME tm4c129xnczad + +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_ek-tm4c123gxl.cfg b/openocd-win/openocd/scripts/board/ti_ek-tm4c123gxl.cfg new file mode 100644 index 0000000..91390fa --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_ek-tm4c123gxl.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit +# +# http://www.ti.com/tool/ek-tm4c123gxl +# + +source [find interface/ti-icdi.cfg] + +transport select hla_jtag + +set WORKAREASIZE 0x8000 +set CHIPNAME tm4c123gh6pm +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_ek-tm4c1294xl.cfg b/openocd-win/openocd/scripts/board/ti_ek-tm4c1294xl.cfg new file mode 100644 index 0000000..63612c6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_ek-tm4c1294xl.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit +# +# http://www.ti.com/tool/ek-tm4c1294xl +# + +source [find interface/ti-icdi.cfg] + +transport select hla_jtag + +set WORKAREASIZE 0x8000 +set CHIPNAME tm4c1294ncpdt + +source [find target/stellaris.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_j7200evm.cfg b/openocd-win/openocd/scripts/board/ti_j7200evm.cfg new file mode 100644 index 0000000..cc70056 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_j7200evm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J7200 EVM +# + +# J7200 EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC j7200 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_j721e_swd_native.cfg b/openocd-win/openocd/scripts/board/ti_j721e_swd_native.cfg new file mode 100644 index 0000000..3041c3c --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_j721e_swd_native.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments TDA4VM/J721E +# Link: https://www.ti.com/product/TDA4VM +# +# This configuration file is used as a self hosted debug configuration that +# works on every TDA4VM platform based on firewall configuration permitted +# in the system. +# +# In this system openOCD runs on one of the CPUs inside TDA4VM and provides +# network ports that can then be used to debug the microcontrollers on the +# SoC - either self hosted IDE OR remotely. + +# We are using dmem, which uses dapdirect_swd transport +adapter driver dmem + +if { ![info exists SOC] } { + set SOC j721e +} +source [find target/ti_k3.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_j721evm.cfg b/openocd-win/openocd/scripts/board/ti_j721evm.cfg new file mode 100644 index 0000000..d0c4b74 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_j721evm.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J721E EVM +# + +# J721E EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC j721e +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_j721s2evm.cfg b/openocd-win/openocd/scripts/board/ti_j721s2evm.cfg new file mode 100644 index 0000000..72418b5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_j721s2evm.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments J721s2 EVM +# Link(SoM): https://www.ti.com/lit/zip/sprr439 +# + +# J721s2 EVM has an xds110 onboard. +source [find interface/xds110.cfg] + +transport select jtag + +# default JTAG configuration has only SRST and no TRST +reset_config srst_only srst_push_pull + +# delay after SRST goes inactive +adapter srst delay 20 + +if { ![info exists SOC] } { + set SOC j721s2 +} + +source [find target/ti_k3.cfg] + +adapter speed 2500 diff --git a/openocd-win/openocd/scripts/board/ti_msp432_launchpad.cfg b/openocd-win/openocd/scripts/board/ti_msp432_launchpad.cfg new file mode 100644 index 0000000..4832b83 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_msp432_launchpad.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI MSP432 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter speed 10000 +transport select swd +source [find target/ti_msp432.cfg] diff --git a/openocd-win/openocd/scripts/board/ti_pandaboard.cfg b/openocd-win/openocd/scripts/board/ti_pandaboard.cfg new file mode 100644 index 0000000..45092e0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_pandaboard.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +jtag_rclk 6000 + +source [find target/omap4430.cfg] + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/ti_pandaboard_es.cfg b/openocd-win/openocd/scripts/board/ti_pandaboard_es.cfg new file mode 100644 index 0000000..f837358 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_pandaboard_es.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +jtag_rclk 6000 + +source [find target/omap4460.cfg] + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/ti_tmdx570ls20susb.cfg b/openocd-win/openocd/scripts/board/ti_tmdx570ls20susb.cfg new file mode 100644 index 0000000..9c5ef74 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_tmdx570ls20susb.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TMS570 Microcontroller USB Kit +# http://www.ti.com/tool/TMDX570LS20SUSB + +# Board uses a FT2232H to emulate an XDS100v2 JTAG debugger +# TODO: board also supports an SCI UART on the 2232's B Bus +source [find interface/ftdi/xds100v2.cfg] + +# Processor is TMS570LS20216 +source [find target/ti_tms570ls20xxx.cfg] + +reset_config trst_only + +# xds100v2 config says add this to the end +init +ftdi set_signal PWR_RST 1 +jtag arp_init diff --git a/openocd-win/openocd/scripts/board/ti_tmdx570ls31usb.cfg b/openocd-win/openocd/scripts/board/ti_tmdx570ls31usb.cfg new file mode 100644 index 0000000..324f003 --- /dev/null +++ b/openocd-win/openocd/scripts/board/ti_tmdx570ls31usb.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter speed 1500 + +source [find interface/ftdi/xds100v2.cfg] +source [find target/ti_tms570.cfg] + +reset_config trst_only diff --git a/openocd-win/openocd/scripts/board/tocoding_poplar.cfg b/openocd-win/openocd/scripts/board/tocoding_poplar.cfg new file mode 100644 index 0000000..5f9dba4 --- /dev/null +++ b/openocd-win/openocd/scripts/board/tocoding_poplar.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# board configuration for Tocoding Poplar +# + +# board does not feature anything but JTAG +transport select jtag + +adapter speed 10000 + +# SRST-only reset configuration +reset_config srst_only srst_push_pull + +source [find target/hi3798.cfg] + +# make sure the default target is the boot core +targets ${_TARGETNAME}0 + +proc core_up { args } { + global _TARGETNAME + + # examine remaining cores + foreach _core $args { + ${_TARGETNAME}$_core arp_examine + } +} diff --git a/openocd-win/openocd/scripts/board/topas910.cfg b/openocd-win/openocd/scripts/board/topas910.cfg new file mode 100644 index 0000000..f45f6e7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/topas910.cfg @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Toshiba TOPAS910 -- TMPA910 Starterkit +# +###################################### + +# We add to the minimal configuration. +source [find target/tmpa910.cfg] + +###################### +# Target configuration +###################### + +#$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { topas910_init } + +proc topas910_init { } { +# Init PLL +# my settings + mww 0xf005000c 0x00000007 + mww 0xf0050010 0x00000065 + mww 0xf005000c 0x000000a7 + sleep 10 + mdw 0xf0050008 + mww 0xf0050008 0x00000002 + mww 0xf0050004 0x00000000 +# NEW: set CLKCR5 + mww 0xf0050054 0x00000040 +# + sleep 10 +# Init SDRAM +# _PMCDRV = 0x00000071; +# // +# // Initialize SDRAM timing parameter +# // +# _DMC_CAS_LATENCY = 0x00000006; +# _DMC_T_DQSS = 0x00000000; +# _DMC_T_MRD = 0x00000002; +# _DMC_T_RAS = 0x00000007; +# +# _DMC_T_RC = 0x0000000A; +# _DMC_T_RCD = 0x00000013; +# +# _DMC_T_RFC = 0x0000010A; +# +# _DMC_T_RP = 0x00000013; +# _DMC_T_RRD = 0x00000002; +# _DMC_T_WR = 0x00000002; +# _DMC_T_WTR = 0x00000001; +# _DMC_T_XP = 0x0000000A; +# _DMC_T_XSR = 0x0000000B; +# _DMC_T_ESR = 0x00000014; +# +# // +# // Configure SDRAM type parameter +# _DMC_MEMORY_CFG = 0x00008011; +# _DMC_USER_CONFIG = 0x00000011; +# // 32 bit memory interface +# +# +# _DMC_REFRESH_PRD = 0x00000A60; +# _DMC_CHIP_0_CFG = 0x000140FC; +# +# _DMC_DIRECT_CMD = 0x000C0000; +# _DMC_DIRECT_CMD = 0x00000000; +# +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00080031; +# // +# // Finally start SDRAM +# // +# _DMC_MEMC_CMD = MEMC_CMD_GO; +# */ + + mww 0xf0020260 0x00000071 + mww 0xf4300014 0x00000006 + mww 0xf4300018 0x00000000 + mww 0xf430001C 0x00000002 + mww 0xf4300020 0x00000007 + mww 0xf4300024 0x0000000A + mww 0xf4300028 0x00000013 + mww 0xf430002C 0x0000010A + mww 0xf4300030 0x00000013 + mww 0xf4300034 0x00000002 + mww 0xf4300038 0x00000002 + mww 0xf430003C 0x00000001 + mww 0xf4300040 0x0000000A + mww 0xf4300044 0x0000000B + mww 0xf4300048 0x00000014 + mww 0xf430000C 0x00008011 + mww 0xf4300304 0x00000011 + mww 0xf4300010 0x00000A60 + mww 0xf4300200 0x000140FC + mww 0xf4300008 0x000C0000 + mww 0xf4300008 0x00000000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00080031 + mww 0xf4300004 0x00000000 + + sleep 10 +# adapter speed NNNN + +# remap off in case of IROM boot + mww 0xf0000004 0x00000001 + +} + +# comment the following out if usinf J-Link, it soes not support DCC +arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + +##################### +# Flash configuration +##################### + +#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/topasa900.cfg b/openocd-win/openocd/scripts/board/topasa900.cfg new file mode 100644 index 0000000..d6ddc44 --- /dev/null +++ b/openocd-win/openocd/scripts/board/topasa900.cfg @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Thanks to Pieter Conradie for this script! +# Target: Toshiba TOPAS900 -- TMPA900 Starterkit +###################################### + +# We add to the minimal configuration. +source [find target/tmpa900.cfg] + +###################### +# Target configuration +###################### + +#$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { topasa900_init } + +proc topasa900_init { } { +# Init PLL +# my settings + mww 0xf005000c 0x00000007 + mww 0xf0050010 0x00000065 + mww 0xf005000c 0x000000a7 + sleep 10 + mdw 0xf0050008 + mww 0xf0050008 0x00000002 + mww 0xf0050004 0x00000000 +# NEW: set CLKCR5 + mww 0xf0050054 0x00000040 +# +# bplan settings +# mww 0xf0050004 0x00000000 +# mww 0xf005000c 0x000000a7 +# sleep 10 +# mdw 0xf0050008 +# mww 0xf0050008 0x00000002 +# mww 0xf0050010 0x00000065 +# mww 0xf0050054 0x00000040 + sleep 10 +# Init SDRAM +# _PMCDRV = 0x00000071; +# // +# // Initialize SDRAM timing parameter +# // +# _DMC_CAS_LATENCY = 0x00000006; +# _DMC_T_DQSS = 0x00000000; +# _DMC_T_MRD = 0x00000002; +# _DMC_T_RAS = 0x00000007; +# +# _DMC_T_RC = 0x0000000A; +# _DMC_T_RCD = 0x00000013; +# +# _DMC_T_RFC = 0x0000010A; +# +# _DMC_T_RP = 0x00000013; +# _DMC_T_RRD = 0x00000002; +# _DMC_T_WR = 0x00000002; +# _DMC_T_WTR = 0x00000001; +# _DMC_T_XP = 0x0000000A; +# _DMC_T_XSR = 0x0000000B; +# _DMC_T_ESR = 0x00000014; +# +# // +# // Configure SDRAM type parameter +# _DMC_MEMORY_CFG = 0x00008011; +# _DMC_USER_CONFIG = 0x00000011; // 32 bit memory interface +# +# +# _DMC_REFRESH_PRD = 0x00000A60; +# _DMC_CHIP_0_CFG = 0x000140FC; +# +# _DMC_DIRECT_CMD = 0x000C0000; +# _DMC_DIRECT_CMD = 0x00000000; +# +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00040000; +# _DMC_DIRECT_CMD = 0x00080031; +# // +# // Finally start SDRAM +# // +# _DMC_MEMC_CMD = MEMC_CMD_GO; +# */ + + mww 0xf0020260 0x00000071 + mww 0xf4300014 0x00000006 + mww 0xf4300018 0x00000000 + mww 0xf430001C 0x00000002 + mww 0xf4300020 0x00000007 + mww 0xf4300024 0x0000000A + mww 0xf4300028 0x00000013 + mww 0xf430002C 0x0000010A + mww 0xf4300030 0x00000013 + mww 0xf4300034 0x00000002 + mww 0xf4300038 0x00000002 + mww 0xf430003C 0x00000001 + mww 0xf4300040 0x0000000A + mww 0xf4300044 0x0000000B + mww 0xf4300048 0x00000014 + mww 0xf430000C 0x00008011 + mww 0xf4300304 0x00000011 + mww 0xf4300010 0x00000A60 + mww 0xf4300200 0x000140FC + mww 0xf4300008 0x000C0000 + mww 0xf4300008 0x00000000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00040000 + mww 0xf4300008 0x00080031 + mww 0xf4300004 0x00000000 + + sleep 10 +# adapter speed NNNN + +# remap off in case of IROM boot + mww 0xf0000004 0x00000001 + +} + +# comment the following out if usinf J-Link, it soes not support DCC +arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + +##################### +# Flash configuration +##################### + +#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/tp-link_tl-mr3020.cfg b/openocd-win/openocd/scripts/board/tp-link_tl-mr3020.cfg new file mode 100644 index 0000000..1d1d627 --- /dev/null +++ b/openocd-win/openocd/scripts/board/tp-link_tl-mr3020.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/atheros_ar9331.cfg] + +$_TARGETNAME configure -event reset-init { + ar9331_25mhz_pll_init + sleep 1 + ar9331_ddr1_init +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0 diff --git a/openocd-win/openocd/scripts/board/tp-link_wdr4300.cfg b/openocd-win/openocd/scripts/board/tp-link_wdr4300.cfg new file mode 100644 index 0000000..9947366 --- /dev/null +++ b/openocd-win/openocd/scripts/board/tp-link_wdr4300.cfg @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/atheros_ar9344.cfg] + +reset_config trst_only separate + +proc ar9344_40mhz_pll_init {} { + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0x13210f00 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0x13210f00 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_BB_DPLL_BASE_REG + mww 0xb8116188 0x03000000 + + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x0130001C + mww 0xb8050008 0x0130001C + mww 0xb8050008 0x0130001C + + # QCA_PLL_CPU_PLL_CFG_REG + mww 0xb8050000 0x40021380 + # QCA_PLL_DDR_PLL_CFG_REG + mww 0xb8050004 0x40815800 + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x0130801C + + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0x10810F00 + mww 0xb81161C0 0x41C00000 + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0xD0810F00 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0xD0800F00 + + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x43000000 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x030003E8 + + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0x10810F00 + mww 0xb8116240 0x41680000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0xD0810F00 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0xD0800F00 + + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x43000000 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000718 + + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x01308018 + mww 0xb8050008 0x01308010 + mww 0xb8050008 0x01308000 + + # QCA_PLL_DDR_PLL_DITHER_REG + mww 0xb8050044 0x78180200 + # QCA_PLL_CPU_PLL_DITHER_REG + mww 0xb8050048 0x41C00000 + +} + +proc ar9344_ddr_init {} { + # QCA_DDR_CTRL_CFG_REG + mww 0xb8000108 0x40 + # QCA_DDR_RD_DATA_THIS_CYCLE_REG + mww 0xb8000018 0xFF + # QCA_DDR_BURST_REG + mww 0xb80000C4 0x74444444 + # QCA_DDR_BURST2_REG + mww 0xb80000C8 0x0222 + # QCA_AHB_MASTER_TOUT_MAX_REG + mww 0xb80000CC 0xFFFFF + + # QCA_DDR_CFG_REG + mww 0xb8000000 0xC7D48CD0 + # QCA_DDR_CFG2_REG + mww 0xb8000004 0x9DD0E6A8 + + # QCA_DDR_DDR2_CFG_REG + mww 0xb80000B8 0x0E59 + # QCA_DDR_CFG2_REG + mww 0xb8000004 0x9DD0E6A8 + + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x08 + mww 0xb8000010 0x08 + mww 0xb8000010 0x10 + mww 0xb8000010 0x20 + # QCA_DDR_EMR_REG + mww 0xb800000C 0x02 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x02 + + # QCA_DDR_MR_REG + mww 0xb8000008 0x0133 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x1 + mww 0xb8000010 0x8 + mww 0xb8000010 0x8 + mww 0xb8000010 0x4 + mww 0xb8000010 0x4 + + # QCA_DDR_MR_REG + mww 0xb8000008 0x33 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x1 + + # QCA_DDR_EMR_REG + mww 0xb800000C 0x0382 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x2 + # QCA_DDR_EMR_REG + mww 0xb800000C 0x0402 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x2 + + # QCA_DDR_REFRESH_REG + mww 0xb8000014 0x4270 + + # QCA_DDR_TAP_CTRL_0_REG + mww 0xb800001C 0x0e + # QCA_DDR_TAP_CTRL_1_REG + mww 0xb8000020 0x0e + # QCA_DDR_TAP_CTRL_2_REG + mww 0xb8000024 0x0e + # QCA_DDR_TAP_CTRL_3_REG + mww 0xb8000028 0x0e +} + +$_TARGETNAME configure -event reset-init { + + # mww 0xb806001c 0x1000000 + ar9344_40mhz_pll_init + sleep 100 + + # flash remap + # SPI_CONTROL_ADDR + mww 0xbF000004 0x43 + + ar9344_ddr_init + sleep 100 +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000 + +flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0 diff --git a/openocd-win/openocd/scripts/board/trion_t20_bga256.cfg b/openocd-win/openocd/scripts/board/trion_t20_bga256.cfg new file mode 100644 index 0000000..045d63d --- /dev/null +++ b/openocd-win/openocd/scripts/board/trion_t20_bga256.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Trion® T20 BGA256 Development Kit +# https://www.efinixinc.com/docs/trion20-devkit-ug-v1.5.pdf +# +# works after power cycle or pushing sw1. +# it is because we cannot control CDONE which is connected to ftdi channel 0 +# note from an006: For JTAG programming, T4, T8, T13, and T20 FPGAs use the +# CRESET_N and SS_N pins in addition to the standard JTAG pins. + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 1 +ftdi layout_init 0x0008 0x008b +reset_config none +transport select jtag +adapter speed 6000 + +source [find fpga/efinix_trion.cfg] + +#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load 0 outflow/trion_blinker.bit" +#ipdbg -start -tap trion.tap -hub 0x8 -port 5555 -tool 0 + diff --git a/openocd-win/openocd/scripts/board/twr-k60f120m.cfg b/openocd-win/openocd/scripts/board/twr-k60f120m.cfg new file mode 100644 index 0000000..5914cf0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/twr-k60f120m.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale TWRK60F120M development board +# + +source [find target/k60.cfg] + +$_TARGETNAME configure -event reset-init { + puts "-event reset-init occurred" +} + +# +# Definitions for the additional 'program flash' banks +# (instructions and/or data) +# +flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME +flash bank pflash.2 kinetis 0x00080000 0x40000 0 4 $_TARGETNAME +flash bank pflash.3 kinetis 0x000c0000 0x40000 0 4 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/twr-k60n512.cfg b/openocd-win/openocd/scripts/board/twr-k60n512.cfg new file mode 100644 index 0000000..b7743a5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/twr-k60n512.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale TWRK60N512 development board +# + +source [find target/k60.cfg] + +$_TARGETNAME configure -event reset-init { + puts "-event reset-init occurred" +} + +# +# Definitions for the additional 'program flash' bank +# (instructions and/or data) +# +flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/twr-vf65gs10.cfg b/openocd-win/openocd/scripts/board/twr-vf65gs10.cfg new file mode 100644 index 0000000..bfc7288 --- /dev/null +++ b/openocd-win/openocd/scripts/board/twr-vf65gs10.cfg @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Board configuration file for the Freescale VF65GS10 tower board +# +# Board has a 20 pin Cortex+ETM debug connector with only nSRST available +reset_config srst_only + +# This configuration file only deals with the hardware JTAG. +# There is has also an embedded Kinetis K20 with OpenSDA +# where a CMSIS-DAP application can be installed. + +# Source generic VF6xx target configuration +source [find target/vybrid_vf6xx.cfg] + +# basic DDR memory init, setting up pad configuration +# for DDR first then configuring the DDRMC for the +# board +proc ddr_init { } { + # iomux ddr + mww phys 0x40048220 0x00000180 + mww phys 0x40048224 0x00000180 + mww phys 0x40048228 0x00000180 + mww phys 0x4004822c 0x00000180 + mww phys 0x40048230 0x00000180 + mww phys 0x40048234 0x00000180 + mww phys 0x40048238 0x00000180 + mww phys 0x4004823c 0x00000180 + mww phys 0x40048240 0x00000180 + mww phys 0x40048244 0x00000180 + mww phys 0x40048248 0x00000180 + mww phys 0x4004824c 0x00000180 + mww phys 0x40048250 0x00000180 + mww phys 0x40048254 0x00000180 + mww phys 0x40048258 0x00000180 + mww phys 0x4004825c 0x00000180 + mww phys 0x40048260 0x00000180 + mww phys 0x40048264 0x00000180 + mww phys 0x40048268 0x00000180 + mww phys 0x4004826c 0x00000180 + mww phys 0x40048270 0x00000180 + mww phys 0x40048274 0x00000180 + mww phys 0x40048278 0x00000180 + mww phys 0x4004827c 0x00010180 + mww phys 0x40048280 0x00010180 + mww phys 0x40048284 0x00010180 + mww phys 0x40048288 0x00010180 + mww phys 0x4004828c 0x00010180 + mww phys 0x40048290 0x00010180 + mww phys 0x40048294 0x00010180 + mww phys 0x40048298 0x00010180 + mww phys 0x4004829c 0x00010180 + mww phys 0x400482a0 0x00010180 + mww phys 0x400482a4 0x00010180 + mww phys 0x400482a8 0x00010180 + mww phys 0x400482ac 0x00010180 + mww phys 0x400482b0 0x00010180 + mww phys 0x400482b4 0x00010180 + mww phys 0x400482b8 0x00010180 + mww phys 0x400482bc 0x00010180 + mww phys 0x400482c0 0x00010180 + mww phys 0x400482c4 0x00010180 + mww phys 0x400482c8 0x00010180 + mww phys 0x400482cc 0x00000180 + mww phys 0x400482d0 0x00000180 + mww phys 0x400482d4 0x00000180 + mww phys 0x400482d8 0x00000180 + mww phys 0x4004821c 0x000001a0 + # ddr_ctrl_init + mww phys 0x400ae000 0x00000600 + mww phys 0x400ae008 0x00000020 + mww phys 0x400ae028 0x00013880 + mww phys 0x400ae02c 0x00030d40 + mww phys 0x400ae030 0x0000050c + mww phys 0x400ae034 0x15040400 + mww phys 0x400ae038 0x1406040f + mww phys 0x400ae040 0x04040000 + mww phys 0x400ae044 0x006db00c + mww phys 0x400ae048 0x00000403 + mww phys 0x400ae050 0x01000000 + mww phys 0x400ae054 0x00060001 + mww phys 0x400ae058 0x000c0000 + mww phys 0x400ae05c 0x03000200 + mww phys 0x400ae060 0x00000006 + mww phys 0x400ae064 0x00010000 + mww phys 0x400ae068 0x0c30002c + mww phys 0x400ae070 0x00000000 + mww phys 0x400ae074 0x00000003 + mww phys 0x400ae078 0x0000000a + mww phys 0x400ae07c 0x003001d4 + mww phys 0x400ae084 0x00010000 + mww phys 0x400ae088 0x00050500 + mww phys 0x400ae098 0x00000000 + mww phys 0x400ae09c 0x04001002 + mww phys 0x400ae0a4 0x00000001 + mww phys 0x400ae0c0 0x00460420 + mww phys 0x400ae108 0x01000200 + mww phys 0x400ae10c 0x00000040 + mww phys 0x400ae114 0x00000200 + mww phys 0x400ae118 0x00000040 + mww phys 0x400ae120 0x00000000 + mww phys 0x400ae124 0x0a010300 + mww phys 0x400ae128 0x01014040 + mww phys 0x400ae12c 0x01010101 + mww phys 0x400ae130 0x03030100 + mww phys 0x400ae134 0x01000101 + mww phys 0x400ae138 0x0700000c + mww phys 0x400ae13c 0x00000000 + mww phys 0x400ae148 0x10000000 + mww phys 0x400ae15c 0x01000000 + mww phys 0x400ae160 0x00040000 + mww phys 0x400ae164 0x00000002 + mww phys 0x400ae16c 0x00020000 + mww phys 0x400ae180 0x00002819 + mww phys 0x400ae184 0x01000000 + mww phys 0x400ae188 0x00000000 + mww phys 0x400ae18c 0x00000000 + mww phys 0x400ae198 0x00000000 + mww phys 0x400ae1a4 0x00000c00 + mww phys 0x400ae1a8 0x00000000 + mww phys 0x400ae1b8 0x0000000c + mww phys 0x400ae1c8 0x00000000 + mww phys 0x400ae1cc 0x00000000 + mww phys 0x400ae1d4 0x00000000 + mww phys 0x400ae1d8 0x01010000 + mww phys 0x400ae1e0 0x02020000 + mww phys 0x400ae1e4 0x00000202 + mww phys 0x400ae1e8 0x01010064 + mww phys 0x400ae1ec 0x00010101 + mww phys 0x400ae1f0 0x00000064 + mww phys 0x400ae1f8 0x00000800 + mww phys 0x400ae210 0x00000506 + mww phys 0x400ae224 0x00020000 + mww phys 0x400ae228 0x01000000 + mww phys 0x400ae22c 0x04070303 + mww phys 0x400ae230 0x00000040 + mww phys 0x400ae23c 0x06000080 + mww phys 0x400ae240 0x04070303 + mww phys 0x400ae244 0x00000040 + mww phys 0x400ae248 0x00000040 + mww phys 0x400ae24c 0x000f0000 + mww phys 0x400ae250 0x000f0000 + mww phys 0x400ae25c 0x00000101 + mww phys 0x400ae268 0x682c4000 + mww phys 0x400ae26c 0x00000012 + mww phys 0x400ae278 0x00000006 + mww phys 0x400ae284 0x00010202 + mww phys 0x400ae400 0x00002613 + mww phys 0x400ae440 0x00002613 + mww phys 0x400ae404 0x00002615 + mww phys 0x400ae444 0x00002615 + mww phys 0x400ae408 0x00210000 + mww phys 0x400ae448 0x00210000 + mww phys 0x400ae488 0x00210000 + mww phys 0x400ae40c 0x0001012a + mww phys 0x400ae44c 0x0001012a + mww phys 0x400ae48c 0x0001012a + mww phys 0x400ae410 0x00002400 + mww phys 0x400ae450 0x00002400 + mww phys 0x400ae490 0x00002400 + mww phys 0x400ae4c4 0x00000000 + mww phys 0x400ae4c8 0x00001100 + mww phys 0x400ae4d0 0x00010101 + mww phys 0x400ae000 0x00000601 +} + +# clock control init, setting up basic +# clocks +proc clock_init { } { + # captured from u-boot + mww phys 0x4006b040 0xffffffff + mww phys 0x4006b044 0xffffffff + mww phys 0x4006b048 0xffffffff + mww phys 0x4006b04c 0xffffffff + mww phys 0x4006b050 0xffffffff + mww phys 0x4006b058 0xffffffff + mww phys 0x4006b05c 0xffffffff + mww phys 0x4006b060 0xffffffff + mww phys 0x4006b064 0xffffffff + mww phys 0x4006b068 0xffffffff + mww phys 0x40050030 0x00002001 + mww phys 0x40050270 0x80002001 + mww phys 0x4006b000 0x00011005 + mww phys 0x4006b008 0x0001ff24 + mww phys 0x4006b00c 0x00000810 + mww phys 0x4006b010 0x00cc0000 + mww phys 0x4006b014 0x01000000 + mww phys 0x4006b018 0x20000000 + mww phys 0x4006b01c 0x0000001f + mww phys 0x4006b020 0x00000000 +} + +# This function applies the initial configuration after a "reset init" +# command +proc board_init { } { + clock_init + ddr_init +} + +# hook the init function into the reset-init event +${_TARGETNAME}0 configure -event reset-init { board_init } +# set a slow default JTAG clock, can be overridden later +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/board/twr-vf65gs10_cmsisdap.cfg b/openocd-win/openocd/scripts/board/twr-vf65gs10_cmsisdap.cfg new file mode 100644 index 0000000..86930c5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/twr-vf65gs10_cmsisdap.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Board configuration file for the Freescale VF65GS10 tower board +# +# CMSIS-DAP via USB-OTG connector +# +source [find interface/cmsis-dap.cfg] + +# only SWD is supported by the CMSIS-DAP on this board +transport select swd + +# Source generic part of twr-vf65gs10 configuration +source [find board/twr-vf65gs10.cfg] + +# override reset configuration +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/tx25_stk5.cfg b/openocd-win/openocd/scripts/board/tx25_stk5.cfg new file mode 100644 index 0000000..5bf8fd0 --- /dev/null +++ b/openocd-win/openocd/scripts/board/tx25_stk5.cfg @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ------------------------------------------------------------------------- +# KaRo TX25 CPU Module on a StarterkitV base board +# http://www.karo-electronics.com/tx25.html +# ------------------------------------------------------------------------- + + +source [find target/imx25.cfg] + + #------------------------------------------------------------------------- + # Declare Nand + #------------------------------------------------------------------------- + + nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap + + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { tx25_init } + + +proc tx25_init { } { + + #------------------------------------------------------------------------- + # AIPS setup - Only setup MPROTx registers. The PACR default values are good. + # Set all MPROTx to be non-bufferable, trusted for R/W, + # not forced to user-mode. + #------------------------------------------------------------------------- + + mww 0x43f00000 0x77777777 + mww 0x43f00004 0x77777777 + mww 0x53f00000 0x77777777 + mww 0x53f00004 0x77777777 + + sleep 100 + + #------------------------------------------------------------------------- + # MAX (Multi-Layer AHB Crossbar Switch) setup + # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB + #------------------------------------------------------------------------- + + mww 0x43f04000 0x00043210 + mww 0x43f04100 0x00043210 + mww 0x43f04200 0x00043210 + mww 0x43f04300 0x00043210 + mww 0x43f04400 0x00043210 + + # SGPCR - always park on last master + mww 0x43f04010 0x10 + mww 0x43f04110 0x10 + mww 0x43f04210 0x10 + mww 0x43f04310 0x10 + mww 0x43f04410 0x10 + + # MGPCR - restore default values + mww 0x43f04800 0x0 + mww 0x43f04900 0x0 + mww 0x43f04a00 0x0 + mww 0x43f04b00 0x0 + mww 0x43f04c00 0x0 + + # Configure M3IF registers + # M3IF Control Register (M3IFCTL) for MX25 + # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 + # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 + # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 + # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 + # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 + # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 + # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 + # ---------- + # 0x00000001 + mww 0xb8003000 0x00000001 + + #------------------------------------------------------------------------- + # configure ARM CLK + #------------------------------------------------------------------------- + + # Set the Clock CTL (HRM p. 355) + mww 0x53F80008 0x20034000 + + # Setup Clock Gating CTL 0-2 (HRM p. 357) + mww 0x53F8000C 0x1fffffff + mww 0x53F80010 0xffffffff + mww 0x53F80014 0x000fdfff + + #------------------------------------------------------------------------- + # SDRAM initialization + #------------------------------------------------------------------------- + + # set to 3.3v SDRAM + mww 0x43FAC454 0x00000800 + + # reset (set up ESDMISC) + mww 0xB8001010 0x00000002 + + # Setup for SDRAM Bank 0 + #------------------------------------------------------------------------- + + # Write ESDCFG0 + mww 0xB8001004 0x00095728 + + # CTL SMode = Precharge command + mww 0xB8001000 0x92116480 + mww 0x80000400 0x00000000 + + # CTL SMode = Auto Refresh command + mww 0xB8001000 0xA2116480 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + mww 0x80000000 0x0 + + # CTL SMode = Load Mode Register command + mww 0xB8001000 0xB2116480 + mwb 0x80000033 0x00 + + # CTL SMode = normal + mww 0xB8001000 0x82116480 + + # Setup for SDRAM Bank 1 + #------------------------------------------------------------------------- + + # Write ESDCFG1 + mww 0xB800100C 0x00095728 + + # CTL SMode = Precharge command + mww 0xB8001008 0x92116480 + mww 0x90000400 0x00000000 + + # CTL SMode = Auto Refresh command + mww 0xB8001008 0xA2116480 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + mww 0x90000000 0x00000000 + + # CTL SMode = Load Mode Register command + mww 0xB8001008 0xB2116480 + mwb 0x90000033 0x00 + + # CTL SMode = normal + mww 0xB8001008 0x82116480 + + # GPIO configuration + #------------------------------------------------------------------------- + + mww 0x43FAC02C 0x00000015 + mww 0x53FD0000 0x01000000 + mww 0x53FD0004 0x00000080 +} diff --git a/openocd-win/openocd/scripts/board/tx27_stk5.cfg b/openocd-win/openocd/scripts/board/tx27_stk5.cfg new file mode 100644 index 0000000..061f1f9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/tx27_stk5.cfg @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# KaRo TX27 CPU Module on a StarterkitV base board +# +# http://www.karo-electronics.com/tx27.html +# +source [find target/imx27.cfg] + +$_TARGETNAME configure -event gdb-attach { reset init } +$_TARGETNAME configure -event reset-init { tx27_init } + +proc tx27_init { } { + # This setup puts RAM at 0xA0000000 + # init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1) + mww 0x10000000 0x20040304 + mww 0x10020000 0x00000000 + mww 0x10000004 0xDFFBFCFB + mww 0x10020004 0xFFFFFFFF + + sleep 100 + + #init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR) + mww 0x1003F000 0x00302145 + mww 0x1003F004 0x00302145 + mww 0x1003F100 0x00302145 + mww 0x1003F104 0x00302145 + mww 0x1003F200 0x00302145 + mww 0x1003F204 0x00302145 + + #init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 ) + mww 0x10027828 0x55555555 + mww 0x10027830 0x55555555 + mww 0x10027834 0x55555555 + mww 0x10027838 0x00005005 + mww 0x1002783C 0x15555555 + + #init_sdram_speed + #mww 0xD8001010 0x00000004 + mww 0xD8001010 0x00000024 + + mww 0xD8001004 0x00395729 + + mww 0xD8001000 0x92120000 + mww 0xA0000400 0x0 + + mww 0xD8001000 0xA2120000 + mww 0xA0000000 0x0 + mww 0xA0000000 0x0 + + mww 0xD8001000 0xB2120000 + mdb 0xA0000000 + mdb 0xA0000033 + + mww 0xD8001000 0x82126485 + + # ============================================= + # Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz) + # ============================================= + mww 0xD8002000 0x23524E80 + mww 0xD8002004 0x10000D03 + mww 0xD8002008 0x00720900 + + nand probe 0 +} + +nand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap diff --git a/openocd-win/openocd/scripts/board/unknown_at91sam9260.cfg b/openocd-win/openocd/scripts/board/unknown_at91sam9260.cfg new file mode 100644 index 0000000..cab18b6 --- /dev/null +++ b/openocd-win/openocd/scripts/board/unknown_at91sam9260.cfg @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Thanks to Pieter Conradie for this script! +# +# Unknown vendor board contains: +# +# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz +# OSCSEL configured for internal RC oscillator (22 to 42 kHz) +# +# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit +# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks +################################################################## + +# We add to the minimal configuration. +source [find target/at91sam9260.cfg] + +$_TARGETNAME configure -event reset-start { + # At reset CPU runs at 22 to 42 kHz. + # JTAG Frequency must be 6 times slower. + jtag_rclk 3 + halt + # RSTC_MR : enable user reset, MMU may be enabled... use physical address + mww phys 0xfffffd08 0xa5000501 +} + + +$_TARGETNAME configure -event reset-init { + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2) + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz) + sleep 10 ;# wait 10 ms + + # Increase JTAG Speed to 6 MHz if RCLK is not supported + jtag_rclk 6000 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + + mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit + mww 0xffffec04 0x09070806 ;# SMC_PULSE0 + mww 0xffffec08 0x000d000b ;# SMC_CYCLE0 + mww 0xffffec0c 0x00001003 ;# SMC_MODE0 + + flash probe 0 ;# Identify flash bank 0 + + mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 + mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups + + mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM + # VDDIOMSEL set for +3V3 memory + # Disable D0..D15 pull-ups + + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode + mww 0x20000000 0 + mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us +} + + +##################### +# Flash configuration +##################### + +#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/uptech_2410.cfg b/openocd-win/openocd/scripts/board/uptech_2410.cfg new file mode 100644 index 0000000..ba269f5 --- /dev/null +++ b/openocd-win/openocd/scripts/board/uptech_2410.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target Configuration for the Uptech 2410 board. +# This configuration should also work on smdk2410, but I haven't tested it yet. +# Author: xionglingfeng@Gmail.com + +source [find target/samsung_s3c2410.cfg] + +$_TARGETNAME configure -event reset-init { uptech2410_init } +$_TARGETNAME configure -event gdb-attach { reset init } + +proc init_pll_sdram { } { + #echo "---------- Initializing PLL and SDRAM ---------" + #watchdog timer disable + mww phys 0x53000000 0x00000000 + + #disable all interrupts + mww phys 0x4a000008 0xffffffff + + #disable all sub-interrupts + mww phys 0x4a00001c 0x000007ff + + #clear all source pending bits + mww phys 0x4a000000 0xffffffff + + #clear all sub-source pending bits + mww phys 0x4a000018 0x000007ff + + #clear interrupt pending bit + mww phys 0x4a000010 0xffffffff + + #PLL locktime counter + mww phys 0x4c000000 0x00ffffff + + #Fin=12MHz Fout=202.8MHz + #mww phys 0x4c000004 0x000a1031 + + #FCLK:HCLK:PCLK = 1:2:4 + mww phys 0x4c000014 0x00000003 + + + mww phys 0x48000000 0x11111110 + mww phys 0x48000004 0x00007FFC + mww phys 0x48000008 0x00007FFC + mww phys 0x4800000c 0x00000700 + mww phys 0x48000010 0x00000700 + mww phys 0x48000014 0x00002E50 + mww phys 0x48000018 0x00002E50 + mww phys 0x4800001c 0x00018005 + mww phys 0x48000020 0x00018005 + mww phys 0x48000024 0x008c04e9 + mww phys 0x48000028 0x000000b2 + mww phys 0x4800002c 0x00000030 + mww phys 0x48000030 0x00000030 +} + +proc uptech2410_init { } { + init_pll_sdram + #echo "---------- Probing Nand flash ----------" + nand probe 0 + #echo "---------- Enable some functions ----------" +} + +set _NANDNAME $_CHIPNAME.nand +nand device $_NANDNAME s3c2410 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/vd_a53x2_dap.cfg b/openocd-win/openocd/scripts/board/vd_a53x2_dap.cfg new file mode 100644 index 0000000..4cf5594 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_a53x2_dap.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex A53x2 through DAP + +source [find interface/vdebug.cfg] + +set _CORES 2 +set _CHIPNAME a53 +set _MEMSTART 0x00000000 +set _MEMSIZE 0x1000000 + +# vdebug select transport +transport select dapdirect_swd + +# JTAG reset config, frequency and reset delay +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_swdp_bfm 10ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE + +source [find target/swj-dp.tcl] + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +source [find target/vd_aarch64.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_a53x2_jtag.cfg b/openocd-win/openocd/scripts/board/vd_a53x2_jtag.cfg new file mode 100644 index 0000000..a5e8d24 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_a53x2_jtag.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex A53x2 through JTAG + +source [find interface/vdebug.cfg] + +set _CORES 2 +set _CHIPNAME a53 +set _MEMSTART 0x00000000 +set _MEMSIZE 0x1000000 +set _CPUTAPID 0x5ba00477 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_aarch64.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_m4_dap.cfg b/openocd-win/openocd/scripts/board/vd_m4_dap.cfg new file mode 100644 index 0000000..691b623 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_m4_dap.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex m4 through DAP + +source [find interface/vdebug.cfg] + +set _CHIPNAME m4 +set _MEMSTART 0x00000000 +set _MEMSIZE 0x10000 + +# vdebug select transport +transport select dapdirect_swd +adapter speed 25000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_swdp_bfm 20ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE + +source [find target/swj-dp.tcl] + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +source [find target/vd_cortex_m.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_m4_jtag.cfg b/openocd-win/openocd/scripts/board/vd_m4_jtag.cfg new file mode 100644 index 0000000..4c795eb --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_m4_jtag.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex m4 through JTAG + +source [find interface/vdebug.cfg] + +set _CHIPNAME m4 +set _MEMSTART 0x00000000 +set _MEMSIZE 0x10000 +set _CPUTAPID 0x4ba00477 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 25000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 20ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_cortex_m.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_m7_jtag.cfg b/openocd-win/openocd/scripts/board/vd_m7_jtag.cfg new file mode 100644 index 0000000..880ef9b --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_m7_jtag.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm Cortex m7 through JTAG + +source [find interface/vdebug.cfg] + +set _CHIPNAME m7 +set _MEMSTART 0x00000000 +set _MEMSIZE 0x100000 +set _CPUTAPID 0x0ba02477 + +# vdebug select JTAG transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_cortex_m.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_pulpissimo_jtag.cfg b/openocd-win/openocd/scripts/board/vd_pulpissimo_jtag.cfg new file mode 100644 index 0000000..a3f5a84 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_pulpissimo_jtag.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# RISCV Ibex core with Pulpissimo through JTAG + +source [find interface/vdebug.cfg] + +set _CHIPNAME ibex +set _HARTID 0x20 +set _CPUTAPID 0x249511c3 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 12500 +adapter srst delay 10 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 40ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000 +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000 +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000 + +# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01 +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_riscv.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_swerv_jtag.cfg b/openocd-win/openocd/scripts/board/vd_swerv_jtag.cfg new file mode 100644 index 0000000..c5d33f2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_swerv_jtag.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# RISCV swerv core with Swerv through JTAG + +source [find interface/vdebug.cfg] + +set _CHIPNAME rv32 +set _HARTID 0x00 +set _CPUTAPID 0x1000008b +set _MEMSTART 0x00000000 +set _MEMSIZE 0x10000 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE + +# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01 +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_riscv.cfg] diff --git a/openocd-win/openocd/scripts/board/vd_xt8_jtag.cfg b/openocd-win/openocd/scripts/board/vd_xt8_jtag.cfg new file mode 100644 index 0000000..867b9e7 --- /dev/null +++ b/openocd-win/openocd/scripts/board/vd_xt8_jtag.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Xtensa xt8 through JTAG + +source [find interface/vdebug.cfg] + +set CHIPNAME xt8 +set CPUTAPID 0x120034e5 + +# vdebug select transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +# BFM hierarchical path and input clk period +vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns + +# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg +#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000 +#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000 + +# Create Xtensa target first +source [find target/xtensa.cfg] +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" +source [find target/xtensa-core-xt8.cfg] diff --git a/openocd-win/openocd/scripts/board/verdex.cfg b/openocd-win/openocd/scripts/board/verdex.cfg new file mode 100644 index 0000000..8511120 --- /dev/null +++ b/openocd-win/openocd/scripts/board/verdex.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Gumstix Verdex XM4 and XL6P (PXA270) + +set CHIPNAME verdex +source [find target/pxa270.cfg] + +# The board supports separate reset lines +# Override this in the interface config for parallel dongles +reset_config trst_and_srst separate + +# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz +adapter speed 40000 + +# flash bank <driver> <base> <size> <chip_width> <bus_width> +# XL6P has 32 MB flash +flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x02000000 2 2 $_TARGETNAME +# XM4 has 16 MB flash +#flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/voipac.cfg b/openocd-win/openocd/scripts/board/voipac.cfg new file mode 100644 index 0000000..74e651a --- /dev/null +++ b/openocd-win/openocd/scripts/board/voipac.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Voipac PXA270/PXA270M module. + +set CHIPNAME voipac +source [find target/pxa270.cfg] + +# The board supports separate reset lines +# Override this in the interface config for parallel dongles +reset_config trst_and_srst separate + +# flash bank <driver> <base> <size> <chip_width> <bus_width> +flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME +flash bank $_CHIPNAME.flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/board/voltcraft_dso-3062c.cfg b/openocd-win/openocd/scripts/board/voltcraft_dso-3062c.cfg new file mode 100644 index 0000000..fd56a81 --- /dev/null +++ b/openocd-win/openocd/scripts/board/voltcraft_dso-3062c.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Voltcraft DSO-3062C digital oscilloscope (uses a Samsung S3C2440) +# +# http://www.eevblog.com/forum/general-chat/hantek-tekway-dso-hack-get-200mhz-bw-for-free/ +# http://www.mikrocontroller.net/topic/249628 +# http://elinux.org/Das_Oszi +# http://randomprojects.org/wiki/Voltcraft_DSO-3062C +# + +# Enable this if your JTAG adapter supports multiple transports (JTAG or SWD). +# Otherwise comment it out, as it will cause an OpenOCD error. +### transport select jtag + +source [find target/samsung_s3c2440.cfg] + +adapter speed 16000 + +# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit) +nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME + +# arm7_9 fast_memory_access enable +# arm7_9 dcc_downloads enable + +init +reset +halt +scan_chain +targets +nand probe 0 +nand list diff --git a/openocd-win/openocd/scripts/board/x300t.cfg b/openocd-win/openocd/scripts/board/x300t.cfg new file mode 100644 index 0000000..c57c9d9 --- /dev/null +++ b/openocd-win/openocd/scripts/board/x300t.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is for the T-Home X300T / X301T IPTV box, +# which are based on IPTV reference designs from Kiss/Cisco KMM-3*** +# +# It has Sigma Designs SMP8634 chip. +source [find target/smp8634.cfg] + +$_TARGETNAME configure -event reset-init { x300t_init } + +# 1MB CFI capable flash +# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 $_TARGETNAME + +proc x300t_init { } { + # Setup SDRAM config and flash mapping + # initialize ram + mww 0xa003fffc 3 + mww 0xa003fffc 2 + mww 0xa0030000 0xE34111BA + mww 0xa003fffc 0xa4444 + mww 0xa003fffc 0 + + # remap boot vector in CPU local RAM + mww 0xa006f000 0x60000 + + # map flash to CPU address space REG_BASE_cpu_block+CPU_remap4 + mww 0x0006f010 0x48000000 + + # map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS) + mww 0x00061ff0 0x48000000 +} diff --git a/openocd-win/openocd/scripts/board/xmc-2go.cfg b/openocd-win/openocd/scripts/board/xmc-2go.cfg new file mode 100644 index 0000000..dd78a12 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc-2go.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC 2Go +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME xmc1100 +set WORKAREASIZE 0x4000 +source [find target/xmc1xxx.cfg] + +reset_config srst_only srst_nogate diff --git a/openocd-win/openocd/scripts/board/xmc1100-boot-kit.cfg b/openocd-win/openocd/scripts/board/xmc1100-boot-kit.cfg new file mode 100644 index 0000000..12ee3e2 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc1100-boot-kit.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC1100 Boot Kit +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME xmc1100 +set WORKAREASIZE 0x4000 +source [find target/xmc1xxx.cfg] + +reset_config srst_only srst_nogate diff --git a/openocd-win/openocd/scripts/board/xmc4200-application-kit-actuator.cfg b/openocd-win/openocd/scripts/board/xmc4200-application-kit-actuator.cfg new file mode 100644 index 0000000..79befaa --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4200-application-kit-actuator.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4200 Application Kit - Actuator +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME xmc4200 +source [find target/xmc4xxx.cfg] diff --git a/openocd-win/openocd/scripts/board/xmc4300-relax.cfg b/openocd-win/openocd/scripts/board/xmc4300-relax.cfg new file mode 100644 index 0000000..b748793 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4300-relax.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4300 Relax EtherCAT Kit +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +set CHIPNAME xmc4300 +source [find target/xmc4xxx.cfg] diff --git a/openocd-win/openocd/scripts/board/xmc4500-application-kit-general.cfg b/openocd-win/openocd/scripts/board/xmc4500-application-kit-general.cfg new file mode 100644 index 0000000..dbb5325 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4500-application-kit-general.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4500 Application Kit - General Purpose +# + +set CHIPNAME xmc4500 +source [find target/xmc4xxx.cfg] + +reset_config srst_only diff --git a/openocd-win/openocd/scripts/board/xmc4500-application-kit-sdram.cfg b/openocd-win/openocd/scripts/board/xmc4500-application-kit-sdram.cfg new file mode 100644 index 0000000..580dfd8 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4500-application-kit-sdram.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4500 Application Kit - SDRAM +# + +# +# Segger J-Link Lite XMC4200 on-board +# + +set CHIPNAME xmc4500 +source [find target/xmc4xxx.cfg] diff --git a/openocd-win/openocd/scripts/board/xmc4500-relax.cfg b/openocd-win/openocd/scripts/board/xmc4500-relax.cfg new file mode 100644 index 0000000..1239f04 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4500-relax.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4500 Relax Kit / Relax Lite Kit +# + +# +# Segger J-Link Lite XMC4500 on-board +# +source [find interface/jlink.cfg] +transport select swd + +# There's also an unpopulated 10-pin 0.05" pinout. + +set CHIPNAME xmc4500 +source [find target/xmc4xxx.cfg] diff --git a/openocd-win/openocd/scripts/board/xmc4700-relax.cfg b/openocd-win/openocd/scripts/board/xmc4700-relax.cfg new file mode 100644 index 0000000..ac8ce26 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4700-relax.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4700 Relax Lite Kit / Relax Kit for 5V Shields / Relax Kit +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +# There's also an unpopulated 10-pin 0.05" pinout. + +set CHIPNAME xmc4700 +source [find target/xmc4xxx.cfg] + +# Relax Kit only: N25Q032A qSPI flash diff --git a/openocd-win/openocd/scripts/board/xmc4800-relax.cfg b/openocd-win/openocd/scripts/board/xmc4800-relax.cfg new file mode 100644 index 0000000..d63159f --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmc4800-relax.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4800 Relax EtherCAT Kit +# + +# +# Segger J-Link Lite XMC4200 on-board +# +source [find interface/jlink.cfg] +transport select swd + +# There's also an unpopulated 10-pin 0.05" pinout. + +set CHIPNAME xmc4800 +source [find target/xmc4xxx.cfg] + +# N25Q032A qSPI flash diff --git a/openocd-win/openocd/scripts/board/xmos_xk-xac-xa8_arm.cfg b/openocd-win/openocd/scripts/board/xmos_xk-xac-xa8_arm.cfg new file mode 100644 index 0000000..2e83977 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xmos_xk-xac-xa8_arm.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# xCORE-XA Core Module +# +# https://www.xmos.com/support/boards?product=17940 +# + +# +# J-Link OB STM32F103 +# +source [find interface/jlink.cfg] +transport select swd + +# +# XS1-XAU8A-10 +# +source [find target/xmos_xs1-xau8a-10_arm.cfg] diff --git a/openocd-win/openocd/scripts/board/xtensa-kc705-ext-dap.cfg b/openocd-win/openocd/scripts/board/xtensa-kc705-ext-dap.cfg new file mode 100644 index 0000000..ac92c70 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xtensa-kc705-ext-dap.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with various external adapters that support DAP, e.g. JLink +# + +adapter speed 5000 + +# KC705 supports DAP/JTAG +transport select jtag +set XTENSA_DAP enable +set XTENSA_DAP_BASE 0x10000 + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/openocd-win/openocd/scripts/board/xtensa-kc705-ext.cfg b/openocd-win/openocd/scripts/board/xtensa-kc705-ext.cfg new file mode 100644 index 0000000..6be0681 --- /dev/null +++ b/openocd-win/openocd/scripts/board/xtensa-kc705-ext.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with various external adapters, e.g. Flyswatter2 or JLink +# + +adapter speed 10000 + +# KC705 supports JTAG only +transport select jtag + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/openocd-win/openocd/scripts/board/xtensa-kc705-onboard.cfg b/openocd-win/openocd/scripts/board/xtensa-kc705-onboard.cfg new file mode 100644 index 0000000..f0a616c --- /dev/null +++ b/openocd-win/openocd/scripts/board/xtensa-kc705-onboard.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence KC705 FPGA Development Platform for Xtensa targets +# Can be used with on-board (FTDI) adapter or various external adapters +# + +source [find interface/ftdi/xt_kc705_ml605.cfg] +adapter speed 10000 + +# KC705 supports JTAG only +transport select jtag + +# Create Xtensa target first +source [find target/xtensa.cfg] diff --git a/openocd-win/openocd/scripts/board/xtensa-palladium-vdebug.cfg b/openocd-win/openocd/scripts/board/xtensa-palladium-vdebug.cfg new file mode 100644 index 0000000..d4a700e --- /dev/null +++ b/openocd-win/openocd/scripts/board/xtensa-palladium-vdebug.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# for Palladium emulation systems +# + +source [find interface/vdebug.cfg] + +# vdebug select JTAG transport +transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 50000 +adapter srst delay 5 + +source [find target/vd_xtensa_jtag.cfg] diff --git a/openocd-win/openocd/scripts/board/xtensa-rt685-ext.cfg b/openocd-win/openocd/scripts/board/xtensa-rt685-ext.cfg new file mode 100644 index 0000000..03edb8d --- /dev/null +++ b/openocd-win/openocd/scripts/board/xtensa-rt685-ext.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP RT6XX Developemnt Platform with Xtensa HiFi DSP +# Can be used with various external adapters that support DAP, e.g. JLink +# + +adapter speed 10000 + +# RT6XX supports SWD only +transport select swd +set XTENSA_DAP enable + +# Create Xtensa target first +source [find target/xtensa.cfg] + +source [find target/xtensa-core-nxp_rt600.cfg] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/aic.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/aic.tcl new file mode 100644 index 0000000..6657b60 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/aic.tcl @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ] +global AIC_SMR +set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ] +global AIC_SVR +set AIC_IVR [expr {$AT91C_BASE_AIC + 0x00000100} ] +global AIC_IVR +set AIC_FVR [expr {$AT91C_BASE_AIC + 0x00000104} ] +global AIC_FVR +set AIC_ISR [expr {$AT91C_BASE_AIC + 0x00000108} ] +global AIC_ISR +set AIC_IPR [expr {$AT91C_BASE_AIC + 0x0000010C} ] +global AIC_IPR +set AIC_IMR [expr {$AT91C_BASE_AIC + 0x00000110} ] +global AIC_IMR +set AIC_CISR [expr {$AT91C_BASE_AIC + 0x00000114} ] +global AIC_CISR +set AIC_IECR [expr {$AT91C_BASE_AIC + 0x00000120} ] +global AIC_IECR +set AIC_IDCR [expr {$AT91C_BASE_AIC + 0x00000124} ] +global AIC_IDCR +set AIC_ICCR [expr {$AT91C_BASE_AIC + 0x00000128} ] +global AIC_ICCR +set AIC_ISCR [expr {$AT91C_BASE_AIC + 0x0000012C} ] +global AIC_ISCR +set AIC_EOICR [expr {$AT91C_BASE_AIC + 0x00000130} ] +global AIC_EOICR +set AIC_SPU [expr {$AT91C_BASE_AIC + 0x00000134} ] +global AIC_SPU +set AIC_DCR [expr {$AT91C_BASE_AIC + 0x00000138} ] +global AIC_DCR +set AIC_FFER [expr {$AT91C_BASE_AIC + 0x00000140} ] +global AIC_FFER +set AIC_FFDR [expr {$AT91C_BASE_AIC + 0x00000144} ] +global AIC_FFDR +set AIC_FFSR [expr {$AT91C_BASE_AIC + 0x00000148} ] +global AIC_FFSR + + +proc aic_enable_disable_list { VAL ENAME DNAME } { + global AT91C_ID + + show_mmr32_bits AT91C_ID $VAL + +} + +proc show_AIC_IPR_helper { NAME ADDR VAL } { + aic_enable_disable_list $VAL "IRQ PENDING" "irq not-pending" +} + +proc show_AIC_IMR_helper { NAME ADDR VAL } { + aic_enable_disable_list $VAL "IRQ ENABLED" "irq disabled" +} + + +proc show_AIC { } { + global AIC_SMR + if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] { + error [format "%s (%s)" $msg AIC_SMR] + } + echo "AIC_SMR: Mode & Type" + global AT91C_ID + for { set x 0 } { $x < 32 } { } { + echo -n " " + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + } + global AIC_SVR + if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] { + error [format "%s (%s)" $msg AIC_SVR] + } + echo "AIC_SVR: Vectors" + for { set x 0 } { $x < 32 } { } { + echo -n " " + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) [lindex $aaa $x]] + incr x + } + + foreach REG { + AIC_IVR AIC_FVR AIC_ISR + AIC_IPR AIC_IMR AIC_CISR AIC_IECR AIC_IDCR + AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR + AIC_FFER AIC_FFDR AIC_FFSR } { + if [catch { show_mmr32_reg $REG } msg ] { + error $msg + break + } + } +} diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91_pio.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91_pio.cfg new file mode 100644 index 0000000..10a1d48 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91_pio.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set PIO_PER 0x00 ;# Enable Register +set PIO_PDR 0x04 ;# Disable Register +set PIO_PSR 0x08 ;# Status Register +set PIO_OER 0x10 ;# Output Enable Register +set PIO_ODR 0x14 ;# Output Disable Register +set PIO_OSR 0x18 ;# Output Status Register +set PIO_IFER 0x20 ;# Glitch Input Filter Enable +set PIO_IFDR 0x24 ;# Glitch Input Filter Disable +set PIO_IFSR 0x28 ;# Glitch Input Filter Status +set PIO_SODR 0x30 ;# Set Output Data Register +set PIO_CODR 0x34 ;# Clear Output Data Register +set PIO_ODSR 0x38 ;# Output Data Status Register +set PIO_PDSR 0x3c ;# Pin Data Status Register +set PIO_IER 0x40 ;# Interrupt Enable Register +set PIO_IDR 0x44 ;# Interrupt Disable Register +set PIO_IMR 0x48 ;# Interrupt Mask Register +set PIO_ISR 0x4c ;# Interrupt Status Register +set PIO_MDER 0x50 ;# Multi-driver Enable Register +set PIO_MDDR 0x54 ;# Multi-driver Disable Register +set PIO_MDSR 0x58 ;# Multi-driver Status Register +set PIO_PUDR 0x60 ;# Pull-up Disable Register +set PIO_PUER 0x64 ;# Pull-up Enable Register +set PIO_PUSR 0x68 ;# Pull-up Status Register +set PIO_ASR 0x70 ;# Peripheral A Select Register +set PIO_BSR 0x74 ;# Peripheral B Select Register +set PIO_ABSR 0x78 ;# AB Status Register +set PIO_OWER 0xa0 ;# Output Write Enable Register +set PIO_OWDR 0xa4 ;# Output Write Disable Register +set PIO_OWSR 0xa8 ;# Output Write Status Register diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91_pmc.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91_pmc.cfg new file mode 100644 index 0000000..a75cecd --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91_pmc.cfg @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register +set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register + +set AT91_PMC_SCSR [expr {$AT91_PMC + 0x08}] ;# System Clock Status Register +set AT91_PMC_PCK [expr {1 << 0}] ;# Processor Clock +set AT91RM9200_PMC_UDP [expr {1 << 1}] ;# USB Devcice Port Clock [AT91RM9200 only] +set AT91RM9200_PMC_MCKUDP [expr {1 << 2}] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] +set AT91CAP9_PMC_DDR [expr {1 << 2}] ;# DDR Clock [CAP9 revC & some SAM9 only] +set AT91RM9200_PMC_UHP [expr {1 << 4}] ;# USB Host Port Clock [AT91RM9200 only] +set AT91SAM926x_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91SAM926x only] +set AT91CAP9_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91CAP9 only] +set AT91SAM926x_PMC_UDP [expr {1 << 7}] ;# USB Devcice Port Clock [AT91SAM926x only] +set AT91_PMC_PCK0 [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1 [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2 [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3 [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_HCK0 [expr {1 << 16}] ;# AHB Clock (USB host) [AT91SAM9261 only] +set AT91_PMC_HCK1 [expr {1 << 17}] ;# AHB Clock (LCD) [AT91SAM9261 only] + +set AT91_PMC_PCER [expr {$AT91_PMC + 0x10}] ;# Peripheral Clock Enable Register +set AT91_PMC_PCDR [expr {$AT91_PMC + 0x14}] ;# Peripheral Clock Disable Register +set AT91_PMC_PCSR [expr {$AT91_PMC + 0x18}] ;# Peripheral Clock Status Register + +set AT91_CKGR_UCKR [expr {$AT91_PMC + 0x1C}] ;# UTMI Clock Register [some SAM9, CAP9] +set AT91_PMC_UPLLEN [expr {1 << 16}] ;# UTMI PLL Enable +set AT91_PMC_UPLLCOUNT [expr {0xf << 20}] ;# UTMI PLL Start-up Time +set AT91_PMC_BIASEN [expr {1 << 24}] ;# UTMI BIAS Enable +set AT91_PMC_BIASCOUNT [expr {0xf << 28}] ;# UTMI BIAS Start-up Time + +set AT91_CKGR_MOR [expr {$AT91_PMC + 0x20}] ;# Main Oscillator Register [not on SAM9RL] +set AT91_PMC_MOSCEN [expr {1 << 0}] ;# Main Oscillator Enable +set AT91_PMC_OSCBYPASS [expr {1 << 1}] ;# Oscillator Bypass [SAM9x, CAP9] +set AT91_PMC_OSCOUNT [expr {0xff << 8}] ;# Main Oscillator Start-up Time + +set AT91_CKGR_MCFR [expr {$AT91_PMC + 0x24}] ;# Main Clock Frequency Register +set AT91_PMC_MAINF [expr {0xffff << 0}] ;# Main Clock Frequency +set AT91_PMC_MAINRDY [expr {1 << 16}] ;# Main Clock Ready + +set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register +set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register +set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider +set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter +set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range +set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier +set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only) +set AT91_PMC_USBDIV_1 [expr {0 << 28}] +set AT91_PMC_USBDIV_2 [expr {1 << 28}] +set AT91_PMC_USBDIV_4 [expr {2 << 28}] +set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only) +set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register + +set AT91_PMC_MCKR [expr {$AT91_PMC + 0x30}] ;# Master Clock Register +set AT91_PMC_CSS [expr {3 << 0}] ;# Master Clock Selection +set AT91_PMC_CSS_SLOW [expr {0 << 0}] +set AT91_PMC_CSS_MAIN [expr {1 << 0}] +set AT91_PMC_CSS_PLLA [expr {2 << 0}] +set AT91_PMC_CSS_PLLB [expr {3 << 0}] +set AT91_PMC_CSS_UPLL [expr {3 << 0}] ;# [some SAM9 only] +set AT91_PMC_PRES [expr {7 << 2}] ;# Master Clock Prescaler +set AT91_PMC_PRES_1 [expr {0 << 2}] +set AT91_PMC_PRES_2 [expr {1 << 2}] +set AT91_PMC_PRES_4 [expr {2 << 2}] +set AT91_PMC_PRES_8 [expr {3 << 2}] +set AT91_PMC_PRES_16 [expr {4 << 2}] +set AT91_PMC_PRES_32 [expr {5 << 2}] +set AT91_PMC_PRES_64 [expr {6 << 2}] +set AT91_PMC_MDIV [expr {3 << 8}] ;# Master Clock Division +set AT91RM9200_PMC_MDIV_1 [expr {0 << 8}] ;# [AT91RM9200 only] +set AT91RM9200_PMC_MDIV_2 [expr {1 << 8}] +set AT91RM9200_PMC_MDIV_3 [expr {2 << 8}] +set AT91RM9200_PMC_MDIV_4 [expr {3 << 8}] +set AT91SAM9_PMC_MDIV_1 [expr {0 << 8}] ;# [SAM9,CAP9 only] +set AT91SAM9_PMC_MDIV_2 [expr {1 << 8}] +set AT91SAM9_PMC_MDIV_4 [expr {2 << 8}] +set AT91SAM9_PMC_MDIV_6 [expr {3 << 8}] ;# [some SAM9 only] +set AT91SAM9_PMC_MDIV_3 [expr {3 << 8}] ;# [some SAM9 only] +set AT91_PMC_PDIV [expr {1 << 12}] ;# Processor Clock Division [some SAM9 only] +set AT91_PMC_PDIV_1 [expr {0 << 12}] +set AT91_PMC_PDIV_2 [expr {1 << 12}] +set AT91_PMC_PLLADIV2 [expr {1 << 12}] ;# PLLA divisor by 2 [some SAM9 only] +set AT91_PMC_PLLADIV2_OFF [expr {0 << 12}] +set AT91_PMC_PLLADIV2_ON [expr {1 << 12}] + +set AT91_PMC_USB [expr {$AT91_PMC + 0x38}] ;# USB Clock Register [some SAM9 only] +set AT91_PMC_USBS [expr {0x1 << 0}] ;# USB OHCI Input clock selection +set AT91_PMC_USBS_PLLA [expr {0 << 0}] +set AT91_PMC_USBS_UPLL [expr {1 << 0}] +set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock + +;# set AT91_PMC_PCKR(n) [expr {$AT91_PMC + 0x40 + ((n) * 4)}] ;# Programmable Clock 0-N Registers +set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection +set AT91_PMC_CSSMCK_CSS [expr {0 << 8}] +set AT91_PMC_CSSMCK_MCK [expr {1 << 8}] + +set AT91_PMC_IER [expr {$AT91_PMC + 0x60}] ;# Interrupt Enable Register +set AT91_PMC_IDR [expr {$AT91_PMC + 0x64}] ;# Interrupt Disable Register +set AT91_PMC_SR [expr {$AT91_PMC + 0x68}] ;# Status Register +set AT91_PMC_MOSCS [expr {1 << 0}] ;# MOSCS Flag +set AT91_PMC_LOCKA [expr {1 << 1}] ;# PLLA Lock +set AT91_PMC_LOCKB [expr {1 << 2}] ;# PLLB Lock +set AT91_PMC_MCKRDY [expr {1 << 3}] ;# Master Clock +set AT91_PMC_LOCKU [expr {1 << 6}] ;# UPLL Lock [some SAM9, AT91CAP9 only] +set AT91_PMC_OSCSEL [expr {1 << 7}] ;# Slow Clock Oscillator [AT91CAP9 revC only] +set AT91_PMC_PCK0RDY [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1RDY [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2RDY [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3RDY [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_IMR [expr {$AT91_PMC + 0x6c}] ;# Interrupt Mask Register + +set AT91_PMC_PROT [expr {$AT91_PMC + 0xe4}] ;# Protect Register [AT91CAP9 revC only] +set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code + +set AT91_PMC_VER [expr {$AT91_PMC + 0xfc}] ;# PMC Module Version [AT91CAP9 only] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91_rstc.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91_rstc.cfg new file mode 100644 index 0000000..fd17438 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91_rstc.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register +set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset +set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset +set AT91_RSTC_EXTRST [expr {1 << 3}] ;# External Reset +set AT91_RSTC_KEY [expr {0xa5 << 24}] ;# KEY Password + +set AT91_RSTC_SR [expr {$AT91_RSTC + 0x04}] ;# Reset Controller Status Register +set AT91_RSTC_URSTS [expr {1 << 0}] ;# User Reset Status +set AT91_RSTC_RSTTYP [expr {7 << 8}] ;# Reset Type +set AT91_RSTC_RSTTYP_GENERAL [expr {0 << 8}] +set AT91_RSTC_RSTTYP_WAKEUP [expr {1 << 8}] +set AT91_RSTC_RSTTYP_WATCHDOG [expr {2 << 8}] +set AT91_RSTC_RSTTYP_SOFTWARE [expr {3 << 8}] +set AT91_RSTC_RSTTYP_USER [expr {4 << 8}] +set AT91_RSTC_NRSTL [expr {1 << 16}] ;# NRST Pin Level +set AT91_RSTC_SRCMP [expr {1 << 17}] ;# Software Reset Command in Progress + +set AT91_RSTC_MR [expr {$AT91_RSTC + 0x08}] ;# Reset Controller Mode Register +set AT91_RSTC_URSTEN [expr {1 << 0}] ;# User Reset Enable +set AT91_RSTC_URSTIEN [expr {1 << 4}] ;# User Reset Interrupt Enable +set AT91_RSTC_ERSTL [expr {0xf << 8}] ;# External Reset Length diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91_wdt.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91_wdt.cfg new file mode 100644 index 0000000..8bba62e --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91_wdt.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register +set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart +set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password + +set AT91_WDT_MR [expr {$AT91_WDT + 0x04}] ;# Watchdog Mode Register +set AT91_WDT_WDV [expr {0xfff << 0}] ;# Counter Value +set AT91_WDT_WDFIEN [expr {1 << 12}] ;# Fault Interrupt Enable +set AT91_WDT_WDRSTEN [expr {1 << 13}] ;# Reset Processor +set AT91_WDT_WDRPROC [expr {1 << 14}] ;# Timer Restart +set AT91_WDT_WDDIS [expr {1 << 15}] ;# Watchdog Disable +set AT91_WDT_WDD [expr {0xfff << 16}] ;# Delta Value +set AT91_WDT_WDDBGHLT [expr {1 << 28}] ;# Debug Halt +set AT91_WDT_WDIDLEHLT [expr {1 << 29}] ;# Idle Halt + +set AT91_WDT_SR [expr {$AT91_WDT + 0x08}] ;# Watchdog Status Register +set AT91_WDT_WDUNF [expr {1 << 0}] ;# Watchdog Underflow +set AT91_WDT_WDERR [expr {1 << 1}] ;# Watchdog Error diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x128.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x128.tcl new file mode 100644 index 0000000..8f46827 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x128.tcl @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find bitsbytes.tcl] +source [find cpu/arm/arm7tdmi.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +set CHIP_MAKER atmel +set CHIP_FAMILY at91sam7 +set CHIP_NAME at91sam7x128 +# how many flash regions. +set N_FLASH 1 +set FLASH(0,CHIPSELECT) -1 +set FLASH(0,BASE) 0x00100000 +set FLASH(0,LEN) $__128K +set FLASH(0,HUMAN) "internal flash" +set FLASH(0,TYPE) "flash" +set FLASH(0,RWX) $RWX_R_X +set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY +# how many ram regions. +set N_RAM 1 +set RAM(0,CHIPSELECT) -1 +set RAM(0,BASE) 0x00200000 +set RAM(0,LEN) $__32K +set RAM(0,HUMAN) "internal ram" +set RAM(0,TYPE) "ram" +set RAM(0,RWX) $RWX_RWX +set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +# I AM LAZY... I create 1 region for all MMRs. +set N_MMREGS 1 +set MMREGS(0,CHIPSELECT) -1 +set MMREGS(0,BASE) 0xfff00000 +set MMREGS(0,LEN) 0x000fffff +set MMREGS(0,HUMAN) "mm-regs" +set MMREGS(0,TYPE) "mmr" +set MMREGS(0,RWX) $RWX_RW +set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +# no external memory +set N_XMEM 0 + + + + +set AT91C_BASE_SYS 0xFFFFF000 +set AT91C_BASE_AIC 0xFFFFF000 +set AT91C_BASE_PDC_DBGU 0xFFFFF300 +set AT91C_BASE_DBGU 0xFFFFF200 +set AT91C_BASE_PIOA 0xFFFFF400 +set AT91C_BASE_PIOB 0xFFFFF600 +set AT91C_BASE_CKGR 0xFFFFFC20 +set AT91C_BASE_PMC 0xFFFFFC00 +set AT91C_BASE_RSTC 0xFFFFFD00 +set AT91C_BASE_RTTC 0xFFFFFD20 +set AT91C_BASE_PITC 0xFFFFFD30 +set AT91C_BASE_WDTC 0xFFFFFD40 +set AT91C_BASE_VREG 0xFFFFFD60 +set AT91C_BASE_MC 0xFFFFFF00 +set AT91C_BASE_PDC_SPI1 0xFFFE4100 +set AT91C_BASE_SPI1 0xFFFE4000 +set AT91C_BASE_PDC_SPI0 0xFFFE0100 +set AT91C_BASE_SPI0 0xFFFE0000 +set AT91C_BASE_PDC_US1 0xFFFC4100 +set AT91C_BASE_US1 0xFFFC4000 +set AT91C_BASE_PDC_US0 0xFFFC0100 +set AT91C_BASE_US0 0xFFFC0000 +set AT91C_BASE_PDC_SSC 0xFFFD4100 +set AT91C_BASE_SSC 0xFFFD4000 +set AT91C_BASE_TWI 0xFFFB8000 +set AT91C_BASE_PWMC_CH3 0xFFFCC260 +set AT91C_BASE_PWMC_CH2 0xFFFCC240 +set AT91C_BASE_PWMC_CH1 0xFFFCC220 +set AT91C_BASE_PWMC_CH0 0xFFFCC200 +set AT91C_BASE_PWMC 0xFFFCC000 +set AT91C_BASE_UDP 0xFFFB0000 +set AT91C_BASE_TC0 0xFFFA0000 +set AT91C_BASE_TC1 0xFFFA0040 +set AT91C_BASE_TC2 0xFFFA0080 +set AT91C_BASE_TCB 0xFFFA0000 +set AT91C_BASE_CAN_MB0 0xFFFD0200 +set AT91C_BASE_CAN_MB1 0xFFFD0220 +set AT91C_BASE_CAN_MB2 0xFFFD0240 +set AT91C_BASE_CAN_MB3 0xFFFD0260 +set AT91C_BASE_CAN_MB4 0xFFFD0280 +set AT91C_BASE_CAN_MB5 0xFFFD02A0 +set AT91C_BASE_CAN_MB6 0xFFFD02C0 +set AT91C_BASE_CAN_MB7 0xFFFD02E0 +set AT91C_BASE_CAN 0xFFFD0000 +set AT91C_BASE_EMAC 0xFFFDC000 +set AT91C_BASE_PDC_ADC 0xFFFD8100 +set AT91C_BASE_ADC 0xFFFD8000 + +set AT91C_ID(0) FIQ +set AT91C_ID(1) SYS +set AT91C_ID(2) PIOA +set AT91C_ID(3) PIOB +set AT91C_ID(4) SPI0 +set AT91C_ID(5) SPI1 +set AT91C_ID(6) US0 +set AT91C_ID(7) US1 +set AT91C_ID(8) SSC +set AT91C_ID(9) TWI +set AT91C_ID(10) PWMC +set AT91C_ID(11) UDP +set AT91C_ID(12) TC0 +set AT91C_ID(13) TC1 +set AT91C_ID(14) TC2 +set AT91C_ID(15) CAN +set AT91C_ID(16) EMAC +set AT91C_ID(17) ADC +set AT91C_ID(18) "" +set AT91C_ID(19) "" +set AT91C_ID(20) "" +set AT91C_ID(21) "" +set AT91C_ID(22) "" +set AT91C_ID(23) "" +set AT91C_ID(24) "" +set AT91C_ID(25) "" +set AT91C_ID(26) "" +set AT91C_ID(27) "" +set AT91C_ID(28) "" +set AT91C_ID(29) "" +set AT91C_ID(30) IRQ0 +set AT91C_ID(31) IRQ1 + +source [find chip/atmel/at91/aic.tcl] +source [find chip/atmel/at91/usarts.tcl] +source [find chip/atmel/at91/pmc.tcl] +source [find chip/atmel/at91/rtt.tcl] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x256.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x256.tcl new file mode 100644 index 0000000..49d5244 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x256.tcl @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find bitsbytes.tcl] +source [find cpu/arm/arm7tdmi.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +set CHIP_MAKER atmel +set CHIP_FAMILY at91sam7 +set CHIP_NAME at91sam7x256 +# how many flash regions. +set N_FLASH 1 +set FLASH(0,CHIPSELECT) -1 +set FLASH(0,BASE) 0x00100000 +set FLASH(0,LEN) $__256K +set FLASH(0,HUMAN) "internal flash" +set FLASH(0,TYPE) "flash" +set FLASH(0,RWX) $RWX_R_X +set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY +# how many ram regions. +set N_RAM 1 +set RAM(0,CHIPSELECT) -1 +set RAM(0,BASE) 0x00200000 +set RAM(0,LEN) $__64K +set RAM(0,HUMAN) "internal ram" +set RAM(0,TYPE) "ram" +set RAM(0,RWX) $RWX_RWX +set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +# I AM LAZY... I create 1 region for all MMRs. +set N_MMREGS 1 +set MMREGS(0,CHIPSELECT) -1 +set MMREGS(0,BASE) 0xfff00000 +set MMREGS(0,LEN) 0x000fffff +set MMREGS(0,HUMAN) "mm-regs" +set MMREGS(0,TYPE) "mmr" +set MMREGS(0,RWX) $RWX_RW +set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +# no external memory +set N_XMEM 0 + +set AT91C_BASE_SYS 0xFFFFF000 +set AT91C_BASE_AIC 0xFFFFF000 +set AT91C_BASE_PDC_DBGU 0xFFFFF300 +set AT91C_BASE_DBGU 0xFFFFF200 +set AT91C_BASE_PIOA 0xFFFFF400 +set AT91C_BASE_PIOB 0xFFFFF600 +set AT91C_BASE_CKGR 0xFFFFFC20 +set AT91C_BASE_PMC 0xFFFFFC00 +set AT91C_BASE_RSTC 0xFFFFFD00 +set AT91C_BASE_RTTC 0xFFFFFD20 +set AT91C_BASE_PITC 0xFFFFFD30 +set AT91C_BASE_WDTC 0xFFFFFD40 +set AT91C_BASE_VREG 0xFFFFFD60 +set AT91C_BASE_MC 0xFFFFFF00 +set AT91C_BASE_PDC_SPI1 0xFFFE4100 +set AT91C_BASE_SPI1 0xFFFE4000 +set AT91C_BASE_PDC_SPI0 0xFFFE0100 +set AT91C_BASE_SPI0 0xFFFE0000 +set AT91C_BASE_PDC_US1 0xFFFC4100 +set AT91C_BASE_US1 0xFFFC4000 +set AT91C_BASE_PDC_US0 0xFFFC0100 +set AT91C_BASE_US0 0xFFFC0000 +set AT91C_BASE_PDC_SSC 0xFFFD4100 +set AT91C_BASE_SSC 0xFFFD4000 +set AT91C_BASE_TWI 0xFFFB8000 +set AT91C_BASE_PWMC_CH3 0xFFFCC260 +set AT91C_BASE_PWMC_CH2 0xFFFCC240 +set AT91C_BASE_PWMC_CH1 0xFFFCC220 +set AT91C_BASE_PWMC_CH0 0xFFFCC200 +set AT91C_BASE_PWMC 0xFFFCC000 +set AT91C_BASE_UDP 0xFFFB0000 +set AT91C_BASE_TC0 0xFFFA0000 +set AT91C_BASE_TC1 0xFFFA0040 +set AT91C_BASE_TC2 0xFFFA0080 +set AT91C_BASE_TCB 0xFFFA0000 +set AT91C_BASE_CAN_MB0 0xFFFD0200 +set AT91C_BASE_CAN_MB1 0xFFFD0220 +set AT91C_BASE_CAN_MB2 0xFFFD0240 +set AT91C_BASE_CAN_MB3 0xFFFD0260 +set AT91C_BASE_CAN_MB4 0xFFFD0280 +set AT91C_BASE_CAN_MB5 0xFFFD02A0 +set AT91C_BASE_CAN_MB6 0xFFFD02C0 +set AT91C_BASE_CAN_MB7 0xFFFD02E0 +set AT91C_BASE_CAN 0xFFFD0000 +set AT91C_BASE_EMAC 0xFFFDC000 +set AT91C_BASE_PDC_ADC 0xFFFD8100 +set AT91C_BASE_ADC 0xFFFD8000 + +set AT91C_ID(0) "FIQ" +set AT91C_ID(1) "SYS" +set AT91C_ID(2) "PIOA" +set AT91C_ID(3) "PIOB" +set AT91C_ID(4) "SPI0" +set AT91C_ID(5) "SPI1" +set AT91C_ID(6) "US0" +set AT91C_ID(7) "US1" +set AT91C_ID(8) "SSC" +set AT91C_ID(9) "TWI" +set AT91C_ID(10) "PWMC" +set AT91C_ID(11) "UDP" +set AT91C_ID(12) "TC0" +set AT91C_ID(13) "TC1" +set AT91C_ID(14) "TC2" +set AT91C_ID(15) "CAN" +set AT91C_ID(16) "EMAC" +set AT91C_ID(17) "ADC" +set AT91C_ID(18) "" +set AT91C_ID(19) "" +set AT91C_ID(20) "" +set AT91C_ID(21) "" +set AT91C_ID(22) "" +set AT91C_ID(23) "" +set AT91C_ID(24) "" +set AT91C_ID(25) "" +set AT91C_ID(26) "" +set AT91C_ID(27) "" +set AT91C_ID(28) "" +set AT91C_ID(29) "" +set AT91C_ID(30) "IRQ0" +set AT91C_ID(31) "IRQ1" + + +source [find chip/atmel/at91/aic.tcl] +source [find chip/atmel/at91/usarts.tcl] +source [find chip/atmel/at91/pmc.tcl] +source [find chip/atmel/at91/rtt.tcl] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261.cfg new file mode 100644 index 0000000..51e7101 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261.cfg @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Peripheral identifiers/interrupts. +# +set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ) +set AT91_ID_SYS 1 ;# System Peripherals +set AT91SAM9261_ID_PIOA 2 ;# Parallel IO Controller A +set AT91SAM9261_ID_PIOB 3 ;# Parallel IO Controller B +set AT91SAM9261_ID_PIOC 4 ;# Parallel IO Controller C +set AT91SAM9261_ID_US0 6 ;# USART 0 +set AT91SAM9261_ID_US1 7 ;# USART 1 +set AT91SAM9261_ID_US2 8 ;# USART 2 +set AT91SAM9261_ID_MCI 9 ;# Multimedia Card Interface +set AT91SAM9261_ID_UDP 10 ;# USB Device Port +set AT91SAM9261_ID_TWI 11 ;# Two-Wire Interface +set AT91SAM9261_ID_SPI0 12 ;# Serial Peripheral Interface 0 +set AT91SAM9261_ID_SPI1 13 ;# Serial Peripheral Interface 1 +set AT91SAM9261_ID_SSC0 14 ;# Serial Synchronous Controller 0 +set AT91SAM9261_ID_SSC1 15 ;# Serial Synchronous Controller 1 +set AT91SAM9261_ID_SSC2 16 ;# Serial Synchronous Controller 2 +set AT91SAM9261_ID_TC0 17 ;# Timer Counter 0 +set AT91SAM9261_ID_TC1 18 ;# Timer Counter 1 +set AT91SAM9261_ID_TC2 19 ;# Timer Counter 2 +set AT91SAM9261_ID_UHP 20 ;# USB Host port +set AT91SAM9261_ID_LCDC 21 ;# LDC Controller +set AT91SAM9261_ID_IRQ0 29 ;# Advanced Interrupt Controller (IRQ0) +set AT91SAM9261_ID_IRQ1 30 ;# Advanced Interrupt Controller (IRQ1) +set AT91SAM9261_ID_IRQ2 31 ;# Advanced Interrupt Controller (IRQ2) + + +# +# User Peripheral physical base addresses. +# +set AT91SAM9261_BASE_TCB0 0xfffa0000 +set AT91SAM9261_BASE_TC0 0xfffa0000 +set AT91SAM9261_BASE_TC1 0xfffa0040 +set AT91SAM9261_BASE_TC2 0xfffa0080 +set AT91SAM9261_BASE_UDP 0xfffa4000 +set AT91SAM9261_BASE_MCI 0xfffa8000 +set AT91SAM9261_BASE_TWI 0xfffac000 +set AT91SAM9261_BASE_US0 0xfffb0000 +set AT91SAM9261_BASE_US1 0xfffb4000 +set AT91SAM9261_BASE_US2 0xfffb8000 +set AT91SAM9261_BASE_SSC0 0xfffbc000 +set AT91SAM9261_BASE_SSC1 0xfffc0000 +set AT91SAM9261_BASE_SSC2 0xfffc4000 +set AT91SAM9261_BASE_SPI0 0xfffc8000 +set AT91SAM9261_BASE_SPI1 0xfffcc000 +set AT91_BASE_SYS 0xffffea00 + + +# +# System Peripherals (offset from AT91_BASE_SYS) +# +set AT91_SDRAMC 0xffffea00 +set AT91_SMC 0xffffec00 +set AT91_MATRIX 0xffffee00 +set AT91_AIC 0xfffff000 +set AT91_DBGU 0xfffff200 +set AT91_PIOA 0xfffff400 +set AT91_PIOB 0xfffff600 +set AT91_PIOC 0xfffff800 +set AT91_PMC 0xfffffc00 +set AT91_RSTC 0xfffffd00 +set AT91_SHDWC 0xfffffd10 +set AT91_RTT 0xfffffd20 +set AT91_PIT 0xfffffd30 +set AT91_WDT 0xfffffd40 +set AT91_GPBR 0xfffffd50 + +set AT91_USART0 $AT91SAM9261_BASE_US0 +set AT91_USART1 $AT91SAM9261_BASE_US1 +set AT91_USART2 $AT91SAM9261_BASE_US2 + + +# +# Internal Memory. +# +set AT91SAM9261_SRAM_BASE 0x00300000 ;# Internal SRAM base address +set AT91SAM9261_SRAM_SIZE 0x00028000 ;# Internal SRAM size (160Kb) + +set AT91SAM9261_ROM_BASE 0x00400000 ;# Internal ROM base address +set AT91SAM9261_ROM_SIZE 0x00008000 ;# Internal ROM size (32Kb) + +set AT91SAM9261_UHP_BASE 0x00500000 ;# USB Host controller +set AT91SAM9261_LCDC_BASE 0x00600000 ;# LDC controller + +# +# Cpu Name +# +set AT91_CPU_NAME "AT91SAM9261" diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261_matrix.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261_matrix.cfg new file mode 100644 index 0000000..c3656bd --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261_matrix.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register # +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) + +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x04}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x08}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x0C}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x10}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x14}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {7 << 18}] ;# Fixed Index of Default Master + +set AT91_MATRIX_TCR [expr {$AT91_MATRIX + 0x24}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_ITCM_64 [expr {7 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] +set AT91_MATRIX_DTCM_64 [expr {7 << 4}] + +set AT91_MATRIX_EBICSA [expr {$AT91_MATRIX + 0x30}] ;# EBI Chip Select Assignment Register +set AT91_MATRIX_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration + +set AT91_MATRIX_USBPUCR [expr {$AT91_MATRIX + 0x34}] ;# USB Pad Pull-Up Control Register +set AT91_MATRIX_USBPUCR_PUON [expr {1 << 30}] ;# USB Device PAD Pull-up Enable diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263.cfg new file mode 100644 index 0000000..600c548 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263.cfg @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Peripheral identifiers/interrupts. +# +set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ) +set AT91_ID_SYS 1 ;# System Peripherals +set AT91SAM9263_ID_PIOA 2 ;# Parallel IO Controller A +set AT91SAM9263_ID_PIOB 3 ;# Parallel IO Controller B +set AT91SAM9263_ID_PIOCDE 4 ;# Parallel IO Controller C, D and E +set AT91SAM9263_ID_US0 7 ;# USART 0 +set AT91SAM9263_ID_US1 8 ;# USART 1 +set AT91SAM9263_ID_US2 9 ;# USART 2 +set AT91SAM9263_ID_MCI0 10 ;# Multimedia Card Interface 0 +set AT91SAM9263_ID_MCI1 11 ;# Multimedia Card Interface 1 +set AT91SAM9263_ID_CAN 12 ;# CAN +set AT91SAM9263_ID_TWI 13 ;# Two-Wire Interface +set AT91SAM9263_ID_SPI0 14 ;# Serial Peripheral Interface 0 +set AT91SAM9263_ID_SPI1 15 ;# Serial Peripheral Interface 1 +set AT91SAM9263_ID_SSC0 16 ;# Serial Synchronous Controller 0 +set AT91SAM9263_ID_SSC1 17 ;# Serial Synchronous Controller 1 +set AT91SAM9263_ID_AC97C 18 ;# AC97 Controller +set AT91SAM9263_ID_TCB 19 ;# Timer Counter 0, 1 and 2 +set AT91SAM9263_ID_PWMC 20 ;# Pulse Width Modulation Controller +set AT91SAM9263_ID_EMAC 21 ;# Ethernet +set AT91SAM9263_ID_2DGE 23 ;# 2D Graphic Engine +set AT91SAM9263_ID_UDP 24 ;# USB Device Port +set AT91SAM9263_ID_ISI 25 ;# Image Sensor Interface +set AT91SAM9263_ID_LCDC 26 ;# LCD Controller +set AT91SAM9263_ID_DMA 27 ;# DMA Controller +set AT91SAM9263_ID_UHP 29 ;# USB Host port +set AT91SAM9263_ID_IRQ0 30 ;# Advanced Interrupt Controller (IRQ0) +set AT91SAM9263_ID_IRQ1 31 ;# Advanced Interrupt Controller (IRQ1) + + +# +# User Peripheral physical base addresses. +# +set AT91SAM9263_BASE_UDP 0xfff78000 +set AT91SAM9263_BASE_TCB0 0xfff7c000 +set AT91SAM9263_BASE_TC0 0xfff7c000 +set AT91SAM9263_BASE_TC1 0xfff7c040 +set AT91SAM9263_BASE_TC2 0xfff7c080 +set AT91SAM9263_BASE_MCI0 0xfff80000 +set AT91SAM9263_BASE_MCI1 0xfff84000 +set AT91SAM9263_BASE_TWI 0xfff88000 +set AT91SAM9263_BASE_US0 0xfff8c000 +set AT91SAM9263_BASE_US1 0xfff90000 +set AT91SAM9263_BASE_US2 0xfff94000 +set AT91SAM9263_BASE_SSC0 0xfff98000 +set AT91SAM9263_BASE_SSC1 0xfff9c000 +set AT91SAM9263_BASE_AC97C 0xfffa0000 +set AT91SAM9263_BASE_SPI0 0xfffa4000 +set AT91SAM9263_BASE_SPI1 0xfffa8000 +set AT91SAM9263_BASE_CAN 0xfffac000 +set AT91SAM9263_BASE_PWMC 0xfffb8000 +set AT91SAM9263_BASE_EMAC 0xfffbc000 +set AT91SAM9263_BASE_ISI 0xfffc4000 +set AT91SAM9263_BASE_2DGE 0xfffc8000 +set AT91_BASE_SYS 0xffffe000 + +# +# System Peripherals (offset from AT91_BASE_SYS) +# +set AT91_ECC0 0xffffe000 +set AT91_SDRAMC0 0xffffe200 +set AT91_SMC0 0xffffe400 +set AT91_ECC1 0xffffe600 +set AT91_SDRAMC1 0xffffe800 +set AT91_SMC1 0xffffea00 +set AT91_MATRIX 0xffffec00 +set AT91_CCFG 0xffffed10 +set AT91_DBGU 0xffffee00 +set AT91_AIC 0xfffff000 +set AT91_PIOA 0xfffff200 +set AT91_PIOB 0xfffff400 +set AT91_PIOC 0xfffff600 +set AT91_PIOD 0xfffff800 +set AT91_PIOE 0xfffffa00 +set AT91_PMC 0xfffffc00 +set AT91_RSTC 0xfffffd00 +set AT91_SHDWC 0xfffffd10 +set AT91_RTT0 0xfffffd20 +set AT91_PIT 0xfffffd30 +set AT91_WDT 0xfffffd40 +set AT91_RTT1 0xfffffd50 +set AT91_GPBR 0xfffffd60 + +set AT91_USART0 $AT91SAM9263_BASE_US0 +set AT91_USART1 $AT91SAM9263_BASE_US1 +set AT91_USART2 $AT91SAM9263_BASE_US2 + +set AT91_SMC $AT91_SMC0 +set AT91_SDRAMC $AT91_SDRAMC0 + +# +# Internal Memory. +# +set AT91SAM9263_SRAM0_BASE 0x00300000 ;# Internal SRAM 0 base address +set AT91SAM9263_SRAM0_SIZE 0x00014000 ;# Internal SRAM 0 size (80Kb) + +set AT91SAM9263_ROM_BASE 0x00400000 ;# Internal ROM base address +set AT91SAM9263_ROM_SIZE 0x00020000 ;# Internal ROM size (128Kb) + +set AT91SAM9263_SRAM1_BASE 0x00500000 ;# Internal SRAM 1 base address +set AT91SAM9263_SRAM1_SIZE 0x00004000 ;# Internal SRAM 1 size (16Kb) + +set AT91SAM9263_LCDC_BASE 0x00700000 ;# LCD Controller +set AT91SAM9263_DMAC_BASE 0x00800000 ;# DMA Controller +set AT91SAM9263_UHP_BASE 0x00a00000 ;# USB Host controller + +# +# Cpu Name +# +set AT91_CPU_NAME "AT91SAM9263" diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263_matrix.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263_matrix.cfg new file mode 100644 index 0000000..20a3107 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263_matrix.cfg @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0 +set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1 +set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2 +set AT91_MATRIX_MCFG3 [expr {$AT91_MATRIX + 0x0C}] ;# Master Configuration Register 3 +set AT91_MATRIX_MCFG4 [expr {$AT91_MATRIX + 0x10}] ;# Master Configuration Register 4 +set AT91_MATRIX_MCFG5 [expr {$AT91_MATRIX + 0x14}] ;# Master Configuration Register 5 +set AT91_MATRIX_MCFG6 [expr {$AT91_MATRIX + 0x18}] ;# Master Configuration Register 6 +set AT91_MATRIX_MCFG7 [expr {$AT91_MATRIX + 0x1C}] ;# Master Configuration Register 7 +set AT91_MATRIX_MCFG8 [expr {$AT91_MATRIX + 0x20}] ;# Master Configuration Register 8 +set AT91_MATRIX_ULBT [expr {7 << 0}] ;# Undefined Length Burst Type +set AT91_MATRIX_ULBT_INFINITE [expr {0 << 0}] +set AT91_MATRIX_ULBT_SINGLE [expr {1 << 0}] +set AT91_MATRIX_ULBT_FOUR [expr {2 << 0}] +set AT91_MATRIX_ULBT_EIGHT [expr {3 << 0}] +set AT91_MATRIX_ULBT_SIXTEEN [expr {4 << 0}] + +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x40}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x44}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x48}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x4C}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x50}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SCFG5 [expr {$AT91_MATRIX + 0x54}] ;# Slave Configuration Register 5 +set AT91_MATRIX_SCFG6 [expr {$AT91_MATRIX + 0x58}] ;# Slave Configuration Register 6 +set AT91_MATRIX_SCFG7 [expr {$AT91_MATRIX + 0x5C}] ;# Slave Configuration Register 7 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {0xf << 18}] ;# Fixed Index of Default Master +set AT91_MATRIX_ARBT [expr {3 << 24}] ;# Arbitration Type +set AT91_MATRIX_ARBT_ROUND_ROBIN [expr {0 << 24}] +set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr {1 << 24}] + +set AT91_MATRIX_PRAS0 [expr {$AT91_MATRIX + 0x80}] ;# Priority Register A for Slave 0 +set AT91_MATRIX_PRBS0 [expr {$AT91_MATRIX + 0x84}] ;# Priority Register B for Slave 0 +set AT91_MATRIX_PRAS1 [expr {$AT91_MATRIX + 0x88}] ;# Priority Register A for Slave 1 +set AT91_MATRIX_PRBS1 [expr {$AT91_MATRIX + 0x8C}] ;# Priority Register B for Slave 1 +set AT91_MATRIX_PRAS2 [expr {$AT91_MATRIX + 0x90}] ;# Priority Register A for Slave 2 +set AT91_MATRIX_PRBS2 [expr {$AT91_MATRIX + 0x94}] ;# Priority Register B for Slave 2 +set AT91_MATRIX_PRAS3 [expr {$AT91_MATRIX + 0x98}] ;# Priority Register A for Slave 3 +set AT91_MATRIX_PRBS3 [expr {$AT91_MATRIX + 0x9C}] ;# Priority Register B for Slave 3 +set AT91_MATRIX_PRAS4 [expr {$AT91_MATRIX + 0xA0}] ;# Priority Register A for Slave 4 +set AT91_MATRIX_PRBS4 [expr {$AT91_MATRIX + 0xA4}] ;# Priority Register B for Slave 4 +set AT91_MATRIX_PRAS5 [expr {$AT91_MATRIX + 0xA8}] ;# Priority Register A for Slave 5 +set AT91_MATRIX_PRBS5 [expr {$AT91_MATRIX + 0xAC}] ;# Priority Register B for Slave 5 +set AT91_MATRIX_PRAS6 [expr {$AT91_MATRIX + 0xB0}] ;# Priority Register A for Slave 6 +set AT91_MATRIX_PRBS6 [expr {$AT91_MATRIX + 0xB4}] ;# Priority Register B for Slave 6 +set AT91_MATRIX_PRAS7 [expr {$AT91_MATRIX + 0xB8}] ;# Priority Register A for Slave 7 +set AT91_MATRIX_PRBS7 [expr {$AT91_MATRIX + 0xBC}] ;# Priority Register B for Slave 7 +set AT91_MATRIX_M0PR [expr {3 << 0}] ;# Master 0 Priority +set AT91_MATRIX_M1PR [expr {3 << 4}] ;# Master 1 Priority +set AT91_MATRIX_M2PR [expr {3 << 8}] ;# Master 2 Priority +set AT91_MATRIX_M3PR [expr {3 << 12}] ;# Master 3 Priority +set AT91_MATRIX_M4PR [expr {3 << 16}] ;# Master 4 Priority +set AT91_MATRIX_M5PR [expr {3 << 20}] ;# Master 5 Priority +set AT91_MATRIX_M6PR [expr {3 << 24}] ;# Master 6 Priority +set AT91_MATRIX_M7PR [expr {3 << 28}] ;# Master 7 Priority +set AT91_MATRIX_M8PR [expr {3 << 0}] ;# Master 8 Priority (in Register B) + +set AT91_MATRIX_MRCR [expr {$AT91_MATRIX + 0x100}] ;# Master Remap Control Register +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) +set AT91_MATRIX_RCB2 [expr {1 << 2}] +set AT91_MATRIX_RCB3 [expr {1 << 3}] +set AT91_MATRIX_RCB4 [expr {1 << 4}] +set AT91_MATRIX_RCB5 [expr {1 << 5}] +set AT91_MATRIX_RCB6 [expr {1 << 6}] +set AT91_MATRIX_RCB7 [expr {1 << 7}] +set AT91_MATRIX_RCB8 [expr {1 << 8}] + +set AT91_MATRIX_TCMR [expr {$AT91_MATRIX + 0x114}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] + +set AT91_MATRIX_EBI0CSA [expr {$AT91_MATRIX + 0x120}] ;# EBI0 Chip Select Assignment Register +set AT91_MATRIX_EBI0_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI0_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI0_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignmen +set AT91_MATRIX_EBI0_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI0_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_EBI0_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_EBI0_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_EBI0_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_EBI0_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI0_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr {1 << 16}] + +set AT91_MATRIX_EBI1CSA [expr {$AT91_MATRIX + 0x124}] ;# EBI1 Chip Select Assignment Register +set AT91_MATRIX_EBI1_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI1_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI1_CS2A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_EBI1_CS2A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI1_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI1_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr {1 << 16}] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_init.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_init.cfg new file mode 100644 index 0000000..a64d6ea --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_init.cfg @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]] +uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]] + +proc at91sam9_reset_start { } { + + arm7_9 fast_memory_access disable + + jtag_rclk 8 + halt + wait_halt 10000 + set rstc_mr_val $::AT91_RSTC_KEY + set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}] + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] + mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset. +} + +proc at91sam9_reset_init { config } { + + mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog + + set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}] + + mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc. + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 } + + set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog + set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}] + set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}] + set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}] + set pllar_val [expr {$pllar_val | $config(master_pll_div)}] + + mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 } + + ;# PCK/2 = MCK Master Clock from PLLA + set mckr_val $::AT91_PMC_CSS_PLLA + set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}] + set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}] + set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}] + + mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 } + + ## switch JTAG clock to highspeed clock + jtag_rclk 0 + + arm7_9 dcc_downloads enable ;# Enable faster DCC downloads + arm7_9 fast_memory_access enable + + set rstc_mr_val $::AT91_RSTC_KEY + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] + mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable + + if { [info exists config(sdram_piod)] } { + set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}] + set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}] + mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] + mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] + mww $asr_addr 0xffff0000 + } else { + set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}] + mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] + mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] + } + + mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val) + mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register + mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register + mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register + mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM + mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR + mww $config(sdram_base) 0 ;# SDRAM_BASE + mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR + mww $config(sdram_base) 0 ;# SDRAM_BASE + + mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters +} diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_sdramc.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_sdramc.cfg new file mode 100644 index 0000000..658b6c3 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_sdramc.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# SDRAM Controller (SDRAMC) registers +set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register +set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode +set AT91_SDRAMC_MODE_NORMAL 0 +set AT91_SDRAMC_MODE_NOP 1 +set AT91_SDRAMC_MODE_PRECHARGE 2 +set AT91_SDRAMC_MODE_LMR 3 +set AT91_SDRAMC_MODE_REFRESH 4 +set AT91_SDRAMC_MODE_EXT_LMR 5 +set AT91_SDRAMC_MODE_DEEP 6 + +set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register +set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter + +set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register +set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits +set AT91_SDRAMC_NC_8 [expr {0 << 0}] +set AT91_SDRAMC_NC_9 [expr {1 << 0}] +set AT91_SDRAMC_NC_10 [expr {2 << 0}] +set AT91_SDRAMC_NC_11 [expr {3 << 0}] +set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits +set AT91_SDRAMC_NR_11 [expr {0 << 2}] +set AT91_SDRAMC_NR_12 [expr {1 << 2}] +set AT91_SDRAMC_NR_13 [expr {2 << 2}] +set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks +set AT91_SDRAMC_NB_2 [expr {0 << 4}] +set AT91_SDRAMC_NB_4 [expr {1 << 4}] +set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency +set AT91_SDRAMC_CAS_1 [expr {1 << 5}] +set AT91_SDRAMC_CAS_2 [expr {2 << 5}] +set AT91_SDRAMC_CAS_3 [expr {3 << 5}] +set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width +set AT91_SDRAMC_DBW_32 [expr {0 << 7}] +set AT91_SDRAMC_DBW_16 [expr {1 << 7}] +set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay +set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay +set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay +set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay +set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay +set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay + +set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register +set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations +set AT91_SDRAMC_LPCB_DISABLE 0 +set AT91_SDRAMC_LPCB_SELF_REFRESH 1 +set AT91_SDRAMC_LPCB_POWER_DOWN 2 +set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 +set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh +set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh +set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength +set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled +set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}] +set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}] +set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}] + +set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register +set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register +set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register +set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register +set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status + +set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register +set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type +set AT91_SDRAMC_MD_SDRAM 0 +set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_smc.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_smc.cfg new file mode 100644 index 0000000..c096c4a --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_smc.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode +set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode +set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode +set AT91_SMC_EXNWMODE_DISABLE [expr {0 << 4}] +set AT91_SMC_EXNWMODE_FROZEN [expr {2 << 4}] +set AT91_SMC_EXNWMODE_READY [expr {3 << 4}] +set AT91_SMC_BAT [expr {1 << 8}] ;# Byte Access Type +set AT91_SMC_BAT_SELECT [expr {0 << 8}] +set AT91_SMC_BAT_WRITE [expr {1 << 8}] +set AT91_SMC_DBW [expr {3 << 12}] ;# Data Bus Width */ +set AT91_SMC_DBW_8 [expr {0 << 12}] +set AT91_SMC_DBW_16 [expr {1 << 12}] +set AT91_SMC_DBW_32 [expr {2 << 12}] +set AT91_SMC_TDFMODE [expr {1 << 20}] ;# TDF Optimization - Enabled +set AT91_SMC_PMEN [expr {1 << 24}] ;# Page Mode Enabled +set AT91_SMC_PS [expr {3 << 28}] ;# Page Size +set AT91_SMC_PS_4 [expr {0 << 28}] +set AT91_SMC_PS_8 [expr {1 << 28}] +set AT91_SMC_PS_16 [expr {2 << 28}] +set AT91_SMC_PS_32 [expr {3 << 28}] diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/hardware.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/hardware.cfg new file mode 100644 index 0000000..069d4b7 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/hardware.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# External Memory Map +set AT91_CHIPSELECT_0 0x10000000 +set AT91_CHIPSELECT_1 0x20000000 +set AT91_CHIPSELECT_2 0x30000000 +set AT91_CHIPSELECT_3 0x40000000 +set AT91_CHIPSELECT_4 0x50000000 +set AT91_CHIPSELECT_5 0x60000000 +set AT91_CHIPSELECT_6 0x70000000 +set AT91_CHIPSELECT_7 0x80000000 diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/pmc.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/pmc.tcl new file mode 100644 index 0000000..0f997ca --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/pmc.tcl @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if [info exists AT91C_MAINOSC_FREQ] { + # user set this... let it be. +} { + # 18.432mhz is a common thing... + set AT91C_MAINOSC_FREQ 18432000 +} +global AT91C_MAINOSC_FREQ + +if [info exists AT91C_SLOWOSC_FREQ] { + # user set this... let it be. +} { + # 32khz is the norm + set AT91C_SLOWOSC_FREQ 32768 +} +global AT91C_SLOWOSC_FREQ diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/rtt.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/rtt.tcl new file mode 100644 index 0000000..1ef8373 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/rtt.tcl @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}] +set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}] +set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}] +set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}] +global RTTC_RTMR +global RTTC_RTAR +global RTTC_RTVR +global RTTC_RTSR + +proc show_RTTC_RTMR_helper { NAME ADDR VAL } { + set rtpres [expr {$VAL & 0x0ffff}] + global BIT16 BIT17 + if { $rtpres == 0 } { + set rtpres 65536; + } + global AT91C_SLOWOSC_FREQ + # Nasty hack, make this a float by tacking a .0 on the end + # otherwise, jim makes the value an integer + set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"] + echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f] + if { $VAL & $BIT16 } { + echo "\tBit16 -> Alarm IRQ Enabled" + } else { + echo "\tBit16 -> Alarm IRQ Disabled" + } + if { $VAL & $BIT17 } { + echo "\tBit17 -> RTC Inc IRQ Enabled" + } else { + echo "\tBit17 -> RTC Inc IRQ Disabled" + } + # Bit 18 is write only. +} + +proc show_RTTC_RTSR_helper { NAME ADDR VAL } { + global BIT0 BIT1 + if { $VAL & $BIT0 } { + echo "\tBit0 -> ALARM PENDING" + } else { + echo "\tBit0 -> alarm not pending" + } + if { $VAL & $BIT1 } { + echo "\tBit0 -> RTINC PENDING" + } else { + echo "\tBit0 -> rtinc not pending" + } +} + +proc show_RTTC { } { + + show_mmr32_reg RTTC_RTMR + show_mmr32_reg RTTC_RTAR + show_mmr32_reg RTTC_RTVR + show_mmr32_reg RTTC_RTSR +} diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/sam9_smc.cfg b/openocd-win/openocd/scripts/chip/atmel/at91/sam9_smc.cfg new file mode 100644 index 0000000..87880c7 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/sam9_smc.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Setup register +# +# ncs_read_setup +# nrd_setup +# ncs_write_setup +# set nwe_setup +# +# +# Pulse register +# +# ncs_read_pulse +# nrd_pulse +# ncs_write_pulse +# nwe_pulse +# +# +# Cycle register +# +# read_cycle 0 +# write_cycle 0 +# +# +# Mode register +# +# mode +# tdf_cycles +proc sam9_smc_config { cs smc_config } { + ;# Setup Register for CS n + set AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}] + set val [expr {$smc_config(nwe_setup) << 0}] + set val [expr {$val | $smc_config(ncs_write_setup) << 8}] + set val [expr {$val | $smc_config(nrd_setup)) << 16}] + set val [expr {$val | $smc_config(ncs_read_setup) << 24}] + mww $AT91_SMC_SETUP $val + + ;# Pulse Register for CS n + set AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}] + set val [expr {$smc_config(nwe_pulse) << 0}] + set val [expr {$val | $smc_config(ncs_write_pulse) << 8}] + set val [expr {$val | $smc_config(nrd_pulse) << 16}] + set val [expr {$val | $smc_config(ncs_read_pulse) << 24}] + mww $AT91_SMC_PULSE $val + + ;# Cycle Register for CS n + set AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}] + set val [expr {$smc_config(write_cycle) << 0}] + set val [expr {$val | $smc_config(read_cycle) << 16}] + mww $AT91_SMC_CYCLE $val + + ;# Mode Register for CS n + set AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}] + set val [expr {$smc_config(mode) << 0}] + set val [expr {$val | $smc_config(tdf_cycles) << 16}] + mww $AT91_SMC_MODE $val +} diff --git a/openocd-win/openocd/scripts/chip/atmel/at91/usarts.tcl b/openocd-win/openocd/scripts/chip/atmel/at91/usarts.tcl new file mode 100644 index 0000000..62a651b --- /dev/null +++ b/openocd-win/openocd/scripts/chip/atmel/at91/usarts.tcl @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# the DBGU and USARTs are 'almost' indentical' +set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}] +set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}] +set DBGU_IER [expr {$AT91C_BASE_DBGU + 0x00000008}] +set DBGU_IDR [expr {$AT91C_BASE_DBGU + 0x0000000C}] +set DBGU_IMR [expr {$AT91C_BASE_DBGU + 0x00000010}] +set DBGU_CSR [expr {$AT91C_BASE_DBGU + 0x00000014}] +set DBGU_RHR [expr {$AT91C_BASE_DBGU + 0x00000018}] +set DBGU_THR [expr {$AT91C_BASE_DBGU + 0x0000001C}] +set DBGU_BRGR [expr {$AT91C_BASE_DBGU + 0x00000020}] +# no RTOR +# no TTGR +# no FIDI +# no NER +set DBGU_CIDR [expr {$AT91C_BASE_DBGU + 0x00000040}] +set DBGU_EXID [expr {$AT91C_BASE_DBGU + 0x00000044}] +set DBGU_FNTR [expr {$AT91C_BASE_DBGU + 0x00000048}] + + +set USx_CR 0x00000000 +set USx_MR 0x00000004 +set USx_IER 0x00000008 +set USx_IDR 0x0000000C +set USx_IMR 0x00000010 +set USx_CSR 0x00000014 +set USx_RHR 0x00000018 +set USx_THR 0x0000001C +set USx_BRGR 0x00000020 +set USx_RTOR 0x00000024 +set USx_TTGR 0x00000028 +set USx_FIDI 0x00000040 +set USx_NER 0x00000044 +set USx_IF 0x0000004C + +# Create all the uarts that exist.. +# we blow up if there are >9 + + +proc show_mmr_USx_MR_helper { NAME ADDR VAL } { + # First - just print it + + set x [show_normalize_bitfield $VAL 3 0] + if { $x == 0 } { + echo "\tNormal operation" + } else { + echo [format "\tNon Normal operation mode: 0x%02x" $x] + } + + set x [show_normalize_bitfield $VAL 11 9] + set s "unknown" + switch -exact $x { + 0 { set s "Even" } + 1 { set s "Odd" } + 2 { set s "Force=0" } + 3 { set s "Force=1" } + * { + set $x [expr {$x & 6}] + switch -exact $x { + 4 { set s "None" } + 6 { set s "Multidrop Mode" } + } + } + } + echo [format "\tParity: %s " $s] + + set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}] + echo [format "\tDatabits: %d" $x] + + set x [show_normalize_bitfield $VAL 13 12] + switch -exact $x { + 0 { echo "\tStop bits: 1" } + 1 { echo "\tStop bits: 1.5" } + 2 { echo "\tStop bits: 2" } + 3 { echo "\tStop bits: Illegal/Reserved" } + } +} + +# For every possbile usart... +foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } { + set n AT91C_BASE_[set WHO] + set str "" + + # Only if it exists on the chip + if [ info exists $n ] { + # Hence: $n - is like AT91C_BASE_USx + # For every sub-register + foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF} { + # vn = variable name + set vn [set WHO]_[set REG] + # vn = USx_IER + # vv = variable value + set vv [expr "$$n + [set USx_[set REG]]"] + # And VV is the address in memory of that register + + + # make that VN a GLOBAL so others can find it + global $vn + set $vn $vv + + # Create a command for this specific register. + proc show_$vn { } "show_mmr32_reg $vn" + + # Add this command to the Device(as a whole) command + set str "$str\nshow_$vn" + } + # Now - create the DEVICE(as a whole) command + set fn show_$WHO + proc $fn { } $str + } +} + +# The Debug Uart is special.. +set str "" + + +# For every sub-register +foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR + DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} { + + # Create a command for this specific register. + proc show_$REG { } "show_mmr32_reg $REG" + + # Add this command to the Device(as a whole) command + set str "$str\nshow_$REG" +} + +# Now - create the DEVICE(as a whole) command +proc show_DBGU { } $str + +unset str + +proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL } diff --git a/openocd-win/openocd/scripts/chip/st/spear/quirk_no_srst.tcl b/openocd-win/openocd/scripts/chip/st/spear/quirk_no_srst.tcl new file mode 100644 index 0000000..e8640f4 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/spear/quirk_no_srst.tcl @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Quirks to bypass missing SRST on JTAG connector +# EVALSPEAr310 Rev. 2.0 +# http://www.st.com/spear +# +# Date: 2010-08-17 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + +# For boards that have JTAG SRST not connected. +# We use "arm9 vector_catch reset" to catch button reset event. + + +$_TARGETNAME configure -event reset-assert sp_reset_assert +$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post + +# keeps the name of the SPEAr target +global sp_target_name +set sp_target_name $_TARGETNAME + +# Keeps the argument of "reset" command (run, init, halt). +global sp_reset_mode +set sp_reset_mode "" + +# Helper procedure. Returns 0 is target is halted. +proc sp_is_halted {} { + global sp_target_name + + return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}] +} + +# wait for reset button to be pressed, causing CPU to get halted +proc sp_reset_deassert_post {} { + global sp_reset_mode + + set bar(0) | + set bar(1) / + set bar(2) - + set bar(3) \\ + + poll on + echo "====> Press reset button on the board <====" + for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} { + echo -n "$bar([expr {$i & 3}])\r" + sleep 200 + } + + # Remove catch reset event + arm9 vector_catch none + + # CPU is halted, but we typed "reset run" ... + if { [string compare $sp_reset_mode "run"] == 0 } { + resume + } +} + +# Override reset-assert, since no SRST available +# Catch reset event +proc sp_reset_assert {} { + arm9 vector_catch reset +} + +# Override default init_reset{mode} to catch parameter "mode" +proc init_reset {mode} { + global sp_reset_mode + + set sp_reset_mode $mode + + # We need to detect CPU get halted, so exit from halt + if { [sp_is_halted] } { + echo "Resuming CPU to detect reset" + resume + } + + # Execute default init_reset{mode} + jtag arp_init-reset +} diff --git a/openocd-win/openocd/scripts/chip/st/spear/spear3xx.tcl b/openocd-win/openocd/scripts/chip/st/spear/spear3xx.tcl new file mode 100644 index 0000000..474ebe3 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/spear/spear3xx.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Generic init scripts for all ST SPEAr3xx family +# http://www.st.com/spear +# +# Date: 2010-09-23 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + + +# Initialize internal clock +# Default: +# - Crystal = 24 MHz +# - PLL1 = 332 MHz +# - PLL2 = 332 MHz +# - CPU_CLK = 332 MHz +# - DDR_CLK = 332 MHz async +# - HCLK = 166 MHz +# - PCLK = 83 MHz +proc sp3xx_clock_default {} { + mww 0xfca00000 0x00000002 ;# set sysclk slow + mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?) + + # DDRCORE disable to change frequency + set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}] + mww 0xfca8002c $val + mww 0xfca8002c $val ;# Yes, write twice! + + # programming PLL1 + mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12 + mww 0xfca80008 0x00001c0a ;# power down + mww 0xfca80008 0x00001c0e ;# enable + mww 0xfca80008 0x00001c06 ;# strobe + mww 0xfca80008 0x00001c0e + while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 } + + # programming PLL2 + mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12 + mww 0xfca80014 0x00001c0a ;# power down + mww 0xfca80014 0x00001c0e ;# enable + mww 0xfca80014 0x00001c06 ;# strobe + mww 0xfca80014 0x00001c0e + while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 } + + mww 0xfca80028 0x00000082 ;# enable plltimeen + mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2" + + mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode + while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 } + + # Select source of DDR clock + #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1 + mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2 + + # DDRCORE enable after change frequency + mmw 0xfca8002c 0x20000000 0x00000000 +} + +proc sp3xx_common_init {} { + mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals + mww 0xfca80038 0x00000000 ;# remove reset of all peripherals + + mww 0xfca80034 0x0000ffff ;# enable all RAS clocks + mww 0xfca80040 0x00000000 ;# remove all RAS resets + + mww 0xfca800e4 0x78000008 ;# COMP1V8_REG + mww 0xfca800ec 0x78000008 ;# COMP3V3_REG + + mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode + mww 0xfc000000 0x00000f5f + + # Initialize Bus Interconnection Matrix + # All ports Round-Robin and lowest priority + mww 0xfca8007c 0x80000007 + mww 0xfca80080 0x80000007 + mww 0xfca80084 0x80000007 + mww 0xfca80088 0x80000007 + mww 0xfca8008c 0x80000007 + mww 0xfca80090 0x80000007 + mww 0xfca80094 0x80000007 + mww 0xfca80098 0x80000007 + mww 0xfca8009c 0x80000007 +} + + +# Specific init scripts for ST SPEAr300 +proc sp300_init {} { + mww 0x99000000 0x00003fff ;# RAS function enable +} + + +# Specific init scripts for ST SPEAr310 +proc sp310_init {} { + mww 0xb4000008 0x00002ff4 ;# RAS function enable + + mww 0xfca80050 0x00000001 ;# Enable clk mem port 1 + + mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv + mww 0xfca80140 0x017bdef6 +} + +proc sp310_emi_init {} { + # set EMI pad strength + mmw 0xfca80134 0x0e000000 0x00000000 + mmw 0xfca80138 0x0e739ce7 0x00000000 + mmw 0xfca8013c 0x00039ce7 0x00000000 + + # set safe EMI timing as in BootROM + #mww 0x4f000000 0x0000000f ;# tAP_0_reg + #mww 0x4f000004 0x00000000 ;# tSDP_0_reg + #mww 0x4f000008 0x000000ff ;# tDPw_0_reg + #mww 0x4f00000c 0x00000111 ;# tDPr_0_reg + #mww 0x4f000010 0x00000002 ;# tDCS_0_reg + + # set fast EMI timing as in Linux + mww 0x4f000000 0x00000010 ;# tAP_0_reg + mww 0x4f000004 0x00000005 ;# tSDP_0_reg + mww 0x4f000008 0x0000000a ;# tDPw_0_reg + mww 0x4f00000c 0x0000000a ;# tDPr_0_reg + mww 0x4f000010 0x00000005 ;# tDCS_0_re + + # 32bit wide, 8/16/32bit access + mww 0x4f000014 0x0000000e ;# control_0_reg + mww 0x4f000094 0x0000003f ;# ack_reg +} + + +# Specific init scripts for ST SPEAr320 +proc sp320_init {} { + mww 0xb300000c 0xffffac04 ;# RAS function enable + mww 0xb3000010 0x00000001 ;# RAS mode select +} diff --git a/openocd-win/openocd/scripts/chip/st/spear/spear3xx_ddr.tcl b/openocd-win/openocd/scripts/chip/st/spear/spear3xx_ddr.tcl new file mode 100644 index 0000000..5992567 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/spear/spear3xx_ddr.tcl @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Init scripts to configure DDR controller of SPEAr3xx +# http://www.st.com/spear +# Original values taken from XLoader source code +# +# Date: 2010-09-23 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + + +proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { + if { $ddr_chips != 1 && $ddr_chips != 2 } { + error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips + } + + if { $ddr_type == "mt47h64m16_3_333_cl5_async" } { + ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips + set ddr_size 0x08000000 + ## add here new DDR chip definition. Prototype: + #} elseif { $ddr_type == "?????" } { + # ????? $ddr_chips + # set ddr_size 0x????? + } else { + error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type + } + + # MPMC START + mww 0xfc60001c 0x01000100 + + if { $ddr_chips == 2 } { + echo [format \ + "Double chip DDR memory. Total memory size 0x%08x byte" \ + [expr {2 * $ddr_size}]] + } else { + echo [format \ + "Single chip DDR memory. Memory size 0x%08x byte" \ + $ddr_size] + } +} + + +# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S +proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} { + # DDR_PAD_REG + mww 0xfca800f0 0x00003aa5 + + # Use "1:2 sync" only when DDR clock source is PLL1 and + # HCLK is half of PLL1 + mww 0xfc600000 0x00000001 ;# MEMCTL_AHB_SET_00 # This is async + mww 0xfc600004 0x00000000 ;# MEMCTL_AHB_SET_01 +# mww 0xfc600000 0x02020201 ;# MEMCTL_AHB_SET_00 # This is 1:2 sync +# mww 0xfc600004 0x02020202 ;# MEMCTL_AHB_SET_01 + + mww 0xfc600008 0x01000000 ;# MEMCTL_RFSH_SET_00 + mww 0xfc60000c 0x00000101 ;# MEMCTL_DLL_SET_00 + mww 0xfc600010 0x00000101 ;# MEMCTL_GP_00 + mww 0xfc600014 0x01000000 ;# MEMCTL_GP_01 + mww 0xfc600018 0x00010001 ;# MEMCTL_GP_02 + mww 0xfc60001c 0x00000100 ;# MEMCTL_GP_03 + mww 0xfc600020 0x00010001 ;# MEMCTL_GP_04 + if { $ddr_chips == 2 } { + mww 0xfc600024 0x01020203 ;# MEMCTL_GP_05 + mww 0xfc600028 0x01000102 ;# MEMCTL_GP_06 + mww 0xfc60002c 0x02000202 ;# MEMCTL_AHB_SET_02 + } else { + mww 0xfc600024 0x00000201 ;# MEMCTL_GP_05 + mww 0xfc600028 0x02000001 ;# MEMCTL_GP_06 + mww 0xfc60002c 0x02000201 ;# MEMCTL_AHB_SET_02 + } + mww 0xfc600030 0x04040105 ;# MEMCTL_AHB_SET_03 + mww 0xfc600034 0x03030302 ;# MEMCTL_AHB_SET_04 + mww 0xfc600038 0x02040101 ;# MEMCTL_AHB_SET_05 + mww 0xfc60003c 0x00000002 ;# MEMCTL_AHB_SET_06 + mww 0xfc600044 0x03000405 ;# MEMCTL_DQS_SET_0 + mww 0xfc600048 0x03040002 ;# MEMCTL_TIME_SET_01 + mww 0xfc60004c 0x04000305 ;# MEMCTL_TIME_SET_02 + mww 0xfc600050 0x0505053f ;# MEMCTL_AHB_RELPR_00 + mww 0xfc600054 0x05050505 ;# MEMCTL_AHB_RELPR_01 + mww 0xfc600058 0x04040405 ;# MEMCTL_AHB_RELPR_02 + mww 0xfc60005c 0x04040404 ;# MEMCTL_AHB_RELPR_03 + mww 0xfc600060 0x03030304 ;# MEMCTL_AHB_RELPR_04 + mww 0xfc600064 0x03030303 ;# MEMCTL_AHB_RELPR_05 + mww 0xfc600068 0x02020203 ;# MEMCTL_AHB_RELPR_06 + mww 0xfc60006c 0x02020202 ;# MEMCTL_AHB_RELPR_07 + mww 0xfc600070 0x01010102 ;# MEMCTL_AHB_RELPR_08 + mww 0xfc600074 0x01010101 ;# MEMCTL_AHB_RELPR_09 + mww 0xfc600078 0x00000001 ;# MEMCTL_AHB_RELPR_10 + mww 0xfc600088 0x0a0c0a00 ;# MEMCTL_DQS_SET_1 + mww 0xfc60008c 0x0000023f ;# MEMCTL_GP_07 + mww 0xfc600090 0x00050a00 ;# MEMCTL_GP_08 + mww 0xfc600094 0x11000000 ;# MEMCTL_GP_09 + mww 0xfc600098 0x00001302 ;# MEMCTL_GP_10 + mww 0xfc60009c 0x00001c1c ;# MEMCTL_DLL_SET_01 + mww 0xfc6000a0 0x7c000000 ;# MEMCTL_DQS_OUT_SHIFT + mww 0xfc6000a4 0x005c0000 ;# MEMCTL_WR_DQS_SHIFT + mww 0xfc6000a8 0x2b050e00 ;# MEMCTL_TIME_SET_03 + mww 0xfc6000ac 0x00640064 ;# MEMCTL_AHB_PRRLX_00 + mww 0xfc6000b0 0x00640064 ;# MEMCTL_AHB_PRRLX_01 + mww 0xfc6000b4 0x00000064 ;# MEMCTL_AHB_PRRLX_02 + mww 0xfc6000b8 0x00000000 ;# MEMCTL_OUTRANGE_LGTH + mww 0xfc6000bc 0x00200020 ;# MEMCTL_AHB_RW_SET_00 + mww 0xfc6000c0 0x00200020 ;# MEMCTL_AHB_RW_SET_01 + mww 0xfc6000c4 0x00200020 ;# MEMCTL_AHB_RW_SET_02 + mww 0xfc6000c8 0x00200020 ;# MEMCTL_AHB_RW_SET_03 + mww 0xfc6000cc 0x00200020 ;# MEMCTL_AHB_RW_SET_04 + mww 0xfc6000d8 0x00000a24 ;# MEMCTL_TREF + mww 0xfc6000dc 0x00000000 ;# MEMCTL_EMRS3_DATA + mww 0xfc6000e0 0x5b1c00c8 ;# MEMCTL_TIME_SET_04 + mww 0xfc6000e4 0x00c8002e ;# MEMCTL_TIME_SET_05 + mww 0xfc6000e8 0x00000000 ;# MEMCTL_VERSION + mww 0xfc6000ec 0x0001046b ;# MEMCTL_TINIT + mww 0xfc6000f0 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_01 + mww 0xfc6000f4 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_02 + mww 0xfc600104 0x001c0000 ;# MEMCTL_DLL_DQS_DELAY_BYPASS_0 + mww 0xfc600108 0x0019001c ;# MEMCTL_DLL_SET_02 + mww 0xfc60010c 0x00100000 ;# MEMCTL_DLL_SET_03 + mww 0xfc600110 0x001e007a ;# MEMCTL_DQS_SET_2 + mww 0xfc600188 0x00000000 ;# MEMCTL_USER_DEF_REG_0 + mww 0xfc60018c 0x00000000 ;# MEMCTL_USER_DEF_REG_1 + mww 0xfc600190 0x01010001 ;# MEMCTL_GP_11 + mww 0xfc600194 0x01000000 ;# MEMCTL_GP_12 + mww 0xfc600198 0x00000001 ;# MEMCTL_GP_13 + mww 0xfc60019c 0x00400000 ;# MEMCTL_GP_14 + mww 0xfc6001a0 0x00000000 ;# MEMCTL_EMRS2_DATA_X + mww 0xfc6001a4 0x00000000 ;# MEMCTL_LWPWR_CNT + mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG + mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15 + mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX +} diff --git a/openocd-win/openocd/scripts/chip/st/stm32/stm32.tcl b/openocd-win/openocd/scripts/chip/st/stm32/stm32.tcl new file mode 100644 index 0000000..3826a57 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/stm32/stm32.tcl @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find bitsbytes.tcl] +source [find cpu/arm/cortex_m3.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +source [find chip/st/stm32/stm32_regs.tcl] +source [find chip/st/stm32/stm32_rcc.tcl] diff --git a/openocd-win/openocd/scripts/chip/st/stm32/stm32_rcc.tcl b/openocd-win/openocd/scripts/chip/st/stm32/stm32_rcc.tcl new file mode 100644 index 0000000..afa4cbf --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/stm32/stm32_rcc.tcl @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set RCC_CR [expr {$RCC_BASE + 0x00}] +set RCC_CFGR [expr {$RCC_BASE + 0x04}] +set RCC_CIR [expr {$RCC_BASE + 0x08}] +set RCC_APB2RSTR [expr {$RCC_BASE + 0x0c}] +set RCC_APB1RSTR [expr {$RCC_BASE + 0x10}] +set RCC_AHBENR [expr {$RCC_BASE + 0x14}] +set RCC_APB2ENR [expr {$RCC_BASE + 0x18}] +set RCC_APB1ENR [expr {$RCC_BASE + 0x1c}] +set RCC_BDCR [expr {$RCC_BASE + 0x20}] +set RCC_CSR [expr {$RCC_BASE + 0x24}] + + +proc show_RCC_CR { } { + if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] { + error $msg + } + + show_mmr_bitfield 0 0 $val HSI { OFF ON } + show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY } + show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ } + show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ } + show_mmr_bitfield 16 16 $val HSEON { OFF ON } + show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY } + show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED } + show_mmr_bitfield 19 19 $val CSSON { OFF ON } + show_mmr_bitfield 24 24 $val PLLON { OFF ON } + show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY } +} + +proc show_RCC_CFGR { } { + if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] { + error $msg + } + + + show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL } + show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL } + show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 } + show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } + show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 } + show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 } + show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE } + show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 } + show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 } + show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 } + show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 } +} + + +proc show_RCC_CIR { } { + if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] { + error $msg + } + +} + +proc show_RCC_APB2RSTR { } { + if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] { + error $msg + } + for { set x 0 } { $x < 32 } { incr x } { + set bits($x) xxx + } + set bits(15) adc3 + set bits(14) usart1 + set bits(13) tim8 + set bits(12) spi1 + set bits(11) tim1 + set bits(10) adc2 + set bits(9) adc1 + set bits(8) iopg + set bits(7) iopf + set bits(6) iope + set bits(5) iopd + set bits(4) iopc + set bits(3) iopb + set bits(2) iopa + set bits(1) xxx + set bits(0) afio + show_mmr32_bits bits $val +} + +proc show_RCC_APB1RSTR { } { + if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] { + error $msg + } + set bits(31) xxx + set bits(30) xxx + set bits(29) dac + set bits(28) pwr + set bits(27) bkp + set bits(26) xxx + set bits(25) can + set bits(24) xxx + set bits(23) usb + set bits(22) i2c2 + set bits(21) i2c1 + set bits(20) uart5 + set bits(19) uart4 + set bits(18) uart3 + set bits(17) uart2 + set bits(16) xxx + set bits(15) spi3 + set bits(14) spi2 + set bits(13) xxx + set bits(12) xxx + set bits(11) wwdg + set bits(10) xxx + set bits(9) xxx + set bits(8) xxx + set bits(7) xxx + set bits(6) xxx + set bits(5) tim7 + set bits(4) tim6 + set bits(3) tim5 + set bits(2) tim4 + set bits(1) tim3 + set bits(0) tim2 + show_mmr32_bits bits $val + +} + +proc show_RCC_AHBENR { } { + if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] { + error $msg + } + set bits(31) xxx + set bits(30) xxx + set bits(29) xxx + set bits(28) xxx + set bits(27) xxx + set bits(26) xxx + set bits(25) xxx + set bits(24) xxx + set bits(23) xxx + set bits(22) xxx + set bits(21) xxx + set bits(20) xxx + set bits(19) xxx + set bits(18) xxx + set bits(17) xxx + set bits(16) xxx + set bits(15) xxx + set bits(14) xxx + set bits(13) xxx + set bits(12) xxx + set bits(11) xxx + set bits(10) sdio + set bits(9) xxx + set bits(8) fsmc + set bits(7) xxx + set bits(6) crce + set bits(5) xxx + set bits(4) flitf + set bits(3) xxx + set bits(2) sram + set bits(1) dma2 + set bits(0) dma1 + show_mmr32_bits bits $val +} + +proc show_RCC_APB2ENR { } { + if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] { + error $msg + } + set bits(31) xxx + set bits(30) xxx + set bits(29) xxx + set bits(28) xxx + set bits(27) xxx + set bits(26) xxx + set bits(25) xxx + set bits(24) xxx + set bits(23) xxx + set bits(22) xxx + set bits(21) xxx + set bits(20) xxx + set bits(19) xxx + set bits(18) xxx + set bits(17) xxx + set bits(16) xxx + set bits(15) adc3 + set bits(14) usart1 + set bits(13) tim8 + set bits(12) spi1 + set bits(11) tim1 + set bits(10) adc2 + set bits(9) adc1 + set bits(8) iopg + set bits(7) iopf + set bits(6) iope + set bits(5) iopd + set bits(4) iopc + set bits(3) iopb + set bits(2) iopa + set bits(1) xxx + set bits(0) afio + show_mmr32_bits bits $val + +} + +proc show_RCC_APB1ENR { } { + if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] { + error $msg + } + set bits(31) xxx + set bits(30) xxx + set bits(29) dac + set bits(28) pwr + set bits(27) bkp + set bits(26) xxx + set bits(25) can + set bits(24) xxx + set bits(23) usb + set bits(22) i2c2 + set bits(21) i2c1 + set bits(20) usart5 + set bits(19) usart4 + set bits(18) usart3 + set bits(17) usart2 + set bits(16) xxx + set bits(15) spi3 + set bits(14) spi2 + set bits(13) xxx + set bits(12) xxx + set bits(11) wwdg + set bits(10) xxx + set bits(9) xxx + set bits(8) xxx + set bits(7) xxx + set bits(6) xxx + set bits(5) tim7 + set bits(4) tim6 + set bits(3) tim5 + set bits(2) tim4 + set bits(1) tim3 + set bits(0) tim2 + show_mmr32_bits bits $val +} + +proc show_RCC_BDCR { } { + if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] { + error $msg + } + for { set x 0 } { $x < 32 } { incr x } { + set bits($x) xxx + } + set bits(0) lseon + set bits(1) lserdy + set bits(2) lsebyp + set bits(8) rtcsel0 + set bits(9) rtcsel1 + set bits(15) rtcen + set bits(16) bdrst + show_mmr32_bits bits $val +} + +proc show_RCC_CSR { } { + if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] { + error $msg + } + for { set x 0 } { $x < 32 } { incr x } { + set bits($x) xxx + } + set bits(0) lsion + set bits(1) lsirdy + set bits(24) rmvf + set bits(26) pin + set bits(27) por + set bits(28) sft + set bits(29) iwdg + set bits(30) wwdg + set bits(31) lpwr + show_mmr32_bits bits $val +} + +proc show_RCC { } { + + show_RCC_CR + show_RCC_CFGR + show_RCC_CIR + show_RCC_APB2RSTR + show_RCC_APB1RSTR + show_RCC_AHBENR + show_RCC_APB2ENR + show_RCC_APB1ENR + show_RCC_BDCR + show_RCC_CSR +} diff --git a/openocd-win/openocd/scripts/chip/st/stm32/stm32_regs.tcl b/openocd-win/openocd/scripts/chip/st/stm32/stm32_regs.tcl new file mode 100644 index 0000000..07ff1aa --- /dev/null +++ b/openocd-win/openocd/scripts/chip/st/stm32/stm32_regs.tcl @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# /* Peripheral and SRAM base address in the alias region */ +set PERIPH_BB_BASE 0x42000000 +set SRAM_BB_BASE 0x22000000 + +# /*Peripheral and SRAM base address in the bit-band region */ +set SRAM_BASE 0x20000000 +set PERIPH_BASE 0x40000000 + +# /*FSMC registers base address */ +set FSMC_R_BASE 0xA0000000 + +# /*Peripheral memory map */ +set APB1PERIPH_BASE [set PERIPH_BASE] +set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}] +set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}] + +set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}] +set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}] +set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}] +set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}] +set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}] +set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}] +set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}] +set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}] +set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}] +set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}] +set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}] +set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}] +set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}] +set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}] +set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}] +set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}] +set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}] +set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}] +set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}] +set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}] +set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}] + +set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}] +set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}] +set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}] +set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}] +set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}] +set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}] +set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}] +set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}] +set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}] +set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}] +set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}] +set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}] +set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}] +set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}] +set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}] +set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}] + +set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}] + +set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}] +set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}] +set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}] +set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}] +set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}] +set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}] +set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}] +set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}] +set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}] +set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}] +set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}] +set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}] +set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}] +set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}] +set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}] +set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}] + +# /*Flash registers base address */ +set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}] +# /*Flash Option Bytes base address */ +set OB_BASE 0x1FFFF800 + +# /*FSMC Bankx registers base address */ +set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}] +set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}] +set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}] +set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}] +set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}] + +# /*Debug MCU registers base address */ +set DBGMCU_BASE 0xE0042000 + +# /*System Control Space memory map */ +set SCS_BASE 0xE000E000 + +set SysTick_BASE [expr {$SCS_BASE + 0x0010}] +set NVIC_BASE [expr {$SCS_BASE + 0x0100}] +set SCB_BASE [expr {$SCS_BASE + 0x0D00}] diff --git a/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s.tcl b/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s.tcl new file mode 100644 index 0000000..324aad0 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s.tcl @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find chip/ti/lm3s/lm3s_regs.tcl] diff --git a/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s_regs.tcl b/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s_regs.tcl new file mode 100644 index 0000000..1e86e29 --- /dev/null +++ b/openocd-win/openocd/scripts/chip/ti/lm3s/lm3s_regs.tcl @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#***************************************************************************** +# +# The following are defines for the System Control register addresses. +# +#***************************************************************************** + +set SYSCTL_DID0 0x400FE000 ;# Device Identification 0 +set SYSCTL_DID1 0x400FE004 ;# Device Identification 1 +set SYSCTL_DC0 0x400FE008 ;# Device Capabilities 0 +set SYSCTL_DC1 0x400FE010 ;# Device Capabilities 1 +set SYSCTL_DC2 0x400FE014 ;# Device Capabilities 2 +set SYSCTL_DC3 0x400FE018 ;# Device Capabilities 3 +set SYSCTL_DC4 0x400FE01C ;# Device Capabilities 4 +set SYSCTL_DC5 0x400FE020 ;# Device Capabilities 5 +set SYSCTL_DC6 0x400FE024 ;# Device Capabilities 6 +set SYSCTL_DC7 0x400FE028 ;# Device Capabilities 7 +set SYSCTL_DC8 0x400FE02C ;# Device Capabilities 8 ADC + ;# Channels +set SYSCTL_PBORCTL 0x400FE030 ;# Brown-Out Reset Control +set SYSCTL_LDOPCTL 0x400FE034 ;# LDO Power Control +set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0 +set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1 +set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2 +set SYSCTL_RIS 0x400FE050 ;# Raw Interrupt Status +set SYSCTL_IMC 0x400FE054 ;# Interrupt Mask Control +set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and + ;# Clear +set SYSCTL_RESC 0x400FE05C ;# Reset Cause +set SYSCTL_RCC 0x400FE060 ;# Run-Mode Clock Configuration +set SYSCTL_PLLCFG 0x400FE064 ;# XTAL to PLL Translation +set SYSCTL_GPIOHSCTL 0x400FE06C ;# GPIO High-Speed Control +set SYSCTL_GPIOHBCTL 0x400FE06C ;# GPIO High-Performance Bus + ;# Control +set SYSCTL_RCC2 0x400FE070 ;# Run-Mode Clock Configuration 2 +set SYSCTL_MOSCCTL 0x400FE07C ;# Main Oscillator Control +set SYSCTL_RCGC0 0x400FE100 ;# Run Mode Clock Gating Control + ;# Register 0 +set SYSCTL_RCGC1 0x400FE104 ;# Run Mode Clock Gating Control + ;# Register 1 +set SYSCTL_RCGC2 0x400FE108 ;# Run Mode Clock Gating Control + ;# Register 2 +set SYSCTL_SCGC0 0x400FE110 ;# Sleep Mode Clock Gating Control + ;# Register 0 +set SYSCTL_SCGC1 0x400FE114 ;# Sleep Mode Clock Gating Control + ;# Register 1 +set SYSCTL_SCGC2 0x400FE118 ;# Sleep Mode Clock Gating Control + ;# Register 2 +set SYSCTL_DCGC0 0x400FE120 ;# Deep Sleep Mode Clock Gating + ;# Control Register 0 +set SYSCTL_DCGC1 0x400FE124 ;# Deep-Sleep Mode Clock Gating + ;# Control Register 1 +set SYSCTL_DCGC2 0x400FE128 ;# Deep Sleep Mode Clock Gating + ;# Control Register 2 +set SYSCTL_DSLPCLKCFG 0x400FE144 ;# Deep Sleep Clock Configuration +set SYSCTL_CLKVCLR 0x400FE150 ;# Clock Verification Clear +set SYSCTL_PIOSCCAL 0x400FE150 ;# Precision Internal Oscillator + ;# Calibration +set SYSCTL_PIOSCSTAT 0x400FE154 ;# Precision Internal Oscillator + ;# Statistics +set SYSCTL_LDOARST 0x400FE160 ;# Allow Unregulated LDO to Reset + ;# the Part +set SYSCTL_I2SMCLKCFG 0x400FE170 ;# I2S MCLK Configuration +set SYSCTL_DC9 0x400FE190 ;# Device Capabilities 9 ADC + ;# Digital Comparators +set SYSCTL_NVMSTAT 0x400FE1A0 ;# Non-Volatile Memory Information + +set SYSCTL_RCC_USESYSDIV 0x00400000 ;# Enable System Clock Divider +set SYSCTL_RCC2_BYPASS2 0x00000800 ;# PLL Bypass 2 +set SYSCTL_RCC_MOSCDIS 0x00000001 ;# Main Oscillator Disable + +set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0 +set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1 +set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2 + +set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and Clear + +set FLASH_FMA 0x400FD000 ;# Flash Memory Address +set FLASH_FMD 0x400FD004 ;# Flash Memory Data +set FLASH_FMC 0x400FD008 ;# Flash Memory Control +set FLASH_FCRIS 0x400FD00C ;# Flash Controller Raw Interrupt Status +set FLASH_FCIM 0x400FD010 ;# Flash Controller Interrupt Mask +set FLASH_FCMISC 0x400FD014 ;# Flash Controller Masked Interrupt Status and Clear +set FLASH_FMC2 0x400FD020 ;# Flash Memory Control 2 +set FLASH_FWBVAL 0x400FD030 ;# Flash Write Buffer Valid diff --git a/openocd-win/openocd/scripts/cpld/altera-5m570z-cpld.cfg b/openocd-win/openocd/scripts/cpld/altera-5m570z-cpld.cfg new file mode 100644 index 0000000..4504a80 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/altera-5m570z-cpld.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg +echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg" + +#just to be backward compatible: +#tap will be 5m570z.tap instead of maxv.tap: +set CHIPNAME 5m570z +source [find cpld/altera-maxv.cfg] diff --git a/openocd-win/openocd/scripts/cpld/altera-epm240.cfg b/openocd-win/openocd/scripts/cpld/altera-epm240.cfg new file mode 100644 index 0000000..185925a --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/altera-epm240.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# file altera-epm240.cfg replaced by altera-maxii.cfg +echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg" + +#just to be backward compatible: +#tap will be epm240.tap instead of maxii.tap: +set CHIPNAME epm240 +source [find cpld/altera-maxii.cfg] + +# 200ns seems like a good speed +# c.f. Table 5-34: MAX II JTAG Timing Parameters +adapter speed 5000 diff --git a/openocd-win/openocd/scripts/cpld/altera-max10.cfg b/openocd-win/openocd/scripts/cpld/altera-max10.cfg new file mode 100644 index 0000000..a2ed00a --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/altera-max10.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# see MAX 10 FPGA Device Architecture +# Table 3-1: IDCODE Information for MAX 10 Devices +# Intel MAX 10M02 0x31810dd +# Intel MAX 10M04 0x318a0dd +# Intel MAX 10M08 0x31820dd +# Intel MAX 10M16 0x31830dd +# Intel MAX 10M25 0x31840dd +# Intel MAX 10M40 0x318d0dd +# Intel MAX 10M50 0x31850dd +# Intel MAX 10M02 0x31010dd +# Intel MAX 10M04 0x310a0dd +# Intel MAX 10M08 0x31020dd +# Intel MAX 10M16 0x31030dd +# Intel MAX 10M25 0x31040dd +# Intel MAX 10M40 0x310d0dd +# Intel MAX 10M50 0x31050dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME max10 +} + +jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \ + -expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \ + -expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \ + -expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \ + -expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd diff --git a/openocd-win/openocd/scripts/cpld/altera-maxii.cfg b/openocd-win/openocd/scripts/cpld/altera-maxii.cfg new file mode 100644 index 0000000..2dee37f --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/altera-maxii.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Altera MAXII CPLD + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME maxii +} + +# see MAX II Device Handbook +# Table 3-3: 32-Bit MAX II Device IDCODE +# Version Part Number Manuf. ID LSB +# 0000 0010 0000 1010 0001 000 0110 1110 1 +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020a10dd \ + -expected-id 0x020a20dd \ + -expected-id 0x020a30dd \ + -expected-id 0x020a40dd \ + -expected-id 0x020a50dd \ + -expected-id 0x020a60dd diff --git a/openocd-win/openocd/scripts/cpld/altera-maxv.cfg b/openocd-win/openocd/scripts/cpld/altera-maxv.cfg new file mode 100644 index 0000000..03fad07 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/altera-maxv.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Altera MAXV 5M24OZ/5M570Z CPLD +# see MAX V Device Handbook +# Table 6-3: 32-Bit MAX V Device IDCODE +# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD +# 5M570Z: 0x020A60DD +# 5M1270Z: 0x020A30DD +# 5M1270Z 5M2210Z: 0x020A40DD + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME maxv +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020A50DD -expected-id 0x020A60DD \ + -expected-id 0x020A30DD -expected-id 0x020A40DD diff --git a/openocd-win/openocd/scripts/cpld/jtagspi.cfg b/openocd-win/openocd/scripts/cpld/jtagspi.cfg new file mode 100644 index 0000000..4c84792 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/jtagspi.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _USER1 0x02 + +if { [info exists JTAGSPI_IR] } { + set _JTAGSPI_IR $JTAGSPI_IR +} else { + set _JTAGSPI_IR $_USER1 +} + +if { [info exists TARGETNAME] } { + set _TARGETNAME $TARGETNAME +} else { + set _TARGETNAME $_CHIPNAME.proxy +} + +if { [info exists FLASHNAME] } { + set _FLASHNAME $FLASHNAME +} else { + set _FLASHNAME $_CHIPNAME.spi +} + +target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap +flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR + +# initialize jtagspi flash +# chain_id: identifier of pld (you can get a list with 'pld devices') +# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD. +# release_from_pwr_down_cmd: optional, command sent to spi flash before probing. +# ex: 0xAB to release from power-dowm. +# Just omit it to not send a command. + +proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} { + # load proxy bitstream $proxy_bit and probe spi flash + global _FLASHNAME + pld load $chain_id $proxy_bit + reset halt + if {$release_from_pwr_down_cmd != -1} { + jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd + } + flash probe $_FLASHNAME +} + +proc jtagspi_program {bin addr} { + # write and verify binary file $bin at offset $addr + global _FLASHNAME + flash write_image erase $bin $addr + flash verify_bank $_FLASHNAME $bin $addr +} diff --git a/openocd-win/openocd/scripts/cpld/lattice-lc4032ze.cfg b/openocd-win/openocd/scripts/cpld/lattice-lc4032ze.cfg new file mode 100644 index 0000000..479180f --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/lattice-lc4032ze.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Lattice ispMACH 4000ZE family, device LC4032ZE +# just configure a tap +jtag newtap LC4032ZE tap -irlen 8 -expected-id 0x01806043 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc3s.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc3s.cfg new file mode 100644 index 0000000..a886739 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc3s.cfg @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx spartan3 +# https://docs.xilinx.com/v/u/en-US/ug332 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc3s +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x01414093 \ + -expected-id 0x0141C093 \ + -expected-id 0x01428093 \ + -expected-id 0x01434093 \ + -expected-id 0x01440093 \ + -expected-id 0x01448093 \ + -expected-id 0x01450093 \ + -expected-id 0x01C10093 \ + -expected-id 0x01C1A093 \ + -expected-id 0x01C22093 \ + -expected-id 0x01C2E093 \ + -expected-id 0x01C3A093 \ + -expected-id 0x0140C093 \ + -expected-id 0x02210093 \ + -expected-id 0x02218093 \ + -expected-id 0x02220093 \ + -expected-id 0x02228093 \ + -expected-id 0x02230093 \ + -expected-id 0x02610093 \ + -expected-id 0x02618093 \ + -expected-id 0x02620093 \ + -expected-id 0x02628093 \ + -expected-id 0x02630093 \ + -expected-id 0x03840093 \ + -expected-id 0x0384e093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc4v.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc4v.cfg new file mode 100644 index 0000000..3eb46eb --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc4v.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 4 +# https://docs.xilinx.com/v/u/en-US/ug071 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc4v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x01658093 \ + -expected-id 0x01E58093 \ + -expected-id 0x0167C093 \ + -expected-id 0x02068093 \ + -expected-id 0x01E64093 \ + -expected-id 0x016A4093 \ + -expected-id 0x02088093 \ + -expected-id 0x016B4093 \ + -expected-id 0x020B0093 \ + -expected-id 0x016D8093 \ + -expected-id 0x01700093 \ + -expected-id 0x01718093 \ + -expected-id 0x01734093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg new file mode 100644 index 0000000..14dde02 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 4 +# https://docs.xilinx.com/v/u/en-US/ug071 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc4vfx +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \ + -expected-id 0x01E8C093 \ + -expected-id 0x01EB4093 \ + -expected-id 0x01EE4093 \ + -expected-id 0x01F14093 \ + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD +virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc5v.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc5v.cfg new file mode 100644 index 0000000..f88bbc1 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc5v.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 5 +# https://docs.xilinx.com/v/u/en-US/ug191 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc5v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x0286E093 \ + -expected-id 0x02896093 \ + -expected-id 0x028AE093 \ + -expected-id 0x028D6093 \ + -expected-id 0x028EC093 \ + -expected-id 0x0290C093 \ + -expected-id 0x0295C093 \ + -expected-id 0x02A56093 \ + -expected-id 0x02A6E093 \ + -expected-id 0x02A96093 \ + -expected-id 0x02AAE093 \ + -expected-id 0x02AD6093 \ + -expected-id 0x02AEC093 \ + -expected-id 0x02B0C093 \ + -expected-id 0x02B5C093 \ + -expected-id 0x02E72093 \ + -expected-id 0x02E9A093 \ + -expected-id 0x02ECE093 \ + -expected-id 0x02F3E093 \ + -expected-id 0x03276093 \ + -expected-id 0x032C6093 \ + -expected-id 0x04502093 \ + -expected-id 0x0453E093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg new file mode 100644 index 0000000..7420233 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 5 +# https://docs.xilinx.com/v/u/en-US/ug191 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc5vfx +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \ + -expected-id 0x032D8093 \ + -expected-id 0x03300093 \ + -expected-id 0x03334093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD +virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc6s.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc6s.cfg new file mode 100644 index 0000000..92b2605 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc6s.cfg @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx spartan6 +# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc6s +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x04000093 \ + -expected-id 0x04001093 \ + -expected-id 0x04002093 \ + -expected-id 0x04004093 \ + -expected-id 0x04024093 \ + -expected-id 0x04008093 \ + -expected-id 0x04028093 \ + -expected-id 0x0400E093 \ + -expected-id 0x0402E093 \ + -expected-id 0x04011093 \ + -expected-id 0x04031093 \ + -expected-id 0x0401D093 \ + -expected-id 0x0403D093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B + +set XC6S_CFG_IN 0x05 +set XC6S_JSHUTDOWN 0x0d +set XC6S_JPROGRAM 0x0b +set XC6S_JSTART 0x0c +set XC6S_BYPASS 0x3f + +proc xc6s_program {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program'" + global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS + irscan $tap $XC6S_JSHUTDOWN + irscan $tap $XC6S_JPROGRAM + irscan $tap $XC6S_JSTART + irscan $tap $XC6S_BYPASS +} + +#xtp038 and xc3sprog approach +proc xc6s_program_iprog {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'xc6s_program_iprog'" + global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN + irscan $tap $XC6S_JSHUTDOWN + runtest 16 + irscan $tap $XC6S_CFG_IN + # xtp038 IPROG 16bit flipped + drscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004 + irscan $tap $XC6S_JSTART + runtest 32 + irscan $tap $XC6S_BYPASS + runtest 1 +} + +set XC6S_ISC_ENABLE 0x10 +set XC6S_ISC_DISABLE 0x16 +set XC6S_ISC_DNA 0x30 + +# Get the "Device DNA" from the Spartan 6. +# Most Xilinx FPGA devices contain an embedded, unique device identifier called +# the "Device DNA". The identifier is nonvolatile, permanently programmed into +# the FPGA, and is unchangeable providing a great serial / tracking number. +proc xc6s_get_dna {tap} { + global XC6S_ISC_ENABLE XC6S_ISC_DISABLE XC6S_ISC_DNA + irscan $tap $XC6S_ISC_ENABLE + runtest 64 + irscan $tap $XC6S_ISC_DNA + # Device DNA is 57 bits long, but we can only read 32bits at a time + # with OpenOCD. + set dna [drscan $tap 16 0 16 0 16 0 9 0] + runtest 64 + irscan $tap $XC6S_ISC_DISABLE + runtest 64 + + # Convert the binary data into the order impact uses + scan $dna "%x %x %x %x" v1 v2 v3 v4 + set bin_dna [string reverse [concat [format "%09b" $v4][format "%016b" $v3][format "%016b" $v2][format "%016b" $v1]]] + + # Return a hex version of binary + scan [format "0b%s" $bin_dna] "%i" hex_dna + return $hex_dna +} + +# Print out the "Device DNA" in the same format that impact uses. +proc xc6s_print_dna {tap} { + set hex_dna [xc6s_get_dna $tap] + + puts [format "DNA = %57b (0x%x)\n" $hex_dna $hex_dna] +} diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc6v.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc6v.cfg new file mode 100644 index 0000000..d37439c --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc6v.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx virtex 6 +# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc6v +} + +# the 4 top bits (28:31) are the die stepping. ignore it. +jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \ + -expected-id 0x042A2093 \ + -expected-id 0x042A4093 \ + -expected-id 0x042A8093 \ + -expected-id 0x042AC093 \ + -expected-id 0x04244093 \ + -expected-id 0x0424A093 \ + -expected-id 0x0424C093 \ + -expected-id 0x04250093 \ + -expected-id 0x04252093 \ + -expected-id 0x04256093 \ + -expected-id 0x0423A093 \ + -expected-id 0x04286093 \ + -expected-id 0x04288093 \ + -expected-id 0x042C4093 \ + -expected-id 0x042CA093 \ + -expected-id 0x042CC093 \ + -expected-id 0x042D0093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap +# cfg_out cfg_in jprogb jstart jshutdown user1-4 +virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD +virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc7.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc7.cfg new file mode 100644 index 0000000..f5b0733 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc7.cfg @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (spartan, artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7 +} + +# the 4 top bits (28:31) are the die stepping/revisions. ignore it. +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x03622093 \ + -expected-id 0x03620093 \ + -expected-id 0x037C4093 \ + -expected-id 0x0362F093 \ + -expected-id 0x037C8093 \ + -expected-id 0x037C7093 \ + -expected-id 0x037C3093 \ + -expected-id 0x0362E093 \ + -expected-id 0x037C2093 \ + -expected-id 0x0362D093 \ + -expected-id 0x0362C093 \ + -expected-id 0x03632093 \ + -expected-id 0x03631093 \ + -expected-id 0x03636093 \ + -expected-id 0x03647093 \ + -expected-id 0x0364C093 \ + -expected-id 0x03651093 \ + -expected-id 0x03747093 \ + -expected-id 0x03656093 \ + -expected-id 0x03752093 \ + -expected-id 0x03751093 \ + -expected-id 0x03671093 \ + -expected-id 0x03667093 \ + -expected-id 0x03682093 \ + -expected-id 0x03687093 \ + -expected-id 0x03692093 \ + -expected-id 0x03691093 \ + -expected-id 0x03696093 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23 + +set XC7_JSHUTDOWN 0x0d +set XC7_JPROGRAM 0x0b +set XC7_JSTART 0x0c +set XC7_BYPASS 0x3f + +proc xc7_program {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'xc7_program'" + global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS + irscan $tap $XC7_JSHUTDOWN + irscan $tap $XC7_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XC7_JSTART + runtest 2000 + irscan $tap $XC7_BYPASS + runtest 2000 +} diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc7v.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc7v.cfg new file mode 100644 index 0000000..8385948 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc7v.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77 +# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77 +# +# this config file is for XC7VX1140T and XC7V2000T only. +# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7v +} + +#0x036D5093: XC7VX1140T +#0x036By093: XC7V2000T +#y = xx11 = 3, 7, B or F + +jtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \ + -expected-id 0x036B3093 -expected-id 0x036B7093 \ + -expected-id 0x036BB093 -expected-id 0x036BF093 \ + -expected-id 0x036D5093 + +#CFG_OUT_SLR0 0x124924 +#CFG_IN_SLR0 0x164924 +#CFG_OUT_SLR1 0x904924 +#CFG_IN_SLR1 0x905924 +#CFG_OUT_SLR2 0x924124 +#CFG_IN_SLR2 0x924164 +#CFG_OUT_SLR3 0x924904 +#CFG_IN_SLR3 0x924905 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc7vh580t.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc7vh580t.cfg new file mode 100644 index 0000000..3748049 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc7vh580t.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77 +# +# this config file is for xc7vh580t only. +# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7vh580t +} + +jtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093 + +#CFG_OUT_SLR0 0x0492A0 +#CFG_IN_SLR0 0x0592A0 +#CFG_OUT_SLR1 0x2412A0 +#CFG_IN_SLR1 0x2416A0 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xc7vh870t.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xc7vh870t.cfg new file mode 100644 index 0000000..25e2e63 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xc7vh870t.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# xilinx series 7 (artix, kintex, virtex) +# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77 +# +# this config file is for xc7vh870t only. +# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xc7vh870t +} + +jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093 + +#CFG_OUT_SLR0 0x0492A092A0 +#CFG_IN_SLR0 0x0592A092A0 +#CFG_OUT_SLR1 0x2412A092A0 +#CFG_IN_SLR1 0x2416A092A0 +#CFG_OUT_SLR2 0x2492A012A0 +#CFG_IN_SLR2 0x2492A016A0 + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart +# cfg_out cfg_in jprogb jstart jshutdown +virtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xcf-p.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xcf-p.cfg new file mode 100644 index 0000000..7b6d384 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xcf-p.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xcf +} + +# IDs acquired from Xilinx's DS123.pdf +# XCF08P <v>5057093 +# XCF16P <v>5058093 +# XCF32P <v>5059093 +# The 4 top bits (28:31) are the device revision. Ignore it. +jtag newtap $_CHIPNAME flash -irlen 16 -ignore-version \ + -expected-id 0x05057093 \ + -expected-id 0x05058093 \ + -expected-id 0x05059093 + +target create xcf.flash testee -chain-position $_CHIPNAME.flash +flash bank XCF_P xcf 0 0 0 0 xcf.flash diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xcf-s.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xcf-s.cfg new file mode 100644 index 0000000..417ecff --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xcf-s.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xcf +} + +# IDs acquired from Xilinx's DS123.pdf +# XCF01S <v>5044093 +# XCF02S <v>5045093 +# XCF04S <v>5046093 +# The 4 top bits (28:31) are the device revision. Ignore it. +jtag newtap $_CHIPNAME flash -irlen 8 -ignore-version \ + -expected-id 0x05044093 \ + -expected-id 0x05045093 \ + -expected-id 0x05046093 + +target create xcf.flash testee -chain-position $_CHIPNAME.flash +flash bank XCF_S xcf 0 0 0 0 xcf.flash diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xcr3256.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xcr3256.cfg new file mode 100644 index 0000000..4668e54 --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xcr3256.cfg @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#xilinx coolrunner xcr3256 +#simple device - just configure a tap +jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id 0x0494c093 diff --git a/openocd-win/openocd/scripts/cpld/xilinx-xcu.cfg b/openocd-win/openocd/scripts/cpld/xilinx-xcu.cfg new file mode 100644 index 0000000..4d7f26c --- /dev/null +++ b/openocd-win/openocd/scripts/cpld/xilinx-xcu.cfg @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Xilinx Ultrascale (Kintex, Virtex, Zynq) +# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xcu +} + +# The various chips in the Ultrascale family have different IR length. +# Set $CHIP before including this file to determine the device. +array set _XCU_DATA { + XCKU025 {0x03824093 6} + XCKU035 {0x03823093 6} + XCKU040 {0x03822093 6} + XCKU060 {0x03919093 6} + XCKU060_CIV {0x0381b093 6} + XCKU095 {0x03844093 6} + XCKU095_CIV {0x03845093 6} + XCKU3P {0x04A63093 6} + XCKU5P {0x04A62093 6} + XCKU9P {0x0484A093 6} + XCKU11P {0x04A4E093 6} + XCKU11P_CIV {0x04A51093 6} + XCKU13P {0x04A52093 6} + XCKU15P {0x04A56093 6} + XCKU15P_CIV {0x04A59093 6} + XCVU065 {0x03939093 6} + XCVU065_CIV {0x0393b093 6} + XCVU080 {0x03843093 6} + XCVU080_CIV {0x03845093 6} + XCVU095 {0x03842093 6} + XCVU2P {0x04aea093 6} + XCVU3P {0x04B39093 6} + XCVU3P_CIV {0x04b3d093 6} + XCAU10P {0x04AC4033 6} + XCAU10P_FFVB676 {0x04AC4093 6} + XCAU15P {0x04AC2033 6} + XCAU15P_FFVB676 {0x04AC2093 6} + XCAU20P {0x04A65093 6} + XCAU25P {0x04A64093 6} + XCKU5P_CIV {0x04A64093 6} + XCKU19P {0x04ACF093 6} + XCKU19P_CIV {0x04AD3093 6} + XCKU085 {0x0380F093 12} + XCKU115 {0x0390D093 12} + XCVU125 {0x0392D093 12} + XCVU125_CIV {0x0392f093 12} + XCVU5P {0x04B2B093 12} + XCVU5P_CIV {0x04b2f093 12} + XCVU7P {0x04B29093 12} + XCVU7P_CIV {0x04b2d093 12} + XCVU160 {0x03933093 18} + XCVU190 {0x03931093 18} + XCVU440 {0x0396D093 18} + XCVU440_CIV {0x0396f093 18} + XCVU9P {0x04B31093 18} + XCVU9P_CIV {0x04b35093 18} + XCVU11P {0x04B49093 18} + XCVU11P_CIV {0x04b4f093 18} + XCU200_FSGD2104 {0x04b37093 18} + XCU250 {0x04b57093 24} + XCVU13P {0x04B51093 24} + XCVU13P_CIV {0x04b55093 24} + XCVU15P {0x04ba3093 24} + XCVU19P {0x04ba1093 24} + XCVU19P_CIV {0x04ba5093 24} +} + +if { ![info exists CHIP] } { + error "set CHIP to one of "[concat [array names _XCU_DATA]] +} + +if { ![llength [array names _XCU_DATA $CHIP]] } { + error "unknown CHIP: "$CHIP +} + +set _EXPID [lindex $_XCU_DATA($CHIP) 0] +set _IRLEN [lindex $_XCU_DATA($CHIP) 1] + +# the 4 top bits (28:31) are the die stepping/revisions. ignore it. +jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID + +pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart + +# set the correct instruction codes for jtag hub and +# at least the right code for jprogb, jstart and jshutdown for SSI devices +if { $_IRLEN == 6 } { + virtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23 +} elseif {$_IRLEN == 12 } { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d + virtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4 +} elseif {$_IRLEN == 18 } { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d + virtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4 +} else { + puts "loading bitstream through jtag will not work, but reprogram (refresh)" + virtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d + virtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924 +} + +set XCU_JSHUTDOWN 0x0d +set XCU_JPROGRAM 0x0b +set XCU_JSTART 0x0c +set XCU_BYPASS 0x3f + +proc xcu_program {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'xcu_program'" + global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS + irscan $tap $XCU_JSHUTDOWN + irscan $tap $XCU_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XCU_JSTART + runtest 2000 + irscan $tap $XCU_BYPASS + runtest 2000 +} diff --git a/openocd-win/openocd/scripts/cpu/arc/common.tcl b/openocd-win/openocd/scripts/cpu/arc/common.tcl new file mode 100644 index 0000000..e0de70b --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arc/common.tcl @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2015, 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# Things common to all ARCs + +# It is assumed that target is already halted. +proc arc_common_reset { {target ""} } { + if { $target != "" } { + targets $target + } + + halt + + # 1. Interrupts are disabled (STATUS32.IE) + # 2. The status register flags are cleared. + # All fields, except the H bit, are set to 0 when the processor is Reset. + + arc jtag set-aux-reg 0xA 0x1 + + # 3. The loop count, loop start, and loop end registers are cleared. + arc jtag set-core-reg 60 0 + arc jtag set-aux-reg 0x2 0 + arc jtag set-aux-reg 0x3 0 + + # Program execution begins at the address referenced by the four byte reset + # vector located at the interrupt vector base address, which is the first + # entry (offset 0x00) in the vector table. + set int_vector_base [arc jtag get-aux-reg 0x25] + set start_pc [read_memory $int_vector_base 32 1] + arc jtag set-aux-reg 0x6 $start_pc + + # It is OK to do uncached writes - register cache will be invalidated by + # the reset_assert() function. +} + +# vim:expandtab: diff --git a/openocd-win/openocd/scripts/cpu/arc/em.tcl b/openocd-win/openocd/scripts/cpu/arc/em.tcl new file mode 100644 index 0000000..13c5b43 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arc/em.tcl @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2015, 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +source [find cpu/arc/v2.tcl] + +proc arc_em_examine_target { {target ""} } { + # Will set current target + arc_v2_examine_target $target +} + +proc arc_em_init_regs { } { + arc_v2_init_regs + + [target current] configure \ + -event examine-end "arc_em_examine_target [target current]" +} + +# Scripts in "target" folder should call this function instead of direct +# invocation of arc_common_reset. +proc arc_em_reset { {target ""} } { + arc_v2_reset $target + + # Set DEBUG.ED bit to enable clock in actionpoint module. + # This is specific to ARC EM. + set debug [arc jtag get-aux-reg 5] + if { !($debug & (1 << 20)) } { + arc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}] + } +} diff --git a/openocd-win/openocd/scripts/cpu/arc/hs.tcl b/openocd-win/openocd/scripts/cpu/arc/hs.tcl new file mode 100644 index 0000000..28e04f9 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arc/hs.tcl @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2015, 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +source [find cpu/arc/v2.tcl] + +proc arc_hs_examine_target { target } { + # Will set current target for us. + arc_v2_examine_target $target +} + +proc arc_hs_init_regs { } { + arc_v2_init_regs + + [target current] configure \ + -event examine-end "arc_hs_examine_target [target current]" +} + +# Scripts in "target" folder should call this function instead of direct +# invocation of arc_common_reset. +proc arc_hs_reset { {target ""} } { + arc_v2_reset $target + + # Invalidate L2 cache if there is one. + set l2_config [$target arc jtag get-aux-reg 0x901] + # Will return 0, if cache is not present and register doesn't exist. + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } { + puts "L2 cache is present and not disabled" + + # Wait until BUSY bit is 0. + puts "Invalidating L2 cache..." + $target arc jtag set-aux-reg 0x905 1 + # Dummy read of SLC_AUX_CACHE_CTRL bit, as described in: + # https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854 + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + while { ($l2_ctrl & 0x100) != 0 } { + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + } + + # Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate + # operation already flushed everything. + if { ($l2_ctrl & 0x40) == 0 } { + puts "Flushing L2 cache..." + $target arc jtag set-aux-reg 0x904 1 + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + while { [expr {$l2_ctrl & 0x100}] != 0 } { + set l2_ctrl [$target arc jtag get-aux-reg 0x903] + } + } + + puts "L2 cache has been flushed and invalidated." + } +} diff --git a/openocd-win/openocd/scripts/cpu/arc/v2.tcl b/openocd-win/openocd/scripts/cpu/arc/v2.tcl new file mode 100644 index 0000000..b24a67d --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arc/v2.tcl @@ -0,0 +1,346 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2015, 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +source [find cpu/arc/common.tcl] + +# Currently 'examine_target' can only read JTAG registers and set properties - +# but it shouldn't write any of registers - writes will be cached, but cache +# will be invalidated before flushing after examine_target, and changes will be +# lost. Perhaps that would be fixed later - perhaps writes shouldn't be cached +# after all. But if write to register is really needed from TCL - then it +# should be done via "arc jtag" for now. +proc arc_v2_examine_target { {target ""} } { + # Set current target, because OpenOCD event handlers don't do this for us. + if { $target != "" } { + targets $target + } + + # Those registers always exist. DEBUG and DEBUGI are formally optional, + # however they come with JTAG interface, and so far there is no way + # OpenOCD can communicate with target without JTAG interface. + arc set-reg-exists identity pc status32 bta debug lp_start lp_end \ + eret erbta erstatus ecr efa + + # 32 core registers + arc set-reg-exists \ + r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 \ + r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \ + gp fp sp ilink r30 blink lp_count pcl + + # Actionpoints + if { [arc get-reg-field ap_build version] == 5 } { + set ap_build_type [arc get-reg-field ap_build type] + # AP_BUILD.TYPE > 0b0110 is reserved in current ISA. + # Current ISA supports up to 8 actionpoints. + if { $ap_build_type < 8 } { + # Two LSB bits of AP_BUILD.TYPE define amount of actionpoints: + # 0b00 - 2 actionpoints + # 0b01 - 4 actionpoints + # 0b10 - 8 actionpoints + # 0b11 - reserved. + set ap_num [expr {0x2 << ($ap_build_type & 3)}] + # Expression on top may produce 16 action points - which is a + # reserved value for now. + if { $ap_num < 16 } { + # Enable actionpoint registers + for {set i 0} {$i < $ap_num} {incr i} { + arc set-reg-exists ap_amv$i ap_amm$i ap_ac$i + } + + # Set amount of actionpoints + arc num-actionpoints $ap_num + } + } + } + + # DCCM + set dccm_version [arc get-reg-field dccm_build version] + if { $dccm_version == 3 || $dccm_version == 4 } { + arc set-reg-exists aux_dccm + } + + # ICCM + if { [arc get-reg-field iccm_build version] == 4 } { + arc set-reg-exists aux_iccm + } + + # MPU + if { [arc get-reg-field mpu_build version] >= 2 && + [arc get-reg-field mpu_build version] <= 4 } { + arc set-reg-exists mpu_en mpu_ecr + set mpu_regions [arc get-reg-field mpu_build regions] + for {set i 0} {$i < $mpu_regions} {incr i} { + arc set-reg-exists mpu_rdp$i mpu_rdb$i + } + + # Secure MPU + if { [arc get-reg-field mpu_build version] == 4 } { + arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper + } + } +} + +proc arc_v2_init_regs { } { + # XML features + set core_feature "org.gnu.gdb.arc.core.v2" + set aux_min_feature "org.gnu.gdb.arc.aux-minimal" + set aux_other_feature "org.gnu.gdb.arc.aux-other" + + # Describe types + # Types are sorted alphabetically according to their name. + arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \ + -bitfield type 8 11 + arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \ + -bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9 + # Cycles field added in version 4. + arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \ + -bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19 + + arc add-reg-type-struct -name debug_t \ + -bitfield fh 1 1 -bitfield ah 2 2 -bitfield asr 3 10 \ + -bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \ + -bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \ + -bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \ + -bitfield sh 30 30 -bitfield ld 31 31 + + arc add-reg-type-struct -name ecr_t \ + -bitfield parameter 0 7 \ + -bitfield cause 8 15 \ + -bitfield vector 16 23 \ + -bitfield U 30 30 \ + -bitfield P 31 31 + arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \ + -bitfield iccm0_size0 8 11 -bitfield iccm1_size0 12 15 \ + -bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23 + arc add-reg-type-struct -name identity_t \ + -bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31 + arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \ + -bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \ + -bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \ + -bitfield c 24 27 -bitfield d 28 31 + arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \ + -bitfield regions 8 15 \ + -bitfield s 16 16 \ + -bitfield i 17 17 + arc add-reg-type-struct -name mpu_ecr_t \ + -bitfield MR 0 7 \ + -bitfield VT 8 9 \ + -bitfield EC_CODE 16 31 + arc add-reg-type-struct -name mpu_en_t \ + -bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \ + -bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \ + -bitfield S 15 15 -bitfield SID 16 23 \ + -bitfield EN 30 30 + arc add-reg-type-struct -name mpu_index_t \ + -bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31 + arc add-reg-type-struct -name mpu_rper_t \ + -bitfield V 0 0 \ + -bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \ + -bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \ + -bitfield S 15 15 -bitfield SID 16 23 + arc add-reg-type-flags -name status32_t \ + -flag H 0 -flag E0 1 -flag E1 2 -flag E2 3 \ + -flag E3 4 -flag AE 5 -flag DE 6 -flag U 7 \ + -flag V 8 -flag C 9 -flag N 10 -flag Z 11 \ + -flag L 12 -flag DZ 13 -flag SC 14 -flag ES 15 \ + -flag RB0 16 -flag RB1 17 -flag RB2 18 \ + -flag AD 19 -flag US 20 -flag IE 31 + + # Core registers + set core_regs { + r0 0 uint32 + r1 1 uint32 + r2 2 uint32 + r3 3 uint32 + r4 4 uint32 + r5 5 uint32 + r6 6 uint32 + r7 7 uint32 + r8 8 uint32 + r9 9 uint32 + r10 10 uint32 + r11 11 uint32 + r12 12 uint32 + r13 13 uint32 + r14 14 uint32 + r15 15 uint32 + r16 16 uint32 + r17 17 uint32 + r18 18 uint32 + r19 19 uint32 + r20 20 uint32 + r21 21 uint32 + r22 22 uint32 + r23 23 uint32 + r24 24 uint32 + r25 25 uint32 + gp 26 data_ptr + fp 27 data_ptr + sp 28 data_ptr + ilink 29 code_ptr + r30 30 uint32 + blink 31 code_ptr + r32 32 uint32 + r33 33 uint32 + r34 34 uint32 + r35 35 uint32 + r36 36 uint32 + r37 37 uint32 + r38 38 uint32 + r39 39 uint32 + r40 40 uint32 + r41 41 uint32 + r42 42 uint32 + r43 43 uint32 + r44 44 uint32 + r45 45 uint32 + r46 46 uint32 + r47 47 uint32 + r48 48 uint32 + r49 49 uint32 + r50 50 uint32 + r51 51 uint32 + r52 52 uint32 + r53 53 uint32 + r54 54 uint32 + r55 55 uint32 + r56 56 uint32 + r57 57 uint32 + accl 58 uint32 + acch 59 uint32 + lp_count 60 uint32 + limm 61 uint32 + reserved 62 uint32 + pcl 63 code_ptr + } + foreach {reg count type} $core_regs { + arc add-reg -name $reg -num $count -core -type $type -g \ + -feature $core_feature + } + + # AUX min + set aux_min { + 0x6 pc code_ptr + 0x2 lp_start code_ptr + 0x3 lp_end code_ptr + 0xA status32 status32_t + } + foreach {num name type} $aux_min { + arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g + } + + # AUX other + set aux_other { + 0x004 identity identity_t + 0x005 debug debug_t + 0x018 aux_dccm int + 0x208 aux_iccm int + + 0x220 ap_amv0 uint32 + 0x221 ap_amm0 uint32 + 0x222 ap_ac0 ap_control_t + 0x223 ap_amv1 uint32 + 0x224 ap_amm1 uint32 + 0x225 ap_ac1 ap_control_t + 0x226 ap_amv2 uint32 + 0x227 ap_amm2 uint32 + 0x228 ap_ac2 ap_control_t + 0x229 ap_amv3 uint32 + 0x22A ap_amm3 uint32 + 0x22B ap_ac3 ap_control_t + 0x22C ap_amv4 uint32 + 0x22D ap_amm4 uint32 + 0x22E ap_ac4 ap_control_t + 0x22F ap_amv5 uint32 + 0x230 ap_amm5 uint32 + 0x231 ap_ac5 ap_control_t + 0x232 ap_amv6 uint32 + 0x233 ap_amm6 uint32 + 0x234 ap_ac6 ap_control_t + 0x235 ap_amv7 uint32 + 0x236 ap_amm7 uint32 + 0x237 ap_ac7 ap_control_t + + 0x400 eret code_ptr + 0x401 erbta code_ptr + 0x402 erstatus status32_t + 0x403 ecr ecr_t + 0x404 efa data_ptr + + 0x409 mpu_en mpu_en_t + + 0x412 bta code_ptr + + 0x420 mpu_ecr mpu_ecr_t + 0x422 mpu_rdb0 int + 0x423 mpu_rdp0 int + 0x424 mpu_rdb1 int + 0x425 mpu_rdp1 int + 0x426 mpu_rdb2 int + 0x427 mpu_rdp2 int + 0x428 mpu_rdb3 int + 0x429 mpu_rdp3 int + 0x42A mpu_rdb4 int + 0x42B mpu_rdp4 int + 0x42C mpu_rdb5 int + 0x42D mpu_rdp5 int + 0x42E mpu_rdb6 int + 0x42F mpu_rdp6 int + 0x430 mpu_rdb7 int + 0x431 mpu_rdp7 int + 0x432 mpu_rdb8 int + 0x433 mpu_rdp8 int + 0x434 mpu_rdb9 int + 0x435 mpu_rdp9 int + 0x436 mpu_rdb10 int + 0x437 mpu_rdp10 int + 0x438 mpu_rdb11 int + 0x439 mpu_rdp11 int + 0x43A mpu_rdb12 int + 0x43B mpu_rdp12 int + 0x43C mpu_rdb13 int + 0x43D mpu_rdp13 int + 0x43E mpu_rdb14 int + 0x43F mpu_rdp14 int + 0x440 mpu_rdb15 int + 0x441 mpu_rdp15 int + 0x448 mpu_index mpu_index_t + 0x449 mpu_rstart uint32 + 0x44A mpu_rend uint32 + 0x44B mpu_rper mpu_rper_t + 0x44C mpu_probe uint32 + } + foreach {num name type} $aux_other { + arc add-reg -name $name -num $num -type $type -feature $aux_other_feature + } + + # AUX BCR + set bcr { + 0x6D mpu_build + 0x74 dccm_build + 0x76 ap_build + 0x78 iccm_build + 0xC1 isa_config + } + foreach {num reg} $bcr { + arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature + } + + [target current] configure \ + -event examine-end "arc_v2_examine_target [target current]" +} + +proc arc_v2_reset { {target ""} } { + arc_common_reset $target + + # Disable all actionpoints. Cannot write via regcache yet, because it will + # not be flushed and all changes to registers will get lost. Therefore has + # to write directly via JTAG layer... + set num_ap [arc num-actionpoints] + for {set i 0} {$i < $num_ap} {incr i} { + arc jtag set-aux-reg [expr {0x222 + $i * 3}] 0 + } +} diff --git a/openocd-win/openocd/scripts/cpu/arm/arm7tdmi.tcl b/openocd-win/openocd/scripts/cpu/arm/arm7tdmi.tcl new file mode 100644 index 0000000..e407a23 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arm/arm7tdmi.tcl @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set CPU_TYPE arm +set CPU_NAME arm7tdmi +set CPU_ARCH armv4t +set CPU_MAX_ADDRESS 0xFFFFFFFF +set CPU_NBITS 32 diff --git a/openocd-win/openocd/scripts/cpu/arm/arm920.tcl b/openocd-win/openocd/scripts/cpu/arm/arm920.tcl new file mode 100644 index 0000000..1c5a8ad --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arm/arm920.tcl @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set CPU_TYPE arm +set CPU_NAME arm920 +set CPU_ARCH armv4t +set CPU_MAX_ADDRESS 0xFFFFFFFF +set CPU_NBITS 32 diff --git a/openocd-win/openocd/scripts/cpu/arm/arm946.tcl b/openocd-win/openocd/scripts/cpu/arm/arm946.tcl new file mode 100644 index 0000000..602d4d7 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arm/arm946.tcl @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set CPU_TYPE arm +set CPU_NAME arm946 +set CPU_ARCH armv5te +set CPU_MAX_ADDRESS 0xFFFFFFFF +set CPU_NBITS 32 diff --git a/openocd-win/openocd/scripts/cpu/arm/arm966.tcl b/openocd-win/openocd/scripts/cpu/arm/arm966.tcl new file mode 100644 index 0000000..0e64312 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arm/arm966.tcl @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set CPU_TYPE arm +set CPU_NAME arm966 +set CPU_ARCH armv5te +set CPU_MAX_ADDRESS 0xFFFFFFFF +set CPU_NBITS 32 diff --git a/openocd-win/openocd/scripts/cpu/arm/cortex_m3.tcl b/openocd-win/openocd/scripts/cpu/arm/cortex_m3.tcl new file mode 100644 index 0000000..0791664 --- /dev/null +++ b/openocd-win/openocd/scripts/cpu/arm/cortex_m3.tcl @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set CPU_TYPE arm +set CPU_NAME cortex_m3 +set CPU_ARCH armv7 +set CPU_MAX_ADDRESS 0xFFFFFFFF +set CPU_NBITS 32 diff --git a/openocd-win/openocd/scripts/fpga/altera-10m50.cfg b/openocd-win/openocd/scripts/fpga/altera-10m50.cfg new file mode 100644 index 0000000..94228d2 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-10m50.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# file altera-10m50.cfg replaced by altera-max10.cfg +echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg" + +#just to be backward compatible: +#tap will be 10m50.tap instead of max10.tap: +set CHIPNAME 10m50 +source [find cpld/altera-max10.cfg] diff --git a/openocd-win/openocd/scripts/fpga/altera-arriaii.cfg b/openocd-win/openocd/scripts/fpga/altera-arriaii.cfg new file mode 100644 index 0000000..d59c182 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-arriaii.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Arria II FPGA +# Arria II Device Handbook +# Table 11–2. 32-Bit IDCODE for Arria II Devices + +#GX: +#EP2AGX45: 0x025120dd +#EP2AGX65: 0x025020dd +#EP2AGX95: 0x025130dd +#EP2AGX125: 0x025030dd +#EP2AGX190: 0x025140dd +#EP2AGX260: 0x025040dd +#EP2AGZ225: 0x024810dd +#EP2AGZ300: 0x0240a0dd +#EP2AGZ350: 0x024820dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME arriaii +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x025120dd -expected-id 0x025040dd \ + -expected-id 0x025020dd -expected-id 0x024810dd \ + -expected-id 0x025130dd -expected-id 0x0240a0dd \ + -expected-id 0x025030dd -expected-id 0x024820dd \ + -expected-id 0x025140dd + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii diff --git a/openocd-win/openocd/scripts/fpga/altera-cyclone10.cfg b/openocd-win/openocd/scripts/fpga/altera-cyclone10.cfg new file mode 100644 index 0000000..3a1bc1f --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-cyclone10.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone 10 FPGA +# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html +# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf + +# GX085: 0x02e120dd +# GX105: 0x02e320dd +# GX150: 0x02e720dd +# GX220: 0x02ef20dd +# 10cl006: 0x020f10dd +# 10cl010: 0x020f10dd +# 10cl016: 0x020f20dd +# 10cl025: 0x020f30dd +# 10cl040: 0x020f40dd +# 10cl055: 0x020f50dd +# 10cl080: 0x020f60dd +# 10cl120: 0x020f70dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cyclone10 +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x02e720dd -expected-id 0x02e120dd \ + -expected-id 0x02ef20dd -expected-id 0x02e320dd \ + -expected-id 0x020f10dd -expected-id 0x020f20dd \ + -expected-id 0x020f30dd -expected-id 0x020f40dd \ + -expected-id 0x020f50dd -expected-id 0x020f60dd \ + -expected-id 0x020f70dd + +pld device intel $_CHIPNAME.tap cyclone10 diff --git a/openocd-win/openocd/scripts/fpga/altera-cycloneiii.cfg b/openocd-win/openocd/scripts/fpga/altera-cycloneiii.cfg new file mode 100644 index 0000000..d9be645 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-cycloneiii.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone III FPGA +# see Cyclone III Device Handbook +# Table 12-2: Device IDCODE for Cyclone III Device Family + +#EP3C5 0x020f10dd +#EP3C10 0x020f10dd +#EP3C16 0x020f20dd +#EP3C25 0x020f30dd +#EP3C40 0x020f40dd +#EP3C55 0x020f50dd +#EP3C80 0x020f60dd +#EP3C120 0x020f70dd +#Cyclone III LS +#EP3CLS70 0x027010dd +#EP3CLS100 0x027000dd +#EP3CLS150 0x027030dd +#EP3CLS200 0x027020dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cycloneiii +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020f10dd -expected-id 0x020f20dd \ + -expected-id 0x020f30dd -expected-id 0x020f40dd \ + -expected-id 0x020f50dd -expected-id 0x020f60dd \ + -expected-id 0x020f70dd -expected-id 0x027010dd \ + -expected-id 0x027000dd -expected-id 0x027030dd \ + -expected-id 0x027020dd + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii diff --git a/openocd-win/openocd/scripts/fpga/altera-cycloneiv.cfg b/openocd-win/openocd/scripts/fpga/altera-cycloneiv.cfg new file mode 100644 index 0000000..6a908e8 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-cycloneiv.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone IV FPGA +# see Cyclone IV Device Handbook +# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices + +#EP4CE6 0x020f10dd +#EP4CE10 0x020f10dd +#EP4CE15 0x020f20dd +#EP4CE22 0x020f30dd +#EP4CE30 0x020f40dd +#EP4CE40 0x020f40dd +#EP4CE55 0x020f50dd +#EP4CE75 0x020f60dd +#EP4CE115 0x020f70dd +#EP4CGX15 0x028010dd +#EP4CGX22 0x028120dd +#EP4CGX30 (3) 0x028020dd +#EP4CGX30 (4) 0x028230dd +#EP4CGX50 0x028130dd +#EP4CGX75 0x028030dd +#EP4CGX110 0x028140dd +#EP4CGX150 0x028040dd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cycloneiv +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x020f10dd -expected-id 0x020f20dd \ + -expected-id 0x020f30dd -expected-id 0x020f40dd \ + -expected-id 0x020f50dd -expected-id 0x020f60dd \ + -expected-id 0x020f70dd -expected-id 0x028010dd \ + -expected-id 0x028120dd -expected-id 0x028020dd \ + -expected-id 0x028230dd -expected-id 0x028130dd \ + -expected-id 0x028030dd -expected-id 0x028140dd \ + -expected-id 0x028040dd + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv diff --git a/openocd-win/openocd/scripts/fpga/altera-cyclonev.cfg b/openocd-win/openocd/scripts/fpga/altera-cyclonev.cfg new file mode 100644 index 0000000..46532a5 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-cyclonev.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel Cyclone 5 FPGA +# see Cyclone V Device Handbook +# Table 9-1: IDCODE Information for Cyclone V Devices + +#5CEA2 0x02b150dd +#5CEA4 0x02b050dd +#5CEA5 0x02b220dd +#5CEA7 0x02b130dd +#5CEA9 0x02b140dd +#5CGXC3 0x02b010dd +#5CGXC4 0x02b120dd +#5CGXC5 0x02b020dd +#5CGXC7 0x02b030dd +#5CGXC9 0x02b040dd +#5CGTD5 0x02b020dd +#5CGTD7 0x02b030dd +#5CGTD9 0x02b040dd +#5CSEA2 0x02d110dd +#5CSEA4 0x02d010dd +#5CSEA5 0x02d120dd +#5CSEA6 0x02d020dd +#5CSXC2 0x02d110dd +#5CSXC4 0x02d010dd +#5CSXC5 0x02d120dd +#5CSXC6 0x02d020dd +#5CSTD5 0x02d120dd +#5CSTD6 0x02d020dd + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cyclonev +} + +jtag newtap $_CHIPNAME tap -irlen 10 \ + -expected-id 0x02b150dd -expected-id 0x02b050dd \ + -expected-id 0x02b220dd -expected-id 0x02b130dd \ + -expected-id 0x02b140dd -expected-id 0x02b010dd \ + -expected-id 0x02b120dd -expected-id 0x02b020dd \ + -expected-id 0x02b030dd -expected-id 0x02b040dd \ + -expected-id 0x02d110dd -expected-id 0x02d010dd \ + -expected-id 0x02d120dd -expected-id 0x02d020dd + +pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev diff --git a/openocd-win/openocd/scripts/fpga/altera-ep3c10.cfg b/openocd-win/openocd/scripts/fpga/altera-ep3c10.cfg new file mode 100644 index 0000000..d7a92d7 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/altera-ep3c10.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg +echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg" + +#just to be backward compatible: +#tap will be ep3c10.tap instead of cycloneiii.tap: +set CHIPNAME ep3c10 +source [find fpga/altera-cycloneiii.cfg] diff --git a/openocd-win/openocd/scripts/fpga/efinix_titanium.cfg b/openocd-win/openocd/scripts/fpga/efinix_titanium.cfg new file mode 100644 index 0000000..3c2cdd7 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/efinix_titanium.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# efinix titanium +# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME titanium +} + +jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \ + -expected-id 0x10661A79 \ + -expected-id 0x00360A79 \ + -expected-id 0x10660A79 \ + -expected-id 0x00681A79 \ + -expected-id 0x00688A79 \ + -expected-id 0x00682A79 \ + -expected-id 0x0068CA79 \ + -expected-id 0x00680A79 \ + -expected-id 0x00684A79 + +pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium diff --git a/openocd-win/openocd/scripts/fpga/efinix_trion.cfg b/openocd-win/openocd/scripts/fpga/efinix_trion.cfg new file mode 100644 index 0000000..1c789f5 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/efinix_trion.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# efinix trion +# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME trion +} + +jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \ + -expected-id 0x00210A79 \ + -expected-id 0x00240A79 \ + -expected-id 0x00220A79 + +pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion diff --git a/openocd-win/openocd/scripts/fpga/gatemate.cfg b/openocd-win/openocd/scripts/fpga/gatemate.cfg new file mode 100644 index 0000000..e8f3382 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/gatemate.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# GateMateTM FPGA +# https://www.colognechip.com/programmable-logic/gatemate/ +# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gatemate +} + +jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ + -expected-id 0x20000001 + +pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/gowin_gw1n.cfg b/openocd-win/openocd/scripts/fpga/gowin_gw1n.cfg new file mode 100644 index 0000000..5e85066 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/gowin_gw1n.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Gowin FPGA IDCODEs +# from JTAG Programming and Configuration Guide +# http://cdn.gowinsemi.com.cn/TN653E.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gw1n +} + +jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \ + -expected-id 0x0900281B \ + -expected-id 0x0900381B \ + -expected-id 0x0100681B \ + -expected-id 0x0300081B \ + -expected-id 0x0300181B \ + -expected-id 0x0120681B \ + -expected-id 0x0100381B \ + -expected-id 0x1100381B \ + -expected-id 0x0100981B \ + -expected-id 0x1100581B \ + -expected-id 0x1100481B \ + -expected-id 0x0100181B \ + -expected-id 0x1100181B \ + -expected-id 0x0100481B + +pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_certus.cfg b/openocd-win/openocd/scripts/fpga/lattice_certus.cfg new file mode 100644 index 0000000..9ddb7d8 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_certus.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME certus +} + +# Lattice Certus +# +# Certus NX LFD2NX-17 0x310f0043 +# Certus NX LFD2NX-40 0x310f1043 + + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x310F1043 -expected-id 0x310F0043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_certuspro.cfg b/openocd-win/openocd/scripts/fpga/lattice_certuspro.cfg new file mode 100644 index 0000000..acaaa57 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_certuspro.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME certuspro +} + +# Lattice CertusPro +# +# 0x010f4043 - LFCPNX-100 +# 0x 043 - LFCPNX-50 + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x010f4043 +# -expected-id 0x01112043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_ecp2.cfg b/openocd-win/openocd/scripts/fpga/lattice_ecp2.cfg new file mode 100644 index 0000000..5b01787 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_ecp2.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ecp2 +} + +# Lattice ECP2 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M +# +# LFE2M20E: 0x01279043 +# LFE2M35E: 0x0127A043 +# LFE2M50E: 0x0127B043 +# LFE2M70E: 0x0127C043 +# LFE2M100E: 0x0127D043 +# LFEC2_6E: 0x01270043 +# LFEC2_12E: 0x01271043 +# LFEC2_20E: 0x01272043 +# LFEC2_35E: 0x01274043 +# LFEC2_50E: 0x01273043 +# LFEC2_70E: 0x01275043 + +jtag newtap $_CHIPNAME tap -irlen 8 \ + -expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \ + -expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \ + -expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \ + -expected-id 0x01273043 -expected-id 0x01275043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_ecp3.cfg b/openocd-win/openocd/scripts/fpga/lattice_ecp3.cfg new file mode 100644 index 0000000..21c8ffa --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_ecp3.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ecp3 +} + +# Lattice ECP3 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3 +# +# LFE3_17: 0x01010043 +# LFE3_35: 0x01012043 +# LFE3_95: 0x01014043 and LFE3_70 +# LFE3_150: 0x01015043 + +jtag newtap $_CHIPNAME tap -irlen 8 \ + -expected-id 0x01010043 -expected-id 0x01012043 \ + -expected-id 0x01014043 -expected-id 0x01015043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_ecp5.cfg b/openocd-win/openocd/scripts/fpga/lattice_ecp5.cfg new file mode 100644 index 0000000..cdc63f0 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_ecp5.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ecp5 +} + +# Lattice ECP5 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5 +# +# 0x01111043 - LAE5UM_25F/LFE5UM_25F +# 0x01112043 - LAE5UM_45F/LFE5UM_45F +# 0x01113043 - LAE5UM_85F/LFE5UM_85 +# 0x21111043 - LFE5U_12F +# 0x41111043 - LFE5U_25F +# 0x41112043 - LFE5U_45F +# 0x41113043 - LFE5U_85F +# 0x81111043 - LFE5UM5G-25 +# 0x81112043 - LFE5UM5G-45 +# 0x81113043 - LFE5UM5G-85 + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \ + -expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \ + -expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \ + -expected-id 0x81113043 + +pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap diff --git a/openocd-win/openocd/scripts/fpga/lattice_machxo3.cfg b/openocd-win/openocd/scripts/fpga/lattice_machxo3.cfg new file mode 100644 index 0000000..37fa054 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/lattice_machxo3.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME machxo3 +} + +# Lattice MachXO3 family +# TAP IDs are extracted from BSDL files found on this page: +# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3 +# +# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121 +# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49 +# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81 +# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324 +# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256 +# 0x412bb043 - LCMXO3L_2100C_XXBG256 +# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324 +# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400 +# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484 +# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36 +# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49 +# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81 +# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324 +# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256 +# 0x612bb043 - LCMXO3LF_2100C_XXBG256 +# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324 +# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400 +# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484 +# 0xc12b2043 - LCMXO3L_640E_XXMG121 +# 0xc12b4043 - LCMXO3L_2100E_XXMG324 +# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256 +# 0xc12bc043 - LCMXO3L_2100C_XXBG324 +# 0xc12bd043 - LCMXO3L_4300C_XXBG400 +# 0xe12b2043 - LCMXO3LF_640E_XXMG121 +# 0xe12b3043 - LCMXO3LF_1300E_XXMG256 +# 0xe12b4043 - LCMXO3LF_2100E_XXMG324 +# 0xe12bb043 - LCMXO3LF_1300C_XXBG256 +# 0xe12bc043 - LCMXO3LF_2100C_XXBG324 +# 0xe12bd043 - LCMXO3LF_4300C_XXBG400 + +jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \ + -expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \ + -expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \ + -expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \ + -expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \ + -expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \ + -expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \ + -expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \ + -expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \ + -expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \ + -expected-id 0xe12bc043 -expected-id 0xe12bd043 diff --git a/openocd-win/openocd/scripts/fpga/xilinx-dna.cfg b/openocd-win/openocd/scripts/fpga/xilinx-dna.cfg new file mode 100644 index 0000000..56f8c14 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/xilinx-dna.cfg @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc xilinx_dna_addr {chip} { + array set addrs { + Spartan6 0x30 + Series7 0x17 + } + return $addrs($chip) +} + +# Get the "Device DNA". +# Most Xilinx FPGA devices contain an embedded, unique device identifier. +# The identifier is nonvolatile, permanently programmed into +# the FPGA, and is unchangeable providing a great serial / tracking number. +# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed. +# This is compatible with the FUSE DNA which contains all 64 bits. +proc xilinx_get_dna {tap chip} { + set XC7_ISC_ENABLE 0x10 + set XC7_ISC_DISABLE 0x16 + set XC7_ISC_DNA [xilinx_dna_addr $chip] + + irscan $tap $XC7_ISC_ENABLE + runtest 64 + irscan $tap $XC7_ISC_DNA + scan [drscan $tap 32 0 32 0] "%08x %08x" hi lo + runtest 64 + irscan $tap $XC7_ISC_DISABLE + runtest 64 + # openocd interprets DR scans as LSB first, bit-reverse it + return [scan [string reverse [format "%032b%032bb0" $lo $hi]] "%i"] +} + +# Print out the "Device DNA" in the same format that impact uses. +proc xilinx_print_dna {dna} { + set dna [expr {$dna >> 64 - 57}] + echo [format "DNA = %057b (0x%016x)" $dna $dna] +} + +proc xc7_get_dna {tap} { + return [xilinx_get_dna $tap Series7] +} + +proc xc6s_get_dna {tap} { + return [xilinx_get_dna $tap Spartan6] +} diff --git a/openocd-win/openocd/scripts/fpga/xilinx-xadc.cfg b/openocd-win/openocd/scripts/fpga/xilinx-xadc.cfg new file mode 100644 index 0000000..fdaf3a9 --- /dev/null +++ b/openocd-win/openocd/scripts/fpga/xilinx-xadc.cfg @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Xilinx XADC support for 7 Series FPGAs +# +# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die +# temperature, internal power supply rail voltages as well as external +# voltages. The XADC is available both from fabric as well as through the +# JTAG TAP. +# +# This code implements access through the JTAG TAP. +# +# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf + +# build a 32 bit DRP command for the XADC DR +proc xadc_cmd {cmd addr data} { + array set cmds { + NOP 0x00 + READ 0x01 + WRITE 0x02 + } + return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}] +} + +# XADC register addresses +# Some addresses (status registers 0-3) have special function when written to. +proc XADC {key} { + array set addrs { + TEMP 0x00 + LOCK 0x00 + VCCINT 0x01 + VCCAUX 0x02 + VAUXEN 0x02 + VPVN 0x03 + RESET 0x03 + VREFP 0x04 + VREFN 0x05 + VCCBRAM 0x06 + SUPAOFFS 0x08 + ADCAOFFS 0x09 + ADCAGAIN 0x0a + VCCPINT 0x0d + VCCPAUX 0x0e + VCCODDR 0x0f + VAUX0 0x10 + VAUX1 0x11 + VAUX2 0x12 + VAUX3 0x13 + VAUX4 0x14 + VAUX5 0x15 + VAUX6 0x16 + VAUX7 0x17 + VAUX8 0x18 + VAUX9 0x19 + VAUX10 0x1a + VAUX11 0x1b + VAUX12 0x1c + VAUX13 0x1d + VAUX14 0x1e + VAUX15 0x1f + SUPBOFFS 0x30 + ADCBOFFS 0x31 + ADCBGAIN 0x32 + FLAG 0x3f + CFG0 0x40 + CFG1 0x41 + CFG2 0x42 + SEQ0 0x48 + SEQ1 0x49 + SEQ2 0x4a + SEQ3 0x4b + SEQ4 0x4c + SEQ5 0x4d + SEQ6 0x4e + SEQ7 0x4f + ALARM0 0x50 + ALARM1 0x51 + ALARM2 0x52 + ALARM3 0x53 + ALARM4 0x54 + ALARM5 0x55 + ALARM6 0x56 + ALARM7 0x57 + ALARM8 0x58 + ALARM9 0x59 + ALARM10 0x5a + ALARM11 0x5b + ALARM12 0x5c + ALARM13 0x5d + ALARM14 0x5e + ALARM15 0x5f + } + return $addrs($key) +} + +# Select the XADC DR +proc xadc_select {tap} { + set XADC_IR 0x37 + irscan $tap $XADC_IR + runtest 10 +} + +# XADC transfer +proc xadc_xfer {tap cmd addr data} { + set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]] + runtest 10 + return [expr "0x$ret"] +} + +# XADC register write +proc xadc_write {tap addr data} { + xadc_xfer $tap WRITE $addr $data +} + +# XADC register read, non-pipelined +proc xadc_read {tap addr} { + xadc_xfer $tap READ $addr 0 + return [xadc_xfer $tap NOP 0 0] +} + +# convert 16 bit register code from ADC measurement on +# external voltages (VAUX) to Volt +proc xadc_volt {code} { + return [expr {$code * 1./(1 << 16)}] +} + +# convert 16 bit temperature measurement to Celsius +proc xadc_temp {code} { + return [expr {$code * 503.975/(1 << 16) - 273.15}] +} + +# convert 16 bit suppply voltage measurement to Volt +proc xadc_sup {code} { + return [expr {$code * 3./(1 << 16)}] +} + +# perform a single channel measurement using default settings +proc xadc_single {tap ch} { + set cfg0 [xadc_read $tap [XADC CFG0]] + set cfg1 [xadc_read $tap [XADC CFG1]] + # set channel + xadc_write $tap [XADC CFG0] $cfg0 + # single channel, disable the sequencer + xadc_write $tap [XADC CFG1] 0x3000 + # leave some time for the conversion + runtest 100 + set ret [xadc_read $tap [XADC $ch]] + # restore CFG0/1 + xadc_write $tap [XADC CFG0] $cfg0 + xadc_write $tap [XADC CFG1] $cfg1 + return $ret +} + +# measure all internal voltages +proc xadc_report {tap} { + xadc_select $tap + echo "TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C" + foreach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \ + VCCPINT VCCPAUX VCCODDR] { + echo "$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V" + } +} diff --git a/openocd-win/openocd/scripts/interface/altera-usb-blaster.cfg b/openocd-win/openocd/scripts/interface/altera-usb-blaster.cfg new file mode 100644 index 0000000..cc6057b --- /dev/null +++ b/openocd-win/openocd/scripts/interface/altera-usb-blaster.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Altera USB-Blaster +# +# http://www.altera.com/literature/ug/ug_usb_blstr.pdf +# + +adapter driver usb_blaster +usb_blaster lowlevel_driver ftdi +# These are already the defaults. +# usb_blaster vid_pid 0x09FB 0x6001 +# usb_blaster device_desc "USB-Blaster" diff --git a/openocd-win/openocd/scripts/interface/altera-usb-blaster2.cfg b/openocd-win/openocd/scripts/interface/altera-usb-blaster2.cfg new file mode 100644 index 0000000..93f9809 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/altera-usb-blaster2.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Altera USB-Blaster II +# + +adapter driver usb_blaster +usb_blaster vid_pid 0x09fb 0x6010 0x09fb 0x6810 +usb_blaster lowlevel_driver ublast2 +usb_blaster firmware /path/to/quartus/blaster_6810.hex diff --git a/openocd-win/openocd/scripts/interface/angie.cfg b/openocd-win/openocd/scripts/interface/angie.cfg new file mode 100644 index 0000000..26cbe39 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/angie.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2023 by NanoXplore, France - all rights reserved +# +# configuration file for ANGIE Adapter from NanoXplore. +# + +adapter driver angie +adapter speed 10000 +reset_config trst_and_srst trst_push_pull srst_open_drain diff --git a/openocd-win/openocd/scripts/interface/arm-jtag-ew.cfg b/openocd-win/openocd/scripts/interface/arm-jtag-ew.cfg new file mode 100644 index 0000000..a064a42 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/arm-jtag-ew.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM-JTAG-EW +# +# http://www.olimex.com/dev/arm-jtag-ew.html +# + +adapter driver arm-jtag-ew diff --git a/openocd-win/openocd/scripts/interface/ast2600-gpiod.cfg b/openocd-win/openocd/scripts/interface/ast2600-gpiod.cfg new file mode 100644 index 0000000..5cad02f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ast2600-gpiod.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Use AST2600 GPIO through linuxgpiod +# +# +-----------+-------------+-------------+ +# | signal | GPIO name | gpio offset | +# +-----------+-------------+-------------+ +# | TCK/SWCLK | GPIOI2 | 66 | +# | TMS/SWDIO | GPIOI3 | 67 | +# | TDI | GPIOI1 | 65 | +# | TDO | GPIOI4 | 68 | +# | nTRST | GPIOI0 | 64 | +# +-----------+-------------+-------------+ + +adapter driver linuxgpiod + +adapter gpio trst 64 -chip 0 +adapter gpio tdi 65 -chip 0 +adapter gpio tck 66 -chip 0 +adapter gpio swclk 66 -chip 0 +adapter gpio tms 67 -chip 0 +adapter gpio swdio 67 -chip 0 +adapter gpio tdo 68 -chip 0 + +reset_config trst_only separate trst_push_pull diff --git a/openocd-win/openocd/scripts/interface/at91rm9200.cfg b/openocd-win/openocd/scripts/interface/at91rm9200.cfg new file mode 100644 index 0000000..caef997 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/at91rm9200.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Various Atmel AT91RM9200 boards +# +# TODO: URL? +# + +adapter driver at91rm9200 +at91rm9200_device rea_ecr diff --git a/openocd-win/openocd/scripts/interface/beaglebone-jtag-native.cfg b/openocd-win/openocd/scripts/interface/beaglebone-jtag-native.cfg new file mode 100644 index 0000000..0240e5d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/beaglebone-jtag-native.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# BeagleBone native GPIO interface for JTAG +# +# This is best used with a fast buffer but it is also suitable for a direct +# connection if the target voltage matches the host's IO voltage (typically +# 3.3V) and the cable is short. +# +# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH. +# +# Do not forget the GND connection. + +adapter driver am335xgpio + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack +# am335xgpio speed SPEED_COEFF SPEED_OFFSET +am335xgpio speed_coeffs 600000 575 + +# BeagleBone pin P9_41 +adapter gpio tdo 20 -chip 0 + +# BeagleBone pin P9_12 +adapter gpio tdi 28 -chip 1 + +# BeagleBone pin P9_18 +adapter gpio tms 4 -chip 0 + +# BeagleBone pin P9_22 +adapter gpio tck 2 -chip 0 + +# BeagleBone pin P9_16 +adapter gpio led 19 -chip 1 + +# BeagleBone pin P8_18 +adapter gpio srst 1 -chip 2 +reset_config srst_only srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/beaglebone-swd-native.cfg b/openocd-win/openocd/scripts/interface/beaglebone-swd-native.cfg new file mode 100644 index 0000000..6c40849 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/beaglebone-swd-native.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# BeagleBone native GPIO interface for SWD +# +# This is best used with a fast buffer but it is also suitable for a direct +# connection if the target voltage matches the host's IO voltage (typically +# 3.3V) and the cable is short. +# +# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH. +# +# Do not forget the GND connection. + +adapter driver am335xgpio + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack +# am335xgpio speed SPEED_COEFF SPEED_OFFSET +am335xgpio speed_coeffs 600000 575 + +# BeagleBone pin P9_22 +adapter gpio swclk 2 -chip 0 + +# BeagleBone pin P9_18 +adapter gpio swdio 4 -chip 0 + +# BeagleBone pin P9_12 +adapter gpio swdio_dir 28 -chip 1 + +# USR0 LED +adapter gpio led 21 -chip 1 + +# BeagleBone pin P8_18 +adapter gpio srst 1 -chip 2 +reset_config srst_only srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/buspirate.cfg b/openocd-win/openocd/scripts/interface/buspirate.cfg new file mode 100644 index 0000000..8f613a7 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/buspirate.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Buspirate with OpenOCD support +# +# http://dangerousprototypes.com/bus-pirate-manual/ +# + +adapter driver buspirate + +# you need to specify port on which BP lives +#buspirate port /dev/ttyUSB0 + +# communication speed setting +buspirate speed normal ;# or fast + +# voltage regulator Enabled = 1 Disabled = 0 +#buspirate vreg 0 + +# pin mode normal or open-drain (jtag only) +#buspirate mode normal + +# pullup state Enabled = 1 Disabled = 0 +#buspirate pullup 0 + +# this depends on the cable, you are safe with this option +reset_config srst_only diff --git a/openocd-win/openocd/scripts/interface/chameleon.cfg b/openocd-win/openocd/scripts/interface/chameleon.cfg new file mode 100644 index 0000000..b73d129 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/chameleon.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Amontec Chameleon POD +# +# http://www.amontec.com/chameleon.shtml +# + +adapter driver parport +parport cable chameleon diff --git a/openocd-win/openocd/scripts/interface/cmsis-dap.cfg b/openocd-win/openocd/scripts/interface/cmsis-dap.cfg new file mode 100644 index 0000000..15efe80 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/cmsis-dap.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# ARM CMSIS-DAP compliant adapter +# +# http://www.keil.com/support/man/docs/dapdebug/ +# + +adapter driver cmsis-dap + +# Optionally specify the serial number of CMSIS-DAP usb device. +# adapter serial 02200201E6661E601B98E3B9 diff --git a/openocd-win/openocd/scripts/interface/dln-2-gpiod.cfg b/openocd-win/openocd/scripts/interface/dln-2-gpiod.cfg new file mode 100644 index 0000000..c9e3388 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/dln-2-gpiod.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Use DLN-2 GPIO through linuxgpiod +# +# +-----------+-------------+-------------+ +# | signal | DLN-2 | gpio offset | +# +-----------+-------------+-------------+ +# | nSRST | J3.1 (PA0) | 0 | +# | TDO | J3.2 (PA1) | 1 | +# | TCK/SWCLK | J3.3 (PA2) | 2 | +# | TMS/SWDIO | J3.4 (PA3) | 3 | +# | TDI | J3.5 (PA4) | 4 | +# | nTRST | J3.6 (PA5) | 5 | +# | LED | J3.7 (PA6) | 6 | +# | GND | J3.12 (GND) | | +# +-----------+-------------+-------------+ + +adapter driver linuxgpiod + +adapter gpio srst 0 -chip 0 +adapter gpio tdo 1 -chip 0 +adapter gpio tck 2 -chip 0 +adapter gpio swclk 2 -chip 0 +adapter gpio tms 3 -chip 0 +adapter gpio swdio 3 -chip 0 +adapter gpio tdi 4 -chip 0 +adapter gpio trst 5 -chip 0 +adapter gpio led 6 -chip 0 + +reset_config trst_and_srst separate srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/dummy.cfg b/openocd-win/openocd/scripts/interface/dummy.cfg new file mode 100644 index 0000000..34e6558 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/dummy.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Dummy interface (for testing purposes) +# + +adapter driver dummy diff --git a/openocd-win/openocd/scripts/interface/esp_usb_bridge.cfg b/openocd-win/openocd/scripts/interface/esp_usb_bridge.cfg new file mode 100644 index 0000000..9342239 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/esp_usb_bridge.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# ESP USB Bridge jtag adapter +# + +adapter driver esp_usb_jtag + +espusbjtag vid_pid 0x303a 0x1002 +espusbjtag caps_descriptor 0x030A # string descriptor index:10 diff --git a/openocd-win/openocd/scripts/interface/esp_usb_jtag.cfg b/openocd-win/openocd/scripts/interface/esp_usb_jtag.cfg new file mode 100644 index 0000000..40427d0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/esp_usb_jtag.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Espressif builtin USB-JTAG adapter +# + +adapter driver esp_usb_jtag + +espusbjtag vid_pid 0x303a 0x1001 +espusbjtag caps_descriptor 0x2000 diff --git a/openocd-win/openocd/scripts/interface/estick.cfg b/openocd-win/openocd/scripts/interface/estick.cfg new file mode 100644 index 0000000..1daaf7c --- /dev/null +++ b/openocd-win/openocd/scripts/interface/estick.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# eStick +# +# http://code.google.com/p/estick-jtag/ +# + +adapter driver opendous diff --git a/openocd-win/openocd/scripts/interface/flashlink.cfg b/openocd-win/openocd/scripts/interface/flashlink.cfg new file mode 100644 index 0000000..d552c50 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/flashlink.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# ST FlashLINK JTAG parallel cable +# +# http://www.st.com/internet/evalboard/product/94023.jsp +# http://www.st.com/stonline/products/literature/um/7889.pdf +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + set _PARPORTADDR 0 +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable flashlink diff --git a/openocd-win/openocd/scripts/interface/ft232r.cfg b/openocd-win/openocd/scripts/interface/ft232r.cfg new file mode 100644 index 0000000..94eed02 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ft232r.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter driver ft232r +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/interface/ft232r/radiona_ulx3s.cfg b/openocd-win/openocd/scripts/interface/ft232r/radiona_ulx3s.cfg new file mode 100644 index 0000000..3fc3d71 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ft232r/radiona_ulx3s.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# This adapter is integrated in to Radiona ULX3S board: +# board/radiona_ulx3s.cfg +# See schematics for the ft232r layout: +# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf + +adapter driver ft232r +adapter speed 1000 +ft232r vid_pid 0x0403 0x6015 +ft232r tck_num DSR +ft232r tms_num DCD +ft232r tdi_num RI +ft232r tdo_num CTS +ft232r trst_num RTS +ft232r srst_num DTR diff --git a/openocd-win/openocd/scripts/interface/ftdi/100ask-openjtag.cfg b/openocd-win/openocd/scripts/interface/ftdi/100ask-openjtag.cfg new file mode 100644 index 0000000..5ab9252 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/100ask-openjtag.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# www.100ask.org OpenJTAG +# +# http://www.100ask.net/OpenJTAG.html +# +# Schematics are available from +# https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf +# + +adapter driver ftdi +ftdi device_desc "USB<=>JTAG&RS232" +ftdi vid_pid 0x1457 0x5118 + +ftdi layout_init 0x0f08 0x0f1b +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg b/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg new file mode 100644 index 0000000..6256aa0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Ashling Opella-LD +# +# https://www.ashling.com/Opella-LD/ +# + +adapter driver ftdi +ftdi device_desc "Opella-LD Debug Probe" +ftdi vid_pid 0x0B6B 0x0040 +ftdi tdo_sample_edge falling +ftdi layout_init 0x0A68 0xFF7B +ftdi channel 0 +ftdi layout_signal JTAGOE -ndata 0x0010 +ftdi layout_signal nTRST -data 0x0020 +ftdi layout_signal nSRST -data 0x0040 +ftdi layout_signal SWD_EN -data 0x0100 +ftdi layout_signal SWDIO_OE -data 0x0200 +ftdi layout_signal LED -ndata 0x0800 +transport select jtag diff --git a/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-swd.cfg b/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-swd.cfg new file mode 100644 index 0000000..4a4e4e0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-swd.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Ashling Opella-LD +# +# https://www.ashling.com/Opella-LD/ +# + +adapter driver ftdi +ftdi device_desc "Opella-LD Debug Probe" +ftdi vid_pid 0x0B6B 0x0040 +ftdi layout_init 0x0860 0x0b7b +ftdi channel 0 +ftdi layout_signal JTAGOE -data 0x0010 +ftdi layout_signal nTRST -data 0x0020 +ftdi layout_signal nSRST -data 0x0040 +ftdi layout_signal SWD_EN -data 0x0100 +ftdi layout_signal SWDIO_OE -data 0x0200 +ftdi layout_signal LED -ndata 0x0800 +transport select swd diff --git a/openocd-win/openocd/scripts/interface/ftdi/axm0432.cfg b/openocd-win/openocd/scripts/interface/ftdi/axm0432.cfg new file mode 100644 index 0000000..5008399 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/axm0432.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Axiom axm0432 +# +# http://www.axman.com +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Symphony SoundBite" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/c232hm.cfg b/openocd-win/openocd/scripts/interface/ftdi/c232hm.cfg new file mode 100644 index 0000000..23c8f3a --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/c232hm.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# FTDI USB Hi-Speed to MPSSE Cable +# +# http://www.ftdichip.com/Products/Cables/USBMPSSE.htm +# +# C232HM-DDHSL-0 and C232HM-EDSL-0 provide 3.3V and 5V on pin 1 (Red), +# respectively. +# +# Adapter: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF +# Chip: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf +# See pinout/colors at end of this file. +# +# Tech notes: +# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf +# http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf + +adapter driver ftdi +#ftdi device_desc "C232HM-DDHSL-0" +#ftdi device_desc "C232HM-EDHSL-0" + +# Common PID for FT232H +ftdi vid_pid 0x0403 0x6014 + +# Layout +# High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low) +# Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low +# High direction byte 0x40 configures red LED on ACBUS6 as high (output) +# Low direction byte 0x0b configures TDO on ACBUS2 as low (input) +ftdi layout_init 0x4008 0x400b + +# ---A*BUS-------CCCCCCCC|DDDDDDDD +# --------\______76543210|76543210 +# LED 0x4000 = 01000000|00000000 = ACBUS6 +#GPIOL0 0x0010 = 00000000|00010000 = ADBUS4 +#GPIOL1 0x0020 = 00000000|00100000 = ADBUS5 +#GPIOL2 0x0040 = 00000000|01000000 = ADBUS6 +#GPIOL3 0x0080 = 00000000|10000000 = ADBUS7 +# -ndata treats the LED as active-low for expected behavior (toggle when transferring) +ftdi layout_signal LED -ndata 0x4000 +# Available for aliasing as desired +ftdi layout_signal GPIOL0 -data 0x0010 -oe 0x0010 +ftdi layout_signal GPIOL1 -data 0x0020 -oe 0x0020 +ftdi layout_signal GPIOL2 -data 0x0040 -oe 0x0040 +ftdi layout_signal GPIOL3 -data 0x0080 -oe 0x0080 + +# C232HM FT232H JTAG/Other +# Num Color Name Func +# 1 Red VCC Optionally, can power the board if it is not using its own power supply. +# 2 Orange ADBUS0 TCK +# 3 Yellow ADBUS1 TDI +# 4 Green ADBUS2 TDO +# 5 Brown ADBUS3 TMS +# 6 Grey ADBUS4 GPIOL0 +# 7 Purple ADBUS5 GPIOL1 +# 8 White ADBUS6 GPIOL2 +# 9 Blue ADBUS7 GPIOL3 +# 10 Black GND Connect to ground diff --git a/openocd-win/openocd/scripts/interface/ftdi/cortino.cfg b/openocd-win/openocd/scripts/interface/ftdi/cortino.cfg new file mode 100644 index 0000000..8bc8d6e --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/cortino.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hitex Cortino +# +# http://www.hitex.com/index.php?id=cortino +# + +adapter driver ftdi +ftdi device_desc "Cortino" +ftdi vid_pid 0x0640 0x0032 + +ftdi layout_init 0x0108 0x010b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/digilent-hs1.cfg b/openocd-win/openocd/scripts/interface/ftdi/digilent-hs1.cfg new file mode 100644 index 0000000..6a632ed --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/digilent-hs1.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# this supports JTAG-HS1 and JTAG-SMT1 +# (the later being the OEM on-board version) + +adapter driver ftdi +ftdi device_desc "Digilent Adept USB Device" +ftdi vid_pid 0x0403 0x6010 +# channel 1 does not have any functionality +ftdi channel 0 +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0088 0x008b +reset_config none diff --git a/openocd-win/openocd/scripts/interface/ftdi/digilent-hs2.cfg b/openocd-win/openocd/scripts/interface/ftdi/digilent-hs2.cfg new file mode 100644 index 0000000..e9fe94e --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/digilent-hs2.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# this supports JTAG-HS2 (and apparently Nexys4 as well) + +adapter driver ftdi +ftdi device_desc "Digilent Adept USB Device" +ftdi vid_pid 0x0403 0x6014 + +ftdi channel 0 +ftdi layout_init 0x00e8 0x60eb + +reset_config none diff --git a/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg new file mode 100644 index 0000000..78a233f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Digilent JTAG-HS3 +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6014 +ftdi device_desc "Digilent USB Device" + +# From Digilent support: +# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable) + +ftdi layout_init 0x2088 0x308b +ftdi layout_signal nSRST -data 0x2000 -noe 0x1000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2.cfg b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2.cfg new file mode 100644 index 0000000..ac623a7 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Digilent JTAG-SMT2 +# +# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1053&Prod=JTAG-SMT2 +# +# Config is based on data from +# http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6014 + +ftdi layout_init 0x20e8 0x3feb +ftdi layout_signal nSRST -data 0x2000 +ftdi layout_signal GPIO2 -data 0x2000 +ftdi layout_signal GPIO1 -data 0x0200 +ftdi layout_signal GPIO0 -data 0x0100 diff --git a/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg new file mode 100644 index 0000000..38236bc --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Digilent JTAG-SMT2-NC +# +# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/ +# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf +# +# Based on reference sheet (above) and Xilinx KCU105 schematics +# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation +# +# Note that the digilent_jtag_smt2 layout does not work and hangs while +# the ftdi device_desc from digilent_hs2 is wrong. + +adapter driver ftdi +ftdi device_desc "Digilent USB Device" +ftdi vid_pid 0x0403 0x6014 +ftdi channel 0 +ftdi layout_init 0x00e8 0x60eb +reset_config none diff --git a/openocd-win/openocd/scripts/interface/ftdi/dlp-usb1232h.cfg b/openocd-win/openocd/scripts/interface/ftdi/dlp-usb1232h.cfg new file mode 100644 index 0000000..67fee6b --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/dlp-usb1232h.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# DLP Design DLP-USB1232H USB-to-UART/FIFO interface module +# +# http://www.dlpdesign.com/usb/usb1232h.shtml +# +# Schematics for OpenOCD usage: +# http://randomprojects.org/wiki/DLP-USB1232H_and_OpenOCD_based_JTAG_adapter +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on schematics and code" +echo "in ft2232.c. Please report your experience with this file to openocd-devel" +echo "mailing list, so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster.cfg b/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster.cfg new file mode 100644 index 0000000..373e122 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Dangerous Prototypes - Bus Blaster +# +# The Bus Blaster has a configurable buffer between the FTDI FT2232H and the +# JTAG header which allows it to emulate various debugger types. It comes +# configured as a JTAGkey device. +# +# http://dangerousprototypes.com/docs/Bus_Blaster +# + +echo "Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster +and use dp_busblaster_kt-link.cfg instead" + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster_kt-link.cfg b/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster_kt-link.cfg new file mode 100644 index 0000000..222ca38 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/dp_busblaster_kt-link.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Dangerous Prototypes - Bus Blaster (with KT-Link buffer) +# +# The Bus Blaster has a configurable buffer between the FTDI FT2232H +# and the JTAG header which allows it to emulate various debugger +# types. This config works with KT-Link compatible implementation from +# https://github.com/bharrisau/busblaster and is SWD-enabled. +# +# http://dangerousprototypes.com/docs/Bus_Blaster +# + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal LED -ndata 0x8000 +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal SWDIO_OE -ndata 0x1000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/esp32_devkitj_v1.cfg b/openocd-win/openocd/scripts/interface/ftdi/esp32_devkitj_v1.cfg new file mode 100644 index 0000000..1b455a9 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/esp32_devkitj_v1.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Driver for the FT2232H JTAG chip on the Espressif DevkitJ board +# (and most other FT2232H and FT232H based boards) +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 0x0403 0x6014 + +# interface 1 is the uart +ftdi channel 0 + +# TCK, TDI, TDO, TMS: ADBUS0-3 +# LEDs: ACBUS4-7 + +ftdi layout_init 0x0008 0xf00b +ftdi layout_signal LED -data 0x1000 +ftdi layout_signal LED2 -data 0x2000 +ftdi layout_signal LED3 -data 0x4000 +ftdi layout_signal LED4 -data 0x8000 + +# ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin. +# The target code doesn't handle SRST reset properly yet, so this is commented out: +# ftdi layout_signal nSRST -oe 0x0020 +# reset_config srst_only diff --git a/openocd-win/openocd/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg b/openocd-win/openocd/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg new file mode 100644 index 0000000..1880bcb --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Driver for the FT2232H JTAG chip on the Espressif Kaluga-1 ESP32-S2 board +# (and most other FT2232H and FT232H based boards) +# +# JTAG DIP switch (labelled SW5 in the schematic) should be "ON" for lines +# labelled TCK, TDO, TDI and TWS, to connect the FT2232H to the ESP32-S2. +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 0x0403 0x6014 + +# interface 1 is the uart +ftdi channel 0 + +# TCK, TDI, TDO, TMS: ADBUS0-3 +# TRST/SRST: ADBUS5 (unused for now) +# LEDs: ACBUS3-4 (inverted) + +ftdi layout_init 0x0008 0x180b +ftdi layout_signal LED -ndata 0x0800 +ftdi layout_signal LED2 -ndata 0x1000 + +# ESP32* series chips do not have a TRST input, and the SRST line is connected +# to the EN pin. +# The target code doesn't handle SRST reset properly yet, so this is +# commented out: +# ftdi layout_signal nSRST -oe 0x0020 +# reset_config srst_only diff --git a/openocd-win/openocd/scripts/interface/ftdi/flossjtag-noeeprom.cfg b/openocd-win/openocd/scripts/interface/ftdi/flossjtag-noeeprom.cfg new file mode 100644 index 0000000..1008e1a --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/flossjtag-noeeprom.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# FlossJTAG +# +# http://github.com/esden/floss-jtag +# +# This is the pre v0.3 Floss-JTAG compatible config file. It can also be used +# for newer versions of Floss-JTAG with empty or not populated EEPROM. If you +# have several Floss-JTAG connected you have to use the USB ID to select a +# specific one. +# +# If you have a Floss-JTAG WITH EEPROM that is programmed, use the +# flossjtag.cfg file. +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/openocd-win/openocd/scripts/interface/ftdi/flossjtag.cfg b/openocd-win/openocd/scripts/interface/ftdi/flossjtag.cfg new file mode 100644 index 0000000..90ba63a --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/flossjtag.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# FlossJTAG +# +# http://github.com/esden/floss-jtag +# +# This is the v0.3 and v1.0 Floss-JTAG compatible config file. It relies on the +# existence of an EEPROM on Floss-JTAG containing a name. If you have several +# Floss-JTAG adapters connected you can use the serial number to select a +# specific device. +# +# If your Floss-JTAG does not have an EEPROM, or the EEPROM is empty, use the +# flossjtag-noeeprom.cfg file. +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 +ftdi device_desc "FLOSS-JTAG" +# adapter serial "FJ000001" + +ftdi layout_init 0x0008 0x180b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_signal LED -data 0x0800 +ftdi layout_signal LED2 -data 0x1000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/flyswatter.cfg b/openocd-win/openocd/scripts/interface/ftdi/flyswatter.cfg new file mode 100644 index 0000000..8bce00d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/flyswatter.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TinCanTools Flyswatter +# +# http://web.archive.org/web/20150419072034/http://www.tincantools.com/JTAG/Flyswatter.html +# + +adapter driver ftdi +ftdi device_desc "Flyswatter" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0818 0x0cfb +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -oe 0x0020 +ftdi layout_signal LED -data 0x0c00 diff --git a/openocd-win/openocd/scripts/interface/ftdi/flyswatter2.cfg b/openocd-win/openocd/scripts/interface/ftdi/flyswatter2.cfg new file mode 100644 index 0000000..ebc00fe --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/flyswatter2.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TinCanTools Flyswatter2 +# +# https://www.tincantools.com/product/flyswatter2/ +# + +adapter driver ftdi +ftdi device_desc "Flyswatter2" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0538 0x057b +ftdi layout_signal LED -ndata 0x0400 +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -data 0x0020 -noe 0x0100 diff --git a/openocd-win/openocd/scripts/interface/ftdi/ft232h-module-swd.cfg b/openocd-win/openocd/scripts/interface/ftdi/ft232h-module-swd.cfg new file mode 100644 index 0000000..d09ccf1 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/ft232h-module-swd.cfg @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# ADAFRUIT FTDI FT232H as a SWD direct connect interface +# Any FT232H based board may work +# +# http://www.ftdichip.com/Products/ICs/FT232H.htm +# +# + +adapter driver ftdi + +ftdi vid_pid 0x0403 0x6014 + +# data MSB..LSB direction (1:out) MSB..LSB +# 0000'0000'0011'0000 0000'0000'0011'1011 +ftdi layout_init 0x0030 0x003b +# 0xfff8 0xfffb +# Those signal are only required on some platforms or may required to be +# enabled explicitly (e.g. nrf5x chips). +ftdi layout_signal nSRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nTRST -data 0x0020 -oe 0x0020 + +# swd enable +ftdi layout_signal SWD_EN -data 0 +# tri-state (configure as input) TDO/TIO when reading +ftdi layout_signal SWDIO_OE -data 0 + +transport select swd + +# re-configure TDO as tri-state +#ftdi layout_signal TDO -data 0x0002 -oe 0x0002 +#ftdi layout_signal TDI -data 0x0004 + +# Adafruit FT232H JTAG SWD +# Name Pin Name Func Func +# D0 J1-3 ADBUS0 TCK SWDCLK +# D1 J1-4 ADBUS1 TDO/DI SWDIO +# D2 J1-5 ADBUS2 TDI/DO SWDIO +# D3 J1-6 ADBUS3 TMS N/A +# D4 J1-7 ADBUS4 (GPIOL0) /nSRST optional module reset +# D5 J1-8 ADBUS5 (GPIOL1) /nTRST optional target reset +# D6 J1-9 ADBUS6 (GPIOL2) +# D7 J1-10 ADBUS7 (GPIOL3) +# C0 J2-1 ACBUS0 (GPIOH0) +# C1 J2-2 ACBUS1 (GPIOH1) +# C2 J2-3 ACBUS2 (GPIOH2) +# C3 J2-4 ACBUS3 (GPIOH3) +# C4 J2-5 ACBUS4 (GPIOH4) +# C5 J2-6 ACBUS5 (GPIOH5) +# C6 J2-7 ACBUS6 (GPIOH6) +# C7 J2-8 ACBUS7 (GPIOH7) +# C8 J2-9 ACBUS8 +# C9 J2-10 ACBUS9 diff --git a/openocd-win/openocd/scripts/interface/ftdi/gw16042.cfg b/openocd-win/openocd/scripts/interface/ftdi/gw16042.cfg new file mode 100644 index 0000000..326a88f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/gw16042.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Gateworks GW16042 JTAG Dongle +# +# http://www.gateworks.com/ +# +# Layout: FTDI FT2232H +# ADBUS0 TCK +# ADBUS1 TDI +# ADBUS2 TDO (input) +# ADBUS3 TMS +# ADBUS4 nTRST +# ADBUS5 nSRST +# ADBUS6 OE (active high) for TRST, TDI, TMS, TCK +# ADBUS7 NC +# ACBUS0-7 NC +# BDBUS0 RXD +# BDBUS1 TXD (input) +# + +adapter driver ftdi +ftdi device_desc "USB-JTAG" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0058 0x007b +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -oe 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hie-jtag.cfg b/openocd-win/openocd/scripts/interface/ftdi/hie-jtag.cfg new file mode 100644 index 0000000..6694df0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hie-jtag.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Hofstädtler Industrie-Electronic (HIE) JTAG Debugger +# +# https://www.hofstaedtler.com/jtag +# + +adapter driver ftdi +ftdi channel 0 +ftdi vid_pid 0x0403 0x6014 +ftdi device_desc "HIE JTAG Debugger" + +ftdi layout_init 0x0c08 0x4f1b + +# define both Reset signals +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 + +# Toggle USB LED +ftdi layout_signal LED -ndata 0x4000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg new file mode 100644 index 0000000..d5d24e5 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hilscher NXHX 10-ETM +# +# http://de.hilscher.com/products_details_hardware.html?p_id=P_4ce145a5983e6 +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "NXHX 10-ETM" +ftdi vid_pid 0x0640 0x0028 + +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg new file mode 100644 index 0000000..003b9df --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hilscher NXHX 500-ETM +# +# http://de.hilscher.com/files_design/8/NXHX500-ETM_description_Rev01_EN.pdf +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "NXHX 500-ETM" +ftdi vid_pid 0x0640 0x0028 + +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_re.cfg b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_re.cfg new file mode 100644 index 0000000..97ad380 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_re.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hilscher NXHX 500-RE +# +# http://de.hilscher.com/products_details_hardware.html?p_id=P_461ff2053bad1&bs=20 +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "NXHX 500-RE" +ftdi vid_pid 0x0640 0x0028 + +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg new file mode 100644 index 0000000..06280c1 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hilscher NXHX 50-ETM +# +# http://de.hilscher.com/files_design/8/NXHX50-ETM_description_Rev01_EN.pdf +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "NXHX 50-ETM" +ftdi vid_pid 0x0640 0x0028 + +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_re.cfg b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_re.cfg new file mode 100644 index 0000000..f14be62 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_re.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hilscher NXHX 50-RE +# +# http://de.hilscher.com/products_details_hardware.html?p_id=P_483c0f582ad36&bs=20 +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "NXHX50-RE" +ftdi vid_pid 0x0640 0x0028 + +ftdi layout_init 0x0308 0x030b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hitex_lpc1768stick.cfg b/openocd-win/openocd/scripts/interface/ftdi/hitex_lpc1768stick.cfg new file mode 100644 index 0000000..91bd5a8 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hitex_lpc1768stick.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hitex LPC1768-Stick +# +# http://www.hitex.com/?id=1602 +# + + +adapter driver ftdi +ftdi device_desc "LPC1768-Stick" +ftdi vid_pid 0x0640 0x0026 + +ftdi layout_init 0x0388 0x038b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0080 -noe 0x200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/hitex_str9-comstick.cfg b/openocd-win/openocd/scripts/interface/ftdi/hitex_str9-comstick.cfg new file mode 100644 index 0000000..f698677 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/hitex_str9-comstick.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hitex STR9-comStick +# +# http://www.hitex.com/index.php?id=383 +# + +adapter driver ftdi +ftdi device_desc "STR9-comStick" +ftdi vid_pid 0x0640 0x002c + +ftdi layout_init 0x0108 0x010b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/icebear.cfg b/openocd-win/openocd/scripts/interface/ftdi/icebear.cfg new file mode 100644 index 0000000..4a76399 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/icebear.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Section5 ICEBear +# +# http://section5.ch/icebear +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "ICEbear JTAG adapter" +ftdi vid_pid 0x0403 0xc140 + +ftdi layout_init 0x0028 0x002b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/imx8mp-evk.cfg b/openocd-win/openocd/scripts/interface/ftdi/imx8mp-evk.cfg new file mode 100644 index 0000000..02564dc --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/imx8mp-evk.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG +# +# Using this interface requires enabling "remote mode" for the board using the +# NXP bcu tool (see https://github.com/NXPmicro/bcu) +# +# bcu set_gpio remote_en 1 -board=imx8mpevk +# +# The REMOTE_EN gpio is accessible through the same FTDI adapter but it's +# behind an I2C GPIO expander. +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6011 +ftdi channel 0 + +ftdi layout_init 0x00f8 0x000b + +ftdi layout_signal RESET_B -data 0x0010 -oe 0x0010 +# Called SYS_nRST in schematics +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi layout_signal IO_nRST -data 0x0040 -oe 0x0040 +ftdi layout_signal ONOFF_B -data 0x0080 -oe 0x0080 + +ftdi layout_signal GPIO1 -data 0x0100 -oe 0x0100 +ftdi layout_signal GPIO2 -data 0x0200 -oe 0x0200 +ftdi layout_signal GPIO3 -data 0x0400 -oe 0x0400 +ftdi layout_signal GPIO4 -data 0x0800 -oe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/incircuit-icprog.cfg b/openocd-win/openocd/scripts/interface/ftdi/incircuit-icprog.cfg new file mode 100644 index 0000000..81f2872 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/incircuit-icprog.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# In-Circuit's ICprog OpenOCD JTAG Adapter +# https://shop.in-circuit.de/product_info.php?products_id=112 +# +# Schematics available at +# http://wiki.in-circuit.de/images/0/06/610000158A_openocd.pdf +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nSRST -noe 0x0400 -data 0x0800 +ftdi layout_signal nTRST -noe 0x0100 -data 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/iotlab-usb.cfg b/openocd-win/openocd/scripts/interface/ftdi/iotlab-usb.cfg new file mode 100644 index 0000000..b7a004e --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/iotlab-usb.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is the integrated adapter as found on the IoT-LAB boards +# https://github.com/iot-lab/iot-lab/wiki +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 diff --git a/openocd-win/openocd/scripts/interface/ftdi/isodebug.cfg b/openocd-win/openocd/scripts/interface/ftdi/isodebug.cfg new file mode 100644 index 0000000..0a6e080 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/isodebug.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# isodebug v1 +# 5 kV isolated JTAG/SWD + UART adapter by Unjo AB + +adapter driver ftdi +ftdi vid_pid 0x22b7 0x150d + +ftdi layout_init 0x0ff8 0xfffb + +ftdi layout_signal LED -ndata 0x0100 +ftdi layout_signal nTRST -data 0x0200 +ftdi layout_signal nSRST -noe 0x0400 +ftdi layout_signal SWDIO_OE -data 0x0008 + +# Mode signals, either of these needs to be high to drive the JTAG/SWD pins. +# The power-on state is low for both signals but the init setting above sets +# JTAG_EN high. +ftdi layout_signal SWD_EN -data 0x1000 +ftdi layout_signal JTAG_EN -data 0x0800 + +# In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the +# second FTDI channel UART RxD to the SWO pin instead of the separate RxD +# pin. Note that the default init state has this pin high so when OpenOCD +# starts in SWD mode, SWO is by default disabled. To enable SWO tracing, +# issue the command 'ftdi set_signal SWO_EN 1' where tracing is configured. +# To switch back to using the separate UART, SWO_EN needs to be disabled +# before exiting OpenOCD, or the adapter replugged. +ftdi layout_signal SWO_EN -nalias JTAG_EN diff --git a/openocd-win/openocd/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/openocd-win/openocd/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg new file mode 100644 index 0000000..ea60dcf --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# DISTORTEC JTAG-lock-pick Tiny 2 +# +# http://www.distortec.com +# + +adapter driver ftdi +ftdi device_desc "JTAG-lock-pick Tiny 2" +ftdi vid_pid 0x0403 0x8220 + +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal SWDIO_OE -ndata 0x1000 +ftdi layout_signal LED -ndata 0x8000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/jtagkey.cfg b/openocd-win/openocd/scripts/interface/ftdi/jtagkey.cfg new file mode 100644 index 0000000..1c1c09d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/jtagkey.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Amontec JTAGkey +# +# http://www.amontec.com/jtagkey.shtml +# + +adapter driver ftdi +ftdi device_desc "Amontec JTAGkey" +ftdi vid_pid 0x0403 0xcff8 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/jtagkey2.cfg b/openocd-win/openocd/scripts/interface/ftdi/jtagkey2.cfg new file mode 100644 index 0000000..80df347 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/jtagkey2.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Amontec JTAGkey2 +# +# http://www.amontec.com/jtagkey2.shtml +# + +adapter driver ftdi +ftdi device_desc "Amontec JTAGkey-2" +ftdi vid_pid 0x0403 0xcff8 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/jtagkey2p.cfg b/openocd-win/openocd/scripts/interface/ftdi/jtagkey2p.cfg new file mode 100644 index 0000000..3a76bd0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/jtagkey2p.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Amontec JTAGkey2P +# +# http://www.amontec.com/jtagkey2p.shtml +# + +adapter driver ftdi +ftdi device_desc "Amontec JTAGkey-2P" +ftdi vid_pid 0x0403 0xcff8 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/kt-link.cfg b/openocd-win/openocd/scripts/interface/ftdi/kt-link.cfg new file mode 100644 index 0000000..61c6b83 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/kt-link.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Kristech KT-Link +# +# http://www.kristech.eu +# + +adapter driver ftdi +ftdi device_desc "KT-LINK" +ftdi vid_pid 0x0403 0xbbe2 + +ftdi layout_init 0x8c28 0xff3b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 +ftdi layout_signal LED -data 0x8000 +ftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000 +ftdi layout_signal SWDIO_OE -ndata 0x1000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg b/openocd-win/openocd/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg new file mode 100644 index 0000000..df4955f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# This adapter is integrated in to LambdaConcept ECPIX-5 board: +# interface/ftdi/lambdaconcept_ecpix-5.cfg +# See schematics for the ftdi layout: +# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF + +adapter driver ftdi +adapter speed 10000 +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0xfff8 0xfffb +transport select jtag diff --git a/openocd-win/openocd/scripts/interface/ftdi/lisa-l.cfg b/openocd-win/openocd/scripts/interface/ftdi/lisa-l.cfg new file mode 100644 index 0000000..75c5cbe --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/lisa-l.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Lisa/L +# +# http://paparazzi.enac.fr/wiki/Lisa +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on schematics and code" +echo "in ft2232.c. Please report your experience with this file to openocd-devel" +echo "mailing list, so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Lisa/L" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 + +ftdi layout_init 0x0008 0x180b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0040 -oe 0x0040 +ftdi layout_signal LED -data 0x1800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/luminary-icdi.cfg b/openocd-win/openocd/scripts/interface/ftdi/luminary-icdi.cfg new file mode 100644 index 0000000..9142503 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/luminary-icdi.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Luminary Micro Stellaris LM3S9B9x Evaluation Kits +# In-Circuit Debug Interface (ICDI) Board +# +# Essentially all Luminary debug hardware is the same, (with both +# JTAG and SWD support compatible with ICDI boards. This ICDI adapter +# configuration is JTAG-only, but the same hardware handles SWD too. +# +# This is a discrete ftdi based debug board which supports ARM's +# JTAG/SWD connectors in both backwards-compatible 20-pin format and +# in the new-style compact 10-pin. There's also an 8-pin connector +# with serial port support. It's included with LM3S9B9x eval boards. +# +# http://www.luminarymicro.com/products/ek-lm3s9b90.html +# http://www.luminarymicro.com/products/ek-lm3s9b92.html +# + +adapter driver ftdi +ftdi device_desc "Luminary Micro ICDI Board" +ftdi vid_pid 0x0403 0xbcda + +ftdi layout_init 0x00a8 0x00eb +ftdi layout_signal nSRST -noe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/openocd-win/openocd/scripts/interface/ftdi/luminary-lm3s811.cfg b/openocd-win/openocd/scripts/interface/ftdi/luminary-lm3s811.cfg new file mode 100644 index 0000000..98be166 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/luminary-lm3s811.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Luminary Micro Stellaris LM3S811 Evaluation Kit +# +# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html +# +# NOTE: this is only for boards *before* Rev C, which adds support +# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals. +# The "evb_lm3s811" layout doesn't set up those signals. +# +# Rev C boards work more like the other Stellaris eval boards. They +# need to use the "luminary_icdi" layout to work correctly. +# + +adapter driver ftdi +ftdi device_desc "LM3S811 Evaluation Board" +ftdi vid_pid 0x0403 0xbcd9 + +ftdi layout_init 0x0088 0x008b +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/openocd-win/openocd/scripts/interface/ftdi/luminary.cfg b/openocd-win/openocd/scripts/interface/ftdi/luminary.cfg new file mode 100644 index 0000000..27d9a9d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/luminary.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Luminary Micro Stellaris Evaluation Kits +# +# http://www.luminarymicro.com/products/evaluation_kits.html +# +# There are a number of evaluation kits for Stellaris Cortex-M3 chips. +# Currently they all bundle ftdi based debug support. When that is +# used (instead of an external adapter), use this config file in one +# of these two modes: +# +# - Eval board debug ... debug of the Stellaris chip via port A. +# +# - Other board debug ... same thing, but the board acts as a debug +# adapter for another board (using a standard ARM JTAG connector). +# The Stellaris chip stays in reset. +# +# Those support both JTAG and SWD. SWD is an ARM-only two-wire debug +# protocol; in 2009, OpenOCD does not support SWD. +# +# Port B of the ftdi chip is normally used as a serial link to the +# Stellaris chip. On most boards (but not older LM3S811 eval boards), +# when SWD is used Port B may instead be used to read low-bandwidth +# "SWO trace" data, including so-called "printf style" output from +# firmware via the ITM module as well as profile data. +# + +adapter driver ftdi +ftdi device_desc "Stellaris Evaluation Board" +ftdi vid_pid 0x0403 0xbcd9 + +ftdi layout_init 0x00a8 0x00eb +ftdi layout_signal nSRST -noe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/openocd-win/openocd/scripts/interface/ftdi/m53evk.cfg b/openocd-win/openocd/scripts/interface/ftdi/m53evk.cfg new file mode 100644 index 0000000..2d9c304 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/m53evk.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# DENX M53EVK +# +# http://www.denx-cs.de/?q=M53EVK +# + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 0 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/mbftdi.cfg b/openocd-win/openocd/scripts/interface/ftdi/mbftdi.cfg new file mode 100644 index 0000000..09cec9f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/mbftdi.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# MBFTDI +# +# http://www.marsohod.org/prodmbftdi +# +# Also the Marsohod2 and the Marsohod3 boards +# include a built-in MBFTDI for FPGA programming. +# See http://www.marsohod.org/prodmarsohod2 +# and http://www.marsohod.org/plata-marsokhod3 for details. +# + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0008 0x000b diff --git a/openocd-win/openocd/scripts/interface/ftdi/minimodule-swd.cfg b/openocd-win/openocd/scripts/interface/ftdi/minimodule-swd.cfg new file mode 100644 index 0000000..3eb2f53 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/minimodule-swd.cfg @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Supports SWD using the FT2232H or FT4232H minimodule. +# Each can support 2 SWD interfaces. +# +# FT2232H or FT4232H minimodule channel 0 (Channel A) +# Connector FTDI Target +# Pin Name +# --------- ------ ------ +# CN2-11 VIO VDD_IO (Or connect to CN2-5 on the minimodule instead for a 3V3 interface) +# CN2-2 GND GND +# CN2-7 ADBUS0 (TCK) SWCLK +# CN2-9 ADBUS2 (TDI/TDO) SWDIO +# CN2-10 ADBUS1 (TDO/TDI) SWDIO +# CN2-14 ADBUS4 (GPIOL0) nRESET +# +# FT2232H minimodule channel 1 (Channel B) +# FTDI Target +# ---- ------ +# CN2-11 - VDD_IO +# CN2-2 - GND +# CN3-26 - SWCLK +# CN3-25 - SWDIO +# CN3-24 - SWDIO +# CN3-21 - nRESET +# +# FT4232H minimodule channel 1 (Channel B) +# FTDI Target +# ---- ------ +# CN2-11 - VDD_IO +# CN2-2 - GND +# CN2-18 - SWCLK +# CN2-17 - SWDIO +# CN2-20 - SWDIO +# CN2-22 - nRESET +# + +adapter driver ftdi + +#Select your module type and channel + +#ftdi device_desc "FT2232H MiniModule" +ftdi vid_pid 0x0403 0x6010 +#ftdi channel 1 + +#ftdi device_desc "FT4232H MiniModule" +#ftdi vid_pid 0x0403 0x6011 +#ftdi channel 1 + +ftdi layout_init 0x0000 0x000b +ftdi layout_signal nSRST -data 0x0010 -oe 0x0010 +ftdi layout_signal SWD_EN -data 0 +ftdi layout_signal SWDIO_OE -data 0 + +transport select swd diff --git a/openocd-win/openocd/scripts/interface/ftdi/minimodule.cfg b/openocd-win/openocd/scripts/interface/ftdi/minimodule.cfg new file mode 100644 index 0000000..825d7c1 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/minimodule.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# FTDI MiniModule +# +# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf +# + +adapter driver ftdi +ftdi device_desc "FT2232H MiniModule" +ftdi vid_pid 0x0403 0x6010 + +# Every pin set as high impedance except TCK, TDI, TDO and TMS +ftdi layout_init 0x0008 0x000b + +# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip) +# This choice is arbitrary. Use other GPIO pin if desired. +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/minispartan6.cfg b/openocd-win/openocd/scripts/interface/ftdi/minispartan6.cfg new file mode 100644 index 0000000..f12bae6 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/minispartan6.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# https://www.scarabhardware.com/minispartan6/ +# https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf +adapter driver ftdi +# The miniSpartan6+ sadly doesn't have a custom device description, so we just +# have to hope you got it right. +#ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 +# interface 1 is the uart +ftdi channel 0 +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0008 0x000b +reset_config none +# this generally works fast: the fpga can handle 30MHz, the spi flash can handle +# 54MHz with simple read, no dummy cycles, and wait-for-write-completion +adapter speed 30000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/miniwiggler.cfg b/openocd-win/openocd/scripts/interface/ftdi/miniwiggler.cfg new file mode 100644 index 0000000..ebaa979 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/miniwiggler.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Infineon DAP miniWiggler V3 +# +# https://www.infineon.com/cms/en/product/evaluation-boards/kit_miniwiggler_3_usb/ +# +# Layout: FTDI FT2232 +# ADBUS0 TCK +# ADBUS1 TDI +# ADBUS2 TDO +# ADBUS3 TMS +# ADBUS4 nOE (output enable) +# ADBUS5 +# ADBUS6 +# ADBUS7 Blue LED +# +# ACBUS0 nTRST +# ACBUS1 nSRST +# ACUBS2 +# ACBUS3 +# ACBUS4 +# ACBUS5 +# ACBUS6 +# ACBUS7 +# + +adapter driver ftdi +ftdi device_desc "DAS JDS miniWiggler V3.1" +ftdi vid_pid 0x058b 0x0043 + +ftdi channel 0 +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/neodb.cfg b/openocd-win/openocd/scripts/interface/ftdi/neodb.cfg new file mode 100644 index 0000000..d3b3541 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/neodb.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Openmoko USB JTAG/RS232 adapter +# +# http://wiki.openmoko.org/wiki/Debug_Board_v3 +# + +adapter driver ftdi +ftdi device_desc "Debug Board for Neo1973" +ftdi vid_pid 0x1457 0x5118 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 +ftdi layout_signal nNOR_WP -data 0x0010 -oe 0x0010 diff --git a/openocd-win/openocd/scripts/interface/ftdi/ngxtech.cfg b/openocd-win/openocd/scripts/interface/ftdi/ngxtech.cfg new file mode 100644 index 0000000..635333f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/ngxtech.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NGX ARM USB JTAG +# +# http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30 +# + +echo "WARNING!" +echo "This file was not tested with real interface, but is assumed to work as this" +echo "interface uses the same layout as configs that were verified. Please report your" +echo "experience with this file to openocd-devel mailing list, so it could be marked" +echo "as working or fixed." + +adapter driver ftdi +ftdi device_desc "NGX JTAG" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg new file mode 100644 index 0000000..6aa13af --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM JTAG SWD adapter +# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/ +# + +transport select swd + +ftdi layout_signal SWD_EN -nalias nTRST +ftdi layout_signal SWDIO_OE -alias TMS diff --git a/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg new file mode 100644 index 0000000..cd11ad8 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM-USB-OCD-H +# +# http://www.olimex.com/dev/arm-usb-ocd-h.html +# + +adapter driver ftdi +ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H" +ftdi vid_pid 0x15ba 0x002b + +ftdi layout_init 0x0908 0x0b1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg new file mode 100644 index 0000000..d2261e2 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM-USB-OCD +# +# http://www.olimex.com/dev/arm-usb-ocd.html +# + +adapter driver ftdi +ftdi device_desc "Olimex OpenOCD JTAG" +ftdi vid_pid 0x15ba 0x0003 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal LED -data 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg new file mode 100644 index 0000000..a2b3e3e --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM-USB-TINY-H +# +# http://www.olimex.com/dev/arm-usb-tiny-h.html +# + +adapter driver ftdi +ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi vid_pid 0x15ba 0x002a + +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/olimex-jtag-tiny.cfg b/openocd-win/openocd/scripts/interface/ftdi/olimex-jtag-tiny.cfg new file mode 100644 index 0000000..7d8e81d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/olimex-jtag-tiny.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Olimex ARM-USB-TINY +# +# http://www.olimex.com/dev/arm-usb-tiny.html +# + +adapter driver ftdi +ftdi device_desc "Olimex OpenOCD JTAG TINY" +ftdi vid_pid 0x15ba 0x0004 + +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/oocdlink.cfg b/openocd-win/openocd/scripts/interface/ftdi/oocdlink.cfg new file mode 100644 index 0000000..0e99b67 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/oocdlink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Joern Kaipf's OOCDLink +# +# http://www.joernonline.de/contrexx2/cms/index.php?page=126 +# + +echo "WARNING!" +echo "This file was not tested with real interface, but is assumed to work as this" +echo "interface uses the same layout as configs that were verified. Please report your" +echo "experience with this file to openocd-devel mailing list, so it could be marked" +echo "as working or fixed." + +adapter driver ftdi +ftdi device_desc "OOCDLink" +ftdi vid_pid 0x0403 0xbaf8 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/opendous_ftdi.cfg b/openocd-win/openocd/scripts/interface/ftdi/opendous_ftdi.cfg new file mode 100644 index 0000000..5d6f5ae --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/opendous_ftdi.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Opendous +# +# http://code.google.com/p/opendous/wiki/JTAG +# +# According to the website, it is similar to jtagkey, but it uses channel B +# (and it has a different pid number). +# + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 + +ftdi layout_init 0x0c08 0x0f1b +ftdi layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/openocd-win/openocd/scripts/interface/ftdi/openocd-usb-hs.cfg b/openocd-win/openocd/scripts/interface/ftdi/openocd-usb-hs.cfg new file mode 100644 index 0000000..af1f61c --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/openocd-usb-hs.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# embedded projects openocd usb adapter v3 +# +# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14 +# + +adapter driver ftdi +ftdi device_desc "Dual RS232-HS" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/openocd-usb.cfg b/openocd-win/openocd/scripts/interface/ftdi/openocd-usb.cfg new file mode 100644 index 0000000..c333d65 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/openocd-usb.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hubert Hoegl's USB to JTAG +# +# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html +# + +adapter driver ftdi +ftdi device_desc "Dual RS232" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/openrd.cfg b/openocd-win/openocd/scripts/interface/ftdi/openrd.cfg new file mode 100644 index 0000000..b6b2d1d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/openrd.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Marvell OpenRD +# +# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp +# + +adapter driver ftdi +ftdi device_desc "OpenRD JTAGKey FT2232D B" +ftdi vid_pid 0x0403 0x9e90 +ftdi channel 0 + +ftdi layout_init 0x0608 0x0f1b +ftdi layout_signal nTRST -data 0x0200 +ftdi layout_signal nSRST -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/pipistrello.cfg b/openocd-win/openocd/scripts/interface/ftdi/pipistrello.cfg new file mode 100644 index 0000000..29ecd12 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/pipistrello.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# http://pipistrello.saanlima.com/ +# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf +adapter driver ftdi +ftdi device_desc "Pipistrello LX45" +ftdi vid_pid 0x0403 0x6010 +# interface 1 is the uart +ftdi channel 0 +# just TCK TDI TDO TMS, no reset +ftdi layout_init 0x0008 0x000b +reset_config none +# this generally works fast: the fpga can handle 30MHz, the spi flash can handle +# 54MHz with simple read, no dummy cycles, and wait-for-write-completion +adapter speed 10000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/pls_spc5.cfg b/openocd-win/openocd/scripts/interface/ftdi/pls_spc5.cfg new file mode 100644 index 0000000..3b3c2d6 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/pls_spc5.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# PLS SPC5-UDESTK +# +# https://www.st.com/en/development-tools/spc5-udestk.html +# +# Reference the SPC56D Discovery schematics. +# +# Layout: FTDI FT2232 +# ADBUS0 TCK +# ADBUS1 TDI +# ADBUS2 TDO +# ADBUS3 TMS +# ADBUS4 TMS +# ADBUS5 RTCK +# ADBUS6 +# ADBUS7 LED1 +# +# ACBUS0 nTRST +# ACBUS1 nSRST (external pull-down) +# ACUBS2 +# ACBUS3 +# ACBUS4 +# ACBUS5 nSRST direction (input=L, output=H, external pull-down) +# ACBUS6 TMS direction (input=L, output=H, external pull-up) +# ACBUS7 LED2 +# + +adapter driver ftdi +ftdi device_desc "PLS USB/JTAG Adapter for SPC5xxx" +ftdi vid_pid 0x263d 0x4001 + +ftdi channel 0 +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal nSRST -ndata 0x2000 -oe 0x2000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/redbee-econotag.cfg b/openocd-win/openocd/scripts/interface/ftdi/redbee-econotag.cfg new file mode 100644 index 0000000..d0d3d83 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/redbee-econotag.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Redwire Redbee-Econotag +# +# http://www.redwirellc.com/store/node/1 +# +# The Redbee-Econotag has an onboard FT2232H with: +# - FT2232H channel A wired to mc13224v JTAG +# - FT2232H channel B wired to mc13224v UART1 +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/redbee-usb.cfg b/openocd-win/openocd/scripts/interface/ftdi/redbee-usb.cfg new file mode 100644 index 0000000..9880553 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/redbee-usb.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Redwire Redbee-USB +# +# http://www.redwirellc.com +# +# The Redbee-USB has an onboard FT2232H with: +# - FT2232H channel B wired to mc13224v JTAG +# - FT2232H channel A wired to mc13224v UART1 +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 +ftdi channel 1 + +ftdi layout_init 0x0c08 0x0c2b +ftdi layout_signal nTRST -data 0x0800 +ftdi layout_signal nSRST -data 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/rowley-cc-arm-swd.cfg b/openocd-win/openocd/scripts/interface/ftdi/rowley-cc-arm-swd.cfg new file mode 100644 index 0000000..585d589 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/rowley-cc-arm-swd.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Rowley ARM SWD Adapter +# http://sites.fastspring.com/rowley/product/armswdadapter +# https://drive.google.com/file/d/0Bzv7UpKpOQhnTUNNdzI5OUR4WGs/edit?usp=sharing +# + +transport select swd + +ftdi layout_signal SWD_EN -nalias nTRST +ftdi layout_signal SWDIO_OE -alias TMS diff --git a/openocd-win/openocd/scripts/interface/ftdi/sheevaplug.cfg b/openocd-win/openocd/scripts/interface/ftdi/sheevaplug.cfg new file mode 100644 index 0000000..29c8688 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/sheevaplug.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Marvel SheevaPlug Development Kit +# +# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp +# + +adapter driver ftdi +ftdi device_desc "SheevaPlug JTAGKey FT2232D B" +ftdi vid_pid 0x9e88 0x9e8f +ftdi channel 0 + +ftdi layout_init 0x0608 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/signalyzer-lite.cfg b/openocd-win/openocd/scripts/interface/ftdi/signalyzer-lite.cfg new file mode 100644 index 0000000..e6c3839 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/signalyzer-lite.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Xverve Signalyzer LITE (DT-USB-SLITE) +# +# http://www.signalyzer.com +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Signalyzer LITE" +ftdi vid_pid 0x0403 0xbca1 + +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/signalyzer.cfg b/openocd-win/openocd/scripts/interface/ftdi/signalyzer.cfg new file mode 100644 index 0000000..fa7a7ed --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/signalyzer.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Xverve Signalyzer Tool (DT-USB-ST) +# +# http://www.signalyzer.com +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on code in ft2232.c." +echo "Please report your experience with this file to openocd-devel mailing list," +echo "so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Signalyzer" +ftdi vid_pid 0x0403 0xbca0 + +ftdi layout_init 0x0008 0x000b +ftdi layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi layout_signal nSRST -data 0x0020 -oe 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/sipeed-rv-debugger.cfg b/openocd-win/openocd/scripts/interface/ftdi/sipeed-rv-debugger.cfg new file mode 100644 index 0000000..ca65398 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/sipeed-rv-debugger.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Interface file for BL702-based SIPEED RV Debugger +# + +adapter driver ftdi +adapter speed 6000 + +ftdi device_desc "JTAG Debugger" +ftdi vid_pid 0x0403 0x6010 +ftdi layout_init 0x0008 0x001b +ftdi layout_signal nSRST -oe 0x0020 -data 0x0020 diff --git a/openocd-win/openocd/scripts/interface/ftdi/snps_sdp.cfg b/openocd-win/openocd/scripts/interface/ftdi/snps_sdp.cfg new file mode 100644 index 0000000..eb2aecc --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/snps_sdp.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent +# HS-1, except that it uses channel B for JTAG communication, instead of +# channel A. +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 +ftdi layout_init 0x0088 0x008b +ftdi channel 1 + + diff --git a/openocd-win/openocd/scripts/interface/ftdi/steppenprobe.cfg b/openocd-win/openocd/scripts/interface/ftdi/steppenprobe.cfg new file mode 100644 index 0000000..f84efe6 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/steppenprobe.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Steppenprobe +# https://github.com/diegoherranz/steppenprobe +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 + +# Initial Layout +ftdi layout_init 0x0058 0x99fb +# Signal Data Direction Notes +# TCK 0 1 (out) +# TDI 0 1 (out) +# TDO 0 0 (in) +# TMS 1 1 (out) JTAG IEEE std recommendation +# LED 1 1 (out) LED off +# SWD_EN 0 1 (out) OpenOCD sets this high for SWD +# SWDIO_OE 1 1 (out) Ext. buffer tristated +# SRST 0 1 (out) Translates to nSRST=Z + +# Unused 0 1 (out) +# GPIO_A 0 0 (in) +# GPIO_B 0 0 (in) +# Unused 0 1 (out) +# Unused 0 1 (out) +# GPIO_C 0 0 (in) +# GPIO_D 0 0 (in) +# Unused 0 1 (out) + +# Signals definition +ftdi layout_signal LED -ndata 0x0010 +ftdi layout_signal SWD_EN -data 0x0020 +ftdi layout_signal SWDIO_OE -ndata 0x0040 +ftdi layout_signal nSRST -oe 0x0080 + +ftdi layout_signal GPIO_A -data 0x0200 -oe 0x0200 -input 0x0200 +ftdi layout_signal GPIO_B -data 0x0400 -oe 0x0400 -input 0x0400 +ftdi layout_signal GPIO_C -data 0x2000 -oe 0x2000 -input 0x2000 +ftdi layout_signal GPIO_D -data 0x4000 -oe 0x4000 -input 0x4000 diff --git a/openocd-win/openocd/scripts/interface/ftdi/stm32-stick.cfg b/openocd-win/openocd/scripts/interface/ftdi/stm32-stick.cfg new file mode 100644 index 0000000..1d72d20 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/stm32-stick.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Hitex STM32-PerformanceStick +# +# http://www.hitex.com/index.php?id=340 +# + +adapter driver ftdi +ftdi device_desc "STM32-PerformanceStick" +ftdi vid_pid 0x0640 0x002d + +ftdi layout_init 0x0388 0x038b +ftdi layout_signal nTRST -data 0x0100 +ftdi layout_signal nSRST -data 0x0080 -noe 0x200 diff --git a/openocd-win/openocd/scripts/interface/ftdi/swd-resistor-hack.cfg b/openocd-win/openocd/scripts/interface/ftdi/swd-resistor-hack.cfg new file mode 100644 index 0000000..d9e7158 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/swd-resistor-hack.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or +# so depending on the drive capability of the target and adapter); +# connect TDO directly to SWDIO. +# +# You also need to have reliable GND connection between the target and +# adapter. Vref of the adapter should be supplied with a voltage equal +# to the target's (preferably connect it to Vcc). You can also +# optionally connect nSRST. Leave everything else unconnected. +# +# FTDI Target +# ---- ------ +# 1 - Vref ----------------- Vcc +# 3 - nTRST - +# 4 - GND ----------------- GND +# 5 - TDI ---/\470 Ohm/\--- SWDIO +# 7 - TMS - +# 9 - TCK ----------------- SWCLK +# 11 - RTCK - +# 13 - TDO ----------------- SWDIO +# 15 - nSRST - - - - - - - - - nRESET +# + +transport select swd + +ftdi layout_signal SWD_EN -data 0 diff --git a/openocd-win/openocd/scripts/interface/ftdi/ti-icdi.cfg b/openocd-win/openocd/scripts/interface/ftdi/ti-icdi.cfg new file mode 100644 index 0000000..964de76 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/ti-icdi.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This is an FTDI-based debugging solution as found on some TI boards, +# e.g. CC3200 LaunchPad. +# +# The schematics are identical to luminary-icdi (including SWD +# support) but the USB IDs are different. +# + +adapter driver ftdi +ftdi vid_pid 0x0451 0xc32a + +ftdi layout_init 0x00a8 0x00eb +ftdi layout_signal nSRST -noe 0x0020 +ftdi layout_signal SWD_EN -ndata 0x0080 +ftdi layout_signal SWDIO_OE -data 0x0008 diff --git a/openocd-win/openocd/scripts/interface/ftdi/tigard.cfg b/openocd-win/openocd/scripts/interface/ftdi/tigard.cfg new file mode 100644 index 0000000..43ce0ad --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/tigard.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Tigard: An FTDI FT2232H-based multi-protocol tool for hardware hacking. +# https://github.com/tigard-tools/tigard + +adapter driver ftdi + +ftdi device_desc "Tigard V1.1" +ftdi vid_pid 0x0403 0x6010 + +ftdi channel 1 + +ftdi layout_init 0x0038 0x003b +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -data 0x0020 + +# This board doesn't support open-drain reset modes since its output buffer is +# always enabled. +reset_config srst_push_pull trst_push_pull diff --git a/openocd-win/openocd/scripts/interface/ftdi/tumpa-lite.cfg b/openocd-win/openocd/scripts/interface/ftdi/tumpa-lite.cfg new file mode 100644 index 0000000..e3f12e3 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/tumpa-lite.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TIAO USB Multi-Protocol Adapter (TUMPA) Lite +# +# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x8a99 + +ftdi layout_init 0x0038 0x087b +ftdi layout_signal nTRST -data 0x0020 -oe 0x0020 +ftdi layout_signal nSRST -data 0x0010 -oe 0x0010 diff --git a/openocd-win/openocd/scripts/interface/ftdi/tumpa.cfg b/openocd-win/openocd/scripts/interface/ftdi/tumpa.cfg new file mode 100644 index 0000000..db4311b --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/tumpa.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TIAO USB Multi-Protocol Adapter (TUMPA) +# +# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x8a98 0x0403 0x6010 + +ftdi layout_init 0x0038 0x087b +ftdi layout_signal nTRST -data 0x0020 +ftdi layout_signal nSRST -data 0x0010 + +reset_config srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revB.cfg b/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revB.cfg new file mode 100644 index 0000000..f90fc58 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revB.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# egnite Turtelizer 2 rev B (with SRST only) +# +# http://www.ethernut.de/en/hardware/turtelizer/index.html +# + +echo "WARNING!" +echo "This file was not tested with real interface, it is based on schematics and code" +echo "in ft2232.c. Please report your experience with this file to openocd-devel" +echo "mailing list, so it could be marked as working or fixed." + +adapter driver ftdi +ftdi device_desc "Turtelizer JTAG/RS232 Adapter" +ftdi vid_pid 0x0403 0xbdc8 + +ftdi layout_init 0x0008 0x0c5b +ftdi layout_signal nSRST -oe 0x0040 +ftdi layout_signal LED -data 0x0c00 diff --git a/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revC.cfg b/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revC.cfg new file mode 100644 index 0000000..94617a1 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revC.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# egnite Turtelizer 2 revC (with TRST and SRST) +# +# http://www.ethernut.de/en/hardware/turtelizer/index.html +# + +adapter driver ftdi +ftdi device_desc "Turtelizer JTAG/RS232 Adapter" +ftdi vid_pid 0x0403 0xbdc8 + +ftdi layout_init 0x0008 0x0c7b +ftdi layout_signal nTRST -oe 0x0020 +ftdi layout_signal nSRST -oe 0x0040 +ftdi layout_signal LED -ndata 0x0c00 diff --git a/openocd-win/openocd/scripts/interface/ftdi/um232h.cfg b/openocd-win/openocd/scripts/interface/ftdi/um232h.cfg new file mode 100644 index 0000000..6be08b5 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/um232h.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# FTDI UM232H as a JTAG interface +# +# http://www.ftdichip.com/Products/Modules/DevelopmentModules.htm#UM232H +# +# This should also work with a UM232H-B, but that has not been tested. +# Note that UM232H and UM232H-B are 3.3V only. +# + +adapter driver ftdi +#ftdi device_desc "UM232H" +ftdi vid_pid 0x0403 0x6014 + +ftdi layout_init 0xfff8 0xfffb +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal nSRST -data 0x0200 -oe 0x0200 + +# UM232H FT232H JTAG +# Name Pin Name Func +# AD0 J2-6 ADBUS0 TCK +# AD1 J2-7 ADBUS1 TDI +# AD2 J2-8 ADBUS2 TDO +# AD3 J2-9 ADBUS3 TMS +# AD4 J2-10 ADBUS4 (GPIOL0) +# AD5 J2-11 ADBUS5 (GPIOL1) +# AD6 J2-12 ADBUS6 (GPIOL2) +# AD7 J2-13 ADBUS7 (GPIOL3) +# AD0 J1-14 ACBUS0 /TRST +# AD1 J1-13 ACBUS1 /SRST +# AD2 J1-12 ACBUS2 (GPIOH2) +# AD3 J1-11 ACBUS3 (GPIOH3) +# AD4 J1-10 ACBUS4 (GPIOH4) +# AD5 J1-9 ACBUS5 (GPIOH5) +# AD6 J1-8 ACBUS6 (GPIOH6) +# AD7 J1-7 ACBUS7 (GPIOH7) diff --git a/openocd-win/openocd/scripts/interface/ftdi/vpaclink.cfg b/openocd-win/openocd/scripts/interface/ftdi/vpaclink.cfg new file mode 100644 index 0000000..ff508f2 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/vpaclink.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Voipac VPACLink +# +# http://voipac.com/27M-JTG-000 +# + +echo "WARNING!" +echo "This file was not tested with real interface, but is assumed to work as this" +echo "interface uses the same layout as configs that were verified. Please report your" +echo "experience with this file to openocd-devel mailing list, so it could be marked" +echo "as working or fixed." + +adapter driver ftdi +ftdi device_desc "VPACLink" +ftdi vid_pid 0x0403 0x6010 + +ftdi layout_init 0x0508 0x0f1b +ftdi layout_signal nTRST -data 0x0200 -noe 0x0100 +ftdi layout_signal nSRST -data 0x0800 -noe 0x0400 diff --git a/openocd-win/openocd/scripts/interface/ftdi/xds100v2.cfg b/openocd-win/openocd/scripts/interface/ftdi/xds100v2.cfg new file mode 100644 index 0000000..373df4f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/xds100v2.cfg @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments XDS100v2 +# +# http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features +# +# Detailed documentation is available only as CPLD verilog source code +# to the registered TI users. +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0xa6d0 0x0403 0x6010 + +ftdi layout_init 0x0038 0x597b + +# 8000 z - unused +# 4000 0 > CPLD loopback (all target side pins high-Z) +# 2000 z < !( cable connected ) (open drain on CPLD side for $reasons) +# 1000 0 > EMU1_oe +# +# 800 0 > PWR_RST = clear power-loss flag on rising edge +# 400 z < !( power-loss flag ) +# 200 z < nSRST +# 100 0 > nSRST_oe +# +# 80 z < RTCK +# 40 0 > EMU0_oe +# 20 1 > EMU_EN +# 10 1 > nTRST +# +# 8 1 > TMS +# 4 z < TDO +# 2 0 > TDI +# 1 0 > TCK +# +# As long as the power-loss flag is set, all target-side pins are +# high-Z except the EMU-pins for which the opposite holds unless +# EMU_EN is high. +# +# To use wait-in-reset, drive EMU0 low at power-on reset. If the +# target normally reuses EMU0 for other purposes, clear EMU_EN to +# keep the EMU pins high-Z until the target is power-cycled. +# +# The LED only turns off at USB suspend, which is also the only way to +# set the power-loss flag manually. (Can be done in software e.g. by +# changing the USB configuration to zero.) +# + +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -oe 0x0100 +ftdi layout_signal EMU_EN -data 0x0020 +ftdi layout_signal EMU0 -oe 0x0040 +ftdi layout_signal EMU1 -oe 0x1000 +ftdi layout_signal PWR_RST -data 0x0800 +ftdi layout_signal LOOPBACK -data 0x4000 + +echo "\nInfo : to use this adapter you MUST add ``init; ftdi set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\n" +# note: rising edge on PWR_RST is also needed after power-cycling the +# target diff --git a/openocd-win/openocd/scripts/interface/ftdi/xds100v3.cfg b/openocd-win/openocd/scripts/interface/ftdi/xds100v3.cfg new file mode 100644 index 0000000..dc72233 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/xds100v3.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments XDS100 ver 3.0 +# +# http://processors.wiki.ti.com/index.php/XDS100 +# + +# Version 3.0 is the same as 2.0 as far as OpenOCD is concerned +source [find interface/ftdi/xds100v2.cfg] + +# The USB ids are different. +ftdi vid_pid 0x0403 0xa6d1 diff --git a/openocd-win/openocd/scripts/interface/ftdi/xt_kc705_ml605.cfg b/openocd-win/openocd/scripts/interface/ftdi/xt_kc705_ml605.cfg new file mode 100644 index 0000000..dda8c0a --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ftdi/xt_kc705_ml605.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232 +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 +# Specify "adapter serial <identifier>" here as needed + +ftdi layout_init 0x0010 0x007b +ftdi layout_signal nTRST -data 0x0010 +ftdi layout_signal nSRST -ndata 0x0020 diff --git a/openocd-win/openocd/scripts/interface/imx-native.cfg b/openocd-win/openocd/scripts/interface/imx-native.cfg new file mode 100644 index 0000000..01e42e3 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/imx-native.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Config for using NXP IMX CPU +# +# This is best used with a fast enough buffer but also +# is suitable for direct connection if the target voltage +# matches to host voltage and the cable is short enough. +# +# + +adapter driver imx_gpio + +# For most IMX processors 0x0209c000 +imx_gpio_peripheral_base 0x0209c000 + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on system clock, calibrated for IMX6UL@528MHz +# imx_gpio_speed SPEED_COEFF SPEED_OFFSET +imx_gpio_speed_coeffs 50000 50 + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo. +# Example configuration: +# imx_gpio_jtag_nums 6 7 8 9 + +# SWD interface pins: swclk swdio +# Example configuration: +imx_gpio_swd_nums 1 6 + +# imx_gpio_trst_num 10 +# reset_config trst_only + +# imx_gpio_srst_num 11 +# reset_config srst_only srst_push_pull + +# or if you have both connected, +# reset_config trst_and_srst srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/jlink.cfg b/openocd-win/openocd/scripts/interface/jlink.cfg new file mode 100644 index 0000000..181c2cc --- /dev/null +++ b/openocd-win/openocd/scripts/interface/jlink.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# SEGGER J-Link +# +# http://www.segger.com/jlink.html +# + +adapter driver jlink + +# The serial number can be used to select a specific device in case more than +# one is connected to the host. +# +# Example: Select J-Link with serial number 123456789 +# +# adapter serial 123456789 diff --git a/openocd-win/openocd/scripts/interface/jtag_dpi.cfg b/openocd-win/openocd/scripts/interface/jtag_dpi.cfg new file mode 100644 index 0000000..225d4d5 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/jtag_dpi.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Provide support for the Cadence JTAG BFM +# +# Copyright (c) 2020, Ampere Computing LLC +# + +adapter driver jtag_dpi + +# Set the DPI JTAG server port +if { [info exists DPI_PORT] } { + set _DPI_PORT $DPI_PORT +} else { + set _DPI_PORT 5555 +} + +# Set the DPI JTAG server address +if { [info exists DPI_ADDRESS] } { + set _DPI_ADDRESS $DPI_ADDRESS +} else { + set _DPI_ADDRESS "127.0.0.1" +} + +jtag_dpi set_port $_DPI_PORT +jtag_dpi set_address $_DPI_ADDRESS diff --git a/openocd-win/openocd/scripts/interface/jtag_hat_rpi2.cfg b/openocd-win/openocd/scripts/interface/jtag_hat_rpi2.cfg new file mode 100644 index 0000000..cd1cbfb --- /dev/null +++ b/openocd-win/openocd/scripts/interface/jtag_hat_rpi2.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Blinkinlabs JTAG_Hat +# +# https://github.com/blinkinlabs/jtag_hat +# + +adapter driver bcm2835gpio + +bcm2835gpio peripheral_base 0x3F000000 + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# These depend on system clock, calibrated for stock 700MHz +# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET +bcm2835gpio speed_coeffs 146203 36 + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +# Header pin numbers: 23 22 19 21 +adapter gpio tck -chip 0 11 +adapter gpio tms -chip 0 25 +adapter gpio tdi -chip 0 10 +adapter gpio tdo -chip 0 9 + +# Each of the SWD lines need a gpio number set: swclk swdio +# Header pin numbers: 23 22 +adapter gpio swclk -chip 0 11 +adapter gpio swdio -chip 0 25 + +# Direction pin for SWDIO level shifting buffer +adapter gpio swdio_dir -chip 0 6 + +# If you define trst or srst, use appropriate reset_config +# Header pin numbers: TRST - 26, SRST - 18 + +adapter gpio trst -chip 0 7 +#reset_config trst_only + +adapter gpio srst -chip 0 24 +#reset_config srst_only + +# or if you have both connected +#reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/interface/jtag_vpi.cfg b/openocd-win/openocd/scripts/interface/jtag_vpi.cfg new file mode 100644 index 0000000..e8164ab --- /dev/null +++ b/openocd-win/openocd/scripts/interface/jtag_vpi.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter driver jtag_vpi + +# Set the VPI JTAG server port +if { [info exists VPI_PORT] } { + set _VPI_PORT $VPI_PORT +} else { + set _VPI_PORT 5555 +} + +# Set the VPI JTAG server address +if { [info exists VPI_ADDRESS] } { + set _VPI_ADDRESS $VPI_ADDRESS +} else { + set _VPI_ADDRESS "127.0.0.1" +} + +jtag_vpi set_port $_VPI_PORT +jtag_vpi set_address $_VPI_ADDRESS diff --git a/openocd-win/openocd/scripts/interface/kitprog.cfg b/openocd-win/openocd/scripts/interface/kitprog.cfg new file mode 100644 index 0000000..eb9ad98 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/kitprog.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Cypress Semiconductor KitProg +# +# Note: This is the driver for the proprietary KitPtog protocol. If the +# KitProg is in CMSIS-DAP mode, you should either use the cmsis-dap +# interface driver or switch the KitProg to KitProg mode. +# + +adapter driver kitprog + +# Optionally specify the serial number of the KitProg you want to use. +# adapter serial 1926402735485200 diff --git a/openocd-win/openocd/scripts/interface/nulink.cfg b/openocd-win/openocd/scripts/interface/nulink.cfg new file mode 100644 index 0000000..2a4bc0b --- /dev/null +++ b/openocd-win/openocd/scripts/interface/nulink.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nuvoton Nu-Link in-circuit debugger/programmer +# + +adapter driver hla +hla_layout nulink +hla_device_desc "Nu-Link" +hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201 + +# Only swd is supported +transport select hla_swd diff --git a/openocd-win/openocd/scripts/interface/opendous.cfg b/openocd-win/openocd/scripts/interface/opendous.cfg new file mode 100644 index 0000000..9c5a804 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/opendous.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# opendous-jtag +# +# http://code.google.com/p/opendous-jtag/ +# + +adapter driver opendous diff --git a/openocd-win/openocd/scripts/interface/openjtag.cfg b/openocd-win/openocd/scripts/interface/openjtag.cfg new file mode 100644 index 0000000..1602352 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/openjtag.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# OpenJTAG +# +# www.openjtag.org +# + +adapter driver openjtag +openjtag device_desc "Open JTAG Project" diff --git a/openocd-win/openocd/scripts/interface/osbdm.cfg b/openocd-win/openocd/scripts/interface/osbdm.cfg new file mode 100644 index 0000000..e21848d --- /dev/null +++ b/openocd-win/openocd/scripts/interface/osbdm.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# P&E Micro OSBDM (aka OSJTAG) interface +# +# http://pemicro.com/osbdm/ +# +adapter driver osbdm +reset_config srst_only diff --git a/openocd-win/openocd/scripts/interface/parport.cfg b/openocd-win/openocd/scripts/interface/parport.cfg new file mode 100644 index 0000000..b9fceeb --- /dev/null +++ b/openocd-win/openocd/scripts/interface/parport.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Parallel port wiggler (many clones available) on port 0x378 +# +# Addresses: 0x378/LPT1 or 0x278/LPT2 ... +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + if {$tcl_platform(platform) eq "windows"} { + set _PARPORTADDR 0x378 + } { + set _PARPORTADDR 0 + } +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable wiggler diff --git a/openocd-win/openocd/scripts/interface/parport_dlc5.cfg b/openocd-win/openocd/scripts/interface/parport_dlc5.cfg new file mode 100644 index 0000000..24acea7 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/parport_dlc5.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Xilinx Parallel Cable III 'DLC 5' (and various clones) +# +# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html +# + +if { [info exists PARPORTADDR] } { + set _PARPORTADDR $PARPORTADDR +} else { + set _PARPORTADDR 0 +} + +adapter driver parport +parport port $_PARPORTADDR +parport cable dlc5 diff --git a/openocd-win/openocd/scripts/interface/raspberrypi-gpio-connector.cfg b/openocd-win/openocd/scripts/interface/raspberrypi-gpio-connector.cfg new file mode 100644 index 0000000..eff73fc --- /dev/null +++ b/openocd-win/openocd/scripts/interface/raspberrypi-gpio-connector.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Config for Raspberry Pi GPIO header +# +# This is best used with a fast enough buffer but also +# is suitable for direct connection if the target voltage +# matches RPi's 3.3V and the cable is short enough. +# +# Do not forget the GND connection, e.g. pin 20 of the GPIO header. +# + +# GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default. +# The JTAG/SWD specification requires pull-up at the target board +# for either signal. Connecting the signal pulled-up on the target +# to the pull-down on the adapter is not a good idea. +# GPIO 8 is pulled-up by default. +echo "Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!" + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +# Header pin numbers: 23 24 19 21 +adapter gpio tck -chip 0 11 +adapter gpio tms -chip 0 8 +adapter gpio tdi -chip 0 10 +adapter gpio tdo -chip 0 9 + +# Each of the SWD lines need a gpio number set: swclk swdio +# Header pin numbers: 23 24 +adapter gpio swclk -chip 0 11 +adapter gpio swdio -chip 0 8 + +# If you define trst or srst, use appropriate reset_config +# Header pin numbers: TRST - 26, SRST - 18 + +# adapter gpio trst -chip 0 7 +# reset_config trst_only + +# adapter gpio srst -chip 0 24 +# reset_config srst_only srst_push_pull + +# or if you have both connected, +# reset_config trst_and_srst srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/raspberrypi-native.cfg b/openocd-win/openocd/scripts/interface/raspberrypi-native.cfg new file mode 100644 index 0000000..7224723 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/raspberrypi-native.cfg @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Raspberry Pi used as a bitbang adapter. +# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html + +# Supports all models with 40-pin or 26-pin GPIO connector up to Raspberry Pi 4 B +# also supports Raspberry Pi Zero, Zero W and Zero 2 W. + +# Adapter speed calibration is computed from cpufreq/scaling_max_freq. +# Adjusts automatically if CPU is overclocked. + +adapter driver bcm2835gpio + +proc read_file { name } { + if {[catch {open $name r} fd]} { + return "" + } + set result [read $fd] + close $fd + return $result +} + +proc measure_clock {} { + set result [exec vcgencmd measure_clock arm] + set clock_hz [lindex [split $result "="] 1] + expr { $clock_hz / 1000 } +} + +proc get_max_cpu_clock { default } { + set clock [read_file /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq] + if { $clock > 100000 } { + return $clock + } + + # cpufreq not available. As the last resort try Broadcom's proprietary utility + if {![catch measure_clock clock] && $clock > 100000} { + return $clock + } + + echo "WARNING: Host CPU clock unknown." + echo "WARNING: Using the highest possible value $default kHz as a safe default." + echo "WARNING: Expect JTAG/SWD clock significantly slower than requested." + + return $default +} + +set compat [read_file /proc/device-tree/compatible] +set clocks_per_timing_loop 4 + +if {[string match *bcm2711* $compat]} { + set speed_offset 52 +} elseif {[string match *bcm2837* $compat] || [string match *bcm2710* $compat]} { + set speed_offset 34 +} elseif {[string match *bcm2836* $compat] || [string match *bcm2709* $compat]} { + set speed_offset 36 +} elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} { + set clocks_per_timing_loop 6 + set speed_offset 32 +} else { + set speed_offset 32 + echo "WARNING: Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested." +} + +set clock [get_max_cpu_clock 2000000] +set speed_coeff [expr { $clock / $clocks_per_timing_loop }] + +# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET +# The coefficients depend on system clock and CPU frequency scaling. +bcm2835gpio speed_coeffs $speed_coeff $speed_offset + +source [find interface/raspberrypi-gpio-connector.cfg] diff --git a/openocd-win/openocd/scripts/interface/raspberrypi2-native.cfg b/openocd-win/openocd/scripts/interface/raspberrypi2-native.cfg new file mode 100644 index 0000000..fe9186f --- /dev/null +++ b/openocd-win/openocd/scripts/interface/raspberrypi2-native.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/raspberrypi2-native.cfg is deprecated." +echo "WARNING: Please use interface/raspberrypi-native.cfg for all Raspberry Pi models." + +source [find interface/raspberrypi-native.cfg] diff --git a/openocd-win/openocd/scripts/interface/rlink.cfg b/openocd-win/openocd/scripts/interface/rlink.cfg new file mode 100644 index 0000000..7671a3b --- /dev/null +++ b/openocd-win/openocd/scripts/interface/rlink.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Raisonance RLink +# +# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html +# + +adapter driver rlink diff --git a/openocd-win/openocd/scripts/interface/rshim.cfg b/openocd-win/openocd/scripts/interface/rshim.cfg new file mode 100644 index 0000000..1d5da59 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/rshim.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# BlueField SoC in-circuit debugger/programmer +# + +adapter driver rshim +transport select dapdirect_swd diff --git a/openocd-win/openocd/scripts/interface/stlink-dap.cfg b/openocd-win/openocd/scripts/interface/stlink-dap.cfg new file mode 100644 index 0000000..99c81c1 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/stlink-dap.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# +# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" +# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" +# +# SWIM transport is natively supported +# + +adapter driver st-link +st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# transport select dapdirect_jtag +# transport select dapdirect_swd +# transport select swim + +# Optionally specify the serial number of usb device +# e.g. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/openocd-win/openocd/scripts/interface/stlink-v1.cfg b/openocd-win/openocd/scripts/interface/stlink-v1.cfg new file mode 100644 index 0000000..96ed088 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/stlink-v1.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/openocd-win/openocd/scripts/interface/stlink-v2-1.cfg b/openocd-win/openocd/scripts/interface/stlink-v2-1.cfg new file mode 100644 index 0000000..d2baad4 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/stlink-v2-1.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/openocd-win/openocd/scripts/interface/stlink-v2.cfg b/openocd-win/openocd/scripts/interface/stlink-v2.cfg new file mode 100644 index 0000000..400411e --- /dev/null +++ b/openocd-win/openocd/scripts/interface/stlink-v2.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/openocd-win/openocd/scripts/interface/stlink.cfg b/openocd-win/openocd/scripts/interface/stlink.cfg new file mode 100644 index 0000000..8578bf2 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/stlink.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# + +adapter driver hla +hla_layout stlink +hla_device_desc "ST-LINK" +hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 +# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 +# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial +# number reset issues. +# eg. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/openocd-win/openocd/scripts/interface/sysfsgpio-raspberrypi.cfg b/openocd-win/openocd/scripts/interface/sysfsgpio-raspberrypi.cfg new file mode 100644 index 0000000..d2095a9 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/sysfsgpio-raspberrypi.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Config for using RaspberryPi's expansion header +# +# This is best used with a fast enough buffer but also +# is suitable for direct connection if the target voltage +# matches RPi's 3.3V +# +# Do not forget the GND connection, pin 6 of the expansion header. +# + +adapter driver sysfsgpio + +# Each of the JTAG lines need a gpio number set: tck tms tdi tdo +# Header pin numbers: 23 22 19 21 +sysfsgpio jtag_nums 11 25 10 9 + +# Each of the SWD lines need a gpio number set: swclk swdio +# Header pin numbers: 23 22 +sysfsgpio swd_nums 11 25 + +# If you define trst or srst, use appropriate reset_config +# Header pin numbers: TRST - 26, SRST - 18 + +# sysfsgpio trst_num 7 +# reset_config trst_only + +# sysfsgpio srst_num 24 +# reset_config srst_only srst_push_pull + +# or if you have both connected, +# reset_config trst_and_srst srst_push_pull diff --git a/openocd-win/openocd/scripts/interface/ti-icdi.cfg b/openocd-win/openocd/scripts/interface/ti-icdi.cfg new file mode 100644 index 0000000..db4e1e0 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ti-icdi.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Stellaris In-Circuit Debug Interface (ICDI) Board +# +# This is the propriety ICDI interface used on newer boards such as +# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232 +# Stellaris Launchpad - http://www.ti.com/stellaris-launchpad +# http://www.ti.com/tool/ek-lm4f232 +# + +adapter driver hla +hla_layout ti-icdi +hla_vid_pid 0x1cbe 0x00fd + +# Optionally specify the serial number of TI-ICDI devices, for when using +# multiple devices. Serial numbers can be obtained using lsusb -v +# Ex. +# adapter serial "0F003065" diff --git a/openocd-win/openocd/scripts/interface/ulink.cfg b/openocd-win/openocd/scripts/interface/ulink.cfg new file mode 100644 index 0000000..89a02e9 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/ulink.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Keil ULINK running OpenULINK firmware. +# +# http://www.keil.com/ulink1/ +# http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362 +# + +adapter driver ulink diff --git a/openocd-win/openocd/scripts/interface/usb-jtag.cfg b/openocd-win/openocd/scripts/interface/usb-jtag.cfg new file mode 100644 index 0000000..039c748 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/usb-jtag.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC. +# +# The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware +# including; +# * Xilinx USB Platform Cable +# * Many Digilent boards such as the Nexys, Nexys 2 and Atlys boards +# * Many fpga4fun.com boards from such as the Saxo and Xylo boards +# * The Numato Opsis +# +# Original version - http://www.ixo.de/info/usb_jtag/ +# Updated version - http://ixo-jtag.sourceforge.net/ +# Newest version - http://github.com/mithro/ixo-usb-jtag +# +# Procedure for using is; +# * Get the ixo-usb-jtag firmware for your hardware (or build it yourself). +# * Load the firmware using the fxload tool. +# * Use openocd. +# +# Unless you burn the firmware into the EEPROM on your device, power cycling +# will require you to reload the firmware using the fxload tool. This can be +# automated by using udev rules (which can be found in the firmware +# repository). +# +# Ubuntu packages built from mithro's version (with prebuilt firmware and udev +# rules) can be found at +# https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support +# +# TODO: Refactor the usb_blaster driver to allow loading firmware using any low +# level driver. Loading firmware is currently only supported on the ublast2 +# driver but ixo-usb-jtag requires the ftdi driver. + +adapter driver usb_blaster +usb_blaster vid_pid 0x16C0 0x06AD +usb_blaster device_desc "Van Ooijen Technische Informatica" +# ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the +# ftdi modes, using ublast2 will cause openocd to hang. +usb_blaster lowlevel_driver ftdi diff --git a/openocd-win/openocd/scripts/interface/usbprog.cfg b/openocd-win/openocd/scripts/interface/usbprog.cfg new file mode 100644 index 0000000..4f04b14 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/usbprog.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Embedded Projects USBprog +# +# http://embedded-projects.net/index.php?page_id=135 +# + +adapter driver usbprog +# USBprog is broken w/short TMS sequences, this is a workaround +# until the C code can be fixed. +tms_sequence long diff --git a/openocd-win/openocd/scripts/interface/vdebug.cfg b/openocd-win/openocd/scripts/interface/vdebug.cfg new file mode 100644 index 0000000..7350bb9 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/vdebug.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface + +if { [info exists VDEBUGHOST] } { + set _VDEBUGHOST $VDEBUGHOST +} else { + set _VDEBUGHOST localhost +} +if { [info exists VDEBUGPORT] } { + set _VDEBUGPORT $VDEBUGPORT +} else { + set _VDEBUGPORT 8192 +} + +adapter driver vdebug +# vdebug server:port +vdebug server $_VDEBUGHOST:$_VDEBUGPORT + +# example config debug level and log +#debug_level 3 +#log_output vd_ocd.log + +# example config listen on all interfaces, disable tcl/telnet server +bindto 0.0.0.0 +#gdb_port 3333 +#telnet_port disabled +tcl_port disabled + +# transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw +vdebug batching 1 + +# Polling values +vdebug polling 100 1000 diff --git a/openocd-win/openocd/scripts/interface/vsllink.cfg b/openocd-win/openocd/scripts/interface/vsllink.cfg new file mode 100644 index 0000000..f780c89 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/vsllink.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Versaloon Link -- VSLLink +# +# http://www.versaloon.com/ +# + +adapter driver vsllink diff --git a/openocd-win/openocd/scripts/interface/xds110.cfg b/openocd-win/openocd/scripts/interface/xds110.cfg new file mode 100644 index 0000000..aff0f38 --- /dev/null +++ b/openocd-win/openocd/scripts/interface/xds110.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments XDS110 +# +# http://processors.wiki.ti.com/index.php/XDS110 +# http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities +# + +adapter driver xds110 + +# Use serial number option to use a specific XDS110 +# when more than one are connected to the host. +# adapter serial 00000000 diff --git a/openocd-win/openocd/scripts/mem_helper.tcl b/openocd-win/openocd/scripts/mem_helper.tcl new file mode 100644 index 0000000..0229d54 --- /dev/null +++ b/openocd-win/openocd/scripts/mem_helper.tcl @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Helper for common memory read/modify/write procedures + +# mrw: "memory read word", returns value of $reg +proc mrw {reg} { + return [read_memory $reg 32 1] +} + +add_usage_text mrw "address" +add_help_text mrw "Returns value of word in memory." + +# mrh: "memory read halfword", returns value of $reg +proc mrh {reg} { + return [read_memory $reg 16 1] +} + +add_usage_text mrh "address" +add_help_text mrh "Returns value of halfword in memory." + +# mrb: "memory read byte", returns value of $reg +proc mrb {reg} { + return [read_memory $reg 8 1] +} + +add_usage_text mrb "address" +add_help_text mrb "Returns value of byte in memory." + +# mmw: "memory modify word", updates value of $reg +# $reg <== ((value & ~$clearbits) | $setbits) +proc mmw {reg setbits clearbits} { + set old [mrw $reg] + set new [expr {($old & ~$clearbits) | $setbits}] + mww $reg $new +} + +add_usage_text mmw "address setbits clearbits" +add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;" diff --git a/openocd-win/openocd/scripts/memory.tcl b/openocd-win/openocd/scripts/memory.tcl new file mode 100644 index 0000000..b111749 --- /dev/null +++ b/openocd-win/openocd/scripts/memory.tcl @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MEMORY +# +# All Memory regions have two components. +# (1) A count of regions, in the form N_NAME +# (2) An array within info about each region. +# +# The ARRAY +# +# <NAME>( RegionNumber , ATTRIBUTE ) +# +# Where <NAME> is one of: +# +# N_FLASH & FLASH (internal memory) +# N_RAM & RAM (internal memory) +# N_MMREGS & MMREGS (for memory mapped registers) +# N_XMEM & XMEM (off chip memory, ie: flash on cs0, sdram on cs2) +# or N_UNKNOWN & UNKNOWN for things that do not exist. +# +# We have 1 unknown region. +set N_UNKNOWN 1 +# All MEMORY regions must have these attributes +# CS - chip select (if internal, use -1) +set UNKNOWN(0,CHIPSELECT) -1 +# BASE - base address in memory +set UNKNOWN(0,BASE) 0 +# LEN - length in bytes +set UNKNOWN(0,LEN) $CPU_MAX_ADDRESS +# HUMAN - human name of the region +set UNKNOWN(0,HUMAN) "unknown" +# TYPE - one of: +# flash, ram, mmr, unknown +# For harvard arch: +# iflash, dflash, iram, dram +set UNKNOWN(0,TYPE) "unknown" +# RWX - access ablity +# unix style chmod bits +# 0 - no access +# 1 - execute +# 2 - write +# 4 - read +# hence: 7 - readwrite execute +set RWX_NO_ACCESS 0 +set RWX_X_ONLY $BIT0 +set RWX_W_ONLY $BIT1 +set RWX_R_ONLY $BIT2 +set RWX_RW [expr {$RWX_R_ONLY + $RWX_W_ONLY}] +set RWX_R_X [expr {$RWX_R_ONLY + $RWX_X_ONLY}] +set RWX_RWX [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}] +set UNKNOWN(0,RWX) $RWX_NO_ACCESS + +# WIDTH - access width +# 8,16,32 [0 means ANY] +set ACCESS_WIDTH_NONE 0 +set ACCESS_WIDTH_8 $BIT0 +set ACCESS_WIDTH_16 $BIT1 +set ACCESS_WIDTH_32 $BIT2 +set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}] +set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE + +proc iswithin { ADDRESS BASE LEN } { + return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}] +} + +proc address_info { ADDRESS } { + + foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } { + if { info exists $WHERE } { + set lmt [set N_[set WHERE]] + for { set region 0 } { $region < $lmt } { incr region } { + if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } { + return "$WHERE $region"; + } + } + } + } + + # Return the 'unknown' + return "UNKNOWN 0" +} + +proc memread32 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] { + return $foo + } else { + error "memread32: $msg" + } +} + +proc memread16 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] { + return $foo + } else { + error "memread16: $msg" + } +} + +proc memread8 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] { + return $foo + } else { + error "memread8: $msg" + } +} + +proc memwrite32 {ADDR DATA} { + if ![ catch { write_memory $ADDR 32 $DATA } msg ] { + return $DATA + } else { + error "memwrite32: $msg" + } +} + +proc memwrite16 {ADDR DATA} { + if ![ catch { write_memory $ADDR 16 $DATA } msg ] { + return $DATA + } else { + error "memwrite16: $msg" + } +} + +proc memwrite8 {ADDR DATA} { + if ![ catch { write_memory $ADDR 8 $DATA } msg ] { + return $DATA + } else { + error "memwrite8: $msg" + } +} + +proc memread32_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] { + return $foo + } else { + error "memread32: $msg" + } +} + +proc memread16_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] { + return $foo + } else { + error "memread16: $msg" + } +} + +proc memread8_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] { + return $foo + } else { + error "memread8: $msg" + } +} + +proc memwrite32_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite32: $msg" + } +} + +proc memwrite16_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite16: $msg" + } +} + +proc memwrite8_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite8: $msg" + } +} diff --git a/openocd-win/openocd/scripts/mmr_helpers.tcl b/openocd-win/openocd/scripts/mmr_helpers.tcl new file mode 100644 index 0000000..5c37fcf --- /dev/null +++ b/openocd-win/openocd/scripts/mmr_helpers.tcl @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc proc_exists { NAME } { + set n [info commands $NAME] + set l [string length $n] + return [expr {$l != 0}] +} + +# Give: REGISTER name - must be a global variable. +proc show_mmr32_reg { NAME } { + + global $NAME + # we want $($NAME) + set a [set [set NAME]] + + if ![catch { set v [memread32 $a] } msg ] { + echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v] + + # Was a helper defined? + set fn show_${NAME}_helper + if [ proc_exists $fn ] { + # Then call it + $fn $NAME $a $v + } + return $v; + } else { + error [format "%s (%s)" $msg $NAME ] + } +} + + +# Give: NAMES - an array of names accessible +# in the callers symbol-scope. +# VAL - the bits to display. + +proc show_mmr32_bits { NAMES VAL } { + + upvar $NAMES MYNAMES + + set w 5 + foreach {IDX N} $MYNAMES { + set l [string length $N] + if { $l > $w } { set w $l } + } + + for { set x 24 } { $x >= 0 } { incr x -8 } { + echo -n " " + for { set y 7 } { $y >= 0 } { incr y -1 } { + set s $MYNAMES([expr {$x + $y}]) + echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ] + } + echo "" + + echo -n " " + for { set y 7 } { $y >= 0 } { incr y -1 } { + echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""] + } + echo "" + } +} + + +proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } { + set width [expr {(($MSB - $LSB + 1) + 7) / 4}] + set nval [show_normalize_bitfield $VAL $MSB $LSB ] + set name0 [lindex $FIELDVALUES 0 ] + if [ string compare $name0 _NUMBER_ ] { + set sval [lindex $FIELDVALUES $nval] + } else { + set sval "" + } + echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ] +} + +# Give: ADDR - address of the register. +# BIT - bit's number. + +proc get_mmr_bit { ADDR BIT } { + set val [memread32 $ADDR] + set bit_val [expr {$val & [expr {1 << $BIT}]}] + return $bit_val +} + + +# Give: ADDR - address of the register. +# MSB - MSB bit's number. +# LSB - LSB bit's number. + +proc get_mmr_bitfield { ADDR MSB LSB } { + set rval [memread32 $ADDR] + return normalize_bitfield $rval $MSB $LSB +} diff --git a/openocd-win/openocd/scripts/target/1986ве1т.cfg b/openocd-win/openocd/scripts/target/1986ве1т.cfg new file mode 100644 index 0000000..a3172cc --- /dev/null +++ b/openocd-win/openocd/scripts/target/1986ве1т.cfg @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# 1986ВЕ1Т +# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68 + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME 1986ве1т +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + # SWD IDCODE + set _CPUTAPID 0x2ba01477 + } +} +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +# use AHB-Lite SRAM for work area +$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# can't handle overlapping memory regions +if { [info exists IMEMORY] && [string equal $IMEMORY true] } { + flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4 +} else { + flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/adsp-sc58x.cfg b/openocd-win/openocd/scripts/target/adsp-sc58x.cfg new file mode 100644 index 0000000..3dcfc91 --- /dev/null +++ b/openocd-win/openocd/scripts/target/adsp-sc58x.cfg @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs) +# + +# Evaluation boards by Analog Devices (and designs derived from them) use a +# non-standard 10-pin 0.05" ARM Cortex Debug Connector. In this bastardized +# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST. +# +# As a result, a standards-compliant debug pod will force /TRST active, +# putting the processor's debug interface into reset and preventing usage. +# +# A connector adapter must be employed on these boards to isolate or remap +# /TRST so that it is only asserted when intended. + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ADSP-SC58x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3BA02477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -event examine-end { + global _TARGETNAME + sc58x_enabledebug +} + +proc sc58x_enabledebug {} { + # Enable debugging functionality by setting bits in the TAPC_DBGCTL register + # it is not possible to halt the target unless these bits have been set + ap0.mem mww 0x31131000 0xFFFF +} diff --git a/openocd-win/openocd/scripts/target/aduc702x.cfg b/openocd-win/openocd/scripts/target/aduc702x.cfg new file mode 100644 index 0000000..c903710 --- /dev/null +++ b/openocd-win/openocd/scripts/target/aduc702x.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME aduc702x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +adapter srst delay 200 +jtag_ntrst_delay 200 + +## JTAG scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +## +## Target configuration +## +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +# allocate the entire SRAM as working area +$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000 + +## flash configuration +# only target number is needed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME + +## If you use the watchdog, the following code makes sure that the board +## doesn't reboot when halted via JTAG. Yes, on the older generation +## AdUC702x, timer3 continues running even when the CPU is halted. + +proc watchdog_service {} { + global watchdog_hdl + mww 0xffff036c 0 +# echo "watchdog!!" + set watchdog_hdl [after 500 watchdog_service] +} + +$_TARGETNAME configure -event reset-halt-post { watchdog_service } +$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl } diff --git a/openocd-win/openocd/scripts/target/aducm360.cfg b/openocd-win/openocd/scripts/target/aducm360.cfg new file mode 100644 index 0000000..5cfb483 --- /dev/null +++ b/openocd-win/openocd/scripts/target/aducm360.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# This file was created using as references the stm32f1x.cfg and aduc702x.cfg +# +source [find target/swj-dp.tcl] + +# Chip name +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME aducm360 +} + +# Endianness +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# Eventually, the whole SRAM of ADuCM360 will be used (8kB) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# SWD/JTAG speed +adapter speed 1000 + +## +## Target configuration +## +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +# allocate the working area +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME + +adapter srst delay 100 + +cortex_m reset_config sysresetreq diff --git a/openocd-win/openocd/scripts/target/allwinner_v3s.cfg b/openocd-win/openocd/scripts/target/allwinner_v3s.cfg new file mode 100644 index 0000000..437bd95 --- /dev/null +++ b/openocd-win/openocd/scripts/target/allwinner_v3s.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the config for an Allwinner V3/V3s (sun8iw8). +# +# Notes: +# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz. +# - Thumb-2 Technology +# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction +# for acceleration of media and signal processing functions +# - Support Large Physical Address Extensions(LPAE) +# - VFPv4 Floating Point Unit +# - 32KB L1 Instruction cache and 32KB L1 Data cache +# - 128KB L2 cache +# - has some integrated DDR2 RAM. +# +# Pins related for debug and bootstrap: +# JTAG +# JTAG_TMS PF0, SDC0_D1 +# JTAG_TDI PF1, SDC0_D0 +# JTAG_TDO PF3, SDC0_CMD +# JTAG_TCK PF5, SDC0_D2 +# UART +# None of UART ports seems to be enabled by ROM. +# UART0_TX PF2, SDC0_CLK Per default disabled +# UART0_RX PF4, SDC0_D3 Per default disabled +# UART1_TX PE21 Per default disabled +# UART1_RX PE22 Per default disabled +# UART2_TX PB0 Per default disabled +# UART2_RX PB1 Per default disabled +# +# JTAG is enabled by default after power on on listed JTAG_* pins. So far the +# boot sequence is: +# Time Action +# 0000ms Power ON +# 0200ms JTAG enabled +# 0220ms JTAG pins switched to SD mode +# +# The time frame of 20ms can be not enough to init and halt the CPU. In this +# case I would recommend to set: "adapter speed 15000" +# To get more or less precise timings, the board should provide reset pin, +# or some bench power supply with remote function. In my case I used +# EEZ H24005 with this command to power on and halt the target: +# "exec echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt" +# After this it is possible to enable JTAG mode again from boot loader or OS. +# Following DAPs are available: +# dap[0]->MEM-AP AHB +# dap[1]->MEM-AP APB->CA7[0] +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME v3s +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# No NRST or SRST is present on the SoC. Boards may provide +# some sort of Power cycle reset for complete board or SoC. +# For this case we provide srst_pulls_trst so the board config +# only needs to set srst_only. +reset_config none srst_pulls_trst + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# Add Cortex A7 core +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap diff --git a/openocd-win/openocd/scripts/target/alphascale_asm9260t.cfg b/openocd-win/openocd/scripts/target/alphascale_asm9260t.cfg new file mode 100644 index 0000000..735555e --- /dev/null +++ b/openocd-win/openocd/scripts/target/alphascale_asm9260t.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME asm9260t +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x079264F3 +} + +# And srst_pulls_trst by chip design. +reset_config srst_pulls_trst + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/altera_fpgasoc.cfg b/openocd-win/openocd/scripts/target/altera_fpgasoc.cfg new file mode 100644 index 0000000..a98b346 --- /dev/null +++ b/openocd-win/openocd/scripts/target/altera_fpgasoc.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Altera cyclone V SoC family, 5Cxxx +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME fpgasoc +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# Subsidiary TAP: fpga +if { [info exists FPGA_TAPID] } { + set _FPGA_TAPID $FPGA_TAPID +} else { + set _FPGA_TAPID 0x02d020dd +} +jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID + + +# +# Cortex-A9 target +# + +# GDB target: Cortex-A9, using DAP, configuring only one core +# Base addresses of cores: +# core 0 - 0x80110000 +# core 1 - 0x80112000 + +# Slow speed to be sure it will work +adapter speed 1000 + +set _TARGETNAME1 $_CHIPNAME.cpu.0 +set _TARGETNAME2 $_CHIPNAME.cpu.1 + +# A9 core 0 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x80110000 + +$_TARGETNAME1 configure -event reset-start { adapter speed 1000 } +$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1" + + +# A9 core 1 +#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \ +# -coreid 1 -dbgbase 0x80112000 + +#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 } +#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2" + +proc cycv_dbginit {target} { + # General Cortex-A8/A9 debug initialisation + cortex_a dbginit +} diff --git a/openocd-win/openocd/scripts/target/altera_fpgasoc_arria10.cfg b/openocd-win/openocd/scripts/target/altera_fpgasoc_arria10.cfg new file mode 100644 index 0000000..fe58379 --- /dev/null +++ b/openocd-win/openocd/scripts/target/altera_fpgasoc_arria10.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Intel (Altera) Arria10 FPGA SoC + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME arria10 +} + +# ARM CoreSight Debug Access Port (dap HPS) +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID + +# Subsidiary TAP: fpga (tap) +# See Intel Arria 10 Handbook +# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf +# Intel Arria 10 GX 160 0x02ee20dd +# Intel Arria 10 GX 220 0x02e220dd +# Intel Arria 10 GX 270 0x02ee30dd +# Intel Arria 10 GX 320 0x02e230dd +# Intel Arria 10 GX 480 0x02e240dd +# Intel Arria 10 GX 570 0x02ee50dd +# Intel Arria 10 GX 660 0x02e250dd +# Intel Arria 10 GX 900 0x02ee60dd +# Intel Arria 10 GX 1150 0x02e660dd +# Intel Arria 10 GT 900 0x02e260dd +# Intel Arria 10 GT 1150 0x02e060dd +# Intel Arria 10 SX 160 0x02e620dd +# Intel Arria 10 SX 220 0x02e020dd +# Intel Arria 10 SX 270 0x02e630dd +# Intel Arria 10 SX 320 0x02e030dd +# Intel Arria 10 SX 480 0x02e040dd +# Intel Arria 10 SX 570 0x02e650dd +# Intel Arria 10 SX 660 0x02e050dd +jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \ + -expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \ + -expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \ + -expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \ + -expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \ + -expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \ + -expected-id 0x02e050dd + +set _TARGETNAME $_CHIPNAME.cpu + +# +# Cortex-A9 target + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0 +target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \ + -defer-examine +target smp $_TARGETNAME.0 $_TARGETNAME.1 diff --git a/openocd-win/openocd/scripts/target/am335x.cfg b/openocd-win/openocd/scripts/target/am335x.cfg new file mode 100644 index 0000000..208ebf5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/am335x.cfg @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/icepick.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME am335x +} + +# set the taps to be enabled by default. this can be overridden +# by setting DEFAULT_TAPS in a separate configuration file +# or directly on the command line. +if { [info exists DEFAULT_TAPS] } { + set _DEFAULT_TAPS "$DEFAULT_TAPS" +} else { + set _DEFAULT_TAPS "$_CHIPNAME.tap" +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4b6b902f +} +jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0" +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# +# M3 DAP +# +if { [info exists M3_DAP_TAPID] } { + set _M3_DAP_TAPID $M3_DAP_TAPID +} else { + set _M3_DAP_TAPID 0x4b6b902f +} +jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable +jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0" +dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap + +# +# ICEpick-D (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b94402f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version +jtag configure $_CHIPNAME.jrc -event setup { + global _DEFAULT_TAPS + enable_default_taps $_DEFAULT_TAPS +} +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" + +# +# helper function that enables all taps passed as argument +# +proc enable_default_taps { taps } { + foreach tap $taps { + jtag tapenable $tap + } +} + +# +# Cortex-M3 target +# +set _TARGETNAME_2 $_CHIPNAME.m3 +target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap + +# +# Cortex-A8 target +# +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000 + +# SRAM: 64K at 0x4030.0000; use the first 16K +$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 + + +# when putting the target into 'reset halt', we need to disable the watchdog as +# it would otherwise trigger while we're in JTAG +# FIXME: unify with target/am437x.cfg +source [find mem_helper.tcl] +set WDT1_BASE_ADDR 0x44e35000 +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] +proc disable_watchdog { } { + global WDT1_WSPR + global WDT1_W_PEND_WSPR + global _TARGETNAME + + set curstate [$_TARGETNAME curstate] + + if { [string compare $curstate halted] == 0 } { + set WDT_DISABLE_SEQ1 0xaaaa + set WDT_DISABLE_SEQ2 0x5555 + + mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1 + + # Empty body to make sure this executes as fast as possible. + # We don't want any delays here otherwise romcode might start + # executing and end up changing state of certain IPs. + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } + + mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } + } +} +$_TARGETNAME configure -event reset-end { disable_watchdog } diff --git a/openocd-win/openocd/scripts/target/am437x.cfg b/openocd-win/openocd/scripts/target/am437x.cfg new file mode 100644 index 0000000..5350927 --- /dev/null +++ b/openocd-win/openocd/scripts/target/am437x.cfg @@ -0,0 +1,1003 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/icepick.cfg] +source [find mem_helper.tcl] + +############################################################################### +## AM437x Registers ## +############################################################################### +set PRCM_BASE_ADDR 0x44df0000 +set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}] +set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}] +set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}] +set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}] +set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}] +set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}] +set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}] +set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}] +set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}] +set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}] +set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}] +set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}] +set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}] +set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}] +set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}] +set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}] +set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}] +set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}] +set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}] +set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}] +set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}] +set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}] +set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}] +set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}] +set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}] +set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}] +set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}] +set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}] +set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}] +set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}] +set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}] +set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}] +set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}] +set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}] +set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}] +set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}] +set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}] +set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}] +set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}] +set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}] +set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}] +set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}] +set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}] +set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}] +set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}] +set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}] +set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}] +set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}] +set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}] +set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}] +set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}] +set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}] +set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}] +set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}] +set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}] +set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}] +set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}] +set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}] +set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}] +set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}] +set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}] +set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}] +set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}] +set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}] +set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}] +set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}] +set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}] +set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}] +set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}] +set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}] +set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}] +set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}] +set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}] +set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}] +set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}] +set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}] +set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}] +set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}] +set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}] +set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}] +set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}] +set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}] +set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}] +set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}] +set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}] +set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}] +set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}] +set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}] +set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}] +set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}] +set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}] +set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}] +set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}] +set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}] +set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}] +set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}] +set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}] +set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}] +set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}] +set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}] +set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}] +set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}] +set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}] +set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}] +set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}] +set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}] +set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}] +set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}] +set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}] +set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}] +set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}] +set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}] +set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}] +set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}] +set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}] +set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}] +set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}] +set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}] +set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}] +set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}] +set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}] +set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}] +set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}] +set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}] +set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}] +set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}] +set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}] +set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}] +set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}] +set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}] +set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}] +set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}] +set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}] +set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}] +set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}] +set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}] +set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}] +set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}] +set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}] +set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}] +set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}] +set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}] +set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}] +set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}] +set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}] +set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}] +set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}] +set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}] +set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}] +set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}] +set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}] +set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}] +set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}] +set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}] +set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}] +set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}] +set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}] +set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}] +set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}] +set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}] +set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}] +set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}] +set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}] +set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}] +set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}] +set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}] +set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}] +set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}] +set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}] +set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}] +set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}] +set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}] +set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}] +set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}] +set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}] +set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}] +set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}] +set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}] +set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}] +set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}] +set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}] +set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}] +set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}] +set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}] +set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}] +set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}] +set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}] +set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}] +set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}] +set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}] +set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}] +set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}] +set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}] +set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}] +set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}] +set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}] +set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}] +set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}] +set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}] +set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}] +set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}] +set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}] +set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}] + +set CONTROL_BASE_ADDR 0x44e10000 +set CONTROL_STATUS [expr {$CONTROL_BASE_ADDR + 0x0040}] +set DEVICE_ID [expr {$CONTROL_BASE_ADDR + 0x0600}] +set DEV_FEATURE [expr {$CONTROL_BASE_ADDR + 0x0604}] +set DEV_ATTRIBUTE [expr {$CONTROL_BASE_ADDR + 0x0610}] +set MAC_ID0_LO [expr {$CONTROL_BASE_ADDR + 0x0630}] +set MAC_ID0_HI [expr {$CONTROL_BASE_ADDR + 0x0634}] +set MAC_ID1_LO [expr {$CONTROL_BASE_ADDR + 0x0638}] +set MAC_ID1_HI [expr {$CONTROL_BASE_ADDR + 0x063c}] +set USB_VID_PID [expr {$CONTROL_BASE_ADDR + 0x07f4}] +set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr {$CONTROL_BASE_ADDR + 0x0964}] +set CONTROL_CONF_SPI4_CS0 [expr {$CONTROL_BASE_ADDR + 0x0a5c}] +set CONTROL_CONF_SPI2_SCLK [expr {$CONTROL_BASE_ADDR + 0x0a60}] +set CONTROL_CONF_SPI2_D0 [expr {$CONTROL_BASE_ADDR + 0x0a64}] +set CONTROL_CONF_XDMA_EVENT_INTR0 [expr {$CONTROL_BASE_ADDR + 0x0a70}] +set CONTROL_CONF_XDMA_EVENT_INTR1 [expr {$CONTROL_BASE_ADDR + 0x0a74}] +set CONTROL_CONF_GPMC_A0 [expr {$CONTROL_BASE_ADDR + 0x0840}] +set DDR_IO_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e04}] +set VTP_CTRL_REG [expr {$CONTROL_BASE_ADDR + 0x0e0c}] +set VREF_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e14}] +set DDR_CKE_CTRL [expr {$CONTROL_BASE_ADDR + 0x131c}] +set DDR_ADDRCTRL_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1404}] +set DDR_ADDRCTRL_WD0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1408}] +set DDR_ADDRCTRL_WD1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x140c}] +set DDR_DATA0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1440}] +set DDR_DATA1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1444}] +set DDR_DATA2_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1448}] +set DDR_DATA3_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x144c}] +set EMIF_SDRAM_CONFIG_EXT [expr {$CONTROL_BASE_ADDR + 0x1460}] +set EMIF_SDRAM_STATUS_EXT [expr {$CONTROL_BASE_ADDR + 0x1464}] + +set GPIO0_BASE_ADDR 0x44e07000 +set GPIO0_SYSCONFIG [expr {$GPIO0_BASE_ADDR + 0x0010}] +set GPIO0_SYSSTATUS [expr {$GPIO0_BASE_ADDR + 0x0114}] +set GPIO0_CTRL [expr {$GPIO0_BASE_ADDR + 0x0130}] +set GPIO0_OE [expr {$GPIO0_BASE_ADDR + 0x0134}] +set GPIO0_CLEARDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0190}] +set GPIO0_SETDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0194}] + +set GPIO5_BASE_ADDR 0x48322000 +set GPIO5_SYSCONFIG [expr {$GPIO5_BASE_ADDR + 0x0010}] +set GPIO5_SYSSTATUS [expr {$GPIO5_BASE_ADDR + 0x0114}] +set GPIO5_CTRL [expr {$GPIO5_BASE_ADDR + 0x0130}] +set GPIO5_OE [expr {$GPIO5_BASE_ADDR + 0x0134}] +set GPIO5_CLEARDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0190}] +set GPIO5_SETDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0194}] + +set GPIO1_BASE_ADDR 0x4804c000 +set GPIO1_SYSCONFIG [expr {$GPIO1_BASE_ADDR + 0x0010}] +set GPIO1_SYSSTATUS [expr {$GPIO1_BASE_ADDR + 0x0114}] +set GPIO1_CTRL [expr {$GPIO1_BASE_ADDR + 0x0130}] +set GPIO1_OE [expr {$GPIO1_BASE_ADDR + 0x0134}] +set GPIO1_CLEARDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0190}] +set GPIO1_SETDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0194}] + +set EMIF_BASE_ADDR 0x4c000000 +set EMIF_STATUS [expr {$EMIF_BASE_ADDR + 0x0004}] +set EMIF_SDRAM_CONFIG [expr {$EMIF_BASE_ADDR + 0x0008}] +set EMIF_SDRAM_CONFIG_2 [expr {$EMIF_BASE_ADDR + 0x000c}] +set EMIF_SDRAM_REF_CTRL [expr {$EMIF_BASE_ADDR + 0x0010}] +set EMIF_SDRAM_REF_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x0014}] +set EMIF_SDRAM_TIM_1 [expr {$EMIF_BASE_ADDR + 0x0018}] +set EMIF_SDRAM_TIM_1_SHDW [expr {$EMIF_BASE_ADDR + 0x001c}] +set EMIF_SDRAM_TIM_2 [expr {$EMIF_BASE_ADDR + 0x0020}] +set EMIF_SDRAM_TIM_2_SHDW [expr {$EMIF_BASE_ADDR + 0x0024}] +set EMIF_SDRAM_TIM_3 [expr {$EMIF_BASE_ADDR + 0x0028}] +set EMIF_SDRAM_TIM_3_SHDW [expr {$EMIF_BASE_ADDR + 0x002c}] +set EMIF_LPDDR2_NVM_TIM [expr {$EMIF_BASE_ADDR + 0x0030}] +set EMIF_LPDDR2_NVM_TIM_SHDW [expr {$EMIF_BASE_ADDR + 0x0034}] +set EMIF_PWR_MGMT_CTRL [expr {$EMIF_BASE_ADDR + 0x0038}] +set EMIF_PWR_MGMT_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x003c}] +set EMIF_LPDDR2_MODE_REG_DATA [expr {$EMIF_BASE_ADDR + 0x0040}] +set EMIF_LPDDR2_MODE_REG_CFG [expr {$EMIF_BASE_ADDR + 0x0050}] +set EMIF_OCP_CONFIG [expr {$EMIF_BASE_ADDR + 0x0054}] +set EMIF_OCP_CFG_VAL_1 [expr {$EMIF_BASE_ADDR + 0x0058}] +set EMIF_OCP_CFG_VAL_2 [expr {$EMIF_BASE_ADDR + 0x005c}] +set EMIF_IODFT_TLGC [expr {$EMIF_BASE_ADDR + 0x0060}] +set EMIF_IODFT_CTRL_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0064}] +set EMIF_IODFT_ADDR_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0068}] +set EMIF_IODFT_DATA_MISR_RSLT_1 [expr {$EMIF_BASE_ADDR + 0x006c}] +set EMIF_IODFT_DATA_MISR_RSLT_2 [expr {$EMIF_BASE_ADDR + 0x0070}] +set EMIF_IODFT_DATA_MISR_RSLT_3 [expr {$EMIF_BASE_ADDR + 0x0074}] +set EMIF_PERF_CNT_1 [expr {$EMIF_BASE_ADDR + 0x0080}] +set EMIF_PERF_CNT_2 [expr {$EMIF_BASE_ADDR + 0x0084}] +set EMIF_PERF_CNT_CFG [expr {$EMIF_BASE_ADDR + 0x0088}] +set EMIF_PERF_CNT_SEL [expr {$EMIF_BASE_ADDR + 0x008c}] +set EMIF_PERF_CNT_TIM [expr {$EMIF_BASE_ADDR + 0x0090}] +set EMIF_MISC_REG [expr {$EMIF_BASE_ADDR + 0x0094}] +set EMIF_DLL_CALIB_CTRL [expr {$EMIF_BASE_ADDR + 0x0098}] +set EMIF_DLL_CALIB_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x009c}] +set EMIF_IRQ_EOI [expr {$EMIF_BASE_ADDR + 0x00a0}] +set EMIF_IRQSTATUS_RAW_SYS [expr {$EMIF_BASE_ADDR + 0x00a4}] +set EMIF_IRQSTATUS_SYS [expr {$EMIF_BASE_ADDR + 0x00ac}] +set EMIF_IRQENABLE_SET_SYS [expr {$EMIF_BASE_ADDR + 0x00b4}] +set EMIF_IRQENABLE_CLR_SYS [expr {$EMIF_BASE_ADDR + 0x00bc}] +set EMIF_ZQ_CONFIG [expr {$EMIF_BASE_ADDR + 0x00c8}] +set EMIF_TEMP_ALERT_CONFIG [expr {$EMIF_BASE_ADDR + 0x00cc}] +set EMIF_OCP_ERR_LOG [expr {$EMIF_BASE_ADDR + 0x00d0}] +set EMIF_RDWR_LVL_RMP_WIN [expr {$EMIF_BASE_ADDR + 0x00d4}] +set EMIF_RDWR_LVL_RMP_CTRL [expr {$EMIF_BASE_ADDR + 0x00d8}] +set EMIF_RDWR_LVL_CTRL [expr {$EMIF_BASE_ADDR + 0x00dc}] +set EMIF_DDR_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x00e4}] +set EMIF_DDR_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x00e8}] +set EMIF_DDR_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x00ec}] +set EMIF_PRI_COS_MAP [expr {$EMIF_BASE_ADDR + 0x0100}] +set EMIF_CONNID_COS_1_MAP [expr {$EMIF_BASE_ADDR + 0x0104}] +set EMIF_CONNID_COS_2_MAP [expr {$EMIF_BASE_ADDR + 0x0108}] +set ECC_CTRL [expr {$EMIF_BASE_ADDR + 0x0110}] +set ECC_ADDR_RNG_1 [expr {$EMIF_BASE_ADDR + 0x0114}] +set ECC_ADDR_RNG_2 [expr {$EMIF_BASE_ADDR + 0x0118}] +set EMIF_RD_WR_EXEC_THRSH [expr {$EMIF_BASE_ADDR + 0x0120}] +set COS_CONFIG [expr {$EMIF_BASE_ADDR + 0x0124}] + +set PHY_STATUS_1 [expr {$EMIF_BASE_ADDR + 0x0144}] +set PHY_STATUS_2 [expr {$EMIF_BASE_ADDR + 0x0148}] +set PHY_STATUS_3 [expr {$EMIF_BASE_ADDR + 0x014c}] +set PHY_STATUS_4 [expr {$EMIF_BASE_ADDR + 0x0150}] +set PHY_STATUS_5 [expr {$EMIF_BASE_ADDR + 0x0154}] +set PHY_STATUS_6 [expr {$EMIF_BASE_ADDR + 0x0158}] +set PHY_STATUS_7 [expr {$EMIF_BASE_ADDR + 0x015c}] +set PHY_STATUS_8 [expr {$EMIF_BASE_ADDR + 0x0160}] +set PHY_STATUS_9 [expr {$EMIF_BASE_ADDR + 0x0164}] +set PHY_STATUS_10 [expr {$EMIF_BASE_ADDR + 0x0168}] +set PHY_STATUS_11 [expr {$EMIF_BASE_ADDR + 0x016c}] +set PHY_STATUS_12 [expr {$EMIF_BASE_ADDR + 0x0170}] +set PHY_STATUS_13 [expr {$EMIF_BASE_ADDR + 0x0174}] +set PHY_STATUS_14 [expr {$EMIF_BASE_ADDR + 0x0178}] +set PHY_STATUS_15 [expr {$EMIF_BASE_ADDR + 0x017c}] +set PHY_STATUS_16 [expr {$EMIF_BASE_ADDR + 0x0180}] +set PHY_STATUS_17 [expr {$EMIF_BASE_ADDR + 0x0184}] +set PHY_STATUS_18 [expr {$EMIF_BASE_ADDR + 0x0188}] +set PHY_STATUS_19 [expr {$EMIF_BASE_ADDR + 0x018c}] +set PHY_STATUS_20 [expr {$EMIF_BASE_ADDR + 0x0190}] +set PHY_STATUS_21 [expr {$EMIF_BASE_ADDR + 0x0194}] +set PHY_STATUS_22 [expr {$EMIF_BASE_ADDR + 0x0198}] +set PHY_STATUS_23 [expr {$EMIF_BASE_ADDR + 0x019c}] +set PHY_STATUS_24 [expr {$EMIF_BASE_ADDR + 0x01a0}] +set PHY_STATUS_25 [expr {$EMIF_BASE_ADDR + 0x01a4}] +set PHY_STATUS_26 [expr {$EMIF_BASE_ADDR + 0x01a8}] +set PHY_STATUS_27 [expr {$EMIF_BASE_ADDR + 0x01ac}] +set PHY_STATUS_28 [expr {$EMIF_BASE_ADDR + 0x01b0}] + +set EXT_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x0200}] +set EXT_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x0204}] +set EXT_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x0208}] +set EXT_PHY_CTRL_2_SHDW [expr {$EMIF_BASE_ADDR + 0x020c}] +set EXT_PHY_CTRL_3 [expr {$EMIF_BASE_ADDR + 0x0210}] +set EXT_PHY_CTRL_3_SHDW [expr {$EMIF_BASE_ADDR + 0x0214}] +set EXT_PHY_CTRL_4 [expr {$EMIF_BASE_ADDR + 0x0218}] +set EXT_PHY_CTRL_4_SHDW [expr {$EMIF_BASE_ADDR + 0x021c}] +set EXT_PHY_CTRL_5 [expr {$EMIF_BASE_ADDR + 0x0220}] +set EXT_PHY_CTRL_5_SHDW [expr {$EMIF_BASE_ADDR + 0x0224}] +set EXT_PHY_CTRL_6 [expr {$EMIF_BASE_ADDR + 0x0228}] +set EXT_PHY_CTRL_6_SHDW [expr {$EMIF_BASE_ADDR + 0x022c}] +set EXT_PHY_CTRL_7 [expr {$EMIF_BASE_ADDR + 0x0230}] +set EXT_PHY_CTRL_7_SHDW [expr {$EMIF_BASE_ADDR + 0x0234}] +set EXT_PHY_CTRL_8 [expr {$EMIF_BASE_ADDR + 0x0238}] +set EXT_PHY_CTRL_8_SHDW [expr {$EMIF_BASE_ADDR + 0x023c}] +set EXT_PHY_CTRL_9 [expr {$EMIF_BASE_ADDR + 0x0240}] +set EXT_PHY_CTRL_9_SHDW [expr {$EMIF_BASE_ADDR + 0x0244}] +set EXT_PHY_CTRL_10 [expr {$EMIF_BASE_ADDR + 0x0248}] +set EXT_PHY_CTRL_10_SHDW [expr {$EMIF_BASE_ADDR + 0x024c}] +set EXT_PHY_CTRL_11 [expr {$EMIF_BASE_ADDR + 0x0250}] +set EXT_PHY_CTRL_11_SHDW [expr {$EMIF_BASE_ADDR + 0x0254}] +set EXT_PHY_CTRL_12 [expr {$EMIF_BASE_ADDR + 0x0258}] +set EXT_PHY_CTRL_12_SHDW [expr {$EMIF_BASE_ADDR + 0x025c}] +set EXT_PHY_CTRL_13 [expr {$EMIF_BASE_ADDR + 0x0260}] +set EXT_PHY_CTRL_13_SHDW [expr {$EMIF_BASE_ADDR + 0x0264}] +set EXT_PHY_CTRL_14 [expr {$EMIF_BASE_ADDR + 0x0268}] +set EXT_PHY_CTRL_14_SHDW [expr {$EMIF_BASE_ADDR + 0x026c}] +set EXT_PHY_CTRL_15 [expr {$EMIF_BASE_ADDR + 0x0270}] +set EXT_PHY_CTRL_15_SHDW [expr {$EMIF_BASE_ADDR + 0x0274}] +set EXT_PHY_CTRL_16 [expr {$EMIF_BASE_ADDR + 0x0278}] +set EXT_PHY_CTRL_16_SHDW [expr {$EMIF_BASE_ADDR + 0x027c}] +set EXT_PHY_CTRL_17 [expr {$EMIF_BASE_ADDR + 0x0280}] +set EXT_PHY_CTRL_17_SHDW [expr {$EMIF_BASE_ADDR + 0x0284}] +set EXT_PHY_CTRL_18 [expr {$EMIF_BASE_ADDR + 0x0288}] +set EXT_PHY_CTRL_18_SHDW [expr {$EMIF_BASE_ADDR + 0x028c}] +set EXT_PHY_CTRL_19 [expr {$EMIF_BASE_ADDR + 0x0290}] +set EXT_PHY_CTRL_19_SHDW [expr {$EMIF_BASE_ADDR + 0x0294}] +set EXT_PHY_CTRL_20 [expr {$EMIF_BASE_ADDR + 0x0298}] +set EXT_PHY_CTRL_20_SHDW [expr {$EMIF_BASE_ADDR + 0x029c}] +set EXT_PHY_CTRL_21 [expr {$EMIF_BASE_ADDR + 0x02a0}] +set EXT_PHY_CTRL_21_SHDW [expr {$EMIF_BASE_ADDR + 0x02a4}] +set EXT_PHY_CTRL_22 [expr {$EMIF_BASE_ADDR + 0x02a8}] +set EXT_PHY_CTRL_22_SHDW [expr {$EMIF_BASE_ADDR + 0x02ac}] +set EXT_PHY_CTRL_23 [expr {$EMIF_BASE_ADDR + 0x02b0}] +set EXT_PHY_CTRL_23_SHDW [expr {$EMIF_BASE_ADDR + 0x02b4}] +set EXT_PHY_CTRL_24 [expr {$EMIF_BASE_ADDR + 0x02b8}] +set EXT_PHY_CTRL_24_SHDW [expr {$EMIF_BASE_ADDR + 0x02bc}] +set EXT_PHY_CTRL_25 [expr {$EMIF_BASE_ADDR + 0x02c0}] +set EXT_PHY_CTRL_25_SHDW [expr {$EMIF_BASE_ADDR + 0x02c4}] +set EXT_PHY_CTRL_26 [expr {$EMIF_BASE_ADDR + 0x02c8}] +set EXT_PHY_CTRL_26_SHDW [expr {$EMIF_BASE_ADDR + 0x02cc}] +set EXT_PHY_CTRL_27 [expr {$EMIF_BASE_ADDR + 0x02d0}] +set EXT_PHY_CTRL_27_SHDW [expr {$EMIF_BASE_ADDR + 0x02d4}] +set EXT_PHY_CTRL_28 [expr {$EMIF_BASE_ADDR + 0x02d8}] +set EXT_PHY_CTRL_28_SHDW [expr {$EMIF_BASE_ADDR + 0x02dc}] +set EXT_PHY_CTRL_29 [expr {$EMIF_BASE_ADDR + 0x02e0}] +set EXT_PHY_CTRL_29_SHDW [expr {$EMIF_BASE_ADDR + 0x02e4}] +set EXT_PHY_CTRL_30 [expr {$EMIF_BASE_ADDR + 0x02e8}] +set EXT_PHY_CTRL_30_SHDW [expr {$EMIF_BASE_ADDR + 0x02ec}] +set EXT_PHY_CTRL_31 [expr {$EMIF_BASE_ADDR + 0x02f0}] +set EXT_PHY_CTRL_31_SHDW [expr {$EMIF_BASE_ADDR + 0x02f4}] +set EXT_PHY_CTRL_32 [expr {$EMIF_BASE_ADDR + 0x02f8}] +set EXT_PHY_CTRL_32_SHDW [expr {$EMIF_BASE_ADDR + 0x02fc}] +set EXT_PHY_CTRL_33 [expr {$EMIF_BASE_ADDR + 0x0300}] +set EXT_PHY_CTRL_33_SHDW [expr {$EMIF_BASE_ADDR + 0x0304}] +set EXT_PHY_CTRL_34 [expr {$EMIF_BASE_ADDR + 0x0308}] +set EXT_PHY_CTRL_34_SHDW [expr {$EMIF_BASE_ADDR + 0x030c}] +set EXT_PHY_CTRL_35 [expr {$EMIF_BASE_ADDR + 0x0310}] +set EXT_PHY_CTRL_35_SHDW [expr {$EMIF_BASE_ADDR + 0x0314}] +set EXT_PHY_CTRL_36 [expr {$EMIF_BASE_ADDR + 0x0318}] +set EXT_PHY_CTRL_36_SHDW [expr {$EMIF_BASE_ADDR + 0x031c}] + +set WDT1_BASE_ADDR 0x44e35000 +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] + +set RTC_BASE_ADDR 0x44e3e000 +set RTC_KICK0R [expr {$RTC_BASE_ADDR + 0x6c}] +set RTC_KICK1R [expr {$RTC_BASE_ADDR + 0x70}] + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME am437x +} + +set JRC_MODULE icepick_d +set DEBUGSS_MODULE debugss +set M3_MODULE m3_wakeupss + +set JRC_NAME $_CHIPNAME.$JRC_MODULE +set DEBUGSS_NAME $_CHIPNAME.$DEBUGSS_MODULE +set M3_NAME $_CHIPNAME.$M3_MODULE +set _TARGETNAME $_CHIPNAME.mpuss + +# +# M3 WakeupSS DAP +# +if { [info exists M3_DAP_TAPID] } { + set _M3_DAP_TAPID $M3_DAP_TAPID +} else { + set _M3_DAP_TAPID 0x4b6b902f +} +jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable +jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0" +dap create $M3_NAME.dap -chain-position $M3_NAME + +# +# DebugSS DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x46b6902f +} +jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable +jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0" +dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME + +# +# ICEpick-D (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b98c02f +} +jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version +jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME" + # some TCK tycles are required to activate the DEBUG power domain +jtag configure $JRC_NAME -event post-reset "runtest 100" + +# +# Cortex-A9 target +# +target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000 + + +# SRAM: 256K at 0x4030.0000 +$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000 + +# Disables watchdog timer after reset otherwise board won't stay in +# halted state. +proc disable_watchdog { } { + global WDT1_WSPR + global WDT1_W_PEND_WSPR + global _TARGETNAME + + set curstate [$_TARGETNAME curstate] + + if { [string compare $curstate halted] == 0 } { + set WDT_DISABLE_SEQ1 0xaaaa + set WDT_DISABLE_SEQ2 0x5555 + + mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1 + + # Empty body to make sure this executes as fast as possible. + # We don't want any delays here otherwise romcode might start + # executing and end up changing state of certain IPs. + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } + + mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } + } +} + +proc ceil { x y } { + return [ expr {($x + $y - 1) / $y} ] +} + +proc device_type { } { + global CONTROL_STATUS + + set tmp [ mrw $CONTROL_STATUS ] + set tmp [ expr {$tmp & 0x700} ] + set tmp [ expr {$tmp >> 8} ] + + return $tmp +} + +proc get_input_clock_frequency { } { + global CONTROL_STATUS + + if { [ device_type ] != 3 } { + error "Unknown device type\n" + return -1 + } + + set freq [ mrw $CONTROL_STATUS ] + set freq [ expr {$freq & 0x00c00000} ] + set freq [ expr {$freq >> 22} ] + + switch $freq { + 0 { + set CLKIN 19200000 + } + + 1 { + set CLKIN 24000000 + } + + 2 { + set CLKIN 25000000 + } + + 3 { + set CLKIN 26000000 + } + } + + return $CLKIN +} + +proc mpu_pll_config { CLKIN N M M2 } { + global CM_CLKMODE_DPLL_MPU + global CM_CLKSEL_DPLL_MPU + global CM_DIV_M2_DPLL_MPU + global CM_IDLEST_DPLL_MPU + + set clksel [ mrw $CM_CLKSEL_DPLL_MPU ] + set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ] + + mww $CM_CLKMODE_DPLL_MPU 0x4 + while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { } + + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + mww $CM_CLKSEL_DPLL_MPU $clksel + + set div_m2 [ expr {$div_m2 & (~0x1f)} ] + set div_m2 [ expr {$div_m2 | $M2} ] + mww $CM_DIV_M2_DPLL_MPU $div_m2 + + mww $CM_CLKMODE_DPLL_MPU 0x7 + while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { } + + echo "MPU DPLL locked" +} + +proc core_pll_config { CLKIN N M M4 M5 M6 } { + global CM_CLKMODE_DPLL_CORE + global CM_CLKSEL_DPLL_CORE + global CM_DIV_M4_DPLL_CORE + global CM_DIV_M5_DPLL_CORE + global CM_DIV_M6_DPLL_CORE + global CM_IDLEST_DPLL_CORE + + set clksel [ mrw $CM_CLKSEL_DPLL_CORE ] + + mww $CM_CLKMODE_DPLL_CORE 0x4 + while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { } + + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + mww $CM_CLKSEL_DPLL_CORE $clksel + mww $CM_DIV_M4_DPLL_CORE $M4 + mww $CM_DIV_M5_DPLL_CORE $M5 + mww $CM_DIV_M6_DPLL_CORE $M6 + + mww $CM_CLKMODE_DPLL_CORE 0x7 + while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { } + + echo "CORE DPLL locked" +} + +proc per_pll_config { CLKIN N M M2 } { + global CM_CLKMODE_DPLL_PER + global CM_CLKSEL_DPLL_PER + global CM_DIV_M2_DPLL_PER + global CM_IDLEST_DPLL_PER + + set x [ expr {$M * $CLKIN / 1000000} ] + set y [ expr {($N + 1) * 250} ] + set sd [ ceil $x $y ] + + set clksel [ mrw $CM_CLKSEL_DPLL_PER ] + set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ] + + mww $CM_CLKMODE_DPLL_PER 0x4 + while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { } + + set clksel [ expr {$clksel & (~0xff0fffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + set clksel [ expr {$clksel | ($sd << 24)} ] + mww $CM_CLKSEL_DPLL_PER $clksel + + set div_m2 [ expr {0xffffff80 | $M2} ] + + mww $CM_CLKMODE_DPLL_PER 0x7 + while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { } + + echo "PER DPLL locked" +} + +proc ddr_pll_config { CLKIN N M M2 M4 } { + global CM_CLKMODE_DPLL_DDR + global CM_CLKSEL_DPLL_DDR + global CM_DIV_M2_DPLL_DDR + global CM_DIV_M4_DPLL_DDR + global CM_IDLEST_DPLL_DDR + + set clksel [ mrw $CM_CLKSEL_DPLL_DDR ] + set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ] + + mww $CM_CLKMODE_DPLL_DDR 0x4 + while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { } + + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 8) | $N} ] + mww $CM_CLKSEL_DPLL_DDR $clksel + + set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ] + mww $CM_DIV_M2_DPLL_DDR $div_m2 + mww $CM_DIV_M4_DPLL_DDR $M4 + + mww $CM_CLKMODE_DPLL_DDR 0x7 + while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { } + + echo "DDR DPLL Locked" +} + +proc config_opp100 { } { + set CLKIN [ get_input_clock_frequency ] + + if { $CLKIN == -1 } { + return -1 + } + + switch $CLKIN { + 24000000 { + mpu_pll_config $CLKIN 0 25 1 + core_pll_config $CLKIN 2 125 10 8 4 + per_pll_config $CLKIN 9 400 5 + ddr_pll_config $CLKIN 2 50 1 2 + } + + 25000000 { + mpu_pll_config $CLKIN 0 24 1 + core_pll_config $CLKIN 0 40 10 8 4 + per_pll_config $CLKIN 9 384 5 + ddr_pll_config $CLKIN 0 16 1 2 + } + + 26000000 { + mpu_pll_config $CLKIN 12 300 1 + core_pll_config $CLKIN 12 500 10 8 4 + per_pll_config $CLKIN 12 480 5 + ddr_pll_config $CLKIN 12 200 1 2 + } + + 19200000 { + mpu_pll_config $CLKIN 3 125 1 + core_pll_config $CLKIN 11 625 10 8 4 + per_pll_config $CLKIN 7 400 5 + ddr_pll_config $CLKIN 2 125 1 2 + } + } +} + +proc emif_prcm_clk_enable { } { + global CM_PER_EMIF_FW_CLKCTRL + global CM_PER_EMIF_CLKCTRL + + mww $CM_PER_EMIF_FW_CLKCTRL 0x02 + mww $CM_PER_EMIF_CLKCTRL 0x02 + + while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { } +} + +proc vtp_enable { } { + global VTP_CTRL_REG + + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }] + mww $VTP_CTRL_REG $vtp + + set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }] + mww $VTP_CTRL_REG $vtp + + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }] + mww $VTP_CTRL_REG $vtp + +} + +proc config_ddr_ioctrl { } { + global DDR_ADDRCTRL_IOCTRL + global DDR_ADDRCTRL_WD0_IOCTRL + global DDR_ADDRCTRL_WD1_IOCTRL + global DDR_CKE_CTRL + global DDR_DATA0_IOCTRL + global DDR_DATA1_IOCTRL + global DDR_DATA2_IOCTRL + global DDR_DATA3_IOCTRL + global DDR_IO_CTRL + + mww $DDR_ADDRCTRL_IOCTRL 0x84 + mww $DDR_ADDRCTRL_WD0_IOCTRL 0x00 + mww $DDR_ADDRCTRL_WD1_IOCTRL 0x00 + mww $DDR_DATA0_IOCTRL 0x84 + mww $DDR_DATA1_IOCTRL 0x84 + mww $DDR_DATA2_IOCTRL 0x84 + mww $DDR_DATA3_IOCTRL 0x84 + + mww $DDR_IO_CTRL 0x00 + mww $DDR_CKE_CTRL 0x03 +} + +proc config_ddr_phy { } { + global EMIF_DDR_PHY_CTRL_1 + global EMIF_DDR_PHY_CTRL_1_SHDW + + global EXT_PHY_CTRL_1 + global EXT_PHY_CTRL_1_SHDW + global EXT_PHY_CTRL_2 + global EXT_PHY_CTRL_2_SHDW + global EXT_PHY_CTRL_3 + global EXT_PHY_CTRL_3_SHDW + global EXT_PHY_CTRL_4 + global EXT_PHY_CTRL_4_SHDW + global EXT_PHY_CTRL_5 + global EXT_PHY_CTRL_5_SHDW + global EXT_PHY_CTRL_6 + global EXT_PHY_CTRL_6_SHDW + global EXT_PHY_CTRL_7 + global EXT_PHY_CTRL_7_SHDW + global EXT_PHY_CTRL_8 + global EXT_PHY_CTRL_8_SHDW + global EXT_PHY_CTRL_9 + global EXT_PHY_CTRL_9_SHDW + global EXT_PHY_CTRL_10 + global EXT_PHY_CTRL_10_SHDW + global EXT_PHY_CTRL_11 + global EXT_PHY_CTRL_11_SHDW + global EXT_PHY_CTRL_12 + global EXT_PHY_CTRL_12_SHDW + global EXT_PHY_CTRL_13 + global EXT_PHY_CTRL_13_SHDW + global EXT_PHY_CTRL_14 + global EXT_PHY_CTRL_14_SHDW + global EXT_PHY_CTRL_15 + global EXT_PHY_CTRL_15_SHDW + global EXT_PHY_CTRL_16 + global EXT_PHY_CTRL_16_SHDW + global EXT_PHY_CTRL_17 + global EXT_PHY_CTRL_17_SHDW + global EXT_PHY_CTRL_18 + global EXT_PHY_CTRL_18_SHDW + global EXT_PHY_CTRL_19 + global EXT_PHY_CTRL_19_SHDW + global EXT_PHY_CTRL_20 + global EXT_PHY_CTRL_20_SHDW + global EXT_PHY_CTRL_21 + global EXT_PHY_CTRL_21_SHDW + global EXT_PHY_CTRL_22 + global EXT_PHY_CTRL_22_SHDW + global EXT_PHY_CTRL_23 + global EXT_PHY_CTRL_23_SHDW + global EXT_PHY_CTRL_24 + global EXT_PHY_CTRL_24_SHDW + global EXT_PHY_CTRL_25 + global EXT_PHY_CTRL_25_SHDW + global EXT_PHY_CTRL_26 + global EXT_PHY_CTRL_26_SHDW + global EXT_PHY_CTRL_27 + global EXT_PHY_CTRL_27_SHDW + global EXT_PHY_CTRL_28 + global EXT_PHY_CTRL_28_SHDW + global EXT_PHY_CTRL_29 + global EXT_PHY_CTRL_29_SHDW + global EXT_PHY_CTRL_30 + global EXT_PHY_CTRL_30_SHDW + global EXT_PHY_CTRL_31 + global EXT_PHY_CTRL_31_SHDW + global EXT_PHY_CTRL_32 + global EXT_PHY_CTRL_32_SHDW + global EXT_PHY_CTRL_33 + global EXT_PHY_CTRL_33_SHDW + global EXT_PHY_CTRL_34 + global EXT_PHY_CTRL_34_SHDW + global EXT_PHY_CTRL_35 + global EXT_PHY_CTRL_35_SHDW + global EXT_PHY_CTRL_36 + global EXT_PHY_CTRL_36_SHDW + + mww $EMIF_DDR_PHY_CTRL_1 0x8009 + mww $EMIF_DDR_PHY_CTRL_1_SHDW 0x8009 + + set slave_ratio 0x80 + set gatelvl_init_ratio 0x20 + set wr_dqs_slave_delay 0x60 + set rd_dqs_slave_delay 0x60 + set dq_offset 0x40 + set gatelvl_init_mode 0x01 + set wr_data_slave_delay 0x80 + set gatelvl_num_dq0 0x0f + set wrlvl_num_dq0 0x0f + + mww $EXT_PHY_CTRL_1 [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_1_SHDW [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_26 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_26_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_31 0x00 + mww $EXT_PHY_CTRL_31_SHDW 0x00 + mww $EXT_PHY_CTRL_32 0x00 + mww $EXT_PHY_CTRL_32_SHDW 0x00 + mww $EXT_PHY_CTRL_33 0x00 + mww $EXT_PHY_CTRL_33_SHDW 0x00 + mww $EXT_PHY_CTRL_34 0x00 + mww $EXT_PHY_CTRL_34_SHDW 0x00 + mww $EXT_PHY_CTRL_35 0x00 + mww $EXT_PHY_CTRL_35_SHDW 0x00 + mww $EXT_PHY_CTRL_22 0x00 + mww $EXT_PHY_CTRL_22_SHDW 0x00 + mww $EXT_PHY_CTRL_23 [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_23_SHDW [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_24 [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ] + mww $EXT_PHY_CTRL_24_SHDW [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ] + mww $EXT_PHY_CTRL_25 [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_25_SHDW [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_36 [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] + mww $EXT_PHY_CTRL_36_SHDW [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] +} + +proc config_ddr_timing { } { + global EMIF_SDRAM_TIM_1 + global EMIF_SDRAM_TIM_2 + global EMIF_SDRAM_TIM_3 + global EMIF_SDRAM_TIM_1_SHDW + global EMIF_SDRAM_TIM_2_SHDW + global EMIF_SDRAM_TIM_3_SHDW + global EMIF_ZQ_CONFIG + + mww $EMIF_SDRAM_TIM_1 0xeaaad4db + mww $EMIF_SDRAM_TIM_1_SHDW 0xeaaad4db + + mww $EMIF_SDRAM_TIM_2 0x266b7fda + mww $EMIF_SDRAM_TIM_2_SHDW 0x266b7fda + + mww $EMIF_SDRAM_TIM_3 0x107f8678 + mww $EMIF_SDRAM_TIM_3_SHDW 0x107f8678 + + mww $EMIF_ZQ_CONFIG 0x50074be4 +} + +proc config_ddr_pm { } { + global EMIF_PWR_MGMT_CTRL + global EMIF_PWR_MGMT_CTRL_SHDW + global EMIF_DLL_CALIB_CTRL + global EMIF_DLL_CALIB_CTRL_SHDW + global EMIF_TEMP_ALERT_CONFIG + + mww $EMIF_PWR_MGMT_CTRL 0x00 + mww $EMIF_PWR_MGMT_CTRL_SHDW 0x00 + mww $EMIF_DLL_CALIB_CTRL 0x00050000 + mww $EMIF_DLL_CALIB_CTRL_SHDW 0x00050000 + mww $EMIF_TEMP_ALERT_CONFIG 0x00 +} + +proc config_ddr_priority { } { + global EMIF_PRI_COS_MAP + global EMIF_CONNID_COS_1_MAP + global EMIF_CONNID_COS_2_MAP + global EMIF_RD_WR_EXEC_THRSH + global COS_CONFIG + + mww $EMIF_PRI_COS_MAP 0x00 + mww $EMIF_CONNID_COS_1_MAP 0x00 + mww $EMIF_CONNID_COS_2_MAP 0x0 + mww $EMIF_RD_WR_EXEC_THRSH 0x0405 + mww $COS_CONFIG 0x00ffffff +} + +proc config_ddr3 { SDRAM_CONFIG } { + global CM_DLL_CTRL + global EMIF_IODFT_TLGC + global EMIF_RDWR_LVL_CTRL + global EMIF_RDWR_LVL_RMP_CTRL + global EMIF_SDRAM_CONFIG + global EMIF_SDRAM_CONFIG_EXT + global EMIF_SDRAM_REF_CTRL + global EMIF_SDRAM_REF_CTRL_SHDW + global EMIF_STATUS + global EXT_PHY_CTRL_36 + global EXT_PHY_CTRL_36_SHDW + + emif_prcm_clk_enable + vtp_enable + + set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }] + mww $CM_DLL_CTRL $dll + while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { } + + config_ddr_ioctrl + + mww $EMIF_SDRAM_CONFIG_EXT 0xc163 + mww $EMIF_IODFT_TLGC 0x2011 + mww $EMIF_IODFT_TLGC 0x2411 + mww $EMIF_IODFT_TLGC 0x2011 + mww $EMIF_SDRAM_REF_CTRL 0x80003000 + + config_ddr_phy + + mww $EMIF_IODFT_TLGC 0x2011 + mww $EMIF_IODFT_TLGC 0x2411 + mww $EMIF_IODFT_TLGC 0x2011 + + config_ddr_timing + config_ddr_pm + config_ddr_priority + + mww $EMIF_SDRAM_REF_CTRL 0x3000 + mww $EMIF_SDRAM_CONFIG $SDRAM_CONFIG + + mww $EMIF_SDRAM_REF_CTRL 0x0c30 + mww $EMIF_SDRAM_REF_CTRL_SHDW 0x0c30 + + sleep 10 + + set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }] + mww $EXT_PHY_CTRL_36 $tmp + mww $EXT_PHY_CTRL_36_SHDW $tmp + + mww $EMIF_RDWR_LVL_RMP_CTRL 0x80000000 + mww $EMIF_RDWR_LVL_CTRL 0x80000000 + + while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { } + + if { [ mrw $EMIF_STATUS ] & 0x70 } { + error "DDR3 Hardware Leveling incomplete!!!" + } +} + +proc init_platform { SDRAM_CONFIG } { + config_opp100 + config_ddr3 $SDRAM_CONFIG +} + +$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 } +$_TARGETNAME configure -event reset-end { disable_watchdog } diff --git a/openocd-win/openocd/scripts/target/amdm37x.cfg b/openocd-win/openocd/scripts/target/amdm37x.cfg new file mode 100644 index 0000000..d9adae9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/amdm37x.cfg @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Copyright (C) 2010-2011 by Karl Kurbjun +# Copyright (C) 2009-2011 by Øyvind Harboe +# Copyright (C) 2009 by David Brownell +# Copyright (C) 2009 by Magnus Lundin +# +# TI AM/DM37x Technical Reference Manual (Version R) +# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf +# +# This script is based on the AM3517 initialization. It should be considered +# preliminary since it needs more complete testing and only the basic +# operations work. +# + +############################################################################### +# User modifiable parameters +############################################################################### + +# This script uses the variable CHIPTYPE to determine whether this is an AM35x +# or DM37x target. If CHIPTYPE is not set it will error out. +if { [info exists CHIPTYPE] } { + + if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME + } else { + set _CHIPNAME $CHIPTYPE + } + + switch $CHIPTYPE { + dm37x { + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan + set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f" + } + am35x { + # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan + set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f" + } + default { + error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"." + } + } +} else { + error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration." +} + +# Run the adapter at the fastest acceptable speed with the slowest possible +# core clock. +adapter speed 10 + +############################################################################### +# JTAG setup +# The OpenOCD commands are described in the TAP Declaration section +# http://openocd.org/doc/html/TAP-Declaration.html +############################################################################### + +# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More +# can be read about this module in sprugn4r in chapter 27: "Debug and +# Emulation". The module is used to route the JTAG chain to the various +# subsystems in the chip. +source [find target/icepick.cfg] + +# The TAP order should be described from the TDO connection in OpenOCD to the +# TDI pin. The OpenOCD FAQ describes this in more detail: +# http://openocd.org/doc/html/FAQ.html + +# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO: +# +# Device | TAP number +# ---------|------------ +# DAP | 3 +# Sequencer| 2 Note: The sequencer is an ARM968 +# DSP | 1 +# D2D | 0 +# +# Right now the only secondary tap enabled is the DAP so the rest are left +# undescribed. + +###### +# Start of Chain Description +# The Secondary TAPs all have enable functions defined for use with the ICEPick +# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but +# the TAP numbers for ICEPick do not change. +# +# TODO: A disable function should also be added. +###### + +# Secondary TAP: DAP is closest to the TDO output +# The TAP enable event also needs to be described +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 3" + +# These taps are only present in the DM37x series. +if { $CHIPTYPE == "dm37x" } { + # Secondary TAP: Sequencer (ARM968) it is not in the chain by default + # The ICEPick can be used to enable it in the chain. + jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable + jtag configure $_CHIPNAME.arm2 -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 2" + + # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable) + # The ICEPick can be used to enable it in the chain. + jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable + jtag configure $_CHIPNAME.dsp -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 1" +} + +# Secondary TAP: D2D it is not in the chain by default (-disable) +# The ICEPick can be used to enable it in the chain. +# This IRLEN is probably incorrect - not sure where the documentation is. +jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable +jtag configure $_CHIPNAME.d2d -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# Primary TAP: ICEPick - it is closest to TDI so last in the chain +eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID" + +###### +# End of Chain Description +###### + +###### +# Start JTAG TAP events +###### + +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" + +# Enable the DAP TAP +jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" + +###### +# End JTAG TAP events +###### + +############################################################################### +# Target Setup: +# This section is described in the OpenOCD documentation under CPU Configuration +# http://openocd.org/doc/html/CPU-Configuration.html +############################################################################### + +# Create the CPU target to be used with GDB: Cortex-A8, using DAP +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap + +# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first +# 16K to be used as a scratchpad for OpenOCD. + +$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 + +###### +# Start Target Reset Event Setup: +###### + +# Set the JTAG clock down to 10 kHz to be sure that it will work with the +# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up +# *after* PLL and clock tree setup. + +$_TARGETNAME configure -event "reset-start" { adapter speed 10 } + +# Describe the reset assert process for openocd - this is asserted with the +# ICEPick +$_TARGETNAME configure -event "reset-assert" { + + global _CHIPNAME + + # assert warm system reset through ICEPick + icepick_c_wreset $_CHIPNAME.jrc +} + +# After the reset is asserted we need to re-initialize debugging and speed up +# the JTAG clock. + +$_TARGETNAME configure -event reset-assert-post { + + global _TARGETNAME + amdm37x_dbginit $_TARGETNAME + adapter speed 1000 +} + +$_TARGETNAME configure -event gdb-attach { + + global _TARGETNAME + amdm37x_dbginit $_TARGETNAME + + echo "Halting target" + halt +} + +###### +# End Target Reset Event Setup: +###### + +############################################################################### +# Target Functions +# Add any functions needed for the target here +############################################################################### + +# Run this to enable invasive debugging. This is run automatically in the +# reset sequence. +proc amdm37x_dbginit {target} { + # General Cortex-A8 debug initialisation + cortex_a dbginit + + # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but + # access to the signal appears to be implementation specific. TI does not + # describe this register much except a quick line that states DBGEM (sic) is + # at this address and this bit. + $target mww phys 0x5401d030 0x00002000 +} diff --git a/openocd-win/openocd/scripts/target/ampere_emag.cfg b/openocd-win/openocd/scripts/target/ampere_emag.cfg new file mode 100644 index 0000000..0b0bd9e --- /dev/null +++ b/openocd-win/openocd/scripts/target/ampere_emag.cfg @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# OpenOCD Target Configuration for eMAG ARMv8 Processor +# +# Copyright (c) 2019-2021, Ampere Computing LLC +# + +# +# Configure defaults for target +# Can be overriden in board configuration file +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME emag +} + +if { [info exists NUMCORES] } { + set _NUMCORES $NUMCORES +} else { + set _NUMCORES 32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4BA00477 +} + +# +# Configure JTAG TAP +# + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID +set _TAPNAME $_CHIPNAME.cpu + +set _DAPNAME ${_TAPNAME}_dap +set _APNUM 1 +dap create $_DAPNAME -chain-position $_TAPNAME +$_DAPNAME apsel $_APNUM + +# Create the DAP AP0 MEM-AP AHB-AP target +target create AHB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 0 + +# Create the DAP AP1 MEM-AP APB-AP target +target create APB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 1 + +# +# Configure target CPUs +# + +# Build string used to enable smp mode +set _SMP_STR "target smp" + +for {set _i 0} {$_i < $_NUMCORES} {incr _i} { + # Format a string to reference which CPU target to use + set _TARGETNAME [format "${_TAPNAME}_%02d" $_i] + + # Create and configure Cross Trigger Interface (CTI) - required for halt and resume + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}] + + # Create the target + target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i + set _SMP_STR "$_SMP_STR $_TARGETNAME" + + # Clear CTI output/input enables that are not configured by OpenOCD for aarch64 + $_TARGETNAME configure -event examine-start [subst { + $_CTINAME write INEN0 0x00000000 + $_CTINAME write INEN1 0x00000000 + $_CTINAME write INEN2 0x00000000 + $_CTINAME write INEN3 0x00000000 + $_CTINAME write INEN4 0x00000000 + $_CTINAME write INEN5 0x00000000 + $_CTINAME write INEN6 0x00000000 + $_CTINAME write INEN7 0x00000000 + $_CTINAME write INEN8 0x00000000 + + $_CTINAME write OUTEN2 0x00000000 + $_CTINAME write OUTEN3 0x00000000 + $_CTINAME write OUTEN4 0x00000000 + $_CTINAME write OUTEN5 0x00000000 + $_CTINAME write OUTEN6 0x00000000 + $_CTINAME write OUTEN7 0x00000000 + $_CTINAME write OUTEN8 0x00000000 + }] + + # Enable OpenOCD HWTHREAD RTOS feature for GDB thread (CPU) selection support + # This feature presents CPU cores ("hardware threads") in an SMP system as threads to GDB + $_TARGETNAME configure -rtos hwthread +} +eval $_SMP_STR diff --git a/openocd-win/openocd/scripts/target/ampere_qs_mq.cfg b/openocd-win/openocd/scripts/target/ampere_qs_mq.cfg new file mode 100644 index 0000000..0e83766 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ampere_qs_mq.cfg @@ -0,0 +1,333 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and +# Ampere Altra Max ("Mystique") processors +# +# Copyright (c) 2019-2022, Ampere Computing LLC + +# Command Line Argument Description +# +# SPLITSMP +# Only used for dual socket systems. Do not use for a single socket setup. +# Option pertains to the ARMv8 target core naming in a dual socket setup. +# If specified, name all ARMv8 cores per socket as individual SMP sessions. +# If not specified, name ARMv8 cores from both sockets as one SMP session. +# This option is used in conjunction with the SMP_STR board file option. +# Syntax: -c "set SPLITSMP {}" +# +# PHYS_IDX +# Enable OpenOCD ARMv8 core target physical indexing. +# If not specified, defaults to OpenOCD ARMv8 core target logical indexing. +# Syntax: -c "set PHYS_IDX {}" +# +# CHIPNAME +# Specifies the name of the chip. +# Will typically be either qs, qs0, qs1, mq, mq0 or mq1. +# If not specified, defaults to qs. +# Syntax: -c "set CHIPNAME {qs}" +# +# SYSNAME +# Specifies the name of the system. +# Will typically be either qs or mq. +# If not specified, defaults to qs. +# Syntax: -c "set SYSNAME {qs}" +# +# Life-Cycle State (LCS) +# If not specified, defaults to "Secure LCS". +# LCS=0, "Secure LCS" +# LCS=1, "Chip Manufacturing LCS" +# Syntax: -c "set LCS {0}" +# Syntax: -c "set LCS {1}" +# +# CORELIST +# Specify available physical cores by number. +# Example syntax to connect to physical cores 16 and 17. +# Syntax: -c "set CORELIST {16 17}" +# +# COREMASK_LO +# Specify available physical cores 0-63 by mask. +# Example syntax to connect to physical cores 16 and 17. +# Syntax: -c "set COREMASK_LO {0x0000000000030000}" +# +# COREMASK_HI +# Specify available physical cores 64 and above by mask. +# Example syntax to connect to physical cores 94 and 95. +# Syntax: -c "set COREMASK_HI {0x00000000C0000000}" +# +# ARMV8_TAPID +# Can override the ARMV8 TAPID default value if necessary. +# Experimental Use. Most users will not use this option. +# Syntax: -c "set ARMV8_TAPID {0x3BA06477}" +# +# SMPMPRO_TAPID +# Can override the SMPMPRO TAPID default value if necessary. +# Experimental Use. Most users will not use this option. +# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}" +# +# +# Board File Argument Description +# These optional arguments are defined in the board file and +# referenced by the target file. See the corresponding board +# files for examples of their use. +# +# SMP_STR +# This option is used primarily for a dual socket system and it is not +# recommended for a single socket setup. This option configures whether +# the SMP ARMv8 core grouping is maintained at the board or target cfg level. +# Specify the option if the SMP core grouping is defined at the board level. +# Do not specify if the SMP core grouping is defined at the chip level. +# If not specified, defaults to SMP core grouping defined per socket. +# If specified, "SMP_STR=target smp", the SMP core grouping is maintained +# at the board cfg level. +# Used in conjunction with the SPLITSMP option to group two chips into +# a single SMP configuration or maintain as two separate SMP sessions. +# +# CORE_INDEX_OFFSET +# Specifies the starting logical core index value. +# Used for dual-socket systems. +# For socket #0, set to 0. +# For socket #1, set the starting logical core based from +# the last logical core on socket #0. +# If not specified, defaults to 0. +# + +# +# Configure defaults for target. +# Can be overridden in board configuration file. +# + +if { [info exists SMP_STR] } { + # SMP configured at the dual socket board level + set _SMP_STR $SMP_STR +} else { + # SMP configured at the single socket target level + set _SMP_STR "target smp" +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME qs +} + +if { [info exists SYSNAME] } { + set _SYSNAME $SYSNAME +} else { + set _SYSNAME qs +} + +if { [info exists CORE_INDEX_OFFSET] } { + set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET +} else { + set _CORE_INDEX_OFFSET 0 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists ARMV8_TAPID] } { + set _ARMV8_TAPID $ARMV8_TAPID +} else { + if { [info exists MQ_ENABLE] } { + # Configure for Mystique + set _ARMV8_TAPID 0x3BA06477 + set _MAX_CORE 128 + } else { + # Configure for Quicksilver + set _ARMV8_TAPID 0x2BA06477 + set _MAX_CORE 80 + } +} + +if { [info exists SMPMPRO_TAPID] } { + set _SMPMPRO_TAPID $SMPMPRO_TAPID +} else { + set _SMPMPRO_TAPID 0x4BA00477 +} + +if { [info exists CORELIST] } { + set _CORELIST $CORELIST +} else { + if { [info exists COREMASK_LO] } { + set _COREMASK_LO $COREMASK_LO + } else { + set _COREMASK_LO 0x0 + } + + if { [info exists COREMASK_HI] } { + set _COREMASK_HI $COREMASK_HI + } else { + set _COREMASK_HI 0x0 + } + + set _CORELIST {} + + set _MASK 0x1 + for {set i 0} {$i < 64} {incr i} { + if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } { + set _CORELIST "$_CORELIST $i" + } + set _MASK [expr {$_MASK << 0x1}] + } + + set _MASK 0x1 + for {} {$i < $_MAX_CORE} {incr i} { + if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } { + set _CORELIST "$_CORELIST $i" + } + set _MASK [expr {$_MASK << 0x1}] + } +} + +# +# Definition of target names +# +set _TARGETNAME_PMPRO pmpro +set _TARGETNAME_SMPRO smpro +set _TARGETNAME_ARMV8 armv8 + +# +# Configure JTAG TAPs - TAP chain declaration order is important +# + +jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID +set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap + +jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID +set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap + +jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID +set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap + +set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap +set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap +set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap + +set _AP_PMPRO_AHB 0 +set _AP_SMPRO_AHB 0 +set _AP_ARMV8_APB 0x00010000 +set _AP_ARMV8_AXI 0x00020000 + +# +# Configure JTAG DAPs +# + +dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5 +dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5 +dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6 + +if { [info exists LCS] && [expr {"$LCS"!="0"}] } { + # + # Create the DAP AHB-AP MEM-AP target for the PMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB + + # + # Configure target PMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB + + # + # Create the DAP AHB-AP MEM-AP target for the SMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB + + # + # Configure target SMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB +} + +# Create the DAP APB-AP MEM-AP target for the ARMV8 cores +target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB + +# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores +target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI + +# Set CSW register value default correctly for AXI accessible device memory: +# Select the correct Access Port Number +$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI +# First set the CSW to OpenOCD's internal default +$_DAPNAME_ARMV8 apcsw default +# Set Domain[1:0]=b'11 (CSW[14:13]=b'11) +# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000) +# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'. +# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access. +$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000 + +# +# Configure target CPUs +# + +set logical_index $_CORE_INDEX_OFFSET + +foreach physical_index $_CORELIST { + if { [info exists PHYS_IDX] } { + set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}] + } + + # Format a string to reference which CPU target to use + if { [info exists SPLITSMP] } { + eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index" + } else { + eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index" + } + + # Create and configure Cross Trigger Interface (CTI) - required for halt and resume + set _CTINAME $_TARGETNAME.cti + set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}] + cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}] + + # Create the target + target create $_TARGETNAME aarch64 -endian $_ENDIAN \ + -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \ + -rtos hwthread -cti $_CTINAME -coreid $logical_index + + # Build string used to enable SMP mode for the ARMv8 CPU cores + set _SMP_STR "$_SMP_STR $_TARGETNAME" + + # Clear CTI output/input enables that are not configured by OpenOCD for aarch64 + $_TARGETNAME configure -event reset-init [subst { + $_CTINAME write INEN0 0x00000000 + $_CTINAME write INEN1 0x00000000 + $_CTINAME write INEN2 0x00000000 + $_CTINAME write INEN3 0x00000000 + $_CTINAME write INEN4 0x00000000 + $_CTINAME write INEN5 0x00000000 + $_CTINAME write INEN6 0x00000000 + $_CTINAME write INEN7 0x00000000 + $_CTINAME write INEN8 0x00000000 + + $_CTINAME write OUTEN0 0x00000000 + $_CTINAME write OUTEN1 0x00000000 + $_CTINAME write OUTEN2 0x00000000 + $_CTINAME write OUTEN3 0x00000000 + $_CTINAME write OUTEN4 0x00000000 + $_CTINAME write OUTEN5 0x00000000 + $_CTINAME write OUTEN6 0x00000000 + $_CTINAME write OUTEN7 0x00000000 + $_CTINAME write OUTEN8 0x00000000 + }] + + incr logical_index +} + +if { [info exists SMP_STR] } { + # Return updated SMP configuration string back to board level + set SMP_STR $_SMP_STR +} else { + # For single socket per SMP configuration, evaluate the string + eval $_SMP_STR +} + +if { [info exists CORE_INDEX_OFFSET] } { + # For multi-socket, return total number of cores back to board level + set CORE_INDEX_OFFSET $logical_index +} diff --git a/openocd-win/openocd/scripts/target/ar71xx.cfg b/openocd-win/openocd/scripts/target/ar71xx.cfg new file mode 100644 index 0000000..792b68f --- /dev/null +++ b/openocd-win/openocd/scripts/target/ar71xx.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Atheros AR71xx MIPS 24Kc SoC. +# tested on PB44 refererence board + +adapter srst delay 100 +jtag_ntrst_delay 100 + +reset_config trst_and_srst + +set CHIPNAME ar71xx + +jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 + +set _TARGETNAME $CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-halt-post { + #setup PLL to lowest common denominator 300/300/150 setting + mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 + mww 0xb8050000 0x800f40a3 ;# send to PLL + + #next command will reset for PLL changes to take effect + mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) +} + +$_TARGETNAME configure -event reset-init { + #complete pll initialization + mww 0xb8050000 0x800f0080 ;# set sw_update bit + mww 0xb8050008 0 ;# clear reset_switch bit + mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass + mww 0xb8050008 1 ;# set clock_switch bit + sleep 1 ;# wait for lock + + # Setup DDR config and flash mapping + mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0) + mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8) + + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb800000c 0 ;# clr ext. mode register + mww 0xb8000010 2 ;# force auto refresh all banks + mww 0xb8000010 8 ;# force precharge all banks + mww 0xb8000008 0x31 ;# set DDR mode value CAS=3 + mww 0xb8000010 1 ;# force EMRS update cycle + mww 0xb8000014 0x461b ;# DDR refresh value + mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff) + mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7) + mww 0xb8000020 0 + mww 0xb8000024 0 + mww 0xb8000028 0 +} + +# setup working area somewhere in RAM +$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 + +# serial SPI capable flash +# flash bank <driver> <base> <size> <chip_width> <bus_width> diff --git a/openocd-win/openocd/scripts/target/arm_corelink_sse200.cfg b/openocd-win/openocd/scripts/target/arm_corelink_sse200.cfg new file mode 100644 index 0000000..7327d05 --- /dev/null +++ b/openocd-win/openocd/scripts/target/arm_corelink_sse200.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs. +# + +global TARGET +set TARGET $_CHIPNAME + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# +# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB +# We will configure work area assuming 8-KB bank size in SRAM bank 1. +# Also SRAM start addresses defaults to secure mode alias. +# These values can be overridden as per board configuration +# + +global _WORKAREASIZE_CPU0 +if { [info exists WORKAREASIZE_CPU0] } { + set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0 +} else { + set _WORKAREASIZE_CPU0 0x1000 +} + +global _WORKAREAADDR_CPU0 +if { [info exists WORKAREAADDR_CPU0] } { + set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0 +} else { + set _WORKAREAADDR_CPU0 0x30008000 +} + +# +# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200 +# Core 0 is the boot core and will always be configured. +# + +target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + +${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0 + +${TARGET}.CPU0 cortex_m reset_config sysresetreq + +# +# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200 +# Core 1 is optional and locked at boot until core 0 unlocks it. +# + +if { $_ENABLE_CPU1 } { + global _WORKAREASIZE_CPU1 + if { [info exists WORKAREASIZE_CPU1] } { + set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1 + } else { + set _WORKAREASIZE_CPU1 0x1000 + } + + global _WORKAREAADDR_CPU1 + if { [info exists WORKAREAADDR_CPU1] } { + set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1 + } else { + set _WORKAREAADDR_CPU1 0x30009000 + } + + target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + + ${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0 + + ${TARGET}.CPU1 cortex_m reset_config vectreset +} + +# Make sure the default target is the boot core +targets ${TARGET}.CPU0 diff --git a/openocd-win/openocd/scripts/target/armada370.cfg b/openocd-win/openocd/scripts/target/armada370.cfg new file mode 100644 index 0000000..ccf4b36 --- /dev/null +++ b/openocd-win/openocd/scripts/target/armada370.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# armada370 -- support for the Marvell Armada/370 CPU family +# +# gerg@uclinux.org, OCT-2013 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME armada370 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap + +proc armada370_dbginit {target} { + cortex_a dbginit +} + +$_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME" + +dap apsel 1 diff --git a/openocd-win/openocd/scripts/target/at32ap7000.cfg b/openocd-win/openocd/scripts/target/at32ap7000.cfg new file mode 100644 index 0000000..bbae247 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at32ap7000.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Atmel AT32AP7000 +# +# This is the only core in the now-inactive high end AVR32 product line, +# with MMU, Java Acceleration, and "pixel coprocessor". The AP7 line +# is for "Application Processors" (AP) with 7-stage pipelines. +# +# Most current AVR32 parts are in the UC3 flash based microcontroller (UC) +# product line with 3-stage pipelines and without those extras. +# +# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces +# through their JTAG interfaces. + +jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f + +# REVISIT declare an avr32 target ... needs OpenOCD infrastructure +# for both Nexus (generic) and AVR32 (Atmel-specific). diff --git a/openocd-win/openocd/scripts/target/at91r40008.cfg b/openocd-win/openocd/scripts/target/at91r40008.cfg new file mode 100644 index 0000000..66d32ae --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91r40008.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# AT91R40008 target configuration file + +# TRST is tied to SRST on the AT91X40 family. +reset_config srst_only srst_pulls_trst + + +if {[info exists CHIPNAME]} { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91r40008 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Setup the JTAG scan chain. +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f0f0f0f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/at91rm9200.cfg b/openocd-win/openocd/scripts/target/at91rm9200.cfg new file mode 100644 index 0000000..1bc1287 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91rm9200.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Atmel AT91rm9200 +# http://atmel.com/products/at91/ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91rm9200 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x05b0203f +} + +# Never allow the following! +if { $_CPUTAPID == 0x15b0203f } { + echo "-------------------------------------------------------" + echo "- ERROR: -" + echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -" + echo "- ERROR: The chip/board has a JTAG select pin/jumper -" + echo "- ERROR: -" + echo "- ERROR: In one position (0x05b0203f) it selects the -" + echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -" + echo "- ERROR: it selects boundary-scan not the ARM -" + echo "- ERROR: -" + echo "-------------------------------------------------------" +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME + +# AT91RM9200 has a 16K block of sram @ 0x0020.0000 +$_TARGETNAME configure -work-area-phys 0x00200000 \ + -work-area-size 0x4000 -work-area-backup 1 + +# This chip has a DCC ... use it +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/at91sam3XXX.cfg b/openocd-win/openocd/scripts/target/at91sam3XXX.cfg new file mode 100644 index 0000000..ba1c3c5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3XXX.cfg @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam3, a Cortex-M3 chip +# +# at91sam3u4e +# at91sam3u2e +# at91sam3u1e +# at91sam3u4c +# at91sam3u2c +# at91sam3u1c +# +# at91sam3s4c +# at91sam3s4b +# at91sam3s4a +# at91sam3s2c +# at91sam3s2b +# at91sam3s2a +# at91sam3s1c +# at91sam3s1b +# at91sam3s1a +# +# at91sam3A4C +# at91sam3A8C +# at91sam3X4C +# at91sam3X4E +# at91sam3X8C +# at91sam3X8E +# at91sam3X8H + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam3 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +# 16K is plenty, the smallest chip has this much +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +$_TARGETNAME configure -event gdb-flash-erase-start { + halt +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. + +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/at91sam3ax_4x.cfg b/openocd-win/openocd/scripts/target/at91sam3ax_4x.cfg new file mode 100644 index 0000000..4e0cf79 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3ax_4x.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3ax_xx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME +# This is a 256K chip - it has the 2nd bank +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3ax_8x.cfg b/openocd-win/openocd/scripts/target/at91sam3ax_8x.cfg new file mode 100644 index 0000000..46d580d --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3ax_8x.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3ax_xx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME +# This is a 512K chip - it has the 2nd bank +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3ax_xx.cfg b/openocd-win/openocd/scripts/target/at91sam3ax_xx.cfg new file mode 100644 index 0000000..7837f69 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3ax_xx.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam3, a Cortex-M3 chip +# +# at91sam3A4C +# at91sam3A8C +# at91sam3X4C +# at91sam3X4E +# at91sam3X8C +# at91sam3X8E +# at91sam3X8H +source [find target/at91sam3XXX.cfg] diff --git a/openocd-win/openocd/scripts/target/at91sam3nXX.cfg b/openocd-win/openocd/scripts/target/at91sam3nXX.cfg new file mode 100644 index 0000000..9b20373 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3nXX.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration for Atmel's SAM3N series +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91sam3n +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +set _FLASHNAME $_CHIPNAME.flash +flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/at91sam3sXX.cfg b/openocd-win/openocd/scripts/target/at91sam3sXX.cfg new file mode 100644 index 0000000..a2afda2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3sXX.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam3, a Cortex-M3 chip +# +# at91sam3s4c +# at91sam3s4b +# at91sam3s4a +# at91sam3s2c +# at91sam3s2b +# at91sam3s2a +# at91sam3s1c +# at91sam3s1b +# at91sam3s1a + +source [find target/at91sam3XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u1c.cfg b/openocd-win/openocd/scripts/target/at91sam3u1c.cfg new file mode 100644 index 0000000..b26662b --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u1c.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u1e.cfg b/openocd-win/openocd/scripts/target/at91sam3u1e.cfg new file mode 100644 index 0000000..b26662b --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u1e.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u2c.cfg b/openocd-win/openocd/scripts/target/at91sam3u2c.cfg new file mode 100644 index 0000000..b26662b --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u2c.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u2e.cfg b/openocd-win/openocd/scripts/target/at91sam3u2e.cfg new file mode 100644 index 0000000..b26662b --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u2e.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u4c.cfg b/openocd-win/openocd/scripts/target/at91sam3u4c.cfg new file mode 100644 index 0000000..fb1eeaa --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u4c.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME +# This is a 256K chip, it has the 2nd bank +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3u4e.cfg b/openocd-win/openocd/scripts/target/at91sam3u4e.cfg new file mode 100644 index 0000000..1c75f82 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3u4e.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common stuff +source [find target/at91sam3uxx.cfg] + +# size is automatically "calculated" by probing +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME +# This is a 256K chip - it has the 2nd bank +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam3uxx.cfg b/openocd-win/openocd/scripts/target/at91sam3uxx.cfg new file mode 100644 index 0000000..f084b9b --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam3uxx.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam3, a Cortex-M3 chip +# +# at91sam3u4e +# at91sam3u2e +# at91sam3u1e +# at91sam3u4c +# at91sam3u2c +# at91sam3u1c + +source [find target/at91sam3XXX.cfg] diff --git a/openocd-win/openocd/scripts/target/at91sam4XXX.cfg b/openocd-win/openocd/scripts/target/at91sam4XXX.cfg new file mode 100644 index 0000000..9c30ddf --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4XXX.cfg @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# script for ATMEL sam4, a Cortex-M4 chip +# + +# +# sam4 devices can support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam4 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +# 16K is plenty, the smallest chip has this much +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. + +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/at91sam4c32x.cfg b/openocd-win/openocd/scripts/target/at91sam4c32x.cfg new file mode 100644 index 0000000..ddcdd12 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4c32x.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam4c32, a Cortex-M4 chip +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam4 0x01100000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam4cXXX.cfg b/openocd-win/openocd/scripts/target/at91sam4cXXX.cfg new file mode 100644 index 0000000..a0206ad --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4cXXX.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam4c, a Cortex-M4 chip +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam4lXX.cfg b/openocd-win/openocd/scripts/target/at91sam4lXX.cfg new file mode 100644 index 0000000..0910e30 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4lXX.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam4l, a Cortex-M4 chip +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME + +# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N +# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3). +# +# smap_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the SMAP to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert" + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed. +# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio. +# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2 +# but your mileage may vary. +adapter speed 50 + +# System RC oscillator RCSYS starts in 3 cycles +adapter srst delay 0 diff --git a/openocd-win/openocd/scripts/target/at91sam4sXX.cfg b/openocd-win/openocd/scripts/target/at91sam4sXX.cfg new file mode 100644 index 0000000..2ceca00 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4sXX.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam4, a Cortex-M4 chip +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam4sd32x.cfg b/openocd-win/openocd/scripts/target/at91sam4sd32x.cfg new file mode 100644 index 0000000..24e25e3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam4sd32x.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for ATMEL sam4sd32, a Cortex-M4 chip +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam7a2.cfg b/openocd-win/openocd/scripts/target/at91sam7a2.cfg new file mode 100644 index 0000000..f8090c7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam7a2.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91sam7a2 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam7se512.cfg b/openocd-win/openocd/scripts/target/at91sam7se512.cfg new file mode 100644 index 0000000..2972494 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam7se512.cfg @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ATMEL sam7se512 +# Example: the "Elektor Internet Radio" - EIR +# http://www.ethernut.de/en/hardware/eir/index.html + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7se512 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Force an error until we get a good number. + set _CPUTAPID 0xffffffff +} + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# The target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/openocd-win/openocd/scripts/target/at91sam7sx.cfg b/openocd-win/openocd/scripts/target/at91sam7sx.cfg new file mode 100644 index 0000000..fee4e9a --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam7sx.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91sam7s +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -event reset-init { + soft_reset_halt + # RSTC_CR : Reset peripherals + mww 0xfffffd00 0xa5000004 + # disable watchdog + mww 0xfffffd44 0x00008000 + # enable user reset + mww 0xfffffd08 0xa5000001 + # CKGR_MOR : enable the main oscillator + mww 0xfffffc20 0x00000601 + sleep 10 + # CKGR_PLLR: 96.1097 MHz + mww 0xfffffc2c 0x00481c0e + sleep 10 + # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz + mww 0xfffffc30 0x00000007 + sleep 10 + # MC_FMR: flash mode (FWS=1,FMCN=73) + mww 0xffffff60 0x00490100 + sleep 100 +} + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/openocd-win/openocd/scripts/target/at91sam7x256.cfg b/openocd-win/openocd/scripts/target/at91sam7x256.cfg new file mode 100644 index 0000000..2ebbf22 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam7x256.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7x256 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-init { + # disable watchdog + mww 0xfffffd44 0x00008000 + # enable user reset + mww 0xfffffd08 0xa5000001 + # CKGR_MOR : enable the main oscillator + mww 0xfffffc20 0x00000601 + sleep 10 + # CKGR_PLLR: 96.1097 MHz + mww 0xfffffc2c 0x00481c0e + sleep 10 + # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz + mww 0xfffffc30 0x00000007 + sleep 10 + # MC_FMR: flash mode (FWS=1,FMCN=60) + mww 0xffffff60 0x003c0100 + sleep 100 +} + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 diff --git a/openocd-win/openocd/scripts/target/at91sam7x512.cfg b/openocd-win/openocd/scripts/target/at91sam7x512.cfg new file mode 100644 index 0000000..ccdcfa7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam7x512.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7x512 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-init { + # disable watchdog + mww 0xfffffd44 0x00008000 + # enable user reset + mww 0xfffffd08 0xa5000001 + # CKGR_MOR : enable the main oscillator + mww 0xfffffc20 0x00000601 + sleep 10 + # CKGR_PLLR: 96.1097 MHz + mww 0xfffffc2c 0x00481c0e + sleep 10 + # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz + mww 0xfffffc30 0x00000007 + sleep 10 + # MC_FMR: flash mode (FWS=1,FMCN=60) + mww 0xffffff60 0x003c0100 + sleep 100 +} + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 +flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432 diff --git a/openocd-win/openocd/scripts/target/at91sam9.cfg b/openocd-win/openocd/scripts/target/at91sam9.cfg new file mode 100644 index 0000000..bc90d37 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9 +###################################### + +if { [info exists AT91_CHIPNAME] } { + set _CHIPNAME $AT91_CHIPNAME +} else { + error "you must specify a chip name" +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0792603f +} + +reset_config trst_and_srst separate trst_push_pull srst_open_drain + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +adapter srst delay 300 +jtag_ntrst_delay 200 + +adapter speed 3 + +###################### +# Target configuration +###################### + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91sam9260.cfg b/openocd-win/openocd/scripts/target/at91sam9260.cfg new file mode 100644 index 0000000..3f74d96 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9260.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9260 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9260 +} + +source [find target/at91sam9.cfg] + + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. +# Both areas are 4 kB long. + +#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1 +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg b/openocd-win/openocd/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg new file mode 100644 index 0000000..47117e9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9260 +###################################### + +source [find target/at91sam9261.cfg] + +reset_config trst_and_srst + +adapter speed 4 + +adapter srst delay 200 +jtag_ntrst_delay 200 + +scan_chain +$_TARGETNAME configure -event reset-start { + # at reset chip runs at 32khz + adapter speed 8 +} + +$_TARGETNAME configure -event reset-init {at91sam_init} + +# Flash configuration +#flash bank <name> cfi <base> <size> <chip width> <bus width> <target> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME + +# Faster memory downloads. This is disabled automatically during +# reset init since all reset init sequences are too short for +# fast memory access +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + +proc at91sam_init { } { + mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset + mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog + + mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator + sleep 10 ;# wait 10 ms + mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz + sleep 20 ;# wait 20 ms + mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler + sleep 10 ;# wait 10 ms + mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected + sleep 10 ;# wait 10 ms + + # Now run at anything fast... ie: 10mhz! + adapter speed 10000 ;# Increase JTAG Speed to 6 MHz + + mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit + mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0 + mww 0xffffec08 0x00160016 ;# SMC_CYCLE0 + mww 0xffffec0c 0x00161003 ;# SMC_MODE0 + + mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31 + mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 + + mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM + + mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) + #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) + + mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command + mww 0x20000000 0 + mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command + mww 0x20000000 0 + mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x4 + mww 0x20000000 0 + mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command + mww 0x20000000 0 + mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode + mww 0x20000000 0 + mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us +} diff --git a/openocd-win/openocd/scripts/target/at91sam9261.cfg b/openocd-win/openocd/scripts/target/at91sam9261.cfg new file mode 100644 index 0000000..07456b2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9261.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9261 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9261 +} + +source [find target/at91sam9.cfg] + +# Internal sram1 memory +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9263.cfg b/openocd-win/openocd/scripts/target/at91sam9263.cfg new file mode 100644 index 0000000..3e2585c --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9263.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9263 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9263 +} + +source [find target/at91sam9.cfg] + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9263 has two SRAM areas, +# one starting at 0x00300000 of 80KiB +# and the other starting at 0x00500000 of 16KiB. + +# Internal sram1 memory +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1 +#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9g10.cfg b/openocd-win/openocd/scripts/target/at91sam9g10.cfg new file mode 100644 index 0000000..6836773 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9g10.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9G10 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9g10 +} + +source [find target/at91sam9.cfg] + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB + +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9g20.cfg b/openocd-win/openocd/scripts/target/at91sam9g20.cfg new file mode 100644 index 0000000..4fc2048 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9g20.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9G20 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9g20 +} + +source [find target/at91sam9.cfg] + +# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock). + +adapter speed 5 + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. +# Both areas are 16 kB long. + +#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9g45.cfg b/openocd-win/openocd/scripts/target/at91sam9g45.cfg new file mode 100644 index 0000000..5e6e818 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9g45.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9G45 +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9g45 +} + +source [find target/at91sam9.cfg] + +# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The +# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB. + +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sam9rl.cfg b/openocd-win/openocd/scripts/target/at91sam9rl.cfg new file mode 100644 index 0000000..b253427 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sam9rl.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Atmel AT91SAM9RL +###################################### + +if { [info exists CHIPNAME] } { + set AT91_CHIPNAME $CHIPNAME +} else { + set AT91_CHIPNAME at91sam9rl +} + +source [find target/at91sam9.cfg] + +# Internal sram1 memory +$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/at91sama5d2.cfg b/openocd-win/openocd/scripts/target/at91sama5d2.cfg new file mode 100644 index 0000000..65e5217 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91sama5d2.cfg @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# The JTAG connection is disabled at reset, and during the ROM Code execution. +# It is re-enabled when the ROM code jumps in the boot file copied from an +# external Flash memory into the internalSRAM, or when the ROM code launches +# the SAM-BA monitor, when no boot file has been found in any external Flash +# memory. +# For more JTAG related information see, : +# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf +# +# If JTAGSEL pin: +# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F. +# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91sama5d2 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id 0x5ba00477 + +# Cortex-A5 target +set _TARGETNAME $_CHIPNAME.cpu_a5 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap diff --git a/openocd-win/openocd/scripts/target/at91samdXX.cfg b/openocd-win/openocd/scripts/target/at91samdXX.cfg new file mode 100644 index 0000000..5132109 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91samdXX.cfg @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip +# + +# +# samdXX devices only support SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91samd +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N +# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2) +# +# dsu_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the DSU to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post { + at91samd dsu_reset_deassert +} + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# Do not use a reset button with other SWD adapter than Atmel's EDBG. +# DSU usually locks MCU in reset state until you issue a reset command +# in OpenOCD. + +# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset. +# Other members of family usually use SYSCLK = 4 MHz after reset. +# Datasheet does not specify SYSCLK to SWD clock ratio. +# Usually used SYSCLK/6 is slow, testing shows that debugging can +# work @ SYSCLK/2 but your mileage may vary. +# This limit is most probably imposed by incorrectly handled SWD WAIT +# on some SWD adapters. + +adapter speed 400 + +# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works +# without problem at maximal clock speed. Atmel recommends +# adapter speed less than 10 * CPU clock. +# adapter speed 5000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/at91samg5x.cfg b/openocd-win/openocd/scripts/target/at91samg5x.cfg new file mode 100644 index 0000000..cbe25f6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/at91samg5x.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for the ATMEL samg5x Cortex-M4F chip family +# + +source [find target/at91sam4XXX.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atheros_ar2313.cfg b/openocd-win/openocd/scripts/target/atheros_ar2313.cfg new file mode 100644 index 0000000..aa962b4 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atheros_ar2313.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ar2313 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00000001 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atheros_ar2315.cfg b/openocd-win/openocd/scripts/target/atheros_ar2315.cfg new file mode 100644 index 0000000..3836763 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atheros_ar2315.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ar2315 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00000001 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atheros_ar9331.cfg b/openocd-win/openocd/scripts/target/atheros_ar9331.cfg new file mode 100644 index 0000000..931ac10 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atheros_ar9331.cfg @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Atheros AR9331 is a highly integrated and cost effective +# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless +# local area network (WLAN) AP and router platforms. +# +# Notes: +# - MIPS Processor ID (PRId): 0x00019374 +# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, +# operating at up to 400 MHz +# - External 16-bit DDR1, DDR2, or SDRAM memory interface +# - TRST is not available. +# - EJTAG PrRst signal is not supported +# - RESET_L pin A72 on the SoC will reset internal JTAG logic. +# + +# Pins related for debug and bootstrap: +# Name Pin Description +# JTAG +# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG +# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG +# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG +# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG +# Reset +# RESET_L -, (A72) Input only +# SYS_RST_L ???????? Output reset request or GPIO +# Bootstrap +# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM +# MEM_TYPE[0] GPIO12, (A56) +# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB +# 1 - boot from MDIO. +# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG +# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot +# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz +# UART +# UART0_SOUT GPIO10, (A79) +# UART0_SIN GPIO9, (B68) + +# Per default we need to use "none" variant to be able properly "reset init" +# or "reset halt" the CPU. +reset_config none srst_pulls_trst + +# For SRST based variant we still need proper timings. +# For ETH part the reset should be asserted at least for 10ms +# Since there is no other information let's take 100ms to be sure. +adapter srst pulse_width 100 + +# according to the SoC documentation it should take at least 5ms from +# reset end till bootstrap end. In the practice we need 8ms to get JTAG back +# to live. +adapter srst delay 8 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ar9331 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +# provide watchdog helper. +proc disable_watchdog { } { + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event halted { disable_watchdog } + +# Since PrRst is not supported and SRST will reset complete chip +# with JTAG engine, we need to reset CPU from CPU itself. +$_TARGETNAME configure -event reset-assert-pre { + halt +} + +$_TARGETNAME configure -event reset-assert { + catch "mww 0xb806001C 0x01000000" +} + +# To be able to trigger complete chip reset, in case JTAG is blocked +# or CPU not responding, we still can use this helper. +proc full_reset { } { + reset_config srst_only + reset + halt + reset_config none +} + +proc disable_watchdog { } { + ;# disable watchdog + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event reset-end { disable_watchdog } + +# Section with helpers which can be used by boards +proc ar9331_25mhz_pll_init {} { + mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4 + mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850) + mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL + ;# OUTDIV | REFDIV | DIV_INT + mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register + ;# (disabled?) + mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT + mww 0xb8050008 0x00008000 ;# remove bypass; + ;# AHB_POST_DIV - ratio 2 +} + +proc ar9331_ddr1_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle + mww 0xb8000008 0x133 ;# mode reg: 0x133 - default + mww 0xb8000010 0x1 ;# Forces an MRS update cycl + mww 0xb800000c 0x2 ;# Extended mode register value. + ;# default 0x2 - Reset to weak driver, DLL on + mww 0xb8000010 0x2 ;# Forces an EMRS update cycle + mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle + mww 0xb8000008 0x33 ;# mode reg: remove some bit? + mww 0xb8000010 0x1 ;# Forces an MRS update cycl + mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate + mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0, + ;# DQ[7:0], DQS_0 + mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1, + ;# DQ[15:8], DQS_1. + mww 0xb8000018 0xff ;# DDR read and capture bit mask. + ;# Each bit represents a cycle of valid data. +} + +proc ar9331_ddr2_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb800008c 0x00000a59 + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000090 0x00000000 + mww 0xb8000010 0x00000010 ;# EMR2S update cycle + + mww 0xb8000094 0x00000000 + mww 0xb8000010 0x00000020 ;# EMR3S update cycle + + mww 0xb800000c 0x00000000 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000008 0x00000100 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000010 0x00000004 + mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle + + mww 0xb8000008 0x00000a33 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb800000c 0x00000382 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb800000c 0x00000402 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000014 0x00004186 ;# DDR_REFRESH + mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0 + mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1 + + ;# DDR read and capture bit mask. + ;# Each bit represents a cycle of valid data. + ;# 0xff: use 16-bit DDR + mww 0xb8000018 0x000000ff +} diff --git a/openocd-win/openocd/scripts/target/atheros_ar9344.cfg b/openocd-win/openocd/scripts/target/atheros_ar9344.cfg new file mode 100644 index 0000000..d22bb5f --- /dev/null +++ b/openocd-win/openocd/scripts/target/atheros_ar9344.cfg @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME ar9344 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00000001 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +proc test_ar9344_uart0_tx {} { + echo "configuring uart0.." + mww 0xb802000c 0x87 + mww 0xb8020000 0x15 + mww 0xb8020004 0 + mww 0xb802000c 7 + mww 0xb8020004 0 + + echo "send message: hallo world" + mww 0xb8020000 0x68 + mww 0xb8020000 0x65 + mww 0xb8020000 0x6c + mww 0xb8020000 0x6c + mww 0xb8020000 0x6f + mww 0xb8020000 0x20 + mww 0xb8020000 0x77 + mww 0xb8020000 0x6f + mww 0xb8020000 0x72 + mww 0xb8020000 0x6c + mww 0xb8020000 0x64 + mww 0xb8020000 0x0a +} diff --git a/openocd-win/openocd/scripts/target/atmega128.cfg b/openocd-win/openocd/scripts/target/atmega128.cfg new file mode 100644 index 0000000..c946919 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atmega128.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# for avr + + set _CHIPNAME avr + set _ENDIAN little + +# jtag speed +adapter speed 4500 + +reset_config srst_only +adapter srst delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x8970203F +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME + +#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME + +#to use it, script will be like: +#init +#adapter speed 4500 +#reset init +#verify_ircapture disable +# +#halt +#wait halt +#poll +#avr mass_erase 0 +#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex +#reset run +#shutdown diff --git a/openocd-win/openocd/scripts/target/atmega128rfa1.cfg b/openocd-win/openocd/scripts/target/atmega128rfa1.cfg new file mode 100644 index 0000000..96a83fe --- /dev/null +++ b/openocd-win/openocd/scripts/target/atmega128rfa1.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME avr +set _ENDIAN little + +# jtag speed +adapter speed 4500 + +# avr jtag docs never connect RSTN +reset_config none + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0a70103f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atmega32u4.cfg b/openocd-win/openocd/scripts/target/atmega32u4.cfg new file mode 100644 index 0000000..9199c74 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atmega32u4.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# ATmega32U4 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME avr +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4958703f +} + +adapter speed 4500 + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atsame5x.cfg b/openocd-win/openocd/scripts/target/atsame5x.cfg new file mode 100644 index 0000000..5093d41 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atsame5x.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices +# with a Cortex-M4 core +# + +# +# Devices only support SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME atsame5 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB (the smallest RAM size is 128kB) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# SAM DSU will hold the CPU in reset if TCK is low when RESET_N +# deasserts +# +# dsu_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the DSU to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post { + atsame5 dsu_reset_deassert +} + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# Do not use a reset button with other SWD adapter than Atmel's EDBG. +# DSU usually locks MCU in reset state until you issue a reset command +# in OpenOCD. + +# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset. +# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works +# without problem at clock speed over 5000 khz. Atmel recommends +# adapter speed less than 10 * CPU clock. +adapter speed 2000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/atsaml1x.cfg b/openocd-win/openocd/scripts/target/atsaml1x.cfg new file mode 100644 index 0000000..5a1b8f8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atsaml1x.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Microchip (formerly Atmel) SAM L1x target +# +# Note: These devices support SWD only. +# + +transport select swd + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME saml1x +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +swd newdap $_CHIPNAME cpu -expected-id 0x0bf11477 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/atsamv.cfg b/openocd-win/openocd/scripts/target/atsamv.cfg new file mode 100644 index 0000000..7e9f6c5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/atsamv.cfg @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts +# The chips are very similar; the SAMV series just has +# more peripherals and seems like the "flagship" of the +# family. This script will work for all of them. + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME samv +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bd11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +adapter speed 1800 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/avr32.cfg b/openocd-win/openocd/scripts/target/avr32.cfg new file mode 100644 index 0000000..e16d114 --- /dev/null +++ b/openocd-win/openocd/scripts/target/avr32.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME avr32 +set _ENDIAN big + +set _CPUTAPID 0x21e8203f + +adapter srst delay 100 +jtag_ntrst_delay 100 + +reset_config trst_and_srst separate + +# jtag scan chain +# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/bcm2711.cfg b/openocd-win/openocd/scripts/target/bcm2711.cfg new file mode 100644 index 0000000..f8d2b3a --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm2711.cfg @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Broadcom BCM2711 used in Raspberry Pi 4 +# No documentation was found on Broadcom website + +# Partial information is available in raspberry pi website: +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bcm2711 +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +if { [info exists USE_SMP] } { + set _USE_SMP $USE_SMP +} else { + set _USE_SMP 0 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 +adapter speed 4000 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# MEM-AP for direct access +target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# these addresses are obtained from the ROM table via 'dap info 0' command +set _DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +set _smp_command "target smp" + +for { set _core 0 } { $_core < $_cores } { incr _core } { + set _CTINAME $_CHIPNAME.cti$_core + set _TARGETNAME $_CHIPNAME.cpu$_core + + cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core] + target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME + + set _smp_command "$_smp_command $_TARGETNAME" +} + +if {$_USE_SMP} { + eval $_smp_command +} + +# default target is cpu0 +targets $_CHIPNAME.cpu0 diff --git a/openocd-win/openocd/scripts/target/bcm281xx.cfg b/openocd-win/openocd/scripts/target/bcm281xx.cfg new file mode 100644 index 0000000..a70a9c5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm281xx.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BCM281xx + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bcm281xx +} + + +# Main CPU DAP +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 + + +# Dual Cortex-A9 +set _TARGETNAME0 $_CHIPNAME.cpu0 +set _TARGETNAME1 $_CHIPNAME.cpu1 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000 +target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000 +target smp $_TARGETNAME0 $_TARGETNAME1 diff --git a/openocd-win/openocd/scripts/target/bcm2835.cfg b/openocd-win/openocd/scripts/target/bcm2835.cfg new file mode 100644 index 0000000..32a0366 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm2835.cfg @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Broadcom chip used in the Raspberry Pi Model A, B, B+, +# the Compute Module, and the Raspberry Pi Zero. + +# Partial information is available in raspberry pi website: +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bcm2835 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x07b7617F +} + +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 5 +adapter speed 4000 + +target create $_CHIPNAME.cpu0 arm11 -chain-position $_CHIPNAME.cpu diff --git a/openocd-win/openocd/scripts/target/bcm2836.cfg b/openocd-win/openocd/scripts/target/bcm2836.cfg new file mode 100644 index 0000000..0492131 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm2836.cfg @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The Broadcom chip used in the Raspberry Pi 2 Model B + +# Partial information is available in raspberry pi website: +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bcm2836 +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +if { [info exists USE_SMP] } { + set _USE_SMP $USE_SMP +} else { + set _USE_SMP 0 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 +adapter speed 4000 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# MEM-AP for direct access +target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# these addresses are obtained from the ROM table via 'dap info 0' command +set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000} + +set _smp_command "target smp" + +for { set _core 0 } { $_core < $_cores } { incr _core } { + set _TARGETNAME $_CHIPNAME.cpu$_core + + target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -coreid $_core -dbgbase [lindex $_DBGBASE $_core] + $_TARGETNAME configure -event reset-assert-post { cortex_a dbginit } + + set _smp_command "$_smp_command $_CHIPNAME.cpu$_core" +} + +if {$_USE_SMP} { + eval $_smp_command +} + +# default target is cpu0 +targets $_CHIPNAME.cpu0 diff --git a/openocd-win/openocd/scripts/target/bcm2837.cfg b/openocd-win/openocd/scripts/target/bcm2837.cfg new file mode 100644 index 0000000..749de31 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm2837.cfg @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is the Broadcom chip used in the Raspberry Pi 3, +# and in later models of the Raspberry Pi 2. + +# Partial information is available in raspberry pi website: +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837 +# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bcm2837 +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +if { [info exists USE_SMP] } { + set _USE_SMP $USE_SMP +} else { + set _USE_SMP 0 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4 +adapter speed 4000 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# MEM-AP for direct access +target create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# these addresses are obtained from the ROM table via 'dap info 0' command +set _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000} +set _CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000} + +set _smp_command "target smp" + +for { set _core 0 } { $_core < $_cores } { incr _core } { + set _CTINAME $_CHIPNAME.cti$_core + set _TARGETNAME $_CHIPNAME.cpu$_core + + cti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core] + target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME + $_TARGETNAME configure -event reset-assert-post { aarch64 dbginit } + + set _smp_command "$_smp_command $_TARGETNAME" +} + +if {$_USE_SMP} { + eval $_smp_command +} + +# default target is cpu0 +targets $_CHIPNAME.cpu0 diff --git a/openocd-win/openocd/scripts/target/bcm4706.cfg b/openocd-win/openocd/scripts/target/bcm4706.cfg new file mode 100644 index 0000000..e5d8d19 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm4706.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME bcm4706 +set _CPUID 0x1008c17f + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/bcm4718.cfg b/openocd-win/openocd/scripts/target/bcm4718.cfg new file mode 100644 index 0000000..cc21a5e --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm4718.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME bcm4718 +set _LVTAPID 0x1471617f +set _CPUID 0x0008c17f + +source [find target/bcm47xx.cfg] diff --git a/openocd-win/openocd/scripts/target/bcm47xx.cfg b/openocd-win/openocd/scripts/target/bcm47xx.cfg new file mode 100644 index 0000000..b5365e0 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm47xx.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed" +reset_config none + +jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID +jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu" +jtag configure $_CHIPNAME-lv.tap -event tap-disable {} + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag" + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME + +proc switch_lv_to_ejtag {} { + global _CHIPNAME + poll 0 + irscan $_CHIPNAME-lv.tap 0x143ff3a + drscan $_CHIPNAME-lv.tap 32 1 + jtag tapdisable $_CHIPNAME-lv.tap + poll 1 +} diff --git a/openocd-win/openocd/scripts/target/bcm5352e.cfg b/openocd-win/openocd/scripts/target/bcm5352e.cfg new file mode 100644 index 0000000..084ce04 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm5352e.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME bcm5352e +set _CPUID 0x0535217f + +jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/bcm6348.cfg b/openocd-win/openocd/scripts/target/bcm6348.cfg new file mode 100644 index 0000000..b9d4448 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bcm6348.cfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _CHIPNAME bcm6348 +set _CPUID 0x0634817f + +adapter speed 1000 + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/bluefield.cfg b/openocd-win/openocd/scripts/target/bluefield.cfg new file mode 100644 index 0000000..30ed527 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bluefield.cfg @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# BlueField SoC Target + +set _CHIPNAME bluefield + +# Specify the target device +#rshim device /dev/rshim0/rshim + +# Main DAP +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +adapter speed 1500 + +swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Initialize the target name and command variable. +set _TARGETNAME $_CHIPNAME.cpu +set _smp_command "" + +# CTI relative address +set $_TARGETNAME.cti(0) 0xC4020000 +set $_TARGETNAME.cti(1) 0xC4120000 +set $_TARGETNAME.cti(2) 0xC8020000 +set $_TARGETNAME.cti(3) 0xC8120000 +set $_TARGETNAME.cti(4) 0xCC020000 +set $_TARGETNAME.cti(5) 0xCC120000 +set $_TARGETNAME.cti(6) 0xD0020000 +set $_TARGETNAME.cti(7) 0xD0120000 +set $_TARGETNAME.cti(8) 0xD4020000 +set $_TARGETNAME.cti(9) 0xD4120000 +set $_TARGETNAME.cti(10) 0xD8020000 +set $_TARGETNAME.cti(11) 0xD8120000 +set $_TARGETNAME.cti(12) 0xDC020000 +set $_TARGETNAME.cti(13) 0xDC120000 +set $_TARGETNAME.cti(14) 0xE0020000 +set $_TARGETNAME.cti(15) 0xE0120000 + +# Create debug targets for a number of cores starting from core '_core_start'. +# Adjust the numbers according to board configuration. +set _core_start 0 +set _cores 16 + +# Create each core +for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } { + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + set _command "target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core" + + if { $_core != $_core_start } { + set _smp_command "$_smp_command ${_TARGETNAME}$_core" + } else { + set _smp_command "target smp ${_TARGETNAME}$_core" + } + + eval $_command +} + +# Configure SMP +if { $_cores > 1 } { + eval $_smp_command +} + +# Make sure the default target is the boot core +targets ${_TARGETNAME}0 + +proc core_up { args } { + global _TARGETNAME + + # Examine remaining cores + foreach _core $args { + ${_TARGETNAME}$_core arp_examine + } +} diff --git a/openocd-win/openocd/scripts/target/bluenrg-x.cfg b/openocd-win/openocd/scripts/target/bluenrg-x.cfg new file mode 100644 index 0000000..afa1b51 --- /dev/null +++ b/openocd-win/openocd/scripts/target/bluenrg-x.cfg @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# bluenrg-1/2 and bluenrg-lp devices support only SWD transports. +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME bluenrg-1 +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 24kB-256bytes +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x5F00 +} + +adapter speed 4000 + +swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +set WDOG_VALUE 0 +set WDOG_VALUE_SET 0 + +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME + +# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none +reset_config none + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +set JTAG_IDCODE_B2 0x0200A041 +set JTAG_IDCODE_B1 0x0 + +$_TARGETNAME configure -event halted { + global WDOG_VALUE + global WDOG_VALUE_SET + set _JTAG_IDCODE [mrw 0x40000004] + if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} { + # Stop watchdog during halt, if enabled. Only Bluenrg-1/2 + set WDOG_VALUE [mrw 0x40700008] + if [expr {$WDOG_VALUE & (1 << 1)}] { + set WDOG_VALUE_SET 1 + mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}] + } + } +} +$_TARGETNAME configure -event resumed { + global WDOG_VALUE + global WDOG_VALUE_SET + set _JTAG_IDCODE [mrw 0x40000004] + if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} { + if {$WDOG_VALUE_SET} { + # Restore watchdog enable value after resume. Only Bluenrg-1/2 + mww 0x40700008 $WDOG_VALUE + set WDOG_VALUE_SET 0 + } + } +} diff --git a/openocd-win/openocd/scripts/target/c100.cfg b/openocd-win/openocd/scripts/target/c100.cfg new file mode 100644 index 0000000..c268ba3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/c100.cfg @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# c100 config. +# This is ARM1136 dual core +# this script only configures one core (that is used to run Linux) + +# assume no PLL lock, start slowly +adapter speed 100 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME c100 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x27b3645b +} + +if { [info exists DSPTAPID] } { + set _DSPTAPID $DSPTAPID +} else { + set _DSPTAPID 0x27b3645b +} + +jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID + + +# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME + +# C100's ARAM 64k SRAM +$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/c100config.tcl b/openocd-win/openocd/scripts/target/c100config.tcl new file mode 100644 index 0000000..2545fa7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/c100config.tcl @@ -0,0 +1,413 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# board(-config) specific parameters file. + +# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ] +proc config {label} { + return [dict get [configC100] $label ] +} + +# show the value for the param. with label +proc showconfig {label} { + echo [format "0x%x" [dict get [configC100] $label ]] +} + +# Telo board config +# when there are more then one board config +# use soft links to c100board-config.tcl +# so that only the right board-config gets +# included (just like include/configs/board-configs.h +# in u-boot. +proc configC100 {} { + # xtal freq. 24MHz + dict set configC100 CFG_REFCLKFREQ 24000000 + + # Amba Clk 165MHz + dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000 + dict set configC100 w_amba 1 + dict set configC100 x_amba 1 + # y = amba_clk * (w+1)*(x+1)*2/xtal_clk + dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] + + # Arm Clk 450MHz, must be a multiple of 25 MHz + dict set configC100 CFG_ARM_CLOCK 450000000 + dict set configC100 w_arm 0 + dict set configC100 x_arm 1 + # y = arm_clk * (w+1)*(x+1)*2/xtal_clk + dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] + + +} + +# This should be called for reset init event handler +proc setupTelo {} { + + # setup GPIO used as control signals for C100 + setupGPIO + # This will allow access to lower 8MB or NOR + lowGPIO5 + # setup NOR size,timing,etc. + setupNOR + # setup internals + PLL + DDR2 + initC100 +} + + +proc setupNOR {} { + echo "Setting up NOR: 16MB, 16-bit wide bus, CS0" + # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init() + set EX_CSEN_REG [regs EX_CSEN_REG ] + set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] + set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] + set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] + set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] + set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] + set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] + set EX_MFSM_REG [regs EX_MFSM_REG ] + set EX_CSFSM_REG [regs EX_CSFSM_REG ] + set EX_WRFSM_REG [regs EX_WRFSM_REG ] + set EX_RDFSM_REG [regs EX_RDFSM_REG ] + + # enable Expansion Bus Clock + CS0 (NOR) + mww $EX_CSEN_REG 0x3 + # set the address space for CS0=16MB + mww $EX_CS0_SEG_REG 0x7ff + # set the CS0 bus width to 16-bit + mww $EX_CS0_CFG_REG 0x202 + # set timings to NOR + mww $EX_CS0_TMG1_REG 0x03034006 + mww $EX_CS0_TMG2_REG 0x04040002 + #mww $EX_CS0_TMG3_REG + # set EBUS clock 165/5=33MHz + mww $EX_CLOCK_DIV_REG 0x5 + # everything else is OK with default +} + +proc bootNOR {} { + set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] + set BLOCK_RESET_REG [regs BLOCK_RESET_REG] + set DDR_RST [regs DDR_RST] + + # put DDR controller in reset (so that it comes reset in u-boot) + mmw $BLOCK_RESET_REG 0x0 $DDR_RST + # setup CS0 controller for NOR + setupNOR + # make sure we are accessing the lower part of NOR + lowGPIO5 + # set PC to start of NOR (at boot 0x20000000 = 0x0) + reg pc $EXP_CS0_BASEADDR + # run + resume +} +proc setupGPIO {} { + echo "Setting up GPIO block for Telo" + # This is current setup for Telo (see sch. for details): + #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup + #GPIO1 irq line for FXS-FXO + #GPIO5 addr22 for NOR flash (access to upper 8MB) + #GPIO17 reset for DECT module. + #GPIO29 CS_n for NAND + + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + set GPIO_OE_REG [regs GPIO_OE_REG] + + # set GPIO29=GPIO17=1, GPIO5=0 + mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}] + # enable [as output] GPIO29,GPIO17,GPIO5 + mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}] +} + +proc highGPIO5 {} { + echo "GPIO5 high" + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + # set GPIO5=1 + mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0 +} + +proc lowGPIO5 {} { + echo "GPIO5 low" + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + # set GPIO5=0 + mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}] +} + +proc boardID {id} { + # so far built: + # 4'b1111 + dict set boardID 15 name "EVT1" + dict set boardID 15 ddr2size 128M + # dict set boardID 15 nandsize 1G + # dict set boardID 15 norsize 16M + # 4'b0000 + dict set boardID 0 name "EVT2" + dict set boardID 0 ddr2size 128M + # 4'b0001 + dict set boardID 1 name "EVT3" + dict set boardID 1 ddr2size 256M + # 4'b1110 + dict set boardID 14 name "EVT3_old" + dict set boardID 14 ddr2size 128M + # 4'b0010 + dict set boardID 2 name "EVT4" + dict set boardID 2 ddr2size 256M + + return $boardID +} + + +# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect() +# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors +proc ooma_board_detect {} { + set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] + + # read the current value of the BOOTSTRAP pins + set tmp [mrw $GPIO_BOOTSTRAP_REG] + echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] + # extract the GPBP bits + set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}] + + # display board ID + echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] + # show it on serial console + putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt] + # return the ddr2 size, used to configure DDR2 on a given board. + return [dict get [boardID $gpbt] $gpbt ddr2size] +} + +proc configureDDR2regs_256M {} { + + set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] + set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] + set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] + set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] + set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] + set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] + set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] + set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] + set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] + set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] + set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] + set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] + set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] + set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] + set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] + set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] + set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] + set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] + set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] + set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] + set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] + + set DENALI_CTL_02_VAL 0x0100000000010100 + set DENALI_CTL_11_VAL 0x433a32164a560a00 + + mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 + # 01_DATA mod [40]=1, enable BA2 + mw64bit $DENALI_CTL_01_DATA 0x0100010100000001 + mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL + mw64bit $DENALI_CTL_03_DATA 0x0102020202020201 + mw64bit $DENALI_CTL_04_DATA 0x0000010100000001 + mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 + mw64bit $DENALI_CTL_06_DATA 0x060a020200020202 + mw64bit $DENALI_CTL_07_DATA 0x0000000300000206 + mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209 + mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a + mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18 + # 11_DATA mod [39-32]=16,more refresh + mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL + mw64bit $DENALI_CTL_12_DATA 0x0000000000000800 + mw64bit $DENALI_CTL_13_DATA 0x0010002000100040 + mw64bit $DENALI_CTL_14_DATA 0x0010004000100040 + mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000 + mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000 + mw64bit $DENALI_CTL_17_DATA 0x0000000000000000 + mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 + mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600 + mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8 + + set wr_dqs_shift 0x40 + # start DDRC + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] + # wait int_status[2] (DRAM init complete) + echo -n "Waiting for DDR2 controller to init..." + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { + sleep 1 + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + } + echo "done." + + # do ddr2 training sequence + # TBD (for now, if you need it, run trainDDR command) +} + +# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99() +# The values are computed based on Mindspeed and Nanya datasheets +proc configureDDR2regs_128M {} { + + set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] + set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] + set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] + set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] + set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] + set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] + set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] + set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] + set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] + set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] + set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] + set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] + set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] + set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] + set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] + set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] + set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] + set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] + set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] + set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] + set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] + + + set DENALI_CTL_02_VAL 0x0100010000010100 + set DENALI_CTL_11_VAL 0x433A42124A650A37 + # set some default values + mw64bit $DENALI_CTL_00_DATA 0x0100000101010101 + mw64bit $DENALI_CTL_01_DATA 0x0100000100000101 + mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL + mw64bit $DENALI_CTL_03_DATA 0x0102020202020201 + mw64bit $DENALI_CTL_04_DATA 0x0201010100000201 + mw64bit $DENALI_CTL_05_DATA 0x0203010300010101 + mw64bit $DENALI_CTL_06_DATA 0x050A020200020202 + mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205 + mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209 + mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00 + mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A + mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL + mw64bit $DENALI_CTL_12_DATA 0x0000080000000800 + mw64bit $DENALI_CTL_13_DATA 0x0010002000100040 + mw64bit $DENALI_CTL_14_DATA 0x0010004000100040 + mw64bit $DENALI_CTL_15_DATA 0x0508000000000000 + mw64bit $DENALI_CTL_16_DATA 0x000020472D200000 + mw64bit $DENALI_CTL_17_DATA 0x0000000008000000 + mw64bit $DENALI_CTL_18_DATA 0x0302000000000000 + mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604 + mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8 + + set wr_dqs_shift 0x40 + # start DDRC + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] + # wait int_status[2] (DRAM init complete) + echo -n "Waiting for DDR2 controller to init..." + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { + sleep 1 + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + } + # This is not necessary + #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ] + echo "done." + + # do ddr2 training sequence + # TBD (for now, if you need it, run trainDDR command) +} + + + +proc setupUART0 {} { + # configure UART0 to 115200, 8N1 + set GPIO_LOCK_REG [regs GPIO_LOCK_REG] + set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] + set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] + set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0] + set UART0_LCR [regs UART0_LCR] + set LCR_DLAB [regs LCR_DLAB] + set UART0_DLL [regs UART0_DLL] + set UART0_DLH [regs UART0_DLH] + set UART0_IIR [regs UART0_IIR] + set UART0_IER [regs UART0_IER] + set LCR_ONE_STOP [regs LCR_ONE_STOP] + set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8] + set FCR_XMITRES [regs FCR_XMITRES] + set FCR_RCVRRES [regs FCR_RCVRRES] + set FCR_FIFOEN [regs FCR_FIFOEN] + set IER_UUE [regs IER_UUE] + + # unlock writing to IOCTRL register + mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL + # enable UART0 + mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0 + # baudrate 115200 + # This should really be amba_clk/(16*115200) but amba_clk=165MHz + set tmp 89 + # Enable Divisor Latch access + mmw $UART0_LCR $LCR_DLAB 0x0 + # set the divisor to $tmp + mww $UART0_DLL [expr {$tmp & 0xff}] + mww $UART0_DLH [expr {$tmp >> 8}] + # Disable Divisor Latch access + mmw $UART0_LCR 0x0 $LCR_DLAB + # set the UART to 8N1 + mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0 + # reset FIFO + mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0 + # enable FFUART + mww $UART0_IER $IER_UUE +} + +proc putcUART0 {char} { + + set UART0_LSR [regs UART0_LSR] + set UART0_THR [regs UART0_THR] + set LSR_TEMT [regs LSR_TEMT] + + # convert the 'char' to digit + set tmp [ scan $char %c ] + # /* wait for room in the tx FIFO on FFUART */ + while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 } + mww $UART0_THR $tmp + if { $char == "\n" } { putcUART0 \r } +} + +proc putsUART0 {str} { + set index 0 + set len [string length $str] + while { $index < $len } { + putcUART0 [string index $str $index] + set index [expr {$index + 1}] + } +} + + +proc trainDDR2 {} { + set ARAM_BASEADDR [regs ARAM_BASEADDR] + + # you must have run 'reset init' or u-boot + # load the training code to ARAM + load_image ./images/ddr2train.bin $ARAM_BASEADDR bin + # set PC to start of NOR (at boot 0x20000000 = 0x0) + reg pc $ARAM_BASEADDR + # run + resume +} + +proc flashUBOOT {file} { + # this will update uboot on NOR partition + set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR] + + # setup CS0 controller for NOR + setupNOR + # make sure we are accessing the lower part of NOR + lowGPIO5 + flash probe 0 + echo "Erasing sectors 0-3 for uboot" + putsUART0 "Erasing sectors 0-3 for uboot\n" + flash erase_sector 0 0 3 + echo "Programming u-boot" + putsUART0 "Programming u-boot..." + arm11 memwrite burst enable + flash write_image $file $EXP_CS0_BASEADDR + arm11 memwrite burst disable + putsUART0 "done.\n" + putsUART0 "Rebooting, please wait!\n" + reboot +} diff --git a/openocd-win/openocd/scripts/target/c100helper.tcl b/openocd-win/openocd/scripts/target/c100helper.tcl new file mode 100644 index 0000000..d1d3f25 --- /dev/null +++ b/openocd-win/openocd/scripts/target/c100helper.tcl @@ -0,0 +1,505 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc helpC100 {} { + echo "List of useful functions for C100 processor:" + echo "1) reset init: will set up your Telo board" + echo "2) setupNOR: will setup NOR access" + echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR" + echo "4) setupGPIO: will setup GPIOs for Telo board" + echo "5) showGPIO: will show current GPIO config registers" + echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB" + echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB" + echo "8) showAmbaClk: will show current config registers for Amba Bus Clock" + echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz" + echo "10) showArmClk: will show current config registers for Arm Bus Clock" + echo "11) setupArmClk: will setup Amba Bus Clock=450MHz" + echo "12) ooma_board_detect: will show which version of Telo you have" + echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured" + echo "14) showDDR2: will show DDR2 config registers" + echo "15) showWatchdog: will show current register config for watchdog" + echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)" + echo "17) bootNOR: will boot Telo from NOR" + echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured" + echo "19) putcUART0: will print a character on UART0" + echo "20) putsUART0: will print a string on UART0" + echo "21) trainDDR2: will run DDR2 training program" + echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin" +} + +source [find mem_helper.tcl] + +# read a 64-bit register (memory mapped) +proc mr64bit {reg} { + return [read_memory $reg 32 2] +} + + +# write a 64-bit register (memory mapped) +proc mw64bit {reg value} { + set high [expr {$value >> 32}] + set low [expr {$value & 0xffffffff}] + #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low] + mww $reg $low + mww [expr {$reg+4}] $high +} + + +proc showNOR {} { + echo "This is the current NOR setup" + set EX_CSEN_REG [regs EX_CSEN_REG ] + set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ] + set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ] + set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ] + set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ] + set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ] + set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ] + set EX_MFSM_REG [regs EX_MFSM_REG ] + set EX_CSFSM_REG [regs EX_CSFSM_REG ] + set EX_WRFSM_REG [regs EX_WRFSM_REG ] + set EX_RDFSM_REG [regs EX_RDFSM_REG ] + + echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]] + echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]] + echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]] + echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]] + echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]] + echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]] + echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]] + echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]] + echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]] + echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]] + echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]] +} + + + +proc showGPIO {} { + echo "This is the current GPIO register setup" + # GPIO outputs register + set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] + # GPIO Output Enable register + set GPIO_OE_REG [regs GPIO_OE_REG] + set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG] + set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG] + # GPIO input register + set GPIO_INPUT_REG [regs GPIO_INPUT_REG] + set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] + set MUX_CONF_REG [regs MUX_CONF_REG] + set SYSCONF_REG [regs SYSCONF_REG] + set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG] + set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] + set GPIO_LOCK_REG [regs GPIO_LOCK_REG] + set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] + set GPIO_DEVID_REG [regs GPIO_DEVID_REG] + + echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]] + echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]] + echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]] + echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]] + echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]] + echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]] + echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]] + echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]] + echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]] + echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]] + echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]] + echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]] + echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]] +} + + + +# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk()) +proc showAmbaClk {} { + set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] + set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + + echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] + set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1] + # see if the PLL is in bypass mode + set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}] + echo [format "PLL bypass bit: %d" $bypass] + if {$bypass == 1} { + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] + } else { + # nope, extract x,y,w and compute the PLL output freq. + set x [expr {($value & 0x0001F0000) >> 16}] + echo [format "x: %d" $x] + set y [expr {($value & 0x00000007F)}] + echo [format "y: %d" $y] + set w [expr {($value & 0x000000300) >> 8}] + echo [format "w: %d" $w] + echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] + } +} + + +# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk()) +# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc) +proc setupAmbaClk {} { + set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] + set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL] + set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] + set ARM_AHB_BYP [regs ARM_AHB_BYP] + set PLL_DISABLE [regs PLL_DISABLE] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] + set DIV_BYPASS [regs DIV_BYPASS] + set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK] + set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] + set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK] + set w [config w_amba] + set x [config x_amba] + set y [config y_amba] + + echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]] + #echo [format "setupAmbaClk: w= %d" $w] + #echo [format "setupAmbaClk: x= %d" $x] + #echo [format "setupAmbaClk: y= %d" $y] + # set PLL into BYPASS mode using MUX + mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0 + # do an internal PLL bypass + mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0 + # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us) + # openocd smallest resolution is 1ms so, wait 1ms + sleep 1 + # disable the PLL + mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0 + # wait 1ms + sleep 1 + # enable the PLL + mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE + sleep 1 + # set X, W and X + mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF + mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 + # wait for PLL to lock + echo "Waiting for Amba PLL to lock" + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } + # remove the internal PLL bypass + mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL + # remove PLL from BYPASS mode using MUX + mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS +} + + +# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk()) +proc showArmClk {} { + set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] + set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + + echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] + set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1] + # see if the PLL is in bypass mode + set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}] + echo [format "PLL bypass bit: %d" $bypass] + if {$bypass == 1} { + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] + } else { + # nope, extract x,y,w and compute the PLL output freq. + set x [expr {($value & 0x0001F0000) >> 16}] + echo [format "x: %d" $x] + set y [expr {($value & 0x00000007F)}] + echo [format "y: %d" $y] + set w [expr {($value & 0x000000300) >> 8}] + echo [format "w: %d" $w] + echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] + } +} + +# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk()) +# Arm Clock is used by two ARM1136 cores +proc setupArmClk {} { + set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS] + set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL] + set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL] + set ARM_AHB_BYP [regs ARM_AHB_BYP] + set PLL_DISABLE [regs PLL_DISABLE] + set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS] + set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL] + set DIV_BYPASS [regs DIV_BYPASS] + set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK] + set CFG_REFCLKFREQ [config CFG_REFCLKFREQ] + set CFG_ARM_CLOCK [config CFG_ARM_CLOCK] + set w [config w_arm] + set x [config x_arm] + set y [config y_arm] + + echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]] + #echo [format "setupArmClk: w= %d" $w] + #echo [format "setupArmaClk: x= %d" $x] + #echo [format "setupArmaClk: y= %d" $y] + # set PLL into BYPASS mode using MUX + mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0 + # do an internal PLL bypass + mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0 + # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us) + # openocd smallest resolution is 1ms so, wait 1ms + sleep 1 + # disable the PLL + mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0 + # wait 1ms + sleep 1 + # enable the PLL + mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE + sleep 1 + # set X, W and X + mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF + mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 + # wait for PLL to lock + echo "Waiting for Amba PLL to lock" + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } + # remove the internal PLL bypass + mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL + # remove PLL from BYPASS mode using MUX + mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS +} + + + +proc setupPLL {} { + echo "PLLs setup" + setupAmbaClk + setupArmClk +} + +# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init() +proc setupDDR2 {} { + echo "Configuring DDR2" + + set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR] + set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR] + set MEMORY_CR [regs MEMORY_CR] + set BLOCK_RESET_REG [regs BLOCK_RESET_REG] + set DDR_RST [regs DDR_RST] + + # put DDR controller in reset (so that it is reset and correctly configured) + # this is only necessary if DDR was previously confiured + # and not reset. + mmw $BLOCK_RESET_REG 0x0 $DDR_RST + + set M [expr {1024 * 1024}] + set DDR_SZ_1024M [expr {1024 * $M}] + set DDR_SZ_256M [expr {256 * $M}] + set DDR_SZ_128M [expr {128 * $M}] + set DDR_SZ_64M [expr {64 * $M}] + # ooma_board_detect returns DDR2 memory size + set tmp [ooma_board_detect] + if {$tmp == "128M"} { + echo "DDR2 size 128MB" + set ddr_size $DDR_SZ_128M + } elseif {$tmp == "256M"} { + echo "DDR2 size 256MB" + set ddr_size $DDR_SZ_256M + } else { + echo "Don't know how to handle this DDR2 size?" + } + + # Memory setup register + mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}] + # disable ROM remap + mww $MEMORY_CR 0x0 + # Take DDR controller out of reset + mmw $BLOCK_RESET_REG $DDR_RST 0x0 + # min. 20 ops delay + sleep 1 + + # This will setup Denali DDR2 controller + if {$tmp == "128M"} { + configureDDR2regs_128M + } elseif {$tmp == "256M"} { + configureDDR2regs_256M + } else { + echo "Don't know how to configure DDR2 setup?" + } +} + + + +proc showDDR2 {} { + + set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA] + set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA] + set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA] + set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA] + set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA] + set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA] + set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA] + set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA] + set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA] + set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA] + set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA] + set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA] + set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA] + set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA] + set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA] + set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA] + set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA] + set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA] + set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA] + set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA] + set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA] + + set tmp [mr64bit $DENALI_CTL_00_DATA] + echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_01_DATA] + echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_02_DATA] + echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_03_DATA] + echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_04_DATA] + echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_05_DATA] + echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_06_DATA] + echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_07_DATA] + echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_08_DATA] + echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_09_DATA] + echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_10_DATA] + echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_11_DATA] + echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_12_DATA] + echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_13_DATA] + echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_14_DATA] + echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_15_DATA] + echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_16_DATA] + echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_17_DATA] + echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_18_DATA] + echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_19_DATA] + echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)] + set tmp [mr64bit $DENALI_CTL_20_DATA] + echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)] + +} + +proc initC100 {} { + # this follows u-boot/cpu/arm1136/start.S + set GPIO_LOCK_REG [regs GPIO_LOCK_REG] + set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG] + set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL] + set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG] + set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR] + set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG] + set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR] + set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG] + set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN] + set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN] + set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN] + set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN] + set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN] + set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN] + set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG] + + + # unlock writing to IOCTRL register + mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL + # enable address lines A15-A21 + mmw $GPIO_IOCTRL_REG 0xf 0x0 + # set ARM into supervisor mode (SVC32) + # disable IRQ, FIQ + # Do I need this in JTAG mode? + # it really should be done as 'and ~0x1f | 0xd3 but + # openocd does not support this yet + reg cpsr 0xd3 + # /* + # * flush v4 I/D caches + # */ + # mov r0, #0 + # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + arm mcr 15 0 7 7 0 0x0 + # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + arm mcr 15 0 8 7 0 0x0 + + # /* + # * disable MMU stuff and caches + # */ + # mrc p15, 0, r0, c1, c0, 0 + arm mrc 15 0 1 0 0 + # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + # orr r0, r0, #0x00000002 @ set bit 2 (A) Align + # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + # orr r0, r0, #0x00400000 @ set bit 22 (U) + # mcr p15, 0, r0, c1, c0, 0 + arm mcr 15 0 1 0 0 0x401002 + # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c + # APB init + # // Setting APB Bus Wait states to 1, set post write + # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40; + mww $APB_ACCESS_WS_REG 0x40 + # AHB init + # // enable all 6 masters for ARAM + mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 + # // enable all 6 masters for EBUS + mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 + + # ARAM init + # // disable pipeline mode in ARAM + # I don't think this is documented anywhere? + mww $INTC_ARM1_CONTROL_REG 0x1 + # configure clocks + setupPLL + # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART. + setupUART0 + # enable cache + # ? (u-boot does nothing here) + # DDR2 memory init + setupDDR2 + putsUART0 "C100 initialization complete.\n" + echo "C100 initialization complete." +} + +# show current state of watchdog timer +proc showWatchdog {} { + set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] + set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] + set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] + + echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]] + echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]] + echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] +} + +# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored) +# this will trigger watchdog reset +# the sw. reset does not work on C100 +# watchdog reset effectively works as hw. reset +proc reboot {} { + set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND] + set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL] + set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT] + + # allow the counter to count to high value before triggering + # this is because register writes are slow over JTAG and + # I don't want to miss the high_bound==curr_count condition + mww $TIMER_WDT_HIGH_BOUND 0xffffff + mww $TIMER_WDT_CURRENT_COUNT 0x0 + echo "JTAG speed lowered to 100kHz" + adapter speed 100 + mww $TIMER_WDT_CONTROL 0x1 + # wait until the reset + echo -n "Waiting for watchdog to trigger..." + #while {[mrw $TIMER_WDT_CONTROL] == 1} { + # echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]] + # sleep 1 + # + #} + while {[c100.cpu curstate] != "running"} { sleep 1} + echo "done." + echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]] +} diff --git a/openocd-win/openocd/scripts/target/c100regs.tcl b/openocd-win/openocd/scripts/target/c100regs.tcl new file mode 100644 index 0000000..7be8939 --- /dev/null +++ b/openocd-win/openocd/scripts/target/c100regs.tcl @@ -0,0 +1,495 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Note that I basically converted +# u-boot/include/asm-arm/arch/comcerto_100.h +# defines + +# this is a work-around for 'global' not working under Linux +# access registers by calling this routine. +# For example: +# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG] +proc regs {reg} { + return [dict get [regsC100] $reg ] +} + +proc showreg {reg} { + echo [format "0x%x" [dict get [regsC100] $reg ]] +} + +proc regsC100 {} { +#/* memcore */ +#/* device memory base addresses */ +#// device memory sizes +#/* ARAM SIZE=64K */ +dict set regsC100 ARAM_SIZE 0x00010000 +dict set regsC100 ARAM_BASEADDR 0x0A000000 + +#/* Hardware Interface Units */ +dict set regsC100 APB_BASEADDR 0x10000000 +#/* APB_SIZE=16M address range */ +dict set regsC100 APB_SIZE 0x01000000 + +dict set regsC100 EXP_CS0_BASEADDR 0x20000000 +dict set regsC100 EXP_CS1_BASEADDR 0x24000000 +dict set regsC100 EXP_CS2_BASEADDR 0x28000000 +dict set regsC100 EXP_CS3_BASEADDR 0x2C000000 +dict set regsC100 EXP_CS4_BASEADDR 0x30000000 + +dict set regsC100 DDR_BASEADDR 0x80000000 + +dict set regsC100 TDM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}] +dict set regsC100 PHI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}] +dict set regsC100 TDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}] +dict set regsC100 ASA_DDR_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}] +dict set regsC100 ASA_ARAM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}] +dict set regsC100 TIMER_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}] +dict set regsC100 ASD_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}] +dict set regsC100 GPIO_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}] +dict set regsC100 UART0_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}] +dict set regsC100 UART1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}] +dict set regsC100 SPI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}] +dict set regsC100 I2C_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}] +dict set regsC100 INTC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}] +dict set regsC100 CLKCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 PUI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 GEMAC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}] +dict set regsC100 IDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}] +dict set regsC100 MEMCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}] +dict set regsC100 ASA_EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}] +dict set regsC100 ASA_AAB_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}] +dict set regsC100 GEMAC1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}] +dict set regsC100 EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}] +dict set regsC100 MDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}] + + +#//////////////////////////////////////////////////////////// +#// AHB block // +#//////////////////////////////////////////////////////////// +dict set regsC100 ASA_ARAM_PRI_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}] +dict set regsC100 ASA_ARAM_TC_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}] +dict set regsC100 ASA_ARAM_TC_CR_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}] +dict set regsC100 ASA_ARAM_STAT_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}] + +dict set regsC100 ASA_EBUS_PRI_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}] +dict set regsC100 ASA_EBUS_TC_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}] +dict set regsC100 ASA_EBUS_TC_CR_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}] +dict set regsC100 ASA_EBUS_STAT_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}] + +dict set regsC100 IDMA_MASTER 0 +dict set regsC100 TDMA_MASTER 1 +dict set regsC100 USBIPSEC_MASTER 2 +dict set regsC100 ARM0_MASTER 3 +dict set regsC100 ARM1_MASTER 4 +dict set regsC100 MDMA_MASTER 5 + +#define IDMA_PRIORITY(level) (level) +#define TDM_PRIORITY(level) (level << 4) +#define USBIPSEC_PRIORITY(level) (level << 8) +#define ARM0_PRIORITY(level) (level << 12) +#define ARM1_PRIORITY(level) (level << 16) +#define MDMA_PRIORITY(level) (level << 20) + +dict set regsC100 ASA_TC_REQIDMAEN [expr {1<<18}] +dict set regsC100 ASA_TC_REQTDMEN [expr {1<<19}] +dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}] +dict set regsC100 ASA_TC_REQARM0EN [expr {1<<21}] +dict set regsC100 ASA_TC_REQARM1EN [expr {1<<22}] +dict set regsC100 ASA_TC_REQMDMAEN [expr {1<<23}] + +dict set regsC100 MEMORY_BASE_ADDR 0x80000000 +dict set regsC100 MEMORY_MAX_ADDR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}] +dict set regsC100 MEMORY_CR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}] +dict set regsC100 ROM_REMAP_EN 0x1 + +#define HAL_asb_priority(level) \ +#*(volatile unsigned *)ASA_PRI_REG = level + +#define HAL_aram_priority(level) \ +#*(volatile unsigned *)ASA_ARAM_PRI_REG = level + +#define HAL_aram_arbitration(arbitration_mask) \ +#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask + +#define HAL_aram_defmaster(mask) \ +#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24) + +#//////////////////////////////////////////////////////////// +#// INTC block // +#//////////////////////////////////////////////////////////// + +dict set regsC100 INTC_ARM1_CONTROL_REG [expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}] + +#//////////////////////////////////////////////////////////// +#// TIMER block // +#//////////////////////////////////////////////////////////// + +dict set regsC100 TIMER0_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}] +dict set regsC100 TIMER0_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}] +dict set regsC100 TIMER1_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}] +dict set regsC100 TIMER1_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}] + +dict set regsC100 TIMER2_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}] +dict set regsC100 TIMER2_LBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}] +dict set regsC100 TIMER2_HBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}] +dict set regsC100 TIMER2_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}] + +dict set regsC100 TIMER3_LOBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}] +dict set regsC100 TIMER3_HIBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}] +dict set regsC100 TIMER3_CTRL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}] +dict set regsC100 TIMER3_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}] + +dict set regsC100 TIMER_MASK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}] +dict set regsC100 TIMER_STATUS [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_ACK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}] +dict set regsC100 TIMER_WDT_CONTROL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}] +dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}] + + + +#//////////////////////////////////////////////////////////// +#// EBUS block +#//////////////////////////////////////////////////////////// + +dict set regsC100 EX_SWRST_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}] +dict set regsC100 EX_CSEN_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}] +dict set regsC100 EX_CS0_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}] +dict set regsC100 EX_CS1_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}] +dict set regsC100 EX_CS2_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}] +dict set regsC100 EX_CS3_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}] +dict set regsC100 EX_CS4_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}] +dict set regsC100 EX_CS0_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}] +dict set regsC100 EX_CS1_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}] +dict set regsC100 EX_CS2_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}] +dict set regsC100 EX_CS3_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}] +dict set regsC100 EX_CS4_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}] +dict set regsC100 EX_CS0_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}] +dict set regsC100 EX_CS1_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}] +dict set regsC100 EX_CS2_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}] +dict set regsC100 EX_CS3_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}] +dict set regsC100 EX_CS4_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}] +dict set regsC100 EX_CS0_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}] +dict set regsC100 EX_CS1_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}] +dict set regsC100 EX_CS2_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}] +dict set regsC100 EX_CS3_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}] +dict set regsC100 EX_CS4_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}] +dict set regsC100 EX_CS0_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}] +dict set regsC100 EX_CS1_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}] +dict set regsC100 EX_CS2_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}] +dict set regsC100 EX_CS3_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}] +dict set regsC100 EX_CS4_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}] +dict set regsC100 EX_CLOCK_DIV_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}] + +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_CSFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}] +dict set regsC100 EX_WRFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}] +dict set regsC100 EX_RDFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}] + + +dict set regsC100 EX_CLK_EN 0x00000001 +dict set regsC100 EX_CSBOOT_EN 0x00000002 +dict set regsC100 EX_CS0_EN 0x00000002 +dict set regsC100 EX_CS1_EN 0x00000004 +dict set regsC100 EX_CS2_EN 0x00000008 +dict set regsC100 EX_CS3_EN 0x00000010 +dict set regsC100 EX_CS4_EN 0x00000020 + +dict set regsC100 EX_MEM_BUS_8 0x00000000 +dict set regsC100 EX_MEM_BUS_16 0x00000002 +dict set regsC100 EX_MEM_BUS_32 0x00000004 +dict set regsC100 EX_CS_HIGH 0x00000008 +dict set regsC100 EX_WE_HIGH 0x00000010 +dict set regsC100 EX_RE_HIGH 0x00000020 +dict set regsC100 EX_ALE_MODE 0x00000040 +dict set regsC100 EX_STRB_MODE 0x00000080 +dict set regsC100 EX_DM_MODE 0x00000100 +dict set regsC100 EX_NAND_MODE 0x00000200 +dict set regsC100 EX_RDY_EN 0x00000400 +dict set regsC100 EX_RDY_EDGE 0x00000800 + +#//////////////////////////////////////////////////////////// +#// GPIO block +#//////////////////////////////////////////////////////////// + +# GPIO outputs register +dict set regsC100 GPIO_OUTPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}] +# GPIO Output Enable register +dict set regsC100 GPIO_OE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}] +dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}] +dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}] +# GPIO input register +dict set regsC100 GPIO_INPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}] +dict set regsC100 APB_ACCESS_WS_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}] +dict set regsC100 MUX_CONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}] +dict set regsC100 SYSCONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}] +dict set regsC100 GPIO_ARM_ID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}] +dict set regsC100 GPIO_BOOTSTRAP_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}] +dict set regsC100 GPIO_LOCK_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}] +dict set regsC100 GPIO_IOCTRL_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}] +dict set regsC100 GPIO_DEVID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}] + +dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001 +dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002 +dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004 +dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008 +dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010 +dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020 +dict set regsC100 GPIO_IOCTRL_I2C 0x00000040 +dict set regsC100 GPIO_IOCTRL_UART0 0x00000080 +dict set regsC100 GPIO_IOCTRL_UART1 0x00000100 +dict set regsC100 GPIO_IOCTRL_SPI 0x00000200 +dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400 + +dict set regsC100 GPIO_IOCTRL_VAL 0x55555555 + +dict set regsC100 GPIO_0 0x01 +dict set regsC100 GPIO_1 0x02 +dict set regsC100 GPIO_2 0x04 +dict set regsC100 GPIO_3 0x08 +dict set regsC100 GPIO_4 0x10 +dict set regsC100 GPIO_5 0x20 +dict set regsC100 GPIO_6 0x40 +dict set regsC100 GPIO_7 0x80 + +dict set regsC100 GPIO_RISING_EDGE 1 +dict set regsC100 GPIO_FALLING_EDGE 2 +dict set regsC100 GPIO_BOTH_EDGES 3 + +#//////////////////////////////////////////////////////////// +#// UART +#//////////////////////////////////////////////////////////// + +dict set regsC100 UART0_RBR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_THR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_DLL [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_IER [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_DLH [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_IIR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_FCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_LCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}] +dict set regsC100 UART0_MCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}] +dict set regsC100 UART0_LSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}] +dict set regsC100 UART0_MSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}] +dict set regsC100 UART0_SCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}] + +dict set regsC100 UART1_RBR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_THR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_DLL [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_IER [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_DLH [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_IIR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_FCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_LCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}] +dict set regsC100 UART1_MCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}] +dict set regsC100 UART1_LSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}] +dict set regsC100 UART1_MSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}] +dict set regsC100 UART1_SCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}] + +# /* default */ +dict set regsC100 LCR_CHAR_LEN_5 0x00 +dict set regsC100 LCR_CHAR_LEN_6 0x01 +dict set regsC100 LCR_CHAR_LEN_7 0x02 +dict set regsC100 LCR_CHAR_LEN_8 0x03 +#/* One stop bit! - default */ +dict set regsC100 LCR_ONE_STOP 0x00 +#/* Two stop bit! */ +dict set regsC100 LCR_TWO_STOP 0x04 +#/* Parity Enable */ +dict set regsC100 LCR_PEN 0x08 +dict set regsC100 LCR_PARITY_NONE 0x00 +#/* Even Parity Select */ +dict set regsC100 LCR_EPS 0x10 +#/* Enable Parity Stuff */ +dict set regsC100 LCR_PS 0x20 +#/* Start Break */ +dict set regsC100 LCR_SBRK 0x40 +#/* Parity Stuff Bit */ +dict set regsC100 LCR_PSB 0x80 +#/* UART 16550 Divisor Latch Assess */ +dict set regsC100 LCR_DLAB 0x80 + +#/* FIFO Error Status */ +dict set regsC100 LSR_FIFOE [expr {1 << 7}] +#/* Transmitter Empty */ +dict set regsC100 LSR_TEMT [expr {1 << 6}] +#/* Transmit Data Request */ +dict set regsC100 LSR_TDRQ [expr {1 << 5}] +#/* Break Interrupt */ +dict set regsC100 LSR_BI [expr {1 << 4}] +#/* Framing Error */ +dict set regsC100 LSR_FE [expr {1 << 3}] +#/* Parity Error */ +dict set regsC100 LSR_PE [expr {1 << 2}] +#/* Overrun Error */ +dict set regsC100 LSR_OE [expr {1 << 1}] +#/* Data Ready */ +dict set regsC100 LSR_DR [expr {1 << 0}] + +#/* DMA Requests Enable */ +dict set regsC100 IER_DMAE [expr {1 << 7}] +#/* UART Unit Enable */ +dict set regsC100 IER_UUE [expr {1 << 6}] +#/* NRZ coding Enable */ +dict set regsC100 IER_NRZE [expr {1 << 5}] +#/* Receiver Time Out Interrupt Enable */ +dict set regsC100 IER_RTIOE [expr {1 << 4}] +#/* Modem Interrupt Enable */ +dict set regsC100 IER_MIE [expr {1 << 3}] +#/* Receiver Line Status Interrupt Enable */ +dict set regsC100 IER_RLSE [expr {1 << 2}] +#/* Transmit Data request Interrupt Enable */ +dict set regsC100 IER_TIE [expr {1 << 1}] +#/* Receiver Data Available Interrupt Enable */ +dict set regsC100 IER_RAVIE [expr {1 << 0}] + +#/* FIFO Mode Enable Status */ +dict set regsC100 IIR_FIFOES1 [expr {1 << 7}] +#/* FIFO Mode Enable Status */ +dict set regsC100 IIR_FIFOES0 [expr {1 << 6}] +#/* Time Out Detected */ +dict set regsC100 IIR_TOD [expr {1 << 3}] +#/* Interrupt Source Encoded */ +dict set regsC100 IIR_IID2 [expr {1 << 2}] +#/* Interrupt Source Encoded */ +dict set regsC100 IIR_IID1 [expr {1 << 1}] +#/* Interrupt Pending (active low) */ +dict set regsC100 IIR_IP [expr {1 << 0}] + +#/* UART 16550 FIFO Control Register */ +dict set regsC100 FCR_FIFOEN 0x01 +dict set regsC100 FCR_RCVRRES 0x02 +dict set regsC100 FCR_XMITRES 0x04 + +#/* Interrupt Enable Register */ +#// UART 16550 +#// Enable Received Data Available Interrupt +dict set regsC100 IER_RXTH 0x01 +#// Enable Transmitter Empty Interrupt +dict set regsC100 IER_TXTH 0x02 + + + +#//////////////////////////////////////////////////////////// +#// CLK + RESET block +#//////////////////////////////////////////////////////////// + +dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}] +dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}] +dict set regsC100 CLKCORE_PLL_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}] +dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}] +dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}] +dict set regsC100 CLKCORE_FSYNC_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}] +dict set regsC100 CLKCORE_CLK_PWR_DWN [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}] +dict set regsC100 CLKCORE_RNG_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}] +dict set regsC100 CLKCORE_RNG_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}] +dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}] + +dict set regsC100 ARM_PLL_BY_CTRL 0x80000000 +dict set regsC100 ARM_AHB_BYP 0x04000000 +dict set regsC100 PLL_DISABLE 0x02000000 +dict set regsC100 PLL_CLK_BYPASS 0x01000000 + +dict set regsC100 AHB_PLL_BY_CTRL 0x80000000 +dict set regsC100 DIV_BYPASS 0x40000000 +dict set regsC100 SYNC_MODE 0x20000000 + +dict set regsC100 EPHY_CLKDIV_BYPASS 0x00200000 +dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT 16 +dict set regsC100 PUI_CLKDIV_BYPASS 0x00004000 +dict set regsC100 PUI_CLKDIV_SRCCLK 0x00002000 +dict set regsC100 PUI_CLKDIV_RATIO_SHIFT 8 +dict set regsC100 PCI_CLKDIV_BYPASS 0x00000020 +dict set regsC100 PCI_CLKDIV_RATIO_SHIFT 0 + +dict set regsC100 ARM0_CLK_PD 0x00200000 +dict set regsC100 ARM1_CLK_PD 0x00100000 +dict set regsC100 EPHY_CLK_PD 0x00080000 +dict set regsC100 TDM_CLK_PD 0x00040000 +dict set regsC100 PUI_CLK_PD 0x00020000 +dict set regsC100 PCI_CLK_PD 0x00010000 +dict set regsC100 MDMA_AHBCLK_PD 0x00000400 +dict set regsC100 I2CSPI_AHBCLK_PD 0x00000200 +dict set regsC100 UART_AHBCLK_PD 0x00000100 +dict set regsC100 IPSEC_AHBCLK_PD 0x00000080 +dict set regsC100 TDM_AHBCLK_PD 0x00000040 +dict set regsC100 USB1_AHBCLK_PD 0x00000020 +dict set regsC100 USB0_AHBCLK_PD 0x00000010 +dict set regsC100 GEMAC1_AHBCLK_PD 0x00000008 +dict set regsC100 GEMAC0_AHBCLK_PD 0x00000004 +dict set regsC100 PUI_AHBCLK_PD 0x00000002 +dict set regsC100 HIF_AHBCLK_PD 0x00000001 + +dict set regsC100 ARM1_DIV_BP 0x00001000 +dict set regsC100 ARM1_DIV_VAL_SHIFT 8 +dict set regsC100 ARM0_DIV_BP 0x00000010 +dict set regsC100 ARM0_DIV_VAL_SHIFT 0 + +dict set regsC100 AHBCLK_PLL_LOCK 0x00000002 +dict set regsC100 FCLK_PLL_LOCK 0x00000001 + + +#// reset block +dict set regsC100 BLOCK_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}] +dict set regsC100 CSP_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}] + +dict set regsC100 RNG_RST 0x1000 +dict set regsC100 IPSEC_RST 0x0800 +dict set regsC100 DDR_RST 0x0400 +dict set regsC100 USB1_PHY_RST 0x0200 +dict set regsC100 USB0_PHY_RST 0x0100 +dict set regsC100 USB1_RST 0x0080 +dict set regsC100 USB0_RST 0x0040 +dict set regsC100 GEMAC1_RST 0x0020 +dict set regsC100 GEMAC0_RST 0x0010 +dict set regsC100 TDM_RST 0x0008 +dict set regsC100 PUI_RST 0x0004 +dict set regsC100 HIF_RST 0x0002 +dict set regsC100 PCI_RST 0x0001 + +#//////////////////////////////////////////////////////////////// +#// DDR CONTROLLER block +#//////////////////////////////////////////////////////////////// + +dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000 +dict set regsC100 DENALI_CTL_00_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}] +dict set regsC100 DENALI_CTL_01_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}] +dict set regsC100 DENALI_CTL_02_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}] +dict set regsC100 DENALI_CTL_03_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}] +dict set regsC100 DENALI_CTL_04_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}] +dict set regsC100 DENALI_CTL_05_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}] +dict set regsC100 DENALI_CTL_06_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}] +dict set regsC100 DENALI_CTL_07_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}] +dict set regsC100 DENALI_CTL_08_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}] +dict set regsC100 DENALI_CTL_09_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}] +dict set regsC100 DENALI_CTL_10_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}] +dict set regsC100 DENALI_CTL_11_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}] +dict set regsC100 DENALI_CTL_12_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}] +dict set regsC100 DENALI_CTL_13_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}] +dict set regsC100 DENALI_CTL_14_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}] +dict set regsC100 DENALI_CTL_15_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}] +dict set regsC100 DENALI_CTL_16_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}] +dict set regsC100 DENALI_CTL_17_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}] +dict set regsC100 DENALI_CTL_18_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}] +dict set regsC100 DENALI_CTL_19_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}] +dict set regsC100 DENALI_CTL_20_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}] + +# 32-bit value +dict set regsC100 DENALI_READY_CHECK [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}] +# 8-bit +dict set regsC100 DENALI_WR_DQS [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}] +# 8-bit +dict set regsC100 DENALI_DQS_OUT [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}] +# 8-bit +dict set regsC100 DENALI_DQS_DELAY0 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}] +# 8-bit +dict set regsC100 DENALI_DQS_DELAY1 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}] +# 8-bit +dict set regsC100 DENALI_DQS_DELAY2 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}] +# 8-bit +dict set regsC100 DENALI_DQS_DELAY3 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}] + + +# end of proc regsC100 +} diff --git a/openocd-win/openocd/scripts/target/cc2538.cfg b/openocd-win/openocd/scripts/target/cc2538.cfg new file mode 100644 index 0000000..e4fb02a --- /dev/null +++ b/openocd-win/openocd/scripts/target/cc2538.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config for Texas Instruments low power RF SoC CC2538 +# http://www.ti.com/lit/pdf/swru319 + +adapter speed 100 + +source [find target/icepick.cfg] +source [find target/ti-cjtag.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc2538 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x8B96402F +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# +# ICEpick-C (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x8B96402F +} +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version +# A start sequence is needed to change from cJTAG (Compact JTAG) to +# 4-pin JTAG before talking via JTAG commands +jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" + +# +# Cortex-M3 target +# +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap diff --git a/openocd-win/openocd/scripts/target/cs351x.cfg b/openocd-win/openocd/scripts/target/cs351x.cfg new file mode 100644 index 0000000..e67540a --- /dev/null +++ b/openocd-win/openocd/scripts/target/cs351x.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cs351x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00526fa1 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME + +# There is 16K of SRAM on this chip +# FIXME: flash programming is not working by using this work area. So comment this out for now. +#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1 + +# This chip has a DCC ... use it +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/davinci.cfg b/openocd-win/openocd/scripts/target/davinci.cfg new file mode 100644 index 0000000..54afb64 --- /dev/null +++ b/openocd-win/openocd/scripts/target/davinci.cfg @@ -0,0 +1,379 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Utility code for DaVinci-family chips +# + +# davinci_pinmux: assigns PINMUX$reg <== $value +proc davinci_pinmux {soc reg value} { + mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value +} + +source [find mem_helper.tcl] + +# +# pll_setup: initialize PLL +# - pll_addr ... physical addr of controller +# - mult ... pll multiplier +# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers +# +# For PLLs that don't have a given register (e.g. plldiv8), or where a +# given divider is non-programmable, caller provides *NO* config mapping. +# + +# PLL version 0x02: tested on dm355 +# REVISIT: On dm6446/dm357 the PLLRST polarity is different. +proc pll_v02_setup {pll_addr mult config} { + set pll_ctrl_addr [expr {$pll_addr + 0x100}] + set pll_ctrl [mrw $pll_ctrl_addr] + + # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator + # NOTE: this assumes we should clear that bit + set pll_ctrl [expr {$pll_ctrl & ~0x0100}] + mww $pll_ctrl_addr $pll_ctrl + + # 2 - clear PLLENSRC (bit 5) + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] + mww $pll_ctrl_addr $pll_ctrl + + # 3 - clear PLLEN (bit 0) ... enter bypass mode + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] + mww $pll_ctrl_addr $pll_ctrl + + # 4 - wait at least 4 refclk cycles + sleep 1 + + # 5 - set PLLRST (bit 3) + set pll_ctrl [expr {$pll_ctrl | 0x0008}] + mww $pll_ctrl_addr $pll_ctrl + + # 6 - set PLLDIS (bit 4) + set pll_ctrl [expr {$pll_ctrl | 0x0010}] + mww $pll_ctrl_addr $pll_ctrl + + # 7 - clear PLLPWRDN (bit 1) + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] + mww $pll_ctrl_addr $pll_ctrl + + # 8 - clear PLLDIS (bit 4) + set pll_ctrl [expr {$pll_ctrl & ~0x0010}] + mww $pll_ctrl_addr $pll_ctrl + + # 9 - optional: write prediv, postdiv, and pllm + # NOTE: for dm355 PLL1, postdiv is controlled via MISC register + mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}] + if { [dict exists $config prediv] } { + set div [dict get $config prediv] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div + } + if { [dict exists $config postdiv] } { + set div [dict get $config postdiv] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div + } + + # 10 - optional: set plldiv1, plldiv2, ... + # NOTE: this assumes some registers have their just-reset values: + # - PLLSTAT.GOSTAT is clear when we enter + # - ALNCTL has everything set + set go 0 + if { [dict exists $config div1] } { + set div [dict get $config div1] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div + set go 1 + } + if { [dict exists $config div2] } { + set div [dict get $config div2] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div + set go 1 + } + if { [dict exists $config div3] } { + set div [dict get $config div3] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div + set go 1 + } + if { [dict exists $config div4] } { + set div [dict get $config div4] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div + set go 1 + } + if { [dict exists $config div5] } { + set div [dict get $config div5] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div + set go 1 + } + if {$go != 0} { + # write pllcmd.GO; poll pllstat.GO + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } + } + mww [expr {$pll_addr + 0x0138}] 0x00 + + # 11 - wait at least 5 usec for reset to finish + # (assume covered by overheads including JTAG messaging) + + # 12 - clear PLLRST (bit 3) + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] + mww $pll_ctrl_addr $pll_ctrl + + # 13 - wait at least 8000 refclk cycles for PLL to lock + # if we assume 24 MHz (slowest osc), that's 1/3 msec + sleep 3 + + # 14 - set PLLEN (bit 0) ... leave bypass mode + set pll_ctrl [expr {$pll_ctrl | 0x0001}] + mww $pll_ctrl_addr $pll_ctrl +} + +# PLL version 0x03: tested on dm365 +proc pll_v03_setup {pll_addr mult config} { + set pll_ctrl_addr [expr {$pll_addr + 0x100}] + set pll_secctrl_addr [expr {$pll_addr + 0x108}] + set pll_ctrl [mrw $pll_ctrl_addr] + + # 1 - power up the PLL + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] + mww $pll_ctrl_addr $pll_ctrl + + # 2 - clear PLLENSRC (bit 5) + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] + mww $pll_ctrl_addr $pll_ctrl + + # 2 - clear PLLEN (bit 0) ... enter bypass mode + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] + mww $pll_ctrl_addr $pll_ctrl + + # 3 - wait at least 4 refclk cycles + sleep 1 + + # 4 - set PLLRST (bit 3) + set pll_ctrl [expr {$pll_ctrl | 0x0008}] + mww $pll_ctrl_addr $pll_ctrl + + # 5 - wait at least 5 usec + sleep 1 + + # 6 - clear PLLRST (bit 3) + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] + mww $pll_ctrl_addr $pll_ctrl + + # 9 - optional: write prediv, postdiv, and pllm + mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}] + if { [dict exists $config prediv] } { + set div [dict get $config prediv] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div + } + if { [dict exists $config postdiv] } { + set div [dict get $config postdiv] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div + } + + # 10 - write start sequence to PLLSECCTL + mww $pll_secctrl_addr 0x00470000 + mww $pll_secctrl_addr 0x00460000 + mww $pll_secctrl_addr 0x00400000 + mww $pll_secctrl_addr 0x00410000 + + # 11 - optional: set plldiv1, plldiv2, ... + # NOTE: this assumes some registers have their just-reset values: + # - PLLSTAT.GOSTAT is clear when we enter + set aln 0 + if { [dict exists $config div1] } { + set div [dict get $config div1] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div + set aln [expr {$aln | 0x1}] + } else { + mww [expr {$pll_addr + 0x0118}] 0 + } + if { [dict exists $config div2] } { + set div [dict get $config div2] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div + set aln [expr {$aln | 0x2}] + } else { + mww [expr {$pll_addr + 0x011c}] 0 + } + if { [dict exists $config div3] } { + set div [dict get $config div3] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div + set aln [expr {$aln | 0x4}] + } else { + mww [expr {$pll_addr + 0x0120}] 0 + } + if { [dict exists $config oscdiv] } { + set div [dict get $config oscdiv] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0124}] $div + } else { + mww [expr {$pll_addr + 0x0124}] 0 + } + if { [dict exists $config div4] } { + set div [dict get $config div4] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div + set aln [expr {$aln | 0x8}] + } else { + mww [expr {$pll_addr + 0x0160}] 0 + } + if { [dict exists $config div5] } { + set div [dict get $config div5] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div + set aln [expr {$aln | 0x10}] + } else { + mww [expr {$pll_addr + 0x0164}] 0 + } + if { [dict exists $config div6] } { + set div [dict get $config div6] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0168}] $div + set aln [expr {$aln | 0x20}] + } else { + mww [expr {$pll_addr + 0x0168}] 0 + } + if { [dict exists $config div7] } { + set div [dict get $config div7] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x016c}] $div + set aln [expr {$aln | 0x40}] + } else { + mww [expr {$pll_addr + 0x016c}] 0 + } + if { [dict exists $config div8] } { + set div [dict get $config div8] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0170}] $div + set aln [expr {$aln | 0x80}] + } else { + mww [expr {$pll_addr + 0x0170}] 0 + } + if { [dict exists $config div9] } { + set div [dict get $config div9] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0174}] $div + set aln [expr {$aln | 0x100}] + } else { + mww [expr {$pll_addr + 0x0174}] 0 + } + if {$aln != 0} { + # clear pllcmd.GO + mww [expr {$pll_addr + 0x0138}] 0x00 + # write alignment flags + mww [expr {$pll_addr + 0x0140}] $aln + # write pllcmd.GO; poll pllstat.GO + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } + } + mww [expr {$pll_addr + 0x0138}] 0x00 + set addr [dict get $config ctladdr] + while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 } + + # 12 - set PLLEN (bit 0) ... leave bypass mode + set pll_ctrl [expr {$pll_ctrl | 0x0001}] + mww $pll_ctrl_addr $pll_ctrl +} + +# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain +# modules can be enabled. + +# prepare a non-DSP module to be enabled; finish with psc_go +proc psc_enable {module} { + set psc_addr 0x01c41000 + # write MDCTL + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f +} + +# prepare a non-DSP module to be reset; finish with psc_go +proc psc_reset {module} { + set psc_addr 0x01c41000 + # write MDCTL + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f +} + +# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc +proc psc_go {} { + set psc_addr 0x01c41000 + set ptstat_addr [expr {$psc_addr + 0x0128}] + + # just in case PTSTAT.go isn't clear + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } + + # write PTCMD.go ... ignoring any DSP power domain + mww [expr {$psc_addr + 0x0120}] 1 + + # wait for PTSTAT.go to clear (again ignoring DSP power domain) + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } +} + +# +# A reset using only SRST is a "Warm Reset", resetting everything in the +# chip except ARM emulation (and everything _outside_ the chip that hooks +# up to SRST). But many boards don't expose SRST via their JTAG connectors +# (it's not present on TI-14 headers). +# +# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except +# without any board-wide side effects, since it's triggered using JTAG using +# either (a) ARM watchdog timer, or (b) ICEpick. +# +proc davinci_wdog_reset {} { + set timer2_phys 0x01c21c00 + + # NOTE -- on entry + # - JTAG communication with the ARM *must* be working OK; this + # may imply using adaptive clocking or disabling WFI-in-idle + # - current target must be the DaVinci ARM + # - that ARM core must be halted + # - timer2 clock is still enabled (PSC 29 on most chips) + + # + # Part I -- run regardless of being halted via JTAG + # + # NOTE: for now, we assume there's no DSP that could control the + # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog + # suspend signal is controlled via ARM emulation suspend. + # + + # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 + + # + # Part II -- in case watchdog hasn't been set up + # + + # TCR: disable, force internal clock source + mww phys [expr {$timer2_phys + 0x20}] 0 + + # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) + mww phys [expr {$timer2_phys + 0x24}] 0 + mww phys [expr {$timer2_phys + 0x24}] 0x110b + + # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers + # so watchdog triggers ASAP + mww phys [expr {$timer2_phys + 0x10}] 0 + mww phys [expr {$timer2_phys + 0x14}] 0 + mww phys [expr {$timer2_phys + 0x18}] 0 + mww phys [expr {$timer2_phys + 0x1c}] 0 + + # WDTCR: put into pre-active state, then active + mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000 + mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000 + + # + # Part III -- it's ready to rumble + # + + # WDTCR: write invalid WDKEY to trigger reset + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 +} diff --git a/openocd-win/openocd/scripts/target/dragonite.cfg b/openocd-win/openocd/scripts/target/dragonite.cfg new file mode 100644 index 0000000..249de25 --- /dev/null +++ b/openocd-win/openocd/scripts/target/dragonite.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Marvell Dragonite CPU core +###################################### + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dragonite +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x121003d3 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME + +reset_config trst_and_srst +adapter srst delay 200 +jtag_ntrst_delay 200 diff --git a/openocd-win/openocd/scripts/target/dsp56321.cfg b/openocd-win/openocd/scripts/target/dsp56321.cfg new file mode 100644 index 0000000..fac0ccc --- /dev/null +++ b/openocd-win/openocd/scripts/target/dsp56321.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Script for freescale DSP56321 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp56321 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a big endian + set _ENDIAN big +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1181501d +} + +#jtag speed +adapter speed 4500 + +#has only srst +reset_config srst_only + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID + +#target configuration +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME + +#working area at base of ram +$_TARGETNAME configure -work-area-virt 0 diff --git a/openocd-win/openocd/scripts/target/dsp568013.cfg b/openocd-win/openocd/scripts/target/dsp568013.cfg new file mode 100644 index 0000000..5cf5c02 --- /dev/null +++ b/openocd-win/openocd/scripts/target/dsp568013.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Script for freescale DSP568013 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp568013 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a big endian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x01f2401d +} + +#jtag speed +adapter speed 800 + +reset_config srst_only + +#MASTER tap +jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID + +#CORE tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004 + +#target configuration - There is only 1 tap at a time, hence only 1 target is defined. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME + +# Setup the interesting tap +# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this) +jtag configure $_CHIPNAME.chp -event setup " + jtag tapenable $_TARGETNAME + poll off +" + +#select CORE tap by modifying the TLM register. +#to be used when MASTER tap is selected. +jtag configure $_TARGETNAME -event tap-enable " + irscan $_CHIPNAME.chp 0x05; + drscan $_CHIPNAME.chp 4 0x02; + jtag tapdisable $_CHIPNAME.chp; +" + +#select MASTER tap by modifying the TLM register. +#to be used when CORE tap is selected. +jtag configure $_CHIPNAME.chp -event tap-enable " + irscan $_TARGETNAME 0x08; + drscan $_TARGETNAME 4 0x1; + jtag tapdisable $_TARGETNAME; +" + +#disables the master tap +jtag configure $_TARGETNAME -event tap-disable " +" +#TODO FIND SMARTER WAY. + +jtag configure $_CHIPNAME.chp -event tap-disable " +" +#TODO FIND SMARTER WAY. + + +#working area at base of ram +$_TARGETNAME configure -work-area-virt 0 + +#setup flash +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/dsp568037.cfg b/openocd-win/openocd/scripts/target/dsp568037.cfg new file mode 100644 index 0000000..5d86811 --- /dev/null +++ b/openocd-win/openocd/scripts/target/dsp568037.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Script for freescale DSP568037 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp568037 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a big endian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x01f2801d +} + +#jtag speed +adapter speed 800 + +reset_config srst_only + +#MASTER tap +jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID + +#CORE tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004 + +#target configuration - There is only 1 tap at a time, hence only 1 target is defined. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME + +# Setup the interesting tap +jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME" + +#select CORE tap by modifying the TLM register. +#to be used when MASTER tap is selected. +jtag configure $_TARGETNAME -event tap-enable " + irscan $_CHIPNAME.chp 0x05; + drscan $_CHIPNAME.chp 4 0x02; + jtag tapdisable $_CHIPNAME.chp; +" + +#select MASTER tap by modifying the TLM register. +#to be used when CORE tap is selected. +jtag configure $_CHIPNAME.chp -event tap-enable " + irscan $_TARGETNAME 0x08; + drscan $_TARGETNAME 4 0x1; + jtag tapdisable $_TARGETNAME; +" + +#disables the master tap +jtag configure $_TARGETNAME -event tap-disable " +" +#TODO FIND SMARTER WAY. + +jtag configure $_CHIPNAME.chp -event tap-disable " +" +#TODO FIND SMARTER WAY. + + +#working area at base of ram +$_TARGETNAME configure -work-area-virt 0 + +#setup flash +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/efm32.cfg b/openocd-win/openocd/scripts/target/efm32.cfg new file mode 100644 index 0000000..2187c0a --- /dev/null +++ b/openocd-win/openocd/scripts/target/efm32.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Silicon Labs (formerly Energy Micro) EFM32 target +# +# Note: All EFM32 chips have SWD support, but only newer series 1 +# chips have JTAG support. +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME efm32 +} + +# Work-area is a space in RAM used for flash programming +# By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +adapter speed 1000 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME +flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME +flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/em357.cfg b/openocd-win/openocd/scripts/target/em357.cfg new file mode 100644 index 0000000..ddefa28 --- /dev/null +++ b/openocd-win/openocd/scripts/target/em357.cfg @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Target configuration for the Silicon Labs EM357 chips +# + +# +# em357 family supports JTAG and SWD transports +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME em357 +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x3ba00477 + } else { + set _CPUTAPID 0x1ba00477 + } +} + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x069a962b +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME em358 +} + +if { [info exists FLASHSIZE] } { + set _FLASHSIZE $FLASHSIZE +} else { + set _FLASHSIZE 0x30000 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +if { [using_jtag] } { + jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME + +if { ![using_hla]} { +# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup +# There is a bug in the chip, which means that when using external debuggers the chip +# may lock up in certain CPU clock modes. Affected modes are operating the CPU at +# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC +# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and +# require a pin reset or power cycle. +# +# for details, refer to: +# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf + cortex_m reset_config vectreset +} diff --git a/openocd-win/openocd/scripts/target/em358.cfg b/openocd-win/openocd/scripts/target/em358.cfg new file mode 100644 index 0000000..63f4088 --- /dev/null +++ b/openocd-win/openocd/scripts/target/em358.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the Silicon Labs EM358 chips + +# +# em357 family supports JTAG and SWD transports +# + +if { ![info exists CHIPNAME] } { + set CHIPNAME em358 +} + +if { ![info exists BSTAPID] } { + set BSTAPID 0x069aa62b +} + +# 512K of flash in the em358 chips +set FLASHSIZE 0x80000 +source [find target/em357.cfg] diff --git a/openocd-win/openocd/scripts/target/eos_s3.cfg b/openocd-win/openocd/scripts/target/eos_s3.cfg new file mode 100644 index 0000000..150ef4e --- /dev/null +++ b/openocd-win/openocd/scripts/target/eos_s3.cfg @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# QuickLogic EOS S3 +# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/ + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME eos_s3 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x80000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# For now we use SRAM only for software upload +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +adapter speed 4000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/epc9301.cfg b/openocd-win/openocd/scripts/target/epc9301.cfg new file mode 100644 index 0000000..41021d5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/epc9301.cfg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ep9301 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Force an error until we get a good number. + set _CPUTAPID 0xffffffff +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +adapter srst delay 100 +jtag_ntrst_delay 100 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1 + +#flash configuration +#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/esi32xx.cfg b/openocd-win/openocd/scripts/target/esi32xx.cfg new file mode 100644 index 0000000..a8b0823 --- /dev/null +++ b/openocd-win/openocd/scripts/target/esi32xx.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# EnSilica eSi-32xx SoC (eSi-RISC Family) +# http://www.ensilica.com/risc-ip/ +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME esi32xx +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x11234001 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu + +# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set +# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed. +if { [info exists CACHEARCH] } { + $_TARGETNAME esirisc cache_arch $CACHEARCH +} + +adapter speed 2000 + +reset_config none + +# The default linker scripts provided by the eSi-RISC toolchain do not +# specify attributes on memory regions, which results in incorrect +# application of software breakpoints by GDB. +gdb_breakpoint_override hard diff --git a/openocd-win/openocd/scripts/target/esp32.cfg b/openocd-win/openocd/scripts/target/esp32.cfg new file mode 100644 index 0000000..b30a170 --- /dev/null +++ b/openocd-win/openocd/scripts/target/esp32.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# + +# Source the ESP common configuration file. +source [find target/esp_common.cfg] + +# Target specific global variables +set _CHIPNAME "esp32" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 3 +set _FLASH_VOLTAGE 3.3 +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004 + +if { [info exists ESP32_ONLYCPU] } { + set _ONLYCPU $ESP32_ONLYCPU +} + +if { [info exists ESP32_FLASH_VOLTAGE] } { + set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE +} + +proc esp32_memprot_is_enabled { } { + return 0 +} + +proc esp32_soc_reset { } { + soft_reset_halt +} + +create_esp_target $_ESP_ARCH + +source [find target/xtensa-core-esp32.cfg] diff --git a/openocd-win/openocd/scripts/target/esp32s2.cfg b/openocd-win/openocd/scripts/target/esp32s2.cfg new file mode 100644 index 0000000..4c1362a --- /dev/null +++ b/openocd-win/openocd/scripts/target/esp32s2.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# + +# Source the ESP common configuration file. +source [find target/esp_common.cfg] + +# Target specific global variables +set _CHIPNAME "esp32s2" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 1 +set _ESP_SMP_TARGET 0 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x3f41A004 + +proc esp32s2_memprot_is_enabled { } { + # IRAM0, DPORT_PMS_PRO_IRAM0_0_REG + if { [get_mmr_bit 0x3f4c1010 0] != 0 } { + return 1 + } + # DRAM0, DPORT_PMS_PRO_DRAM0_0_REG + if { [get_mmr_bit 0x3f4c1028 0] != 0 } { + return 1 + } + # PERI1, DPORT_PMS_PRO_DPORT_0_REG + if { [get_mmr_bit 0x3f4c103c 0] != 0 } { + return 1 + } + # PERI2, DPORT_PMS_PRO_AHB_0_REG + if { [get_mmr_bit 0x3f4c105c 0] != 0 } { + return 1 + } + return 0 +} + +proc esp32s2_soc_reset { } { + soft_reset_halt +} + +create_esp_target $_ESP_ARCH + +source [find target/xtensa-core-esp32s2.cfg] diff --git a/openocd-win/openocd/scripts/target/esp32s3.cfg b/openocd-win/openocd/scripts/target/esp32s3.cfg new file mode 100644 index 0000000..12c166c --- /dev/null +++ b/openocd-win/openocd/scripts/target/esp32s3.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# + +# Source the ESP common configuration file. +source [find target/esp_common.cfg] + +# Target specific global variables +set _CHIPNAME "esp32s3" +set _CPUTAPID 0x120034e5 +set _ESP_ARCH "xtensa" +set _ONLYCPU 3 +set _ESP_SMP_TARGET 1 +set _ESP_SMP_BREAK 1 +set _ESP_EFUSE_MAC_ADDR_REG 0x60007044 + +if { [info exists ESP32_S3_ONLYCPU] } { + set _ONLYCPU $ESP32_S3_ONLYCPU +} + +proc esp32s3_memprot_is_enabled { } { + # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10C0 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C1124 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C11D0 0] != 0 } { + return 1 + } + # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10D8 0] != 0 } { + return 1 + } + # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10FC 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C10E4 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C10F0 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1104 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1114 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C119C 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1248 0] != 0 } { + return 1 + } + return 0 +} + +proc esp32s3_soc_reset { } { + soft_reset_halt +} + +create_esp_target $_ESP_ARCH + +source [find target/xtensa-core-esp32s3.cfg] diff --git a/openocd-win/openocd/scripts/target/esp_common.cfg b/openocd-win/openocd/scripts/target/esp_common.cfg new file mode 100644 index 0000000..ac8cd6a --- /dev/null +++ b/openocd-win/openocd/scripts/target/esp_common.cfg @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# + +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +# Common ESP chips definitions + +# Espressif supports only NuttX in the upstream. +# FreeRTOS support is not upstreamed yet. +set _RTOS "hwthread" +if { [info exists ESP_RTOS] } { + set _RTOS "$ESP_RTOS" +} + +# by default current dir (when OOCD has been started) +set _SEMIHOST_BASEDIR "." +if { [info exists ESP_SEMIHOST_BASEDIR] } { + set _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR +} + +proc set_esp_common_variables { } { + global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET + global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 + global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED + + # For now we support dual core at most. + if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} { + set _TARGETNAME_0 $_CHIPNAME + set _CPUNAME_0 cpu + set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0 + } else { + set _CPUNAME_0 cpu0 + set _CPUNAME_1 cpu1 + set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0 + set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1 + set _TAPNAME_0 $_TARGETNAME_0 + set _TAPNAME_1 $_TARGETNAME_1 + } + + set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable" + set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset" + set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled" +} + +proc create_esp_jtag { } { + global _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU + jtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID + if { $_ONLYCPU != 1 } { + jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID + } elseif [info exists _CPUNAME_1] { + jtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID + } +} + +proc create_openocd_targets { } { + global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU + + target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS + if { $_ONLYCPU != 1 } { + target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS + target smp $_TARGETNAME_0 $_TARGETNAME_1 + } +} + +proc create_esp_target { ARCH } { + set_esp_common_variables + create_esp_jtag + create_openocd_targets + configure_openocd_events + + if { $ARCH == "xtensa"} { + configure_esp_xtensa_default_settings + } else { + # riscv targets are not upstreamed yet. + # they can be found at the official Espressif fork. + } +} + +#################### Set event handlers and default settings #################### + +proc configure_event_examine_end { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } + } +} + +proc configure_event_reset_assert_post { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event reset-assert-post { + global _ESP_SOC_RESET + $_ESP_SOC_RESET + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event reset-assert-post { + global _ESP_SOC_RESET + $_ESP_SOC_RESET + } + } +} + +proc configure_event_halted { } { + global _TARGETNAME_0 + + $_TARGETNAME_0 configure -event halted { + global _ESP_WDT_DISABLE + $_ESP_WDT_DISABLE + esp halted_event_handler + } +} + +proc configure_event_gdb_attach { } { + global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU + + $_TARGETNAME_0 configure -event gdb-attach { + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + } + # necessary to auto-probe flash bank when GDB is connected and generate proper memory map + halt 1000 + if { [$_ESP_MEMPROT_IS_ENABLED] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } + } + + if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event gdb-attach { + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut + } + # necessary to auto-probe flash bank when GDB is connected + halt 1000 + if { [$_ESP_MEMPROT_IS_ENABLED] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } + } + } +} + +proc configure_openocd_events { } { + configure_event_examine_end + configure_event_reset_assert_post + configure_event_gdb_attach +} + +proc configure_esp_xtensa_default_settings { } { + global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME + + $_TARGETNAME_0 xtensa maskisr on + if { $_ESP_SMP_BREAK != 0 } { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + } + + gdb_breakpoint_override hard + + if { [info exists _FLASH_VOLTAGE] } { + $_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE + } +} diff --git a/openocd-win/openocd/scripts/target/exynos5250.cfg b/openocd-win/openocd/scripts/target/exynos5250.cfg new file mode 100644 index 0000000..a565022 --- /dev/null +++ b/openocd-win/openocd/scripts/target/exynos5250.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Samsung Exynos 5250 - dual-core ARM Cortex-A15 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME exynos5250 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap +target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap + +target smp ${_TARGETNAME}0 ${_TARGETNAME}1 diff --git a/openocd-win/openocd/scripts/target/faux.cfg b/openocd-win/openocd/scripts/target/faux.cfg new file mode 100644 index 0000000..71cb8b7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/faux.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#Script for faux target - used for testing + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91eb40a +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00000000 +} + + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +#target configuration +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +#dummy flash driver +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/feroceon.cfg b/openocd-win/openocd/scripts/target/feroceon.cfg new file mode 100644 index 0000000..593569d --- /dev/null +++ b/openocd-win/openocd/scripts/target/feroceon.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Marvell Feroceon CPU core +###################################### + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME feroceon +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x20a023d3 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME + +reset_config trst_and_srst +adapter srst delay 200 +jtag_ntrst_delay 200 diff --git a/openocd-win/openocd/scripts/target/fm3.cfg b/openocd-win/openocd/scripts/target/fm3.cfg new file mode 100644 index 0000000..0caf629 --- /dev/null +++ b/openocd-win/openocd/scripts/target/fm3.cfg @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MB9BF506 +# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME mb9bfxx6 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +# delays on reset lines +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +# Fujitsu Cortex-M3 reset configuration +reset_config trst_only + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +# MB9BF506 has 64kB of SRAM on its main system bus +$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0 + +# MB9BF506 has 512kB internal FLASH + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME + +# 4MHz / 6 = 666kHz, so use 500 +adapter speed 500 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/fm4.cfg b/openocd-win/openocd/scripts/target/fm4.cfg new file mode 100644 index 0000000..4318f2e --- /dev/null +++ b/openocd-win/openocd/scripts/target/fm4.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Spansion FM4 (ARM Cortex-M4) +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME fm4 +} + +source [find target/swj-dp.tcl] + +if { [info exists CPUTAPID] } { + set _CPU_TAPID $CPUTAPID +} elseif { [using_jtag] } { + set _CPU_TAPID 0x4ba00477 +} else { + set _CPU_TAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +adapter speed 500 + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/fm4_mb9bf.cfg b/openocd-win/openocd/scripts/target/fm4_mb9bf.cfg new file mode 100644 index 0000000..4bc579c --- /dev/null +++ b/openocd-win/openocd/scripts/target/fm4_mb9bf.cfg @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Spansion FM4 MB9BFxxx (ARM Cortex-M4) +# + +source [find target/fm4.cfg] + +# MB9BF566 M/N/R have 32 KB SRAM0 +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES diff --git a/openocd-win/openocd/scripts/target/fm4_s6e2cc.cfg b/openocd-win/openocd/scripts/target/fm4_s6e2cc.cfg new file mode 100644 index 0000000..7417d38 --- /dev/null +++ b/openocd-win/openocd/scripts/target/fm4_s6e2cc.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Spansion FM4 S6E2CC (ARM Cortex-M4) +# + +source [find target/fm4.cfg] + +# S6E2CC8 H/J/L have 96 KB SRAM0 +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x18000 +} + +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES +flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES diff --git a/openocd-win/openocd/scripts/target/gd32e23x.cfg b/openocd-win/openocd/scripts/target/gd32e23x.cfg new file mode 100644 index 0000000..2504274 --- /dev/null +++ b/openocd-win/openocd/scripts/target/gd32e23x.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for GigaDevice gd32e23x Cortex-M23 Series + +# https://www.gigadevice.com/microcontroller/gd32e230c8t6/ + +# +# gd32e23x devices support SWD transports only. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gd32e23x +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB (as found on some GD32E230s) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # this is the SW-DP tap id not the jtag tap id + set _CPUTAPID 0x0bf11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME + +# SWD speed (may be updated to higher value in board config file) +adapter speed 1000 + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Debug clock enable + # RCU_APB2EN |= DBGMCUEN + mmw 0x40021018 0x00400000 0 + + # Stop watchdog counters during halt + # DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD + mmw 0x40015804 0x00000307 0 +} diff --git a/openocd-win/openocd/scripts/target/gd32vf103.cfg b/openocd-win/openocd/scripts/target/gd32vf103.cfg new file mode 100644 index 0000000..0681243 --- /dev/null +++ b/openocd-win/openocd/scripts/target/gd32vf103.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# GigaDevice GD32VF103 target +# +# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ +# + +source [find mem_helper.tcl] + +transport select jtag + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gd32vf103 +} + +# The smallest RAM size 6kB (GD32VF103C4/T4/R4) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1800 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU +# does not allow the debugger to access memory. +# Stop watchdogs at least before flash programming. +$_TARGETNAME configure -event reset-init { + # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP + mmw 0xE0042004 0x00000300 0 +} diff --git a/openocd-win/openocd/scripts/target/gp326xxxa.cfg b/openocd-win/openocd/scripts/target/gp326xxxa.cfg new file mode 100644 index 0000000..447460b --- /dev/null +++ b/openocd-win/openocd/scripts/target/gp326xxxa.cfg @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Support for General Plus GP326XXXA chips +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME gp326xxxa +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4f1f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +# Use internal SRAM as a work area +$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0 + +# The chip has both lines connected together +reset_config trst_and_srst srst_pulls_trst +# This delay is needed otherwise communication with the target would +# be unreliable +adapter srst delay 100 + +# Set the adapter speed ridiculously low just in case we are +# running off of a 32kHz clock +adapter speed 2 + +proc gp32xxxa_halt_and_reset_control_registers {} { + # System control registers + set P_SYSTEM_CTRL_NEW 0xD0000008 + set P_SYSTEM_CTRL 0xD000000C + set P_SYSTEM_CLK_EN0 0xD0000010 + set P_SYSTEM_CLK_EN1 0xD0000014 + set P_SYSTEM_RESET_FLAG 0xD0000018 + set P_SYSTEM_CLK_CTRL 0xD000001C + set P_SYSTEM_LVR_CTRL 0xD0000020 + set P_SYSTEM_WATCHDOG_CTRL 0xD0000024 + set P_SYSTEM_PLLEN 0xD000005C + + # Since we can't use SRST without pulling TRST + # we can't assume the state of the clock configuration + # or watchdog settings. So reset them before porceeding + + # Set the adapter speed ridiculously low just in case we are + # running off of a 32kHz clock + adapter speed 2 + + # Disable any advanced features at this stage + arm7_9 dcc_downloads disable + arm7_9 fast_memory_access disable + + # Do a "soft reset" + soft_reset_halt + # Reset all system control registers to their default "after-reset" values + mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000 + mwh $P_SYSTEM_LVR_CTRL 0x0000 + + mwh $P_SYSTEM_CTRL_NEW 0x0001 + mwh $P_SYSTEM_CTRL 0x0001 + # Clear all reset flags by writing 1's + mwh $P_SYSTEM_RESET_FLAG 0x001C + + mwh $P_SYSTEM_CLK_CTRL 0x8000 + mwh $P_SYSTEM_CLK_EN0 0xFFFF + mwh $P_SYSTEM_CLK_EN1 0xFFFF + mwh $P_SYSTEM_PLLEN 0x0010 + + # Unfortunately there's no register that would allow us to + # know if PLL is locked. So just wait for 100ms in hopes that + # it would be enough. + sleep 100 + + # Now that we know that we are running at 48Mhz + # Increase JTAG speed and enable speed optimization features + adapter speed 5000 + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable +} + +$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers } diff --git a/openocd-win/openocd/scripts/target/hi3798.cfg b/openocd-win/openocd/scripts/target/hi3798.cfg new file mode 100644 index 0000000..722305d --- /dev/null +++ b/openocd-win/openocd/scripts/target/hi3798.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hisilicon Hi3798 Target + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME hi3798 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# declare the one JTAG tap to access the DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +# declare the 4 main application cores +set _TARGETNAME $_CHIPNAME.cpu +set _smp_command "" + +set $_TARGETNAME.cti(0) 0x80020000 +set $_TARGETNAME.cti(1) 0x80120000 +set $_TARGETNAME.cti(2) 0x80220000 +set $_TARGETNAME.cti(3) 0x80320000 + +set _cores 4 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + set _command "target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + #set _command "$_command -defer-examine" + set _smp_command "$_smp_command ${_TARGETNAME}$_core" + } else { + set _command "$_command -rtos hwthread" + set _smp_command "target smp ${_TARGETNAME}$_core" + } + + eval $_command +} + +eval $_smp_command diff --git a/openocd-win/openocd/scripts/target/hi6220.cfg b/openocd-win/openocd/scripts/target/hi6220.cfg new file mode 100644 index 0000000..5b03899 --- /dev/null +++ b/openocd-win/openocd/scripts/target/hi6220.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Hisilicon Hi6220 Target + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME hi6220 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +# declare the one JTAG tap to access the DAP +jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version + +# create the DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# declare the 8 main application cores +set _TARGETNAME $_CHIPNAME.cpu +set _smp_command "" + +set $_TARGETNAME.cti(0) 0x80198000 +set $_TARGETNAME.cti(1) 0x80199000 +set $_TARGETNAME.cti(2) 0x8019A000 +set $_TARGETNAME.cti(3) 0x8019B000 +set $_TARGETNAME.cti(4) 0x801D8000 +set $_TARGETNAME.cti(5) 0x801D9000 +set $_TARGETNAME.cti(6) 0x801DA000 +set $_TARGETNAME.cti(7) 0x801DB000 + +set _cores 8 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + set _command "target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command ${_TARGETNAME}$_core" + } else { + set _command "$_command -rtos hwthread" + set _smp_command "target smp ${_TARGETNAME}$_core" + } + + eval $_command +} + +eval $_smp_command + +cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000 + +# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin) +target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine + +# declare the auxiliary Cortex-A7 core +target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine diff --git a/openocd-win/openocd/scripts/target/hilscher_netx10.cfg b/openocd-win/openocd/scripts/target/hilscher_netx10.cfg new file mode 100644 index 0000000..054cac8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/hilscher_netx10.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#Hilscher netX 10 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx10 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/hilscher_netx50.cfg b/openocd-win/openocd/scripts/target/hilscher_netx50.cfg new file mode 100644 index 0000000..e8ba015 --- /dev/null +++ b/openocd-win/openocd/scripts/target/hilscher_netx50.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +################################################################################ +# Author: Michael Trensch (MTrensch@googlemail.com) +################################################################################ + +#Hilscher netX 50 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx50 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + +# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from +# DMA controller at init. This function will setup a dummy DMA to free this ares +# and must be called before using SDRAM +proc sdram_fix { } { + + mww 0x1c005830 0x00000001 + + mww 0x1c005104 0xBFFFFFFC + mww 0x1c00510c 0x00480001 + mww 0x1c005110 0x00000001 + + sleep 100 + + mww 0x1c00510c 0 + mww 0x1c005110 0 + mww 0x1c005830 0x00000000 + + puts "SDRAM Fix executed!" +} diff --git a/openocd-win/openocd/scripts/target/hilscher_netx500.cfg b/openocd-win/openocd/scripts/target/hilscher_netx500.cfg new file mode 100644 index 0000000..d838a6b --- /dev/null +++ b/openocd-win/openocd/scripts/target/hilscher_netx500.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#Hilscher netX 500 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx500 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926021 +} + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# that TAP is associated with a target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +proc mread32 {addr} { + return [read_memory $addr 32 1] +} + +# This function must be called on netX100/500 right after halt +# If it is called later the needed register cannot be written anymore +proc sdram_fix { } { + + set accesskey [mread32 0x00100070] + mww 0x00100070 $accesskey + mww 0x0010002c 0x00000001 + + if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} { + puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" + } else { + puts "SDRAM Fix succeeded!" + } +} diff --git a/openocd-win/openocd/scripts/target/icepick.cfg b/openocd-win/openocd/scripts/target/icepick.cfg new file mode 100644 index 0000000..5509532 --- /dev/null +++ b/openocd-win/openocd/scripts/target/icepick.cfg @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Copyright (C) 2011 by Karl Kurbjun +# Copyright (C) 2009 by David Brownell +# + +# Utilities for TI ICEpick-C/D used in most TI SoCs +# Details about the ICEPick are available in the the TRM for each SoC +# and http://processors.wiki.ti.com/index.php/ICEPICK + +# create "constants" +proc CONST { key } { + + array set constant { + # define ICEPick instructions + IR_BYPASS 0x00 + IR_ROUTER 0x02 + IR_CONNECT 0x07 + IF_BYPASS 0x3F + } + return $constant($key) +} + +# Instruction to connect to the icepick module +proc icepick_c_connect {jrc} { + + # Send CONNECT instruction in IR state + irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE + + # Send write and connect key + drscan $jrc 8 0x89 -endstate DRPAUSE +} + +# Instruction to disconnect to the icepick module +proc icepick_c_disconnect {jrc} { + + # Send CONNECT instruction in IR state + irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE + + # Send write and connect key + drscan $jrc 8 0x86 -endstate DRPAUSE +} + +# +# icepick_c_router: +# this function is for sending router commands +# arguments are: +# jrc: TAP name for the ICEpick +# rw: read/write (0 for read, 1 for write) +# block: icepick or DAP +# register: which register to read/write +# payload: value to read/write +# this function is for sending router commands +# +proc icepick_c_router {jrc rw block register payload} { + + set new_dr_value \ + [expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ + ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ] + +# echo "\tNew router value:\t0x[format %x $new_dr_value]" + + # select router + irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE + + # ROUTER instructions are 32 bits wide + set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE] +# echo "\tOld router value:\t0x[format %x $old_dr_value]" +} + +# Configure the icepick control register +proc icepick_c_setup {jrc} { + + # send a router write, block is 0, register is 1, value is 0x2100 + icepick_c_router $jrc 1 0x0 0x1 0x001000 +} + +# jrc == TAP name for the ICEpick +# port == a port number, 0..15 for debug tap, 16..31 for test tap +proc icepick_c_tapenable {jrc port} { + + if { ($port >= 0) && ($port < 16) } { + # Debug tap" + set tap $port + set block 0x2 + } elseif { $port < 32 } { + # Test tap + set tap [expr {$port - 16}] + set block 0x1 + } else { + echo "ERROR: Invalid ICEPick C port number: $port" + return + } + + # First CONNECT to the ICEPick +# echo "Connecting to ICEPick" + icepick_c_connect $jrc + +# echo "Configuring the ICEpick" + icepick_c_setup $jrc + + # NOTE: it's important not to enter RUN/IDLE state until + # done sending these instructions and data to the ICEpick. + # And never to enter RESET, which will disable the TAPs. + + # first enable power and clock for TAP + icepick_c_router $jrc 1 $block $tap 0x110048 + + # TRM states that the register should be read back here, skipped for now + + # enable debug "default" mode + icepick_c_router $jrc 1 $block $tap 0x112048 + + # TRM states that debug enable and debug mode should be read back and + # confirmed - skipped for now + + # Finally select the tap + icepick_c_router $jrc 1 $block $tap 0x112148 + + # Enter the bypass state + irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE + runtest 10 +} + +# jrc == TAP name for the ICEpick +# coreid== core id number 0..15 (not same as port number!) +proc icepick_d_set_core_control {jrc coreid value } { + icepick_c_router $jrc 1 0x6 $coreid $value +} + +# jrc == TAP name for the ICEpick +# port == a port number, 0..15 +# Follow the sequence described in +# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf +proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } { + + # First CONNECT to the ICEPick + icepick_c_connect $jrc + icepick_c_setup $jrc + + # Select the port + icepick_c_router $jrc 1 0x2 $port 0x2108 + + # Set icepick core control for $coreid + icepick_d_set_core_control $jrc $coreid $value + + # Enter the bypass state + irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE + runtest 10 +} + +# This function uses the ICEPick to send a warm system reset +proc icepick_c_wreset {jrc} { + + # send a router write, block is 0, register is 1, value is 0x2100 + icepick_c_router $jrc 1 0x0 0x1 0x002101 +} diff --git a/openocd-win/openocd/scripts/target/imx.cfg b/openocd-win/openocd/scripts/target/imx.cfg new file mode 100644 index 0000000..d76f60e --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# utility fn's for Freescale i.MX series + +global TARGETNAME +set TARGETNAME $_TARGETNAME + +# rewrite commands of the form below to arm11 mcr... +# Data.Set c15:0x042f %long 0x40000015 +proc setc15 {regs value} { + global TARGETNAME + + echo [format "set p15 0x%04x, 0x%08x" $regs $value] + + arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value +} + + +proc imx3x_reset {} { + # this reset script comes from the Freescale PDK + # + # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK + + echo "Target Setup: initialize DRAM controller and peripherals" + +# Data.Set c15:0x01 %long 0x00050078 + setc15 0x01 0x00050078 + + echo "configuring CP15 for enabling the peripheral bus" +# Data.Set c15:0x042f %long 0x40000015 + setc15 0x042f 0x40000015 +} diff --git a/openocd-win/openocd/scripts/target/imx21.cfg b/openocd-win/openocd/scripts/target/imx21.cfg new file mode 100644 index 0000000..7c9cca3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx21.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#use combined on interfaces or targets that can't set TRST/SRST separately +# +# Hmmm.... should srst_pulls_trst be used here like i.MX27??? +reset_config trst_and_srst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx21 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# Note above there is 1 tap + +# The CPU tap +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0792611f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/imx25.cfg b/openocd-win/openocd/scripts/target/imx25.cfg new file mode 100644 index 0000000..ed94cc0 --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx25.cfg @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# imx25 config +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx25 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x1b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0 + +if { [info exists SDMATAPID] } { + set _SDMATAPID $SDMATAPID +} else { + set _SDMATAPID 0x0882301d +} +jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN \ + -chain-position $_TARGETNAME + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/imx27.cfg b/openocd-win/openocd/scripts/target/imx27.cfg new file mode 100644 index 0000000..c79d85e --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx27.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3" +# SRST pulls TRST +# +# Without setting these options correctly you'll see all sorts +# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset +# failing, etc. +reset_config trst_and_srst srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx27 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# Note above there are 2 taps + +# trace buffer +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x1b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID + +# The CPU tap +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926121 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME +# REVISIT what operating environment sets up this virtual address mapping? +$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \ + -work-area-size 0x8000 -work-area-backup 1 +# Internal to the chip, there is 45K of SRAM +# + +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/imx28.cfg b/openocd-win/openocd/scripts/target/imx28.cfg new file mode 100644 index 0000000..d52fc4e --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx28.cfg @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# i.MX28 config file. +# based off of the imx21.cfg file. + +reset_config trst_and_srst + +#jtag nTRST and nSRST delay +adapter srst delay 100 +jtag_ntrst_delay 100 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx28 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# Note above there is 1 tap + +# The CPU tap +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x079264f3 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +# Create the GDB Target. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/imx31.cfg b/openocd-win/openocd/scripts/target/imx31.cfg new file mode 100644 index 0000000..10e9fef --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx31.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# imx31 config +# + +reset_config trst_and_srst srst_gates_jtag + +adapter srst delay 5 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx31 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07b3601d +} + +if { [info exists SDMATAPID] } { + set _SDMATAPID $SDMATAPID +} else { + set _SDMATAPID 0x2190101d +} + +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x2b900f0f +} + +#======================================== + +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID + +# The "SDMA" - <S>mart <DMA> controller debug tap +# Based on some IO pins - this can be disabled & removed +# See diagram: 6-14 +# SIGNAL NAME: +# SJC_MOD - controls multiplexer - disables ARM1136 +# SDMA_BYPASS - disables SDMA - +# +# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +# No IDCODE for this TAP +jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0 + +# Per section 40.17.1, table 40-85 the IR register is 4 bits +# But this conflicts with Diagram 6-13, "3bits ir and drs" +jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME + + +proc power_restore {} { echo "Sensed power restore. No action." } +proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/imx35.cfg b/openocd-win/openocd/scripts/target/imx35.cfg new file mode 100644 index 0000000..fa173bb --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx35.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# imx35 config +# + +reset_config trst_and_srst srst_gates_jtag +jtag_ntrst_delay 100 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx35 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07b3601d +} + +if { [info exists SDMATAPID] } { + set _SDMATAPID $SDMATAPID +} else { + set _SDMATAPID 0x0882601d +} + +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x2b900f0f +} + +#======================================== + +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +# No IDCODE for this TAP +jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0 + +jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME + +proc power_restore {} { echo "Sensed power restore. No action." } +proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/imx51.cfg b/openocd-win/openocd/scripts/target/imx51.cfg new file mode 100644 index 0000000..fc3dfa9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx51.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Freescale i.MX51 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx51 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x1ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf + +# SJC +if { [info exists SJC_TAPID] } { + set _SJC_TAPID SJC_TAPID +} else { + set _SJC_TAPID 0x0190c01d +} + +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \ + -expected-id $_SJC_TAPID -ignore-version + +# GDB target: Cortex-A8, using DAP +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap + +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" + +proc imx51_dbginit {target} { + # General Cortex-A8 debug initialisation + cortex_a dbginit +} + +$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/imx53.cfg b/openocd-win/openocd/scripts/target/imx53.cfg new file mode 100644 index 0000000..855a6ae --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx53.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Freescale i.MX53 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx53 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x1ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf + +# SJC +if { [info exists SJC_TAPID] } { + set _SJC_TAPID SJC_TAPID +} else { + set _SJC_TAPID 0x0190d01d +} + +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \ + -expected-id $_SJC_TAPID -ignore-version + +# GDB target: Cortex-A8, using DAP +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap + +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" + +proc imx53_dbginit {target} { + # General Cortex-A8 debug initialisation + cortex_a dbginit +} + +$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/imx6.cfg b/openocd-win/openocd/scripts/target/imx6.cfg new file mode 100644 index 0000000..c9b6acf --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx6.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale i.MX6 series +# +# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL +# +# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx6 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f + +# System JTAG Controller + +# List supported SJC TAPIDs from imx reference manuals: +set _SJC_TAPID_6Q 0x0191c01d +set _SJC_TAPID_6D 0x0191e01d +set _SJC_TAPID_6QP 0x3191c01d +set _SJC_TAPID_6DP 0x3191d01d +set _SJC_TAPID_6DL 0x0891a01d +set _SJC_TAPID_6S 0x0891b01d +set _SJC_TAPID_6SL 0x0891f01d +set _SJC_TAPID_6SLL 0x088c201d + +# Allow external override of the first SJC TAPID +if { [info exists SJC_TAPID] } { + set _SJC_TAPID $SJC_TAPID +} else { + set _SJC_TAPID $_SJC_TAPID_6Q +} + +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ + -ignore-version \ + -expected-id $_SJC_TAPID \ + -expected-id $_SJC_TAPID_6QP \ + -expected-id $_SJC_TAPID_6DP \ + -expected-id $_SJC_TAPID_6D \ + -expected-id $_SJC_TAPID_6DL \ + -expected-id $_SJC_TAPID_6S \ + -expected-id $_SJC_TAPID_6SL \ + -expected-id $_SJC_TAPID_6SLL + +# GDB target: Cortex-A9, using DAP, configuring only one core +# Base addresses of cores: +# core 0 - 0x82150000 +# core 1 - 0x82152000 +# core 2 - 0x82154000 +# core 3 - 0x82156000 +set _TARGETNAME $_CHIPNAME.cpu.0 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x82150000 + +# some TCK cycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" + +proc imx6_dbginit {target} { + # General Cortex-A8/A9 debug initialisation + cortex_a dbginit +} + +# Slow speed to be sure it will work +adapter speed 1000 +$_TARGETNAME configure -event reset-start { adapter speed 1000 } + +$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/imx6sx.cfg b/openocd-win/openocd/scripts/target/imx6sx.cfg new file mode 100644 index 0000000..3d4240a --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx6sx.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale i.MX6SoloX +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx6sx +} + +# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9 +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4 + +jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9 + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f + +# System JTAG Controller +if { [info exists SJC_TAPID] } { + set _SJC_TAPID $SJC_TAPID +} else { + set _SJC_TAPID 0x0891c01d +} +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ + -expected-id $_SJC_TAPID -ignore-version + +# Cortex-A9 (boot core) +target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \ + -coreid 0 -dbgbase 0x82150000 + +# Cortex-M4 (default off) +target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \ + -ap-num 0 -defer-examine + +# AHB mem-ap target +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0 + +# Default target is Cortex-A9 +targets $_CHIPNAME.cpu_a9 diff --git a/openocd-win/openocd/scripts/target/imx6ul.cfg b/openocd-win/openocd/scripts/target/imx6ul.cfg new file mode 100644 index 0000000..354745e --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx6ul.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx6ul +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# SDMA / no IDCODE +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f + +# System JTAG Controller +set _SJC_TAPID_6UL 0x0891d01d +set _SJC_TAPID_6ULL 0x0891e01d +set _SJC_TAPID_6ULZ 0x1891e01d + +# Allow external override of the first SJC TAPID +if { [info exists SJC_TAPID] } { + set _SJC_TAPID $SJC_TAPID +} else { + set _SJC_TAPID $_SJC_TAPID_6UL +} + +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ + -ignore-version \ + -expected-id $_SJC_TAPID \ + -expected-id $_SJC_TAPID_6ULL \ + -expected-id $_SJC_TAPID_6ULZ \ + +# Create DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Main AHB bus +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# Cortex-A7 single core +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000 diff --git a/openocd-win/openocd/scripts/target/imx7.cfg b/openocd-win/openocd/scripts/target/imx7.cfg new file mode 100644 index 0000000..bd9e3dd --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx7.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx7 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# +# Cortex-A7 target +# +# GDB target: Cortex-A7, using DAP, configuring only one core +# Base addresses of cores: +# core 0 - 0x80070000 +# core 1 - 0x80072000 +set _TARGETNAME $_CHIPNAME.cpu_a7 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x80070000 + +target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x80072000 -defer-examine +# +# Cortex-M4 target +# +set _TARGETNAME_2 $_CHIPNAME.cpu_m4 +target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \ + -defer-examine + +# +# AHB mem-ap target +# +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +targets $_TARGETNAME.0 diff --git a/openocd-win/openocd/scripts/target/imx7ulp.cfg b/openocd-win/openocd/scripts/target/imx7ulp.cfg new file mode 100644 index 0000000..1467f7c --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx7ulp.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP i.MX7ULP: Cortex-A7 + Cortex-M4 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx7ulp +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + # TAPID is from FreeScale! + set _DAP_TAPID 0x188e101d +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Cortex-A7 +target create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x80030000 + +# Cortex-M4 +# Boots by default so don't defer examination +target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3 + +# AHB main soc bus +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# Default is Cortex-A7 +targets $_CHIPNAME.cpu_a7 diff --git a/openocd-win/openocd/scripts/target/imx8m.cfg b/openocd-win/openocd/scripts/target/imx8m.cfg new file mode 100644 index 0000000..6938090 --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx8m.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# configuration file for NXP i.MX8M family of SoCs +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8m +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 1 +} + +# CoreSight Debug Access Port +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# the DAP tap +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + set _command "$_command -rtos hwthread" + set _smp_command "target smp $_TARGETNAME.$_core" + } + + eval $_command +} + +eval $_smp_command + +# declare the auxiliary Cortex-M4 core on AP #4 +target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \ + -defer-examine + +# AHB-AP for direct access to soc bus +target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# default target is A53 core 0 +targets $_TARGETNAME.0 diff --git a/openocd-win/openocd/scripts/target/imx8qm.cfg b/openocd-win/openocd/scripts/target/imx8qm.cfg new file mode 100644 index 0000000..33f9ca1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/imx8qm.cfg @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP i.MX8QuadMax +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8qm +} + +# CoreSight Debug Access Port (DAP) +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + # TAPID is from FreeScale! + set _DAP_TAPID 0x1890101d +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# AXI: Main SOC bus on AP #0 +target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# 4x Cortex-A53 on AP #6 +set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0] +cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1] +cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2] +cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3] +target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0] +target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine +target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine +target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine + +# 2x Cortex-A72 on AP #6 +set _A72_DBGBASE {0x80210000 0x80310000} +set _A72_CTIBASE {0x80220000 0x80220000} + +cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0] +cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \ + -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1] +target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine +target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine + +# All Cortex-A in SMP +target smp \ + $_CHIPNAME.a53.0 \ + $_CHIPNAME.a53.1 \ + $_CHIPNAME.a53.2 \ + $_CHIPNAME.a53.3 \ + $_CHIPNAME.a72.0 \ + $_CHIPNAME.a72.1 + +# SCU: Cortex-M4 core +# always running imx SC firmware +target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1 + +# AHB from SCU perspective +target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4 + +# Cortex-M4 M4_0 core on AP #2 (default off) +target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \ + -defer-examine + +# Cortex-M4 M4_1 core on AP #3 (default off) +target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \ + -defer-examine + +# Debug APB bus +target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6 + +# Default target is boot core a53.0 +targets $_CHIPNAME.a53.0 diff --git a/openocd-win/openocd/scripts/target/infineon/tle987x.cfg b/openocd-win/openocd/scripts/target/infineon/tle987x.cfg new file mode 100644 index 0000000..ac3db6c --- /dev/null +++ b/openocd-win/openocd/scripts/target/infineon/tle987x.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz) +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME tle987x +} + +source [find target/swj-dp.tcl] + +if { [info exists CPU_SWD_TAPID] } { + set _CPU_SWD_TAPID $CPU_SWD_TAPID +} else { + set _CPU_SWD_TAPID 0x2BA01477 +} + +if { [using_jtag] } { + # JTAG not supported, only SWD + set _CPU_TAPID 0 +} else { + set _CPU_TAPID $_CPU_SWD_TAPID +} + +swj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { ![using_hla] } { + cortex_m reset_config sysresetreq +} + +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/is5114.cfg b/openocd-win/openocd/scripts/target/is5114.cfg new file mode 100644 index 0000000..d0b1d92 --- /dev/null +++ b/openocd-win/openocd/scripts/target/is5114.cfg @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Insilica IS-5114 +# AKA: Atmel AT76C114 - an ARM946 chip +# ATMEL sold his product line to Insilica... + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME is5114 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Force an error until we get a good number. + set _CPUTAPID 0xffffffff +} + +# jtag speed. We need to stick to 16kHz until we've finished reset. +adapter speed 16 + +reset_config trst_and_srst + +# Do not specify a tap id here... +jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 +# This is the "arm946" chip. +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf +jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 + + +#arm946e-s and +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-start { adapter speed 16 } +$_TARGETNAME configure -event reset-init { + # We can increase speed now that we know the target is halted. + adapter speed 3000 +} +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1 diff --git a/openocd-win/openocd/scripts/target/ixp42x.cfg b/openocd-win/openocd/scripts/target/ixp42x.cfg new file mode 100644 index 0000000..5c8e903 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ixp42x.cfg @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#xscale ixp42x CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ixp42x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN big +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x19274013 +} +set _CPUTAPID2 0x19275013 +set _CPUTAPID3 0x19277013 +set _CPUTAPID4 0x29274013 +set _CPUTAPID5 0x29275013 +set _CPUTAPID6 0x29277013 + +jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME + + +# register constants for IXP42x SDRAM controller +global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD +global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD +set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000 +set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001 + +global IXP42x_SDRAM_CL3 +global IXP42x_SDRAM_CL2 +set IXP42x_SDRAM_CL3 0x0008 +set IXP42x_SDRAM_CL2 0x0000 + +global IXP42x_SDRAM_8MB_2Mx32_1BANK +global IXP42x_SDRAM_16MB_2Mx32_2BANK +global IXP42x_SDRAM_16MB_4Mx16_1BANK +global IXP42x_SDRAM_32MB_4Mx16_2BANK +global IXP42x_SDRAM_32MB_8Mx16_1BANK +global IXP42x_SDRAM_64MB_8Mx16_2BANK +global IXP42x_SDRAM_64MB_16Mx16_1BANK +global IXP42x_SDRAM_128MB_16Mx16_2BANK +global IXP42x_SDRAM_128MB_32Mx16_1BANK +global IXP42x_SDRAM_256MB_32Mx16_2BANK + +set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030 +set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031 +set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032 +set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033 +set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010 +set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011 +set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012 +set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013 +set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014 +set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015 + + +# helper function to init SDRAM on IXP42x. +# SDRAM_CFG: one of IXP42X_SDRAM_xxx +# REFRESH: refresh counter reload value (integer) +# CASLAT: 2 or 3 +proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { + + switch $CASLAT { + 2 { + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ] + set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD + } + 3 { + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ] + set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD + } + default { error [format "unsupported cas latency \"%s\" " $CASLAT] } + } + echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH] + + mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3 + mww 0xCC000004 0 ;# disable refresh + mww 0xCC000008 3 ;# NOP + sleep 100 + mww 0xCC000004 $REFRESH ;# set refresh counter + mww 0xCC000008 2 ;# Precharge All Banks + sleep 100 + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 4 ;# Auto Refresh + mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3 +} + +proc ixp42x_set_bigendian { } { + reg XSCALE_CTRL 0xF8 +} diff --git a/openocd-win/openocd/scripts/target/k1921vk01t.cfg b/openocd-win/openocd/scripts/target/k1921vk01t.cfg new file mode 100644 index 0000000..a9500ef --- /dev/null +++ b/openocd-win/openocd/scripts/target/k1921vk01t.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# K1921VK01T +# http://niiet.ru/chips/nis?id=354 + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME k1921vk01t +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + # SWD IDCODE + set _CPUTAPID 0x2ba01477 + } +} +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME + +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/k40.cfg b/openocd-win/openocd/scripts/target/k40.cfg new file mode 100644 index 0000000..33e8235 --- /dev/null +++ b/openocd-win/openocd/scripts/target/k40.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Kinetis K40 devices +# + +set CHIPNAME k40 +source [find target/kx.cfg] diff --git a/openocd-win/openocd/scripts/target/k60.cfg b/openocd-win/openocd/scripts/target/k60.cfg new file mode 100644 index 0000000..3b89102 --- /dev/null +++ b/openocd-win/openocd/scripts/target/k60.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Kinetis K60 devices +# + +set CHIPNAME k60 +source [find target/kx.cfg] diff --git a/openocd-win/openocd/scripts/target/ke0x.cfg b/openocd-win/openocd/scripts/target/ke0x.cfg new file mode 100644 index 0000000..b357767 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ke0x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Kinetis KE0x and KEAx series devices +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ke +} + +# Work-area is a space in RAM used for flash programming +# By default use 1kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME + +adapter speed 1000 + +reset_config srst_nogate + +if {![using_hla]} { + + # It is important that "kinetis_ke mdm check_security" is called for + # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start' + # causes "kinetis_ke mdm check_security" to fail the first time openocd + # calls it when it tries to connect after the CPU has been power-cycled. + $_CHIPNAME.cpu configure -event examine-end { + kinetis_ke mdm check_security + } + + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/ke1xf.cfg b/openocd-win/openocd/scripts/target/ke1xf.cfg new file mode 100644 index 0000000..86a1f3b --- /dev/null +++ b/openocd-win/openocd/scripts/target/ke1xf.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP (Freescale) Kinetis KE1xF devices +# + +set CHIPNAME ke + +source [find target/kx.cfg] diff --git a/openocd-win/openocd/scripts/target/ke1xz.cfg b/openocd-win/openocd/scripts/target/ke1xz.cfg new file mode 100644 index 0000000..9e91542 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ke1xz.cfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP (Freescale) Kinetis KE1xZ devices +# + +set CHIPNAME ke + +source [find target/klx.cfg] diff --git a/openocd-win/openocd/scripts/target/kl25.cfg b/openocd-win/openocd/scripts/target/kl25.cfg new file mode 100644 index 0000000..916edf6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/kl25.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Kinetis KL25 devices +# + +set CHIPNAME kl25 +source [find target/klx.cfg] diff --git a/openocd-win/openocd/scripts/target/kl46.cfg b/openocd-win/openocd/scripts/target/kl46.cfg new file mode 100644 index 0000000..bf6b244 --- /dev/null +++ b/openocd-win/openocd/scripts/target/kl46.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Kinetis KL46 devices +# + +set CHIPNAME kl46 +source [find target/klx.cfg] diff --git a/openocd-win/openocd/scripts/target/klx.cfg b/openocd-win/openocd/scripts/target/klx.cfg new file mode 100644 index 0000000..cd236b3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/klx.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP (former Freescale) Kinetis KL series devices +# Also used for Cortex-M0+ equipped members of KVx and KE1xZ series +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME klx +} + +# Work-area is a space in RAM used for flash programming +# By default use 1KiB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.pflash +flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME +kinetis create_banks + +# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual +# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode; +# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency. +adapter speed 1000 + +reset_config srst_nogate + +if {[using_hla]} { + echo "" + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions." + echo " A high level adapter (like a ST-Link) you are currently using cannot access" + echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your" + echo " configuration. Also security locked state of the device will not be reported." + echo "" + echo " Be very careful as you can lock the device though there is no way to unlock" + echo " it without mass erase. Don't set write protection on the first block." + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo "" +} else { + # Detect secured MCU + $_TARGETNAME configure -event examine-fail { + kinetis mdm check_security + } + + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +# Disable watchdog not to disturb OpenOCD algorithms running on MCU +# (e.g. armv7m_checksum_memory() in verify_image) +# Flash driver also disables watchdog before FTFA flash programming. +$_TARGETNAME configure -event reset-init { + kinetis disable_wdog +} diff --git a/openocd-win/openocd/scripts/target/ks869x.cfg b/openocd-win/openocd/scripts/target/ks869x.cfg new file mode 100644 index 0000000..06e710b --- /dev/null +++ b/openocd-win/openocd/scripts/target/ks869x.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ARM920T CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ks869x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x00922f0f +} + +adapter speed 6000 + +# jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0 + +# speed up memory downloads +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/kx.cfg b/openocd-win/openocd/scripts/target/kx.cfg new file mode 100644 index 0000000..c87116b --- /dev/null +++ b/openocd-win/openocd/scripts/target/kx.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP (former Freescale) Kinetis Kx series devices +# Also used for Cortex-M4 equipped members of KVx and KE1xF series +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME kx +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.pflash +flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME +kinetis create_banks + +adapter speed 1000 + +reset_config srst_nogate + +if {[using_hla]} { + echo "" + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo " Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions." + echo " A high level adapter (like a ST-Link) you are currently using cannot access" + echo " the MDM-AP, so commands like 'mdm mass_erase' are not available in your" + echo " configuration. Also security locked state of the device will not be reported." + echo " Expect problems connecting to a blank device without boot ROM." + echo "" + echo " Be very careful as you can lock the device though there is no way to unlock" + echo " it without mass erase. Don't set write protection on the first block." + echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!" + echo "" +} else { + # Detect secured MCU or boot lock-up in RESET/WDOG loop + $_TARGETNAME configure -event examine-fail { + kinetis mdm check_security + } + # During RESET/WDOG loop the target is sometimes falsely examined + $_TARGETNAME configure -event examine-end { + kinetis mdm check_security + } + + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +# Disable watchdog not to disturb OpenOCD algorithms running on MCU +# (e.g. armv7m_checksum_memory() in verify_image) +# Flash driver also disables watchdog before FTFA flash programming. +$_TARGETNAME configure -event reset-init { + kinetis disable_wdog +} diff --git a/openocd-win/openocd/scripts/target/lpc11xx.cfg b/openocd-win/openocd/scripts/target/lpc11xx.cfg new file mode 100644 index 0000000..d288e2a --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc11xx.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC11xx Cortex-M0 with at least 1kB SRAM +set CHIPNAME lpc11xx +set CHIPSERIES lpc1100 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x400 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc12xx.cfg b/openocd-win/openocd/scripts/target/lpc12xx.cfg new file mode 100644 index 0000000..ace5e06 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc12xx.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC12xx Cortex-M0 with at least 4kB SRAM +set CHIPNAME lpc12xx +set CHIPSERIES lpc1200 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x1000 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc13xx.cfg b/openocd-win/openocd/scripts/target/lpc13xx.cfg new file mode 100644 index 0000000..5ac29d3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc13xx.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC13xx Cortex-M3 with at least 4kB SRAM +set CHIPNAME lpc13xx +set CHIPSERIES lpc1300 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x1000 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc17xx.cfg b/openocd-win/openocd/scripts/target/lpc17xx.cfg new file mode 100644 index 0000000..35d8bad --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc17xx.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC17xx Cortex-M3 with at least 8kB SRAM +set CHIPNAME lpc17xx +set CHIPSERIES lpc1700 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x2000 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc1850.cfg b/openocd-win/openocd/scripts/target/lpc1850.cfg new file mode 100644 index 0000000..6dd1ab7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc1850.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/swj-dp.tcl] + +adapter speed 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc1850 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} +# +# M3 JTAG mode TAP +# +if { [info exists M3_JTAG_TAPID] } { + set _M3_JTAG_TAPID $M3_JTAG_TAPID +} else { + set _M3_JTAG_TAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3 + +set _TARGETNAME $_CHIPNAME.m3 +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/lpc1xxx.cfg b/openocd-win/openocd/scripts/target/lpc1xxx.cfg new file mode 100644 index 0000000..70d26d2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc1xxx.cfg @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts +# +# !!!!!! +# +# This file should not be included directly, rather by the lpc11xx.cfg, +# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the +# appropriate values. +# +# !!!!!! + +# LPC8xx chips support only SWD transport. +# LPC11xx chips support only SWD transport. +# LPC12xx chips support only SWD transport. +# LPC11Uxx chips support only SWD transports. +# LPC13xx chips support only SWD transports. +# LPC17xx chips support both JTAG and SWD transports. +# LPC40xx chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." +} + +if { [info exists CHIPSERIES] } { + # Validate chip series is supported + if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { + error "Unsupported LPC1xxx chip series specified." + } + set _CHIPSERIES $CHIPSERIES +} else { + error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)." +} + +# After reset, the chip is clocked by an internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + # Allow user override + set _CCLK $CCLK +} else { + # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x) + if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { + set _CCLK 12000 + } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { + set _CCLK 4000 + } +} + +if { [info exists CPUTAPID] } { + # Allow user override + set _CPUTAPID $CPUTAPID +} else { + # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core. + if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { + set _CPUTAPID 0x0bb11477 + } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } + } +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE." +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE + +# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000) +# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000) +# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) +# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) +# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) +# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000) +# +# All are compatible with the "lpc1700" variant of the LPC2000 flash driver +# (same cmd51 destination boundary alignment, and all three support 256 byte +# transfers). +# +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry] +set _IAP_ENTRY 0 +if { [info exists IAP_ENTRY] } { + set _IAP_ENTRY $IAP_ENTRY +} +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \ + auto $_CCLK calc_checksum $_IAP_ENTRY + +if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { + # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description + # Bit Symbol Value Description + # 1:0 MAP System memory remap + # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. + # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. + # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. + # 31:2 - - Reserved. + $_TARGETNAME configure -event reset-init { + mww 0x40048000 0x02 + } +} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { + # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description + # Bit Symbol Value Description Reset + # value + # 0 MAP Memory map control. 0 + # 0 Boot mode. A portion of the Boot ROM is mapped to address 0. + # 1 User mode. The on-chip Flash memory is mapped to address 0. + # 31:1 - Reserved. The value read from a reserved bit is not defined. NA + # + # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user + $_TARGETNAME configure -event reset-init { + mww 0x400FC040 0x01 + } +} + +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +adapter speed 10 + +# delays on reset lines +adapter srst delay 200 +if {[using_jtag]} { + jtag_ntrst_delay 200 +} + +# LPC8xx (Cortex-M0+ core) support SYSRESETREQ +# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ +# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ +# LPC40xx (Cortex-M4F core) support SYSRESETREQ +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/lpc2103.cfg b/openocd-win/openocd/scripts/target/lpc2103.cfg new file mode 100644 index 0000000..c49b0e5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2103.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2103 {core_freq_khz adapter_freq_khz} { + # 32kB flash and 8kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 12MHz crystal + echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2103 <core_freq_khz> <adapter_freq_khz> + setup_lpc2103 12000 1500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2124.cfg b/openocd-win/openocd/scripts/target/lpc2124.cfg new file mode 100644 index 0000000..053ebeb --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2124.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2124 {core_freq_khz adapter_freq_khz} { + # 256kB flash and 16kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 12MHz crystal + echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2124 <core_freq_khz> <adapter_freq_khz> + setup_lpc2124 12000 1500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2129.cfg b/openocd-win/openocd/scripts/target/lpc2129.cfg new file mode 100644 index 0000000..88ee20f --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2129.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2129 {core_freq_khz adapter_freq_khz} { + # 256kB flash and 16kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 12MHz crystal + echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2129 <core_freq_khz> <adapter_freq_khz> + setup_lpc2129 12000 1500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2148.cfg b/openocd-win/openocd/scripts/target/lpc2148.cfg new file mode 100644 index 0000000..fda622f --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2148.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2148 {core_freq_khz adapter_freq_khz} { + # 500kB flash and 32kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 12MHz crystal + echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2148 <core_freq_khz> <adapter_freq_khz> + setup_lpc2148 12000 1500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2294.cfg b/openocd-win/openocd/scripts/target/lpc2294.cfg new file mode 100644 index 0000000..7537a65 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2294.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2294 {core_freq_khz adapter_freq_khz} { + # 256kB flash and 16kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + + # !! TAPID unknown !! + setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 12MHz crystal + echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2294 <core_freq_khz> <adapter_freq_khz> + setup_lpc2294 12000 1500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2378.cfg b/openocd-win/openocd/scripts/target/lpc2378.cfg new file mode 100644 index 0000000..59e41c9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2378.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2378 {core_freq_khz adapter_freq_khz} { + # 504kB flash and 32kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 4MHz internal oscillator + echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2378 <core_freq_khz> <adapter_freq_khz> + setup_lpc2378 4000 500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2460.cfg b/openocd-win/openocd/scripts/target/lpc2460.cfg new file mode 100644 index 0000000..59b6466 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2460.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2460 {core_freq_khz adapter_freq_khz} { + # 64kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 4MHz internal oscillator + echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2460 <core_freq_khz> <adapter_freq_khz> + setup_lpc2460 4000 500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2478.cfg b/openocd-win/openocd/scripts/target/lpc2478.cfg new file mode 100644 index 0000000..e4fd49d --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2478.cfg @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator + +source [find target/lpc2xxx.cfg] + +# parameters: +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2478 {core_freq_khz adapter_freq_khz} { + # 504kB flash and 64kB SRAM + # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz> + setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz +} + +proc init_targets {} { + # default to core clocked with 4MHz internal oscillator + echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different." + + # setup_lpc2478 <core_freq_khz> <adapter_freq_khz> + setup_lpc2478 4000 500 +} diff --git a/openocd-win/openocd/scripts/target/lpc2900.cfg b/openocd-win/openocd/scripts/target/lpc2900.cfg new file mode 100644 index 0000000..67e3c92 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2900.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2900 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0596802B +} + +if { [info exists HAS_ETB] } { +} else { + # Set default (no ETB). + # Show a warning, because this should have been configured explicitly. + set HAS_ETB 0 + # TODO: warning? +} + +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x1B900F0F +} + +# TRST and SRST both exist, and can be controlled independently +reset_config trst_and_srst separate + +# Define the _TARGETNAME +set _TARGETNAME $_CHIPNAME.cpu + +# Include the ETB tap controller if asked for. +# Has to be done manually for newer devices (not an "old" LPC2917/2919). +if { $HAS_ETB == 1 } { + # Clear the HAS_ETB flag. Must be set again for a new tap in the chain. + set HAS_ETB 0 + + # Add the ETB tap controller and the ARM9 core debug tap + jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + # Create the ".cpu" target + target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME + + # Configure ETM and ETB + etm config $_TARGETNAME 8 normal full etb + etb config $_TARGETNAME $_CHIPNAME.etb + +} else { + # Add the ARM9 core debug tap + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + # Create the ".cpu" target + target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME +} + +arm7_9 dbgrq enable +arm7_9 dcc_downloads enable + +# Flash bank configuration: +# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz> +# Flash base address, total flash size, and number of sectors are all configured automatically. +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK diff --git a/openocd-win/openocd/scripts/target/lpc2xxx.cfg b/openocd-win/openocd/scripts/target/lpc2xxx.cfg new file mode 100644 index 0000000..bc5e600 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc2xxx.cfg @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Common setup for the LPC2xxx parts + +# parameters: +# - chip_name - name of the chip, e.g. lpc2103 +# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f" +# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000 +# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx) +# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000 +# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000 +# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000 + +proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} { + reset_config trst_and_srst + + # reset delays + adapter srst delay 100 + jtag_ntrst_delay 100 + + adapter speed $adapter_freq_khz + + foreach i $cputapids { + append expected_ids "-expected-id " $i " " + } + + eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids" + + global _TARGETNAME + set _TARGETNAME $chip_name.cpu + target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME + + $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0 + + if { $flash_size > 0 } { + # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] + set _FLASHNAME $chip_name.flash + flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum + } +} + +proc init_targets {} { + # FIX!!! read out CPUTAPID here and choose right setup. In addition to the + # CPUTAPID some querying of the target would be required. + return -error "This is a generic LPC2xxx configuration file, use a specific target file." +} diff --git a/openocd-win/openocd/scripts/target/lpc3131.cfg b/openocd-win/openocd/scripts/target/lpc3131.cfg new file mode 100644 index 0000000..09d698a --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc3131.cfg @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: NXP lpc3131 +###################################### + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc3131 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# ARM926EJS core +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926f0f +} + +# Scan Tap +# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module +# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through. +if { [info exists SJCTAPID] } { + set _SJCTAPID $SJCTAPID +} else { + set _SJCTAPID 0x1541E02B +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +################################################################## +# various symbol definitions, to avoid hard-wiring addresses +################################################################## + +global lpc313x +set lpc313x [ dict create ] + +# Physical addresses for controllers and memory +dict set lpc313x sram0 0x11028000 +dict set lpc313x sram1 0x11040000 +dict set lpc313x uart 0x15001000 +dict set lpc313x cgu 0x13004000 +dict set lpc313x ioconfig 0x13003000 +dict set lpc313x sysconfig 0x13002800 +dict set lpc313x wdt 0x13002400 + +################################################################## +# Target configuration +################################################################## + +adapter srst delay 1000 +jtag_ntrst_delay 0 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME invoke-event halted + +$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { + echo "\nRunning reset init script for LPC3131\n" + halt + wait_halt + reg cpsr 0xa00000d3 ;#Supervisor mode + reg pc 0x11029000 + poll + sleep 500 +} + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/lpc3250.cfg b/openocd-win/openocd/scripts/target/lpc3250.cfg new file mode 100644 index 0000000..244d981 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc3250.cfg @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# lpc3250 config +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc3250 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x17900f0f +} + +if { [info exists CPUTAPID_REV_A0] } { + set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0 +} else { + set _CPUTAPID_REV_A0 0x17926f0f +} + +if { [info exists SJCTAPID] } { + set _SJCTAPID $SJCTAPID +} else { + set _SJCTAPID 0x1b900f0f +} + +jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \ + -expected-id $_CPUTAPID_REV_A0 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0 + +proc power_restore {} { echo "Sensed power restore. No action." } +proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } diff --git a/openocd-win/openocd/scripts/target/lpc40xx.cfg b/openocd-win/openocd/scripts/target/lpc40xx.cfg new file mode 100644 index 0000000..f0be5a1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc40xx.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC40xx Cortex-M4F with at least 16kB SRAM +set CHIPNAME lpc40xx +set CHIPSERIES lpc4000 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x4000 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc4350.cfg b/openocd-win/openocd/scripts/target/lpc4350.cfg new file mode 100644 index 0000000..453306a --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc4350.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/swj-dp.tcl] + +adapter speed 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc4350 +} + +# +# M4 JTAG mode TAP +# +if { [info exists M4_JTAG_TAPID] } { + set _M4_JTAG_TAPID $M4_JTAG_TAPID +} else { + set _M4_JTAG_TAPID 0x4ba00477 +} + +# +# M4 SWD mode TAP +# +if { [info exists M4_SWD_TAPID] } { + set _M4_SWD_TAPID $M4_SWD_TAPID +} else { + set _M4_SWD_TAPID 0x2ba01477 +} + +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} { + set _M4_TAPID $_M4_SWD_TAPID +} + +# +# M0 TAP +# +if { [info exists M0_JTAG_TAPID] } { + set _M0_JTAG_TAPID $M0_JTAG_TAPID +} else { + set _M0_JTAG_TAPID 0x0ba01477 +} + +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID +dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap + +if { [using_jtag] } { + swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M0_JTAG_TAPID + dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0 + target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap +} + +# LPC4350 has 96+32 KB SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x20000 +} +$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if {![using_hla]} { + # on this CPU we should use VECTRESET to perform a soft reset and + # manually reset the periphery + # SRST or SYSRESETREQ disable the debug interface for the time of + # the reset and will not fit our requirements for a consistent debug + # session + cortex_m reset_config vectreset +} diff --git a/openocd-win/openocd/scripts/target/lpc4357.cfg b/openocd-win/openocd/scripts/target/lpc4357.cfg new file mode 100644 index 0000000..f783505 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc4357.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP LPC4357 +# + +if { ![info exists CHIPNAME] } { + set CHIPNAME lpc4357 +} +set WORKAREASIZE 0x8000 +source [find target/lpc4350.cfg] + +flash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum +flash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum diff --git a/openocd-win/openocd/scripts/target/lpc4370.cfg b/openocd-win/openocd/scripts/target/lpc4370.cfg new file mode 100644 index 0000000..fe9e76b --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc4370.cfg @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each +# + +adapter speed 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc4370 +} + +# +# M4 JTAG mode TAP +# +if { [info exists M4_JTAG_TAPID] } { + set _M4_JTAG_TAPID $M4_JTAG_TAPID +} else { + set _M4_JTAG_TAPID 0x4ba00477 +} + +# +# M4 SWD mode TAP +# +if { [info exists M4_SWD_TAPID] } { + set _M4_SWD_TAPID $M4_SWD_TAPID +} else { + set _M4_SWD_TAPID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} else { + set _M4_TAPID $_M4_SWD_TAPID +} + +# +# M0 TAP +# +if { [info exists M0_JTAG_TAPID] } { + set _M0_JTAG_TAPID $M0_JTAG_TAPID +} else { + set _M0_JTAG_TAPID 0x0ba01477 +} + +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID +dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap + +# LPC4370 has 96+32 KB contiguous SRAM +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x20000 +} +$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if { [using_jtag] } { + jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M0_JTAG_TAPID + jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M0_JTAG_TAPID + + dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app + dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub + target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap + target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap + + # 32+8+32 KB SRAM + $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \ + -work-area-size 0x92000 -work-area-backup 0 + + # 16+2 KB M0 subsystem SRAM + $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \ + -work-area-size 0x4800 -work-area-backup 0 + + # Default to the Cortex-M4 + targets $_CHIPNAME.m4 +} + +if { ![using_hla] } { + cortex_m reset_config vectreset +} diff --git a/openocd-win/openocd/scripts/target/lpc84x.cfg b/openocd-win/openocd/scripts/target/lpc84x.cfg new file mode 100644 index 0000000..af26f27 --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc84x.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC84x Cortex-M0+ with at least 8kB SRAM +if { ![info exists CHIPNAME] } { + set CHIPNAME lpc84x +} +set CHIPSERIES lpc800 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x1fe0 +} + +set IAP_ENTRY 0x0F001FF1 +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/lpc8nxx.cfg b/openocd-win/openocd/scripts/target/lpc8nxx.cfg new file mode 100644 index 0000000..859e99b --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc8nxx.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM +# Copyright (C) 2018 by Jean-Christian de Rivaz +# Based on NXP proposal https://community.nxp.com/message/1011149 +# Many thanks to Dries Moors from NXP support. +# SWD only transport + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc8nxx +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0 +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap +if {![using_hla]} { + # If srst is not fitted use SYSRESETREQ to perform a soft reset + cortex_m reset_config sysresetreq +} +adapter srst delay 100 + +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0 + +flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500 + +echo "*********************************************************************************" +echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!" +echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also" +echo "* unpowered. These modes can be entered by firmware. The default firmware image" +echo "* (flashed in production) makes use of this. Best is to avoid these power modes" +echo "* during development, and only later add them when the functionality is complete." +echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is" +echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST" +echo "* signal to the chip RESETN pin and add the following in your configuration:" +echo "* reset_config srst_only; flash init; catch init; reset" +echo "* But if the actual firmware immediately set the power down mode after reset," +echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In" +echo "* that case the only solution is to apply a NFC field to keep the SWD powered." +echo "*********************************************************************************" + +# Using soft-reset 'reset_config none' is strongly discouraged. +# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not. +# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset. +# +proc set_sysclk_500khz {} { + set SYSCLKCTRL 0x40048020 + set SYSCLKUEN 0x40048024 + mww $SYSCLKUEN 0 + mmw $SYSCLKCTRL 0x8 0xe + mww $SYSCLKUEN 1 + echo "Notice: sysclock set to 500kHz." +} + +# Do not remap the ARM interrupt vectors to anything but the beginning of the flash. +# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description +# Bit Symbol Value Description +# 0 map - interrupt vector remap. 0 after boot. +# 0 interrupt vector reside in Flash +# 1 interrupt vector reside in SRAM +# 5:1 offset - system memory remap offset. 00000b after boot. +# 00000b interrupt vectors in flash or remapped to SRAM but no offset +# 00001b - +# 00111b interrupt vectors offset in flash or SRAM to 1K word segment +# 01000b - +# 11111b interrupt vectors offset in flash to 1K word segment 8 to 31 +# 31:6 reserved +# +proc set_no_remap {} { + mww 0x40048000 0x00 + echo "Notice: interrupt vector set to no remap." +} + +$_TARGETNAME configure -event reset-init { + set_sysclk_500khz + set_no_remap +} diff --git a/openocd-win/openocd/scripts/target/lpc8xx.cfg b/openocd-win/openocd/scripts/target/lpc8xx.cfg new file mode 100644 index 0000000..4c54a2a --- /dev/null +++ b/openocd-win/openocd/scripts/target/lpc8xx.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM +if { ![info exists CHIPNAME] } { + set CHIPNAME lpc8xx +} +set CHIPSERIES lpc800 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x400 +} + +source [find target/lpc1xxx.cfg] diff --git a/openocd-win/openocd/scripts/target/ls1012a.cfg b/openocd-win/openocd/scripts/target/ls1012a.cfg new file mode 100644 index 0000000..7333ea8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ls1012a.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# NXP LS1012A +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ls1012a +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +if { [info exists SAP_TAPID] } { + set _SAP_TAPID $SAP_TAPID +} else { + set _SAP_TAPID 0x06b2001d +} + +jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID +jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80420000 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti + +target smp $_TARGETNAME + +adapter speed 2000 diff --git a/openocd-win/openocd/scripts/target/ls1028a.cfg b/openocd-win/openocd/scripts/target/ls1028a.cfg new file mode 100644 index 0000000..463ec7d --- /dev/null +++ b/openocd-win/openocd/scripts/target/ls1028a.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP LS1028A + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ls1028a +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x6ba00477 +} + +set _CPUS 2 + +source [find target/lsch3_common.cfg] diff --git a/openocd-win/openocd/scripts/target/ls1046a.cfg b/openocd-win/openocd/scripts/target/ls1046a.cfg new file mode 100644 index 0000000..3d96a99 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ls1046a.cfg @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP LS1046A + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ls1046a +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +if { [info exists SAP_TAPID] } { + set _SAP_TAPID $SAP_TAPID +} else { + set _SAP_TAPID 0x06b3001d +} + +jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +set _CPU_BASE 0x80400000 +set _CPU_STRIDE 0x100000 +set _CPU_DBGOFF 0x10000 +set _CPU_CTIOFF 0x20000 + +set _TARGETS {} +for {set i 0} {$i < 4} {incr i} { + set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}] + cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [expr {$_BASE + $_CPU_CTIOFF}] + target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \ + -coreid $i {*}[expr {$i ? {-defer-examine} : {-rtos hwthread} }] + lappend _TARGETS $_CHIPNAME.cpu$i +} + +target smp {*}$_TARGETS + +jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID +target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big + +proc core_up { args } { + foreach core $args { + $::_CHIPNAME.cpu$core arp_examine + } +} + +targets $_CHIPNAME.cpu0 + +adapter speed 10000 diff --git a/openocd-win/openocd/scripts/target/ls1088a.cfg b/openocd-win/openocd/scripts/target/ls1088a.cfg new file mode 100644 index 0000000..193d6dd --- /dev/null +++ b/openocd-win/openocd/scripts/target/ls1088a.cfg @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# NXP LS1088A + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ls1088a +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +set _CPUS 8 + +source [find target/lsch3_common.cfg] + +# Seems to work OK in testing +adapter speed 10000 diff --git a/openocd-win/openocd/scripts/target/lsch3_common.cfg b/openocd-win/openocd/scripts/target/lsch3_common.cfg new file mode 100644 index 0000000..f48d59b --- /dev/null +++ b/openocd-win/openocd/scripts/target/lsch3_common.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This contains common configuration for NXP Layerscape chassis generation 3 + +if { ![info exists _CPUS] } { + error "_CPUS must be set to the number of cores" +} + +jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1 + +set _CPU_BASE 0x81000000 +set _CPU_STRIDE 0x100000 +set _CPU_DBGOFF 0x10000 +set _CPU_CTIOFF 0x20000 + +set _TARGETS {} +for {set i 0} {$i < $_CPUS} {incr i} { + set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}] + cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \ + -baseaddr [expr {$_BASE + $_CPU_CTIOFF}] + target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \ + -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \ + {*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }] + lappend _TARGETS $_CHIPNAME.cpu$i +} + +target smp {*}$_TARGETS + +# Service processor +target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000 + +# Normally you will not need to call this, but if you are using the hard-coded +# Reset Configuration Word (RCW) you will need to call this manually. The CPU's +# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit +# instructions. This will cause the CPU to almost immediately execute an +# illegal instruction. +# +# This code is idempotent; releasing a released CPU has no effect, although it +# will halt/resume the service processor. +add_help_text release_cpu "Release a cpu which is held off" +proc release_cpu {cpu} { + set RST_BRRL 0x1e60060 + + set old [target current] + targets $::_CHIPNAME.sp + set not_halted [string compare halted [$::_CHIPNAME.sp curstate]] + if {$not_halted} { + halt + } + + # Release the cpu; it will start executing something bogus + mem2array regs 32 $RST_BRRL 1 + mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}] + + if {$not_halted} { + resume + } + targets $old +} + +targets $_CHIPNAME.cpu0 diff --git a/openocd-win/openocd/scripts/target/marvell/88f3710.cfg b/openocd-win/openocd/scripts/target/marvell/88f3710.cfg new file mode 100644 index 0000000..dcc4516 --- /dev/null +++ b/openocd-win/openocd/scripts/target/marvell/88f3710.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Marvell Armada 3710 + +set CORES 1 + +source [find target/marvell/88f37x0.cfg] diff --git a/openocd-win/openocd/scripts/target/marvell/88f3720.cfg b/openocd-win/openocd/scripts/target/marvell/88f3720.cfg new file mode 100644 index 0000000..7c29378 --- /dev/null +++ b/openocd-win/openocd/scripts/target/marvell/88f3720.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Marvell Armada 3720 + +set CORES 2 + +source [find target/marvell/88f37x0.cfg] diff --git a/openocd-win/openocd/scripts/target/marvell/88f37x0.cfg b/openocd-win/openocd/scripts/target/marvell/88f37x0.cfg new file mode 100644 index 0000000..738d221 --- /dev/null +++ b/openocd-win/openocd/scripts/target/marvell/88f37x0.cfg @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Main file for Marvell Armada 3700 series targets +# +# !!!!!! +# +# This file should not be included directly. Instead, please include +# either marvell/88f3710.cfg or marvell/88f3720.cfg, which set the needed +# variables to the appropriate values. +# +# !!!!!! + +# Armada 3700 supports both JTAG and SWD transports. +source [find target/swj-dp.tcl] + +if { [info exists CORES] } { + set _cores $CORES +} else { + error "CORES not set. Please do not include marvell/88f37x0.cfg directly, but the specific chip configuration file (marvell/88f3710.cfg, marvell/88f3720.cfg, etc.)." +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME [format a37%s0 $_cores] +} + +set _ctis {0x80820000 0x80920000} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +# declare the one JTAG tap to access the DAP +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# declare the main application cores +set _TARGETNAME $_CHIPNAME.cpu +set _smp_command "" + +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [lindex $_ctis $_core] -ap-num 0 + + set _command "target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core \ + -cti cti$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command ${_TARGETNAME}$_core" + } else { + set _command "$_command -rtos hwthread" + set _smp_command "target smp ${_TARGETNAME}$_core" + } + + eval $_command +} + +eval $_smp_command + +# declare the auxiliary Cortex-M3 core on AP #3 +target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine + +targets ${_TARGETNAME}0 diff --git a/openocd-win/openocd/scripts/target/max32620.cfg b/openocd-win/openocd/scripts/target/max32620.cfg new file mode 100644 index 0000000..f3a9f84 --- /dev/null +++ b/openocd-win/openocd/scripts/target/max32620.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Maxim Integrated MAX32620 OpenOCD target configuration file +# www.maximintegrated.com + +# adapter speed +adapter speed 4000 + +# reset pin configuration +reset_config srst_only + +if {[using_jtag]} { + jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version + jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version +} else { + swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version +} + +dap create max32620.dap -chain-position max32620.cpu + +# target configuration +target create max32620.cpu cortex_m -dap max32620.dap +max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 + +# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] +# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> +# max32620 flash base address 0x00000000 +# max32620 flash size 0x200000 (2MB) +# max32620 FLC base address 0x40002000 +# max32620 sector (page) size 0x2000 (8kB) +# max32620 clock speed 96 (MHz) +flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96 diff --git a/openocd-win/openocd/scripts/target/max32625.cfg b/openocd-win/openocd/scripts/target/max32625.cfg new file mode 100644 index 0000000..90eb392 --- /dev/null +++ b/openocd-win/openocd/scripts/target/max32625.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Maxim Integrated MAX32625 OpenOCD target configuration file +# www.maximintegrated.com + +# adapter speed +adapter speed 4000 + +# reset pin configuration +reset_config srst_only + +if {[using_jtag]} { + jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version + jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version +} else { + swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version +} + +dap create max32625.dap -chain-position max32625.cpu + +# target configuration +target create max32625.cpu cortex_m -dap max32625.dap +max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 + +# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] +# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> +# max32625 flash base address 0x00000000 +# max32625 flash size 0x80000 (512k) +# max32625 FLC base address 0x40002000 +# max32625 sector (page) size 0x2000 (8kB) +# max32625 clock speed 96 (MHz) +flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96 diff --git a/openocd-win/openocd/scripts/target/max3263x.cfg b/openocd-win/openocd/scripts/target/max3263x.cfg new file mode 100644 index 0000000..852e04a --- /dev/null +++ b/openocd-win/openocd/scripts/target/max3263x.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Maxim Integrated MAX3263X OpenOCD target configuration file +# www.maximintegrated.com + +# adapter speed +adapter speed 4000 + +# reset pin configuration +reset_config srst_only + +if {[using_jtag]} { + jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version + jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version +} else { + swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version +} + +dap create max3263x.dap -chain-position max3263x.cpu + +# target configuration +target create max3263x.cpu cortex_m -dap max3263x.dap +max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 + +# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] +# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> +# max3263x flash base address 0x00000000 +# max3263x flash size 0x200000 (2MB) +# max3263x FLC base address 0x40002000 +# max3263x sector (page) size 0x2000 (8kB) +# max3263x clock speed 96 (MHz) +flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96 diff --git a/openocd-win/openocd/scripts/target/mc13224v.cfg b/openocd-win/openocd/scripts/target/mc13224v.cfg new file mode 100644 index 0000000..29e4d9d --- /dev/null +++ b/openocd-win/openocd/scripts/target/mc13224v.cfg @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find bitsbytes.tcl] +source [find cpu/arm/arm7tdmi.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] + +set CHIP_MAKER freescale +set CHIP_FAMILY mc1322x +set CHIP_NAME mc13224 +set N_RAM 1 +set RAM(0,BASE) 0x00400000 +set RAM(0,LEN) 0x18000 +set RAM(0,HUMAN) "internal SRAM" +set RAM(0,TYPE) "ram" +set RAM(0,RWX) $RWX_RWX +set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +# I AM LAZY... I create 1 region for all MMRs. +set N_MMREGS 1 +set MMREGS(0,CHIPSELECT) -1 +set MMREGS(0,BASE) 0x80000000 +set MMREGS(0,LEN) 0x00030000 +set MMREGS(0,HUMAN) "mm-regs" +set MMREGS(0,TYPE) "mmr" +set MMREGS(0,RWX) $RWX_RW +set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY + +set N_XMEM 0 + +set _CHIPNAME mc13224v +set _CPUTAPID 0x1f1f001d + +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + +reset_config srst_only +jtag_ntrst_delay 200 + +# rclk hasn't been working well. This maybe the mc13224v or something else. +#adapter speed 2000 +adapter speed 2000 + +###################### +# Target configuration +###################### + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME + +# Internal sram memory +$_TARGETNAME configure -work-area-phys 0x00408000 \ + -work-area-size 0x1000 \ + -work-area-backup 1 + +# flash support is pending (should be straightforward to implement) +#flash bank mc1322x 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/mdr32f9q2i.cfg b/openocd-win/openocd/scripts/target/mdr32f9q2i.cfg new file mode 100644 index 0000000..6e958c6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/mdr32f9q2i.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MDR32F9Q2I (1986ВЕ92У) +# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68 + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME mdr32f9q2i +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x4ba00477 + } { + # SWD IDCODE + set _CPUTAPID 0x2ba01477 + } +} +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# can't handle overlapping memory regions +if { [info exists IMEMORY] && [string equal $IMEMORY true] } { + flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4 +} else { + flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/nds32v5.cfg b/openocd-win/openocd/scripts/target/nds32v5.cfg new file mode 100644 index 0000000..56b5fed --- /dev/null +++ b/openocd-win/openocd/scripts/target/nds32v5.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Andes Core +# +# http://www.andestech.com +# + +set _CHIPNAME nds +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/ngultra.cfg b/openocd-win/openocd/scripts/target/ngultra.cfg new file mode 100644 index 0000000..956fdbb --- /dev/null +++ b/openocd-win/openocd/scripts/target/ngultra.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2022 by NanoXplore, France - all rights reserved +# +# configuration file for NG-Ultra SoC from NanoXplore. +# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA. +# +transport select jtag +adapter speed 10000 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NGULTRA +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000} +set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000} + +# Coresight access to the SoC +jtag newtap $_CHIPNAME.coresight cpu -irlen 4 -expected-id 0x6BA00477 + +# Misc TAP devices +jtag newtap $_CHIPNAME.soc cpu -irlen 7 -expected-id 0xFAAA0555 +jtag newtap $_CHIPNAME.pmb unknown1 -irlen 5 -expected-id 0xBA20A005 +jtag newtap $_CHIPNAME.fpga fpga -irlen 4 -ignore-version -ignore-bypass + +# Create the Coresight DAP +dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu + +for { set _core 0 } { $_core < $_cores } { incr _core } { + cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \ + -baseaddr [lindex $CTIBASE $_core] +# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet). + if { $_core == 0} { + target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core + } else { + target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine + } +} + +# Create direct APB and AXI interfaces +target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0 +target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1 diff --git a/openocd-win/openocd/scripts/target/nhs31xx.cfg b/openocd-win/openocd/scripts/target/nhs31xx.cfg new file mode 100644 index 0000000..7e4bc4c --- /dev/null +++ b/openocd-win/openocd/scripts/target/nhs31xx.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP NHS31xx Cortex-M0+ with 8kB SRAM + +set CHIPNAME nhs31xx +source [find target/lpc8nxx.cfg] diff --git a/openocd-win/openocd/scripts/target/npcx.cfg b/openocd-win/openocd/scripts/target/npcx.cfg new file mode 100644 index 0000000..1a21e1f --- /dev/null +++ b/openocd-win/openocd/scripts/target/npcx.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Nuvoton NPCX Cortex-M4 Series + +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NPCX_M4 +} + +# SWD DAP ID of Nuvoton NPCX Cortex-M4. +if { [info exists CPUDAPID ] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x4BA00477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Initial JTAG/SWD speed +# For safety purposes, set for the lowest cpu clock configuration +# 4MHz / 6 = 666KHz, so use 600KHz for it +adapter speed 600 + +# For safety purposes, set for the lowest cpu clock configuration +$_TARGETNAME configure -event reset-start {adapter speed 600} + +# use sysresetreq to perform a system reset +cortex_m reset_config sysresetreq + +# flash configuration +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/nrf51.cfg b/openocd-win/openocd/scripts/target/nrf51.cfg new file mode 100644 index 0000000..48c2715 --- /dev/null +++ b/openocd-win/openocd/scripts/target/nrf51.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# script for Nordic nRF51 series, a Cortex-M0 chip +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf51 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if {![using_hla]} { + # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal + cortex_m reset_config sysresetreq +} + +flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME + +# +# The chip should start up from internal 16Mhz RC, so setting adapter +# clock to 1Mhz should be OK +# +adapter speed 1000 + +proc enable_all_ram {} { + # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks + # are reliably enabled after reset on some revisions (contrary to spec.) So after + # resetting we enable all banks via the RAMON register + mww 0x40000524 0xF +} +$_TARGETNAME configure -event reset-end { enable_all_ram } diff --git a/openocd-win/openocd/scripts/target/nrf52.cfg b/openocd-win/openocd/scripts/target/nrf52.cfg new file mode 100644 index 0000000..2539be0 --- /dev/null +++ b/openocd-win/openocd/scripts/target/nrf52.cfg @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nrf52 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +adapter speed 1000 + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if { [using_hla] } { + echo "" + echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock." + echo "A high level adapter (like a ST-Link) you are currently using cannot access" + echo "the CTRL-AP so 'nrf52_recover' command will not work." + echo "Do not enable UICR APPROTECT." + echo "" +} else { + cortex_m reset_config sysresetreq + + $_TARGETNAME configure -event examine-fail nrf52_check_ap_lock +} + +flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME + +# Test if MEM-AP is locked by UICR APPROTECT +proc nrf52_check_ap_lock {} { + set dap [[target current] cget -dap] + set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}] + if {$err == 0 && $APPROTECTSTATUS != 1} { + echo "****** WARNING ******" + echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)." + echo "Debug access is denied." + echo "Use 'nrf52_recover' to erase and unlock the device." + echo "" + poll off + } +} + +# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1) +# http://www.ebyte.com produces modules with nRF52 locked by default, +# use nrf52_recover to enable flashing and debug. +proc nrf52_recover {} { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg 1 0xfc] + if {$IDR != 0x02880000} { + echo "Error: Cannot access nRF52 CTRL-AP!" + return + } + + poll off + + # Reset and trigger ERASEALL task + $dap apreg 1 4 0 + $dap apreg 1 4 1 + + for {set i 0} {1} {incr i} { + set ERASEALLSTATUS [$dap apreg 1 8] + if {$ERASEALLSTATUS == 0} { + echo "$target device has been successfully erased and unlocked." + break + } + if {$i == 0} { + echo "Waiting for chip erase..." + } + if {$i >= 150} { + echo "Error: $target recovery failed." + break + } + sleep 100 + } + + # Assert reset + $dap apreg 1 0 1 + + # Deassert reset + $dap apreg 1 0 0 + + # Reset ERASEALL task + $dap apreg 1 4 0 + + sleep 100 + $target arp_examine + poll on +} + +add_help_text nrf52_recover "Mass erase and unlock nRF52 device" diff --git a/openocd-win/openocd/scripts/target/nuc910.cfg b/openocd-win/openocd/scripts/target/nuc910.cfg new file mode 100644 index 0000000..31a3ac6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/nuc910.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Nuvoton nuc910 (previously W90P910) based soc +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nuc910 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # set useful default + set _CPUTAPID 0x07926f0f +} + +set _TARGETNAME $_CHIPNAME.cpu +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/numicro.cfg b/openocd-win/openocd/scripts/target/numicro.cfg new file mode 100644 index 0000000..29077f3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/numicro.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Nuvoton MuMicro Cortex-M0 Series + +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NuMicro +} + +# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only. +if { [info exists CPUDAPID] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x0BB11477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 2kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#> +#set _FLASHNAME $_CHIPNAME.flash +#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash_aprom +flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_data +flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_ldrom +flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_config +flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME + +# set default SWCLK frequency +adapter speed 1000 + +# set default srst setting "none" +reset_config none + +# HLA doesn't have cortex_m commands +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/numicro_m4.cfg b/openocd-win/openocd/scripts/target/numicro_m4.cfg new file mode 100644 index 0000000..1302515 --- /dev/null +++ b/openocd-win/openocd/scripts/target/numicro_m4.cfg @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Nuvoton MuMicro Cortex-M4 Series + +source [find target/swj-dp.tcl] + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NuMicro +} + +# SWD DP-ID Nuvoton NuMicro Cortex-M4 has SWD Transport only. +if { [info exists CPUDAPID] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x2BA01477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#> +#set _FLASHNAME $_CHIPNAME.flash +#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash_aprom +flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_data +flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_ldrom +flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash_config +flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME + +# set default SWCLK frequency +adapter speed 1000 + +# set default srst setting "none" +reset_config none + +# HLA doesn't have cortex_m commands +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/omap2420.cfg b/openocd-win/openocd/scripts/target/omap2420.cfg new file mode 100644 index 0000000..3e31baf --- /dev/null +++ b/openocd-win/openocd/scripts/target/omap2420.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Texas Instruments OMAP 2420 +# http://www.ti.com/omap +# as seen in Nokia N8x0 tablets + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap2420 +} + +# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK +reset_config srst_nogate + +# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6). +jtag newtap $_CHIPNAME iva -irlen 4 -disable + +# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2). +jtag newtap $_CHIPNAME dsp -irlen 38 -disable + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID + +# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07b3602f +} +jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID + +# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x01ce4801 +} +jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID + +# GDB target: the ARM. +set _TARGETNAME $_CHIPNAME.arm +target create $_TARGETNAME arm11 -chain-position $_TARGETNAME + +# scratch: framebuffer, may be initially unavailable in some chips +$_TARGETNAME configure -work-area-phys 0x40210000 +$_TARGETNAME configure -work-area-size 0x00081000 +$_TARGETNAME configure -work-area-backup 0 + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb + +# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and +# give it a chance to finish before we talk to the chip again. +set RM_RSTCTRL_WKUP 0x48008450 +$_TARGETNAME configure -event reset-assert \ + "halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200" diff --git a/openocd-win/openocd/scripts/target/omap3530.cfg b/openocd-win/openocd/scripts/target/omap3530.cfg new file mode 100644 index 0000000..bd8b111 --- /dev/null +++ b/openocd-win/openocd/scripts/target/omap3530.cfg @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TI OMAP3530 +# http://focus.ti.com/docs/prod/folders/print/omap3530.html +# Other OMAP3 chips remove DSP and/or the OpenGL support + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap3530 +} + +# ICEpick-C ... used to route Cortex, DSP, and more not shown here +source [find target/icepick.cfg] + +# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick +jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable + +# Subsidiary TAP: CoreSight Debug Access Port (DAP) +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x0b6d602f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 3" + +# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b7ae02f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ + -expected-id $_JRC_TAPID + +# GDB target: Cortex-A8, using DAP +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap + +# SRAM: 64K at 0x4020.0000; use the first 16K +$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000 + +################### + +# the reset sequence is event-driven +# and kind of finicky... + +# some TCK tycles are required to activate the DEBUG power domain +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" + +# have the DAP "always" be active +jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" + +proc omap3_dbginit {target} { + # General Cortex-A8 debug initialisation + cortex_a dbginit + # Enable DBGU signal for OMAP353x + $target mww phys 0x5401d030 0x00002000 +} + +# be absolutely certain the JTAG clock will work with the worst-case +# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in. +# OK to speed up *after* PLL and clock tree setup. +adapter speed 1000 +$_TARGETNAME configure -event "reset-start" { adapter speed 1000 } + +# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset +# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick +# would issue. RST_DPLL3 (4) is a cold reset. +set PRM_RSTCTRL 0x48307250 +$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2" + +$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/omap4430.cfg b/openocd-win/openocd/scripts/target/omap4430.cfg new file mode 100644 index 0000000..a448550 --- /dev/null +++ b/openocd-win/openocd/scripts/target/omap4430.cfg @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OMAP4430 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap4430 +} + + +# Although the OMAP4430 supposedly has an ICEpick-D, only the +# ICEpick-C router commands seem to work. +# See http://processors.wiki.ti.com/index.php/ICEPICK +source [find target/icepick.cfg] + + +# +# A9 DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x3BA00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 9" + + +# +# M3 DAPs, one per core +# +if { [info exists M3_DAP_TAPID] } { + set _M3_DAP_TAPID $M3_DAP_TAPID +} else { + set _M3_DAP_TAPID 0x4BA00477 +} + +jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M3_DAP_TAPID -disable +jtag configure $_CHIPNAME.m31 -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 5" + +jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M3_DAP_TAPID -disable +jtag configure $_CHIPNAME.m30 -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 4" + + +# +# ICEpick-D JRC (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x3b95c02f + set _JRC_TAPID2 0x1b85202f +} + +# PandaBoard REV EA1 (PEAP platforms) +if { [info exists JRC_TAPID2] } { + set _JRC_TAPID2 $JRC_TAPID2 +} else { + set _JRC_TAPID2 0x1b85202f +} + + + +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ + -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 + +# Required by ICEpick to power-up the debug domain +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" + + +# +# GDB target: Cortex-A9, using DAP +# +# The debugger can connect to either core of the A9, but currently +# not both simultaneously. Change -coreid to 1 to connect to the +# second core. +# +set _TARGETNAME $_CHIPNAME.cpu + +# APB DBGBASE reads 0x80040000, but this points to an empty ROM table. +# 0x80000000 is cpu0 coresight region +# +# +# CORTEX_A8_PADDRDBG_CPU_SHIFT 13 +# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) + +set _coreid 0 +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] +echo "Using dbgbase = [format 0x%x $_dbgbase]" + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase $_dbgbase + +# SRAM: 56KiB at 0x4030.0000 +$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 + + +# +# M3 targets, separate TAP/DAP for each core +# +dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 +dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 +target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap +target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap + + +# Once the JRC is up, enable our TAPs +jtag configure $_CHIPNAME.jrc -event setup " + jtag tapenable $_CHIPNAME.cpu + jtag tapenable $_CHIPNAME.m30 + jtag tapenable $_CHIPNAME.m31 +" + +# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset +# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. +set PRM_RSTCTRL 0x4A307B00 +$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" +$_CHIPNAME.m30 configure -event reset-assert { } +$_CHIPNAME.m31 configure -event reset-assert { } + +# Soft breakpoints don't currently work due to broken cache handling +gdb_breakpoint_override hard diff --git a/openocd-win/openocd/scripts/target/omap4460.cfg b/openocd-win/openocd/scripts/target/omap4460.cfg new file mode 100644 index 0000000..bbc824b --- /dev/null +++ b/openocd-win/openocd/scripts/target/omap4460.cfg @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# OMAP4460 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap4460 +} + + +# Although the OMAP4430 supposedly has an ICEpick-D, only the +# ICEpick-C router commands seem to work. +# See http://processors.wiki.ti.com/index.php/ICEPICK +source [find target/icepick.cfg] + + +# +# A9 DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x3BA00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 9" + + +# +# M3 DAPs, one per core +# +if { [info exists M3_DAP_TAPID] } { + set _M3_DAP_TAPID $M3_DAP_TAPID +} else { + set _M3_DAP_TAPID 0x4BA00477 +} + +jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M3_DAP_TAPID -disable +jtag configure $_CHIPNAME.m31 -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 5" + +jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M3_DAP_TAPID -disable +jtag configure $_CHIPNAME.m30 -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 4" + + +# +# ICEpick-D JRC (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x2b94e02f + set _JRC_TAPID2 0x1b85202f +} + +# PandaBoard REV EA1 (PEAP platforms) +if { [info exists JRC_TAPID2] } { + set _JRC_TAPID2 $JRC_TAPID2 +} else { + set _JRC_TAPID2 0x1b85202f +} + + + +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ + -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2 + +# Required by ICEpick to power-up the debug domain +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200" + + +# +# GDB target: Cortex-A9, using DAP +# +# The debugger can connect to either core of the A9, but currently +# not both simultaneously. Change -coreid to 1 to connect to the +# second core. +# +set _TARGETNAME $_CHIPNAME.cpu + +# APB DBGBASE reads 0x80040000, but this points to an empty ROM table. +# 0x80000000 is cpu0 coresight region +# +# +# CORTEX_A8_PADDRDBG_CPU_SHIFT 13 +# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) + +set _coreid 0 +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] +echo "Using dbgbase = [format 0x%x $_dbgbase]" + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase $_dbgbase + +# SRAM: 56KiB at 0x4030.0000 +$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 + + +# +# M3 targets, separate TAP/DAP for each core +# +dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 +dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 +target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap +target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap + + +# Once the JRC is up, enable our TAPs +jtag configure $_CHIPNAME.jrc -event setup " + jtag tapenable $_CHIPNAME.cpu + jtag tapenable $_CHIPNAME.m30 + jtag tapenable $_CHIPNAME.m31 +" + +# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset +# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset. +set PRM_RSTCTRL 0x4A307B00 +$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1" +$_CHIPNAME.m30 configure -event reset-assert { } +$_CHIPNAME.m31 configure -event reset-assert { } + +# Soft breakpoints don't currently work due to broken cache handling +gdb_breakpoint_override hard diff --git a/openocd-win/openocd/scripts/target/omap5912.cfg b/openocd-win/openocd/scripts/target/omap5912.cfg new file mode 100644 index 0000000..783f460 --- /dev/null +++ b/openocd-win/openocd/scripts/target/omap5912.cfg @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TI OMAP5912 dual core processor +# http://focus.ti.com/docs/prod/folders/print/omap5912.html + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap5912 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # NOTE: validated with XOMAP5912 part + set _CPUTAPID 0x0692602f +} + +adapter srst delay 100 + +# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for +# its standalone siblings (like TMS320VC5502) of the same era + +#jtag scan chain +jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81 +jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME unknown -irlen 8 + +set _TARGETNAME $_CHIPNAME.arm +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME + +proc omap5912_reset {} { + # + # halt target + # + poll + sleep 1 + halt + wait_halt + # + # disable wdt + # + mww 0xfffec808 0x000000f5 + mww 0xfffec808 0x000000a0 + + mww 0xfffeb048 0x0000aaaa + sleep 500 + mww 0xfffeb048 0x00005555 + sleep 500 +} + +# omap5912 lcd frame buffer as working area +$_TARGETNAME configure -work-area-phys 0x20000000 \ + -work-area-size 0x3e800 -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/omapl138.cfg b/openocd-win/openocd/scripts/target/omapl138.cfg new file mode 100644 index 0000000..2d670b9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/omapl138.cfg @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments DaVinci family: OMAPL138 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omapl138 +} + +source [find target/icepick.cfg] + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable +jtag configure $_CHIPNAME.etb -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 3" + +# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07926001 +} +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable +jtag configure $_CHIPNAME.arm -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 2" + +# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b7d102f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) +# and the ETB memory (4K) are other options, while trace is unused. +# Little-endian; use the OpenOCD default. +set _TARGETNAME $_CHIPNAME.arm + +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 + +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +adapter speed 1500 +$_TARGETNAME configure -event "reset-start" { adapter speed 1500 } + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb + +gdb_breakpoint_override hard +arm7_9 dbgrq enable diff --git a/openocd-win/openocd/scripts/target/or1k.cfg b/openocd-win/openocd/scripts/target/or1k.cfg new file mode 100644 index 0000000..ddd4fa2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/or1k.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set _ENDIAN big + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME or1k +} + +if { [info exists TAP_TYPE] } { + set _TAP_TYPE $TAP_TYPE +} else { + puts "You need to select a tap type" + shutdown +} + +# Configure the target +if { [string compare $_TAP_TYPE "VJTAG"] == 0 } { + if { [info exists FPGATAPID] } { + set _FPGATAPID $FPGATAPID + } else { + puts "You need to set your FPGA JTAG ID" + shutdown + } + + jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME + + # Select the TAP core we are using + tap_select vjtag + +} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } { + + if { [info exists FPGATAPID] } { + set _FPGATAPID $FPGATAPID + } else { + puts "You need to set your FPGA JTAG ID" + shutdown + } + + jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME + + # Select the TAP core we are using + tap_select xilinx_bscan +} else { + # OpenCores Mohor JTAG TAP ID + set _CPUTAPID 0x14951185 + + jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + + set _TARGETNAME $_CHIPNAME.cpu + target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME + + # Select the TAP core we are using + tap_select mohor +} + +# Select the debug unit core we are using. This debug unit as an option. + +set ADBG_USE_HISPEED 1 +set ENABLE_JSP_SERVER 2 +set ENABLE_JSP_MULTI 4 + +# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped +# on burst reads and writes to improve download speeds. +# This option must match the RTL configured option. + +du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}] diff --git a/openocd-win/openocd/scripts/target/pic32mx.cfg b/openocd-win/openocd/scripts/target/pic32mx.cfg new file mode 100644 index 0000000..df68e80 --- /dev/null +++ b/openocd-win/openocd/scripts/target/pic32mx.cfg @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pic32mx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x30938053 +} + +# default working area is 16384 +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +adapter srst delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME + +# +# At reset the pic32mx does not allow code execution from RAM +# we have to setup the BMX registers to allow this. +# One limitation is that we loose the first 2k of RAM. +# + +global _PIC32MX_DATASIZE +global _WORKAREASIZE +set _PIC32MX_DATASIZE 0x800 +set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}] + +$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0 +$_TARGETNAME configure -event reset-init { + # + # from reset the pic32 cannot execute code in ram - enable ram execution + # minimum offset from start of ram is 2k + # + global _PIC32MX_DATASIZE + global _WORKAREASIZE + + # BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6 + mww 0xbf882000 0x001f0000 + # BMXDKPBA: 2k kernel data @ 0xa0000000 + mww 0xbf882010 $_PIC32MX_DATASIZE + # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA) + mww 0xbf882020 $_WORKAREASIZE + # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA) + mww 0xbf882030 $_WORKAREASIZE + + # + # Set system clock to 8Mhz if the default clock configuration is set + # + + # SYSKEY register, make sure OSCCON is locked + mww 0xbf80f230 0x0 + # SYSKEY register, write unlock sequence + mww 0xbf80f230 0xaa996655 + mww 0xbf80f230 0x556699aa + # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1 + mww 0xbf80f004 0x07000000 + # SYSKEY register, relock OSCCON + mww 0xbf80f230 0x0 +} + +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME +# add virtual banks for kseg0 and kseg1 +flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME +flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME + +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME +# add virtual banks for kseg0 and kseg1 +flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME +flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME diff --git a/openocd-win/openocd/scripts/target/psoc4.cfg b/openocd-win/openocd/scripts/target/psoc4.cfg new file mode 100644 index 0000000..baa2c83 --- /dev/null +++ b/openocd-win/openocd/scripts/target/psoc4.cfg @@ -0,0 +1,218 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Cypress PSoC 4 devices + +# +# PSoC 4 devices support SWD transports only. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME psoc4 +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME + +adapter speed 1500 + +# Reset, bloody PSoC 4 reset +# +# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed. +# High level adapter stops working after SRST and needs OpenOCD restart. +# If your hw does not use SRST for other circuits, use sysresetreq instead +# +# 2) PSoC 4 executes initialization code from system ROM after reset. +# This code subsequently jumps to user flash reset vector address. +# Unfortunately the system ROM code is protected from reading and debugging. +# Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m. +# +# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code +# from user flash. Programming specifications states that TEST_MODE flag must be +# set in time frame 400 usec delayed about 1 msec from reset. +# +# OpenOCD have no standard way how to set TEST_MODE in specified time frame. +# As a workaround the TEST_MODE flag is set before reset instead. +# It worked for the oldest family PSoC4100/4200 even though it is not guaranteed +# by specification. +# +# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE +# clear TEST_MODE flag during device reset so workaround is not possible. +# Use a KitProg adapter for these devices or "reset halt" will not stop +# before executing user code. +# +# 3) SWD cannot be connected during system initialization after reset. +# This might be a reason for unconnecting ST-Link v2 when deasserting reset. +# As a workaround arp_reset deassert is not called for hla + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc psoc4_get_family_id {} { + set err [catch {set romtable_pid [read_memory 0xF0000FE0 32 3]}] + if { $err } { + return 0 + } + if { [expr {[lindex $romtable_pid 0] & 0xffffff00 }] + || [expr {[lindex $romtable_pid 1] & 0xffffff00 }] + || [expr {[lindex $romtable_pid 2] & 0xffffff00 }] } { + echo "Unexpected data in ROMTABLE" + return 0 + } + set designer_id [expr {(( [lindex $romtable_pid 1] & 0xf0 ) >> 4) | (( [lindex $romtable_pid 2] & 0xf ) << 4 ) }] + if { $designer_id != 0xb4 } { + echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id] + return 0 + } + set family_id [expr {( [lindex $romtable_pid 0] & 0xff ) | (( [lindex $romtable_pid 1] & 0xf ) << 8 ) }] + return $family_id +} + +proc ocd_process_reset_inner { MODE } { + global PSOC4_USE_ACQUIRE PSOC4_TEST_MODE_WORKAROUND + global _TARGETNAME + + if { 0 != [string compare $_TARGETNAME [target names]] } { + return -code error "PSoC 4 reset can handle only one $_TARGETNAME target"; + } + set t $_TARGETNAME + + # If this target must be halted... + set halt -1 + if { 0 == [string compare $MODE halt] } { + set halt 1 + } + if { 0 == [string compare $MODE init] } { + set halt 1; + } + if { 0 == [string compare $MODE run ] } { + set halt 0; + } + if { $halt < 0 } { + return -code error "Invalid mode: $MODE, must be one of: halt, init, or run"; + } + + if { ! [info exists PSOC4_USE_ACQUIRE] } { + if { 0 == [string compare [adapter name] kitprog ] } { + set PSOC4_USE_ACQUIRE 1 + } else { + set PSOC4_USE_ACQUIRE 0 + } + } + if { $PSOC4_USE_ACQUIRE } { + set PSOC4_TEST_MODE_WORKAROUND 0 + } elseif { ! [info exists PSOC4_TEST_MODE_WORKAROUND] } { + if { [psoc4_get_family_id] == 0x93 } { + set PSOC4_TEST_MODE_WORKAROUND 1 + } else { + set PSOC4_TEST_MODE_WORKAROUND 0 + } + } + + #$t invoke-event reset-start + $t invoke-event reset-assert-pre + + if { $halt && $PSOC4_USE_ACQUIRE } { + catch { [adapter name] acquire_psoc } + $t arp_examine + } else { + if { $PSOC4_TEST_MODE_WORKAROUND } { + set TEST_MODE 0x40030014 + if { $halt == 1 } { + catch { mww $TEST_MODE 0x80000000 } + } else { + catch { mww $TEST_MODE 0 } + } + } + + $t arp_reset assert 0 + } + + $t invoke-event reset-assert-post + $t invoke-event reset-deassert-pre + if {![using_hla]} { # workaround ST-Link v2 fails and forcing reconnect + $t arp_reset deassert 0 + } + $t invoke-event reset-deassert-post + + # Pass 1 - Now wait for any halt (requested as part of reset + # assert/deassert) to happen. Ideally it takes effect without + # first executing any instructions. + if { $halt } { + # Now PSoC CPU should loop in system ROM + $t arp_waitstate running 200 + $t arp_halt + + # Catch, but ignore any errors. + catch { $t arp_waitstate halted 1000 } + + # Did we succeed? + set s [$t curstate] + + if { 0 != [string compare $s "halted" ] } { + return -code error [format "TARGET: %s - Not halted" $t] + } + + # Check if PSoC CPU is stopped in system ROM + set pc [reg pc] + regsub {pc[^:]*: } $pc "" pc + if { $pc < 0x10000000 || $pc > 0x1000ffff } { + set hint "" + set family_id [psoc4_get_family_id] + if { $family_id == 0x93 } { + set hint ", use 'reset_config none'" + } elseif { $family_id > 0x93 } { + set hint ", use a KitProg adapter" + } + return -code error [format "TARGET: %s - Not halted in system ROM%s" $t $hint] + } + + # Set registers to reset vector values + set value [read_memory 0x0 32 2] + reg pc [expr {[lindex $value 1] & 0xfffffffe}] + reg msp [lindex $value 0] + + if { $PSOC4_TEST_MODE_WORKAROUND } { + catch { mww $TEST_MODE 0 } + } + } + + #Pass 2 - if needed "init" + if { 0 == [string compare init $MODE] } { + set err [catch "$t arp_waitstate halted 5000"] + + # Did it halt? + if { $err == 0 } { + $t invoke-event reset-init + } + } + + $t invoke-event reset-end +} diff --git a/openocd-win/openocd/scripts/target/psoc5lp.cfg b/openocd-win/openocd/scripts/target/psoc5lp.cfg new file mode 100644 index 0000000..fe44174 --- /dev/null +++ b/openocd-win/openocd/scripts/target/psoc5lp.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Cypress PSoC 5LP +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME psoc5lp +} + +if { [info exists CPUTAPID] } { + set _CPU_TAPID $CPUTAPID +} else { + set _CPU_TAPID 0x4BA00477 +} + +if { [using_jtag] } { + set _CPU_DAP_ID $_CPU_TAPID +} else { + set _CPU_DAP_ID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +source [find mem_helper.tcl] + +$_TARGETNAME configure -event reset-init { + # Configure Target Device (PSoC 5LP Device Programming Specification 5.2) + + set PANTHER_DBG_CFG 0x4008000C + set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}] + mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0 + + set PM_ACT_CFG0 0x400043A0 + mww $PM_ACT_CFG0 0xBF + + set FASTCLK_IMO_CR 0x40004200 + set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}] + set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}] + mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/psoc6.cfg b/openocd-win/openocd/scripts/target/psoc6.cfg new file mode 100644 index 0000000..d69515c --- /dev/null +++ b/openocd-win/openocd/scripts/target/psoc6.cfg @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx) +# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share +# the same Flash/RAM/MMIO address space. +# + +source [find target/swj-dp.tcl] + +adapter speed 1000 + +global _CHIPNAME +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME psoc6 +} + +global TARGET +set TARGET $_CHIPNAME.cpu + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Is CM0 Debugging enabled ? +global _ENABLE_CM0 +if { [info exists ENABLE_CM0] } { + set _ENABLE_CM0 $ENABLE_CM0 +} else { + set _ENABLE_CM0 1 +} + +# Is CM4 Debugging enabled ? +global _ENABLE_CM4 +if { [info exists ENABLE_CM4] } { + set _ENABLE_CM4 $ENABLE_CM4 +} else { + set _ENABLE_CM4 1 +} + +global _WORKAREASIZE_CM0 +if { [info exists WORKAREASIZE_CM0] } { + set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0 +} else { + set _WORKAREASIZE_CM0 0x4000 +} + +global _WORKAREASIZE_CM4 +if { [info exists WORKAREASIZE_CM4] } { + set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4 +} else { + set _WORKAREASIZE_CM4 0x4000 +} + +global _WORKAREAADDR_CM0 +if { [info exists WORKAREAADDR_CM0] } { + set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0 +} else { + set _WORKAREAADDR_CM0 0x08000000 +} + +global _WORKAREAADDR_CM4 +if { [info exists WORKAREAADDR_CM4] } { + set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4 +} else { + set _WORKAREAADDR_CM4 0x08000000 +} + +proc init_reset { mode } { + global RESET_MODE + set RESET_MODE $mode + + if {[using_jtag]} { + jtag arp_init-reset + } +} + +# Utility to make 'reset halt' work as reset;halt on a target +# It does not prevent running code after reset +proc psoc6_deassert_post { target } { + # PSoC6 cleared AP registers including TAR during reset + # Force examine to synchronize OpenOCD target status + $target arp_examine + + global RESET_MODE + global TARGET + + if { $RESET_MODE ne "run" } { + $target arp_poll + $target arp_poll + set st [$target curstate] + + if { $st eq "reset" } { + # we assume running state follows + # if reset accidentally halts, waiting is useless + catch { $target arp_waitstate running 100 } + set st [$target curstate] + } + + if { $st eq "running" } { + echo "$target: Ran after reset and before halt..." + if { $target eq "${TARGET}.cm0" } { + # Try to cleanly reset whole system + # and halt the CM0 at entry point + psoc6 reset_halt + $target arp_waitstate halted 100 + } else { + $target arp_halt + } + } + } +} + +if { $_ENABLE_CM0 } { + target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 + ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0 + + flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0 + flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0 + flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0 + flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0 + flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0 + flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0 + + ${TARGET}.cm0 cortex_m reset_config sysresetreq + ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0" +} + +if { $_ENABLE_CM4 } { + target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1 + ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0 + + flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4 + flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4 + flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4 + flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4 + flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4 + flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4 + + ${TARGET}.cm4 cortex_m reset_config vectreset + ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4" +} + +if { $_ENABLE_CM0 } { + # Use CM0+ by default on dual-core devices + targets ${TARGET}.cm0 +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069 +} diff --git a/openocd-win/openocd/scripts/target/pxa255.cfg b/openocd-win/openocd/scripts/target/pxa255.cfg new file mode 100644 index 0000000..14ee13c --- /dev/null +++ b/openocd-win/openocd/scripts/target/pxa255.cfg @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# PXA255 chip ... originally from Intel, PXA line was sold to Marvell. +# This chip is now at end-of-life. Final orders have been taken. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pxa255 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x69264013 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME xscale -endian $_ENDIAN \ + -chain-position $_CHIPNAME.cpu + +# PXA255 comes out of reset using 3.6864 MHz oscillator. +# Until the PLL kicks in, keep the JTAG clock slow enough +# that we get no errors. +adapter speed 300 +$_TARGETNAME configure -event "reset-start" { adapter speed 300 } + +# both TRST and SRST are *required* for debug +# DCSR is often accessed with SRST active +reset_config trst_and_srst separate srst_nogate + +# reset processing that works with PXA +proc init_reset {mode} { + # assert both resets; equivalent to power-on reset + adapter assert trst assert srst + + # drop TRST after at least 32 cycles + sleep 1 + adapter deassert trst assert srst + + # minimum 32 TCK cycles to wake up the controller + runtest 50 + + # now the TAP will be responsive; validate scanchain + jtag arp_init + + # ... and take it out of reset + adapter deassert trst deassert srst +} + +proc jtag_init {} { + init_reset startup +} diff --git a/openocd-win/openocd/scripts/target/pxa270.cfg b/openocd-win/openocd/scripts/target/pxa270.cfg new file mode 100644 index 0000000..3121e96 --- /dev/null +++ b/openocd-win/openocd/scripts/target/pxa270.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#Marvell/Intel PXA270 Script + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pxa270 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +#IDs for pxa270. Are there more? +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # set useful default + set _CPUTAPID 0x49265013 +} + +if { [info exists CPUTAPID2] } { + set _CPUTAPID2 $CPUTAPID2 +} else { + # set useful default + set _CPUTAPID2 0x79265013 +} + +if { [info exists CPUTAPID3] } { + set _CPUTAPID2 $CPUTAPID3 +} else { + # set useful default + set _CPUTAPID3 0x89265013 +} + +# set adapter srst delay to the delay introduced by your reset circuit +# the rest of the needed delays are built into the openocd program +adapter srst delay 260 +# set the jtag_ntrst_delay to the delay introduced by a reset circuit +# the rest of the needed delays are built into the openocd program +jtag_ntrst_delay 250 + +set _TARGETNAME $_CHIPNAME.cpu +jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 + +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME +# maps to PXA internal RAM. If you are using a PXA255 +# you must initialize SDRAM or leave this option off +$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/pxa3xx.cfg b/openocd-win/openocd/scripts/target/pxa3xx.cfg new file mode 100644 index 0000000..d670c84 --- /dev/null +++ b/openocd-win/openocd/scripts/target/pxa3xx.cfg @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Marvell PXA3xx + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pxa3xx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# IDs for all currently known PXA3xx chips +if { [info exists CPUTAPID_PXA30X_A0] } { + set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0 +} else { + set _CPUTAPID_PXA30X_A0 0x0E648013 +} +if { [info exists CPUTAPID_PXA30X_A1] } { + set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1 +} else { + set _CPUTAPID_PXA30X_A1 0x1E648013 +} +if { [info exists CPUTAPID_PXA31X_A0] } { + set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0 +} else { + set _CPUTAPID_PXA31X_A0 0x0E649013 +} +if { [info exists CPUTAPID_PXA31X_A1] } { + set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1 +} else { + set _CPUTAPID_PXA31X_A1 0x1E649013 +} +if { [info exists CPUTAPID_PXA31X_A2] } { + set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2 +} else { + set _CPUTAPID_PXA31X_A2 0x2E649013 +} +if { [info exists CPUTAPID_PXA31X_B0] } { + set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0 +} else { + set _CPUTAPID_PXA31X_B0 0x3E649013 +} +if { [info exists CPUTAPID_PXA32X_B1] } { + set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1 +} else { + set _CPUTAPID_PXA32X_B1 0x5E642013 +} +if { [info exists CPUTAPID_PXA32X_B2] } { + set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2 +} else { + set _CPUTAPID_PXA32X_B2 0x6E642013 +} +if { [info exists CPUTAPID_PXA32X_C0] } { + set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0 +} else { + set _CPUTAPID_PXA32X_C0 0x7E642013 +} + +# set adapter srst delay to the delay introduced by your reset circuit +# the rest of the needed delays are built into the openocd program +adapter srst delay 260 + +# set the jtag_ntrst_delay to the delay introduced by a reset circuit +# the rest of the needed delays are built into the openocd program +jtag_ntrst_delay 250 + +set _TARGETNAME $_CHIPNAME.cpu +jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \ + -expected-id $_CPUTAPID_PXA30X_A0 \ + -expected-id $_CPUTAPID_PXA30X_A1 \ + -expected-id $_CPUTAPID_PXA31X_A0 \ + -expected-id $_CPUTAPID_PXA31X_A1 \ + -expected-id $_CPUTAPID_PXA31X_A2 \ + -expected-id $_CPUTAPID_PXA31X_B0 \ + -expected-id $_CPUTAPID_PXA32X_B1 \ + -expected-id $_CPUTAPID_PXA32X_B2 \ + -expected-id $_CPUTAPID_PXA32X_C0 + +target create $_TARGETNAME xscale -endian $_ENDIAN \ + -chain-position $_TARGETNAME + +# work area in internal RAM. +$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000 diff --git a/openocd-win/openocd/scripts/target/qn908x.cfg b/openocd-win/openocd/scripts/target/qn908x.cfg new file mode 100644 index 0000000..ac3e06b --- /dev/null +++ b/openocd-win/openocd/scripts/target/qn908x.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# NXP QN908x Cortex-M4F with 128 KiB SRAM + +source [find target/swj-dp.tcl] + +set CHIPNAME qn908x +set CHIPSERIES qn9080 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x20000 +} + +# SWD IDCODE (Cortex M4). +set CPUTAPID 0x2ba01477 + +swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID +dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu + +set TARGETNAME $CHIPNAME.cpu +target create $TARGETNAME cortex_m -dap $CHIPNAME.dap + +# SRAM is mapped at 0x04000000. +$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE + +# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum] +# The base must be set as 0x01000000, and the size parameter is unused. +set FLASHNAME $CHIPNAME.flash +flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum + +# We write directly to flash memory over this adapter interface. For debugging +# this could in theory be faster (the Core clock on reset is normally at 32MHz), +# but for flashing 1MHz is more reliable. +adapter speed 1000 + +# Delay on reset line. +adapter srst delay 200 + +cortex_m reset_config sysresetreq diff --git a/openocd-win/openocd/scripts/target/qualcomm_qca4531.cfg b/openocd-win/openocd/scripts/target/qualcomm_qca4531.cfg new file mode 100644 index 0000000..be0c8fa --- /dev/null +++ b/openocd-win/openocd/scripts/target/qualcomm_qca4531.cfg @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable +# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT). +# +# Product page: +# https://www.qualcomm.com/products/qca4531 +# +# Notes: +# - MIPS Processor ID (PRId): 0x00019374 +# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, +# operating at up to 650 MHz +# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up +# to 300 MHz +# - TRST is not available. +# - EJTAG PrRst signal is not supported +# - RESET_L pin B56 on the SoC will reset internal JTAG logic. +# +# Pins related for debug and bootstrap: +# Name Pin Description +# JTAG +# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG +# JTAG_TDI GPIO1, (B23) Software configurable, default JTAG +# JTAG_TDO GPIO2, (A28) Software configurable, default JTAG +# JTAG_TMS GPIO3, (A29) Software configurable, default JTAG +# Reset +# RESET_L -, (B56) Input only +# SYS_RST_L GPIO17, (A79) Output reset request or GPIO +# Bootstrap +# JTAG_MODE GPIO16, (A78) 0 - JTAG (Default); 1 - EJTAG +# DDR_SELECT GPIO10, (A57) 0 - DDR2; 1 - DDR1 +# UART +# UART0_SOUT GPIO10, (A57) +# UART0_SIN GPIO9, (B49) + +# Per default we need to use "none" variant to be able properly "reset init" +# or "reset halt" the CPU. +reset_config none srst_pulls_trst + +# For SRST based variant we still need proper timings. +# For ETH part the reset should be asserted at least for 10ms +# Since there is no other information let's take 100ms to be sure. +adapter srst pulse_width 100 + +# according to the SoC documentation it should take at least 5ms from +# reset end till bootstrap end. In the practice we need 8ms to get JTAG back +# to live. +adapter srst delay 8 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME qca4531 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +# provide watchdog helper. +proc disable_watchdog { } { + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event halted { disable_watchdog } + +# Since PrRst is not supported and SRST will reset complete chip +# with JTAG engine, we need to reset CPU from CPU itself. +$_TARGETNAME configure -event reset-assert-pre { + halt +} + +$_TARGETNAME configure -event reset-assert { + catch "mww 0xb806001C 0x01000000" +} + +# To be able to trigger complete chip reset, in case JTAG is blocked +# or CPU not responding, we still can use this helper. +proc full_reset { } { + reset_config srst_only + reset + halt + reset_config none +} + +# Section with helpers which can be used by boards +proc qca4531_ddr2_550_550_init {} { + # Clear reset flags for different SoC components + mww 0xb806001c 0xfeceffff + mww 0xb806001c 0xeeceffff + mww 0xb806001c 0xe6ceffff + + # PMU configurations + # Internal Switcher + mww 0xb8116c40 0x633c8176 + # Increase the DDR voltage + mww 0xb8116c44 0x10200000 + # XTAL Configurations + mww 0xb81162c0 0x4b962100 + mww 0xb81162c4 0x480 + mww 0xb81162c8 0x04000144 + # Recommended PLL configurations + mww 0xb81161c4 0x54086000 + mww 0xb8116244 0x54086000 + + # PLL init + mww 0xb8050008 0x0131001c + mww 0xb8050000 0x40001580 + mww 0xb8050004 0x40015800 + mww 0xb8050008 0x0131001c + mww 0xb8050000 0x00001580 + mww 0xb8050004 0x00015800 + mww 0xb8050008 0x01310000 + mww 0xb8050044 0x781003ff + mww 0xb8050048 0x003c103f + + # DDR2 init + mww 0xb8000108 0x401f0042 + mww 0xb80000b8 0x0000166d + mww 0xb8000000 0xcfaaf33b + mww 0xb800015c 0x0000000f + mww 0xb8000004 0xa272efa8 + mww 0xb8000018 0x0000ffff + mww 0xb80000c4 0x74444444 + mww 0xb80000c8 0x00000444 + mww 0xb8000004 0xa210ee28 + mww 0xb8000004 0xa2b2e1a8 + mww 0xb8000010 0x8 + mww 0xb80000bc 0x0 + mww 0xb8000010 0x10 + mww 0xb80000c0 0x0 + mww 0xb8000010 0x40 + mww 0xb800000c 0x2 + mww 0xb8000010 0x2 + mww 0xb8000008 0xb43 + mww 0xb8000010 0x1 + mww 0xb8000010 0x8 + mww 0xb8000010 0x4 + mww 0xb8000010 0x4 + mww 0xb8000008 0xa43 + mww 0xb8000010 0x1 + mww 0xb800000c 0x382 + mww 0xb8000010 0x2 + mww 0xb800000c 0x402 + mww 0xb8000010 0x2 + mww 0xb8000014 0x40be + mww 0xb800001C 0x20 + mww 0xb8000020 0x20 + mww 0xb80000cc 0xfffff + + # UART GPIO programming + mww 0xb8040000 0xff30b + mww 0xb8040044 0x908 + mww 0xb8040034 0x160000 +} diff --git a/openocd-win/openocd/scripts/target/quark_d20xx.cfg b/openocd-win/openocd/scripts/target/quark_d20xx.cfg new file mode 100644 index 0000000..ca8f440 --- /dev/null +++ b/openocd-win/openocd/scripts/target/quark_d20xx.cfg @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x38289013 +} + +jtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable +jtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable + +proc quark_d20xx_tapenable {} { + echo "enabling quark core tap" + irscan quark_d20xx.cltap 0x11 + drscan quark_d20xx.cltap 12 1 + runtest 10 +} + +proc quark_d20xx_tapdisable {} { + echo "disabling quark core tap" + irscan quark_d20xx.cltap 0x11 + drscan quark_d20xx.cltap 12 0 + runtest 10 +} + +proc quark_d20xx_setup {} { + jtag tapenable quark_d20xx.quark +} + +jtag configure quark_d20xx.quark -event tap-enable \ + "quark_d20xx_tapenable" + +jtag configure quark_d20xx.quark -event tap-disable \ + "quark_d20xx_tapdisable" + +target create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark + +quark_d20xx.quark configure -event reset-start { + # need to halt the target to write to memory + if {[quark_d20xx.quark curstate] ne "halted"} { halt } + # set resetbreak via the core tap + irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1 + # trigger a warm reset + mww 0xb0800570 0x2 + # clear resetbreak + irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0 +} + +jtag configure quark_d20xx.quark -event setup \ + "quark_d20xx_setup" diff --git a/openocd-win/openocd/scripts/target/quark_x10xx.cfg b/openocd-win/openocd/scripts/target/quark_x10xx.cfg new file mode 100644 index 0000000..6463f21 --- /dev/null +++ b/openocd-win/openocd/scripts/target/quark_x10xx.cfg @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME quark_x10xx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x18289013 +} + +jtag newtap quark_x10xx cpu -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable +jtag newtap quark_x10xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e681013 -enable + +#openocd puts tap at front of chain not end of chain +proc quark_x10xx_tapenable {} { + echo "enabling core tap" + irscan quark_x10xx.cltap 0x11 + drscan quark_x10xx.cltap 64 1 + runtest 10 +} + +proc quark_x10xx_tapdisable {} { + echo "disabling core tap" + irscan quark_x10xx.cltap 0x11 + drscan quark_x10xx.cltap 64 0 + runtest 10 +} + +proc quark_x10xx_setup {} { + jtag tapenable quark_x10xx.cpu +} + +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "quark_x10xx_tapenable" + +jtag configure $_CHIPNAME.cpu -event tap-disable \ + "quark_x10xx_tapdisable" + +set _TARGETNAME $_CHIPNAME.cpu +target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu + +jtag configure $_CHIPNAME.cpu -event setup \ + "quark_x10xx_setup" diff --git a/openocd-win/openocd/scripts/target/readme.txt b/openocd-win/openocd/scripts/target/readme.txt new file mode 100644 index 0000000..deec5b5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/readme.txt @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +Prerequisites: +The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands +do the same thing across all the targets. + +Rules to follow when writing scripts: + +1. The configuration script should be defined such as , for example, the following sequences are working: + reset + flash info <bank> +and + reset + flash erase_address <start> <len> +and + reset init + load + +In most cases this can be accomplished by specifying the default startup mode as reset_init (target command +in the configuration file). + +2. If the target is correctly configured, flash must be writable without any other helper commands. It is +assumed that all write-protect mechanisms should be disabled. + +3. The configuration scripts should be defined such as the binary that was written to flash verifies +(turn off remapping, checksums, etc...) + +flash write_image [file] <parameters> +verify_image [file] <parameters> + +4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked +multiple times only the last setting is used. + +interface/xxx.cfg files are always executed *before* target/xxx.cfg +files, so any adapter speed in interface/xxx.cfg will be overridden by +target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively, +set the default JTAG speed. + +Note that a target/xxx.cfg file can invoke another target/yyy.cfg file, +so one can create target subtype configurations where e.g. only +amount of DRAM, oscillator speeds differ and having a single +config file for the default/common settings. diff --git a/openocd-win/openocd/scripts/target/renesas_r7s72100.cfg b/openocd-win/openocd/scripts/target/renesas_r7s72100.cfg new file mode 100644 index 0000000..dc9a1d8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_r7s72100.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/A1H +# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME r7s72100 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID + +# Configuring only one core using DAP. +# Base addresses of cores: +# core 0 - 0x80030000 +set _TARGETNAME $_CHIPNAME.ca9 +dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu +target create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000 + +targets ${_TARGETNAME} diff --git a/openocd-win/openocd/scripts/target/renesas_rcar_gen2.cfg b/openocd-win/openocd/scripts/target/renesas_rcar_gen2.cfg new file mode 100644 index 0000000..31ba156 --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_rcar_gen2.cfg @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car Generation 2 SOCs +# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC +# - Each SOC can boot through any of the, up to 2, core types that it has +# e.g. H2 can boot through Cortex-A15 or Cortex-A7 + +# Supported Gen2 SOCs and their cores: +# H2: Cortex-A15 x 4, Cortex-A7 x 4 +# M2: Cortex-A15 x 2 +# V2H: Cortex-A15 x 2 +# M2N: Cortex-A15 x 2 +# E2: Cortex-A7 x 2 + +# Usage: +# There are 2 configuration options: +# SOC: Selects the supported SOC. (Default 'H2') +# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7' +# Defaults to 'CA15' if the SOC has one, else defaults to 'CA7' + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc H2 +} + +# Set configuration for each SOC and the default 'BOOT_CORE' +switch $_soc { + H2 { + set _CHIPNAME r8a7790 + set _num_ca15 4 + set _num_ca7 4 + set _boot_core CA15 + } + M2 { + set _CHIPNAME r8a7791 + set _num_ca15 2 + set _num_ca7 0 + set _boot_core CA15 + } + V2H { + set _CHIPNAME r8a7792 + set _num_ca15 2 + set _num_ca7 0 + set _boot_core CA15 + } + M2N { + set _CHIPNAME r8a7793 + set _num_ca15 2 + set _num_ca7 0 + set _boot_core CA15 + } + E2 { + set _CHIPNAME r8a7794 + set _num_ca15 0 + set _num_ca7 2 + set _boot_core CA7 + } + default { + error "'$_soc' is invalid!" + } +} + +# If configured, override the default 'CHIPNAME' +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} + +# If configured, override the default 'BOOT_CORE' +if { [info exists BOOT_CORE] } { + set _boot_core $BOOT_CORE +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)" +echo "\tBoot Core - $_boot_core\n" + +set _DAPNAME $_CHIPNAME.dap + +# TAP and DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID +dap create $_DAPNAME -chain-position $_CHIPNAME.cpu + +set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000} +set CA7_DBGBASE {0x800F0000 0x800F2000 0x800F4000 0x800F6000} + +set _targets "" +set smp_targets "" + +proc setup_ca {core_name dbgbase num boot} { + global _CHIPNAME + global _DAPNAME + global smp_targets + global _targets + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $_CHIPNAME.$core_name.$_core + set _CTINAME $_TARGETNAME.cti + set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \ + -coreid $_core -dbgbase [lindex $dbgbase $_core]" + if { $_core == 0 && $boot == 1 } { + set _targets "$_TARGETNAME" + } else { + set _command "$_command -defer-examine" + } + set smp_targets "$smp_targets $_TARGETNAME" + eval $_command + } +} + +# Organize target list based on the boot core +if { [string equal $_boot_core CA15] } { + setup_ca a15 $CA15_DBGBASE $_num_ca15 1 + setup_ca a7 $CA7_DBGBASE $_num_ca7 0 +} elseif { [string equal $_boot_core CA7] } { + setup_ca a7 $CA7_DBGBASE $_num_ca7 1 + setup_ca a15 $CA15_DBGBASE $_num_ca15 0 +} else { + setup_ca a15 $CA15_DBGBASE $_num_ca15 0 + setup_ca a7 $CA7_DBGBASE $_num_ca7 0 +} + +source [find target/renesas_rcar_reset_common.cfg] + +eval "target smp $smp_targets" +targets $_targets diff --git a/openocd-win/openocd/scripts/target/renesas_rcar_gen3.cfg b/openocd-win/openocd/scripts/target/renesas_rcar_gen3.cfg new file mode 100644 index 0000000..8dc0e7a --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_rcar_gen3.cfg @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car Generation 3 SOCs +# - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC +# - Each SOC can boot through any of the, up to 3, core types that it has +# e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7 + +# Supported Gen3 SOCs and their cores: +# H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step) +# M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step) +# M3N: Cortex-A57 x 2, Cortex-R7 x 2 (Lock-Step) +# V3U: Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step) +# V3H: Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step) +# V3M: Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step) +# E3: Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step) +# D3: Cortex-A53 x 1 + +# Usage: +# There are 2 configuration options: +# SOC: Selects the supported SOC. (Default 'H3') +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7' +# Defaults to 'CA57' if the SOC has one, else defaults to 'CA53' + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc H3 +} + +set _num_ca53 0 +set _num_ca57 0 +set _num_ca76 0 +set _num_cr52 0 +set _num_cr7 0 + +# Set configuration for each SOC and the default 'BOOT_CORE' +switch $_soc { + H3 { + set _CHIPNAME r8a77950 + set _num_ca57 4 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + } + M3W { + set _CHIPNAME r8a77960 + set _num_ca57 2 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + } + M3N { + set _CHIPNAME r8a77965 + set _num_ca57 2 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + } + V3M { + set _CHIPNAME r8a77970 + set _num_ca57 0 + set _num_ca53 2 + set _num_cr7 1 + set _boot_core CA53 + } + V3H { + set _CHIPNAME r8a77980 + set _num_ca57 0 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA53 + } + E3 { + set _CHIPNAME r8a77990 + set _num_ca57 0 + set _num_ca53 1 + set _num_cr7 1 + set _boot_core CA53 + } + D3 { + set _CHIPNAME r8a77995 + set _num_ca57 0 + set _num_ca53 1 + set _num_cr7 0 + set _boot_core CA53 + } + V3U { + set _CHIPNAME r8a779a0 + set _num_ca76 8 + set _num_cr52 1 + set _boot_core CA76 + } + default { + error "'$_soc' is invalid!" + } +} + +# If configured, override the default 'CHIPNAME' +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} + +# If configured, override the default 'BOOT_CORE' +if { [info exists BOOT_CORE] } { + set _boot_core $BOOT_CORE +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)" +echo "\tBoot Core - $_boot_core\n" + +set _DAPNAME $_CHIPNAME.dap + +# TAP and DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID +dap create $_DAPNAME -chain-position $_CHIPNAME.cpu + +set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000} +set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000} +set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} +set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} +set CR52_DBGBASE 0x80c10000 +set CR52_CTIBASE 0x80c20000 +set CR7_DBGBASE 0x80910000 +set CR7_CTIBASE 0x80918000 + +set _targets "" +set smp_targets "" + +proc setup_a5x {core_name dbgbase ctibase num boot} { + global _CHIPNAME + global _DAPNAME + global smp_targets + global _targets + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $_CHIPNAME.$core_name.$_core + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \ + -baseaddr [lindex $ctibase $_core] + set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \ + -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME" + if { $_core == 0 && $boot == 1 } { + set _targets "$_TARGETNAME" + } else { + set _command "$_command -defer-examine" + } + set smp_targets "$smp_targets $_TARGETNAME" + eval $_command + } +} + +proc setup_crx {core_name dbgbase ctibase num boot} { + global _CHIPNAME + global _DAPNAME + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $_CHIPNAME.$core_name + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase + if { $core_name == "r52" } { + set _command "target create $_TARGETNAME armv8r -dap $_DAPNAME \ + -ap-num 1 -dbgbase $dbgbase -cti $_CTINAME" + } else { + set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \ + -ap-num 1 -dbgbase $dbgbase" + } + if { $boot == 1 } { + set _targets "$_TARGETNAME" + } else { + set _command "$_command -defer-examine" + } + eval $_command + } +} + +# Organize target list based on the boot core +if { [string equal $_boot_core CA76] } { + setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1 + setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0 +} elseif { [string equal $_boot_core CA57] } { + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1 + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 +} elseif { [string equal $_boot_core CA53] } { + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1 + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0 +} elseif { [string equal $_boot_core CR52] } { + setup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1 + setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0 +} else { + setup_crx r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 1 + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 +} + +source [find target/renesas_rcar_reset_common.cfg] + +eval "target smp $smp_targets" +targets $_targets diff --git a/openocd-win/openocd/scripts/target/renesas_rcar_reset_common.cfg b/openocd-win/openocd/scripts/target/renesas_rcar_reset_common.cfg new file mode 100644 index 0000000..987f0c8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_rcar_reset_common.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas R-Car Gen2 Evaluation Board common settings + +reset_config trst_and_srst srst_nogate + +proc init_reset {mode} { + # Assert both resets: equivalent to a power-on reset + adapter assert trst assert srst + + # Deassert TRST to begin TAP communication + adapter deassert trst assert srst + + # TAP should now be responsive, validate the scan-chain + jtag arp_init +} diff --git a/openocd-win/openocd/scripts/target/renesas_rz_five.cfg b/openocd-win/openocd/scripts/target/renesas_rz_five.cfg new file mode 100644 index 0000000..5ab94ab --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_rz_five.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/Five SoC +# +# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz) + +transport select jtag + +reset_config trst_and_srst srst_gates_jtag +adapter speed 4000 +adapter srst delay 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME r9A07g043u +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/renesas_rz_g2.cfg b/openocd-win/openocd/scripts/target/renesas_rz_g2.cfg new file mode 100644 index 0000000..a3d5f48 --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_rz_g2.cfg @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/G2 SOCs +# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7 +# and Cortex-M33 for each SOC +# - Each SOC can boot through the Cortex-A5x cores + +# Supported RZ/G2 SOCs and their cores: +# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 +# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 +# RZ/G2N: Cortex-A57 x2, Cortex-R7 +# RZ/G2E: Cortex-A53 x2, Cortex-R7 +# RZ/G2L: Cortex-A55 x2, Cortex-M33 +# RZ/G2LC: Cortex-A55 x2, Cortex-M33 +# RZ/G2UL: Cortex-A55 x1, Cortex-M33 + +# Usage: +# There are 2 configuration options: +# SOC: Selects the supported SOC. (Default 'G2L') +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55' + +transport select jtag +reset_config trst_and_srst srst_gates_jtag +adapter speed 4000 +adapter srst delay 500 + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc G2L +} + +set _num_ca57 0 +set _num_ca55 0 +set _num_ca53 0 +set _num_cr7 0 +set _num_cm33 0 + +# Set configuration for each SOC and the default 'BOOT_CORE' +switch $_soc { + G2H { + set _CHIPNAME r8a774ex + set _num_ca57 4 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2M { + set _CHIPNAME r8a774ax + set _num_ca57 2 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2N { + set _CHIPNAME r8a774bx + set _num_ca57 2 + set _num_ca53 0 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2E { + set _CHIPNAME r8a774c0 + set _num_ca57 0 + set _num_ca53 2 + set _num_cr7 1 + set _boot_core CA53 + set _ap_num 1 + } + G2L { + set _CHIPNAME r9a07g044l + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + G2LC { + set _CHIPNAME r9a07g044c + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + G2UL { + set _CHIPNAME r9a07g043u + set _num_ca55 1 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + default { + error "'$_soc' is invalid!" + } +} + +# If configured, override the default 'CHIPNAME' +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} + +# If configured, override the default 'BOOT_CORE' +if { [info exists BOOT_CORE] } { + set _boot_core $BOOT_CORE +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x6ba00477 +} + +echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \ + $_num_cm33 CM33(s)" +echo "\tBoot Core - $_boot_core\n" + +set _DAPNAME $_CHIPNAME.dap + + +# TAP and DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \ + -ignore-version +dap create $_DAPNAME -chain-position $_CHIPNAME.cpu +echo "$_CHIPNAME.cpu" + +set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set CA55_DBGBASE {0x10E10000 0x10F10000} +set CA55_CTIBASE {0x10E20000 0x10F20000} +set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} +set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} +set CR7_DBGBASE 0x80910000 +set CR7_CTIBASE 0x80918000 +set CM33_DBGBASE 0xE000E000 +set CM33_CTIBASE 0xE0042000 + +set smp_targets "" + +proc setup_a5x {core_name dbgbase ctibase num boot} { + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $::_CHIPNAME.$core_name.$_core + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \ + -baseaddr [lindex $ctibase $_core] + target create $_TARGETNAME aarch64 -dap $::_DAPNAME \ + -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME + if { $_core > 0 || $boot == 0 } { + $_TARGETNAME configure -defer-examine + } + set ::smp_targets "$::smp_targets $_TARGETNAME" + } +} + +proc setup_cr7 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.r7 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase + target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \ + -ap-num 1 -dbgbase $dbgbase -defer-examine +} + +proc setup_cm33 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.m33 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase + target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ + -ap-num 2 -dbgbase $dbgbase -defer-examine +} + +# Organize target list based on the boot core +if { $_boot_core == "CA57" } { + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1 + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA53" } { + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1 + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA55" } { + setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1 + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE +} +echo "SMP targets:$smp_targets" +eval "target smp $smp_targets" + +if { $_soc == "G2L" || $_soc == "G2LC" || $_soc == "G2UL" } { + target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 +} + +proc init_reset {mode} { + # Assert both resets: equivalent to a power-on reset + adapter assert trst assert srst + + # Deassert TRST to begin TAP communication + adapter deassert trst assert srst + + # TAP should now be responsive, validate the scan-chain + jtag arp_init +} diff --git a/openocd-win/openocd/scripts/target/renesas_s7g2.cfg b/openocd-win/openocd/scripts/target/renesas_s7g2.cfg new file mode 100644 index 0000000..fa9c579 --- /dev/null +++ b/openocd-win/openocd/scripts/target/renesas_s7g2.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s7g2 +} + +if { [info exists CPU_JTAG_TAPID] } { + set _CPU_JTAG_TAPID $CPU_JTAG_TAPID +} else { + set _CPU_JTAG_TAPID 0x5ba00477 +} + +if { [info exists CPU_SWD_TAPID] } { + set _CPU_SWD_TAPID $CPU_SWD_TAPID +} else { + set _CPU_SWD_TAPID 0x5ba02477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _CPU_TAPID $_CPU_JTAG_TAPID +} else { + set _CPU_TAPID $_CPU_SWD_TAPID +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # 640 KB On-Chip SRAM + set _WORKAREASIZE 0xa0000 +} + +$_TARGETNAME configure -work-area-phys 0x1ffe0000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if { ![using_hla] } { + cortex_m reset_config sysresetreq +} + +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/rk3308.cfg b/openocd-win/openocd/scripts/target/rk3308.cfg new file mode 100644 index 0000000..b6086f1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/rk3308.cfg @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Rockchip RK3308 Target +# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf +# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rk3308 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x2ba01477 +} + +adapter speed 12000 + +transport select swd + +# declare the one SWD tap to access the DAP +swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version + +# create the DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# declare the 4 main application cores +set _TARGETNAME $_CHIPNAME.core +set _smp_command "" + +set $_TARGETNAME.base(0) 0x81010000 +set $_TARGETNAME.base(1) 0x81012000 +set $_TARGETNAME.base(2) 0x81014000 +set $_TARGETNAME.base(3) 0x81016000 + +set $_TARGETNAME.cti(0) 0x81018000 +set $_TARGETNAME.cti(1) 0x81019000 +set $_TARGETNAME.cti(2) 0x8101a000 +set $_TARGETNAME.cti(3) 0x8101b000 + +set _cores 4 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + set _command "target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \ + -dbgbase [set $_TARGETNAME.base($_core)]" + + if { $_core != 0 } { + set _smp_command "$_smp_command ${_TARGETNAME}$_core" + set _command "$_command -defer-examine" + } else { + # uncomment to use hardware threads pseudo rtos + # set _command "$_command -rtos hwthread" + set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \ + -work-area-backup 0" + set _smp_command "target smp ${_TARGETNAME}$_core" + } + + eval $_command +} + +eval $_smp_command + +targets ${_TARGETNAME}0 diff --git a/openocd-win/openocd/scripts/target/rk3399.cfg b/openocd-win/openocd/scripts/target/rk3399.cfg new file mode 100644 index 0000000..1e90414 --- /dev/null +++ b/openocd-win/openocd/scripts/target/rk3399.cfg @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Rockchip RK3399 Target +# https://rockchip.fr/RK3399%20datasheet%20V1.8.pdf +# https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.4%20Part1.pdf + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rk3399 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba02477 +} + +adapter speed 12000 + +transport select swd + +# declare the one SWD tap to access the DAP +swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version + +# create the DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 +set _TARGETNAME $_CHIPNAME.lcore +# declare the 6 main application cores +set _smp_command "" + +set $_TARGETNAME.base(0) 0x80030000 +set $_TARGETNAME.base(1) 0x80032000 +set $_TARGETNAME.base(2) 0x80034000 +set $_TARGETNAME.base(3) 0x80036000 +set $_TARGETNAME.cti(0) 0x80038000 +set $_TARGETNAME.cti(1) 0x80039000 +set $_TARGETNAME.cti(2) 0x8003a000 +set $_TARGETNAME.cti(3) 0x8003b000 + + +set _TARGETNAME $_CHIPNAME.bcore +set $_TARGETNAME.base(4) 0x80210000 +set $_TARGETNAME.base(5) 0x80310000 +set $_TARGETNAME.cti(4) 0x80220000 +set $_TARGETNAME.cti(5) 0x80320000 + +set _cores 6 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + if {$_core < 4} { + set _TARGETNAME $_CHIPNAME.lcore + } else { + set _TARGETNAME $_CHIPNAME.bcore + } + + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 1 + + target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \ + -dbgbase [set $_TARGETNAME.base($_core)] + + if { $_core != 0 } { + ${_TARGETNAME}$_core configure -defer-examine + } else { + # uncomment to use hardware threads pseudo rtos + # ${_TARGETNAME}$_core configure -rtos hwthread" + ${_TARGETNAME}$_core configure -work-area-size 0x30000 -work-area-phys 0xff8c0000 \ + -work-area-backup 0 + } + set _smp_command "$_smp_command ${_TARGETNAME}$_core" +} + +target smp $_smp_command + +targets rk3399.lcore0 diff --git a/openocd-win/openocd/scripts/target/rp2040.cfg b/openocd-win/openocd/scripts/target/rp2040.cfg new file mode 100644 index 0000000..de76b4e --- /dev/null +++ b/openocd-win/openocd/scripts/target/rp2040.cfg @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# RP2040 is a microcontroller with dual Cortex-M0+ core. +# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html + +# The device requires multidrop SWD for debug. +transport select swd + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rp2040 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x01002927 +} + +# Set to '1' to start rescue mode +if { [info exists RESCUE] } { + set _RESCUE $RESCUE +} else { + set _RESCUE 0 +} + +# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread +# handling of both cores, anything else for isolated debugging of both cores +if { [info exists USE_CORE] } { + set _USE_CORE $USE_CORE +} else { + set _USE_CORE SMP +} +set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }] + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID + +# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the +# PSM (power on state machine) of the RP2040 with a flag set in the +# VREG_AND_POR_CHIP_RESET register. Once the reset is released +# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag, +# and halt. Allowing the user to load some fresh code, rather than loading +# the potentially broken code stored in flash +if { $_RESCUE } { + dap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack + init + + # Clear DBGPWRUPREQ + $_CHIPNAME.rescue_dap dpreg 0x4 0x00000000 + + # Verifying CTRL/STAT is 0 + set _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4] + if {[expr {$_CTRLSTAT & 0xf0000000}]} { + echo "Rescue failed, DP CTRL/STAT readback $_CTRLSTAT" + } else { + echo "Now restart OpenOCD without RESCUE flag and load code to RP2040" + } + shutdown +} + +# core 0 +if { $_USE_CORE != 1 } { + dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0 + set _TARGETNAME_0 $_CHIPNAME.core0 + target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0 + # srst does not exist; use SYSRESETREQ to perform a soft reset + $_TARGETNAME_0 cortex_m reset_config sysresetreq +} + +# core 1 +if { $_USE_CORE != 0 } { + dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1 + set _TARGETNAME_1 $_CHIPNAME.core1 + target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1 + $_TARGETNAME_1 cortex_m reset_config sysresetreq +} + +if {[string compare $_USE_CORE SMP] == 0} { + $_TARGETNAME_0 configure -rtos hwthread + $_TARGETNAME_1 configure -rtos hwthread + target smp $_TARGETNAME_0 $_TARGETNAME_1 +} + +if { $_USE_CORE == 1 } { + set _FLASH_TARGET $_TARGETNAME_1 +} else { + set _FLASH_TARGET $_TARGETNAME_0 +} +# Backup the work area. The flash probe runs an algorithm on the target CPU. +# The flash is probed during gdb connect if gdb_memory_map is enabled (by default). +$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET + +if { $_BOTH_CORES } { + # Alias to ensure gdb connecting to core 1 gets the correct memory map + flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME + + # Select core 0 + targets $_TARGETNAME_0 +} diff --git a/openocd-win/openocd/scripts/target/rsl10.cfg b/openocd-win/openocd/scripts/target/rsl10.cfg new file mode 100644 index 0000000..f4692cc --- /dev/null +++ b/openocd-win/openocd/scripts/target/rsl10.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# RSL10: ARM Cortex-M3 +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rsl10 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# TODO: configure reset +# reset_config srst_only srst_nogate connect_assert_srst + +$_TARGETNAME configure -event examine-fail rsl10_lock_warning + +proc rsl10_check_connection {} { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg 0 0xfc] + if {$IDR != 0x24770011} { + echo "Error: Cannot access RSL10 AP, maybe connection problem!" + return 1 + } + return 0 +} + +proc rsl10_lock_warning {} { + if {[rsl10_check_connection]} {return} + + poll off + echo "****** WARNING ******" + echo "RSL10 device probably has lock engaged." + echo "Debug access is denied." + echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device." + echo "****** ....... ******" + echo "" +} + +flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME + +# TODO: implement flashing for nvr4 +# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/rtl872xd.cfg b/openocd-win/openocd/scripts/target/rtl872xd.cfg new file mode 100644 index 0000000..65730e2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/rtl872xd.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR MIT +# Realtek RTL872xD (ARM Cortex-M33 + M23, wifi+bt dualband soc) + +# HLA does not support AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + shutdown +} + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rtl872xd +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x6ba02477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME.km0 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 +target create $_TARGETNAME.km4 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 2 + +cortex_m reset_config sysresetreq + +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/samsung_s3c2410.cfg b/openocd-win/openocd/scripts/target/samsung_s3c2410.cfg new file mode 100644 index 0000000..5a04871 --- /dev/null +++ b/openocd-win/openocd/scripts/target/samsung_s3c2410.cfg @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Found on the 'TinCanTools' Hammer board. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Force an error until we get a good number. + set _CPUTAPID 0xffffffff +} + +#use combined on interfaces or targets that cannot set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0 + +# speed up memory downloads +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable diff --git a/openocd-win/openocd/scripts/target/samsung_s3c2440.cfg b/openocd-win/openocd/scripts/target/samsung_s3c2440.cfg new file mode 100644 index 0000000..d976a8e --- /dev/null +++ b/openocd-win/openocd/scripts/target/samsung_s3c2440.cfg @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the Samsung 2440 system on chip +# Tested on a S3C2440 Evaluation board by keesj +# Processor : ARM920Tid(wb) rev 0 (v4l) +# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2440 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0032409d +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1 + +#reset configuration +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/target/samsung_s3c2450.cfg b/openocd-win/openocd/scripts/target/samsung_s3c2450.cfg new file mode 100644 index 0000000..801e1bc --- /dev/null +++ b/openocd-win/openocd/scripts/target/samsung_s3c2450.cfg @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the Samsung 2450 system on chip +# Processor : ARM926ejs (wb) rev 0 (v4l) +# Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F + + +# FIX!!! what to use here? +# +# RCLK? +# +# adapter speed 0 +# +# Really low clock during reset? +# +# adapter speed 1 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2450 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926f0f +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +# FIX!!!!! should this really use srst_pulls_trst? +# With srst_pulls_trst "reset halt" will not reset into the +# halted mode, but rather "reset run" and then halt the target. +# +# However, without "srst_pulls_trst", then "reset halt" produces weird +# errors: +# WARNING: unknown debug reason: 0x0 +reset_config trst_and_srst diff --git a/openocd-win/openocd/scripts/target/samsung_s3c4510.cfg b/openocd-win/openocd/scripts/target/samsung_s3c4510.cfg new file mode 100644 index 0000000..45bed2f --- /dev/null +++ b/openocd-win/openocd/scripts/target/samsung_s3c4510.cfg @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c4510 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# This appears to be a "Version 1" arm7tdmi. +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f0f0f0f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/samsung_s3c6410.cfg b/openocd-win/openocd/scripts/target/samsung_s3c6410.cfg new file mode 100644 index 0000000..c157458 --- /dev/null +++ b/openocd-win/openocd/scripts/target/samsung_s3c6410.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# -*- tcl -*- +# Target configuration for the Samsung s3c6410 system on chip +# Tested on a SMDK6410 +# Processor : ARM1176 +# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) +# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places] +# [and I do not believe it to be accurate, hence the 0xffffffff below] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c6410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +# trace buffer +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID +} else { + set _ETBTAPID 0x2b900f0f +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07b76f0f +} + +#jtag scan chain + +jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME + +adapter srst delay 500 +jtag_ntrst_delay 500 + +#reset configuration +reset_config trst_and_srst + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/sharp_lh79532.cfg b/openocd-win/openocd/scripts/target/sharp_lh79532.cfg new file mode 100644 index 0000000..af6ceab --- /dev/null +++ b/openocd-win/openocd/scripts/target/sharp_lh79532.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lh79532 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # sharp changed the number! + set _CPUTAPID 0x00002061 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/sim3x.cfg b/openocd-win/openocd/scripts/target/sim3x.cfg new file mode 100644 index 0000000..e6bea70 --- /dev/null +++ b/openocd-win/openocd/scripts/target/sim3x.cfg @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Silicon Laboratories SiM3x Cortex-M3 +# + +# SiM3x devices support both JTAG and SWD transports. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME SiM3x +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { +# Minimum size of RAM in the Silicon Labs product matrix (8KB) + set _CPURAMSIZE 0x2000 +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { +# Minimum size of FLASH in the Silicon Labs product matrix (32KB) + set _CPUROMSIZE 0x8000 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE $_CPURAMSIZE +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME + +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} diff --git a/openocd-win/openocd/scripts/target/smp8634.cfg b/openocd-win/openocd/scripts/target/smp8634.cfg new file mode 100644 index 0000000..0e609d8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/smp8634.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for Sigma Designs SMP8634 (eventually even SMP8635) + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME smp8634 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x08630001 +} + +adapter srst delay 100 +jtag_ntrst_delay 100 + +reset_config trst_and_srst separate + +# jtag scan chain +# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian $_ENDIAN diff --git a/openocd-win/openocd/scripts/target/snps_em_sk_fpga.cfg b/openocd-win/openocd/scripts/target/snps_em_sk_fpga.cfg new file mode 100644 index 0000000..62f4dec --- /dev/null +++ b/openocd-win/openocd/scripts/target/snps_em_sk_fpga.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2014-2015,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# Xilinx Spartan-6 XC6SLX45 FPGA on EM Starter Kit v1. +# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2. +# + +source [find cpu/arc/em.tcl] + +set _CHIPNAME arc-em +set _TARGETNAME $_CHIPNAME.cpu + +# EM SK IDENTITY is 0x200444b1 +# EM SK v2 IDENTITY is 0x200044b1 +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \ + -expected-id 0x200044b1 + +set _coreid 0 +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \ + -coreid 0 -dbgbase $_dbgbase -endian little + +# There is no SRST, so do a software reset +$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME" + +arc_em_init_regs + +# vim:ft=tcl diff --git a/openocd-win/openocd/scripts/target/snps_hsdk.cfg b/openocd-win/openocd/scripts/target/snps_hsdk.cfg new file mode 100644 index 0000000..b4f3684 --- /dev/null +++ b/openocd-win/openocd/scripts/target/snps_hsdk.cfg @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2019,2020 Synopsys, Inc. +# Anton Kolesov <anton.kolesov@synopsys.com> +# Didin Evgeniy <didin@synopsys.com> + +# +# HS Development Kit SoC. +# +# Contains quad-core ARC HS38. +# + +source [find cpu/arc/hs.tcl] + +set _coreid 0 +set _dbgbase [expr {$_coreid << 13}] + +# CHIPNAME will be used to choose core family (600, 700 or EM). As far as +# OpenOCD is concerned EM and HS are identical. +set _CHIPNAME arc-em + +# OpenOCD discovers JTAG TAPs in reverse order. + +# ARC HS38 core 4 +set _TARGETNAME $_CHIPNAME.cpu4 +jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1 + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME +$_TARGETNAME configure -coreid $_coreid +$_TARGETNAME configure -dbgbase $_dbgbase +# Flush L2$. +$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] + +arc_hs_init_regs + +# Enable L2 cache support for core 4. +$_TARGETNAME arc cache l2 auto 1 + +# ARC HS38 core 3 +set _TARGETNAME $_CHIPNAME.cpu3 +jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1 + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME +$_TARGETNAME configure -coreid $_coreid +$_TARGETNAME configure -dbgbase $_dbgbase +$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] + +arc_hs_init_regs + +# Enable L2 cache support for core 3. +$_TARGETNAME arc cache l2 auto 1 + +# ARC HS38 core 2 +set _TARGETNAME $_CHIPNAME.cpu2 +jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1 + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME +$_TARGETNAME configure -coreid $_coreid +$_TARGETNAME configure -dbgbase $_dbgbase +$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] + +arc_hs_init_regs + +# Enable L2 cache support for core 2. +$_TARGETNAME arc cache l2 auto 1 + +# ARC HS38 core 1 +set _TARGETNAME $_CHIPNAME.cpu1 +jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1 + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME +$_TARGETNAME configure -coreid $_coreid +$_TARGETNAME configure -dbgbase $_dbgbase +$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] +arc_hs_init_regs + +# Enable L2 cache support for core 1. +$_TARGETNAME arc cache l2 auto 1 diff --git a/openocd-win/openocd/scripts/target/snps_hsdk_4xd.cfg b/openocd-win/openocd/scripts/target/snps_hsdk_4xd.cfg new file mode 100644 index 0000000..1520e3d --- /dev/null +++ b/openocd-win/openocd/scripts/target/snps_hsdk_4xd.cfg @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) 2023 Synopsys, Inc. +# Artemiy Volkov <artemiy@synopsys.com> + +# Adapted from tcl/target/snps_hsdk.cfg. + +# +# HS Development Kit SoC. +# +# Contains quad-core ARC HS47D. +# + +source [find cpu/arc/hs.tcl] + +set _coreid 0 +set _dbgbase [expr {$_coreid << 13}] + +# CHIPNAME will be used to choose core family (600, 700 or EM). As far as +# OpenOCD is concerned EM and HS are identical. +set _CHIPNAME arc-em + + +proc setup_cpu {core_index expected_id} { + global _coreid + global _dbgbase + global _CHIPNAME + + set _TARGETNAME $_CHIPNAME.cpu$core_index + jtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id + + target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME + $_TARGETNAME configure -coreid $_coreid + $_TARGETNAME configure -dbgbase $_dbgbase + $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" + + arc_hs_init_regs + + $_TARGETNAME arc cache l2 auto 1 + + set _coreid [expr {$_coreid + 1}] + set _dbgbase [expr {$_coreid << 13}] +} + +# OpenOCD discovers JTAG TAPs in reverse order. + +setup_cpu 4 0x100c54b1 +setup_cpu 3 0x100854b1 +setup_cpu 2 0x100454b1 +setup_cpu 1 0x100054b1 diff --git a/openocd-win/openocd/scripts/target/spear3xx.cfg b/openocd-win/openocd/scripts/target/spear3xx.cfg new file mode 100644 index 0000000..1261cd4 --- /dev/null +++ b/openocd-win/openocd/scripts/target/spear3xx.cfg @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Target configuration for the ST SPEAr3xx family of system on chip +# Supported SPEAr300, SPEAr310, SPEAr320 +# http://www.st.com/spear +# +# Processor: ARM926ejs +# Info: JTAG tap: spear3xx.cpu tap/device found: 0x07926041 +# Date: 2009-10-31 +# Author: Antonio Borneo <borneo.antonio@gmail.com> + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME spear3xx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926041 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \ + -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN \ + -chain-position $_TARGETNAME + +# SPEAr3xx has a 8K block of sram @ 0xd280.0000 +# REVISIT: what OS puts virtual address equal to phys? +$_TARGETNAME configure \ + -work-area-virt 0xd2800000 \ + -work-area-phys 0xd2800000 \ + -work-area-size 0x2000 \ + -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/stellaris.cfg b/openocd-win/openocd/scripts/target/stellaris.cfg new file mode 100644 index 0000000..3cd91eb --- /dev/null +++ b/openocd-win/openocd/scripts/target/stellaris.cfg @@ -0,0 +1,179 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TI/Luminary Stellaris LM3S chip family + +# Some devices have errata in returning their device class. +# DEVICECLASS is provided as a manual override +# Manual setting of a device class of 0xff is not allowed + +global _DEVICECLASS + +if { [info exists DEVICECLASS] } { + set _DEVICECLASS $DEVICECLASS +} else { + set _DEVICECLASS 0xff +} + +# Luminary chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + +# For now we ignore the SPI and UART options, which +# are usable only for ISP style initial flash programming. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s +} + +# CPU TAP ID 0x1ba00477 for early Sandstorm parts +# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2 +# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil) +# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm) +# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard) +# ... we'll ignore the JTAG version field, rather than list every +# chip revision that turns up. +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0ba00477 +} + +# SWD DAP, and JTAG TAP, take same params for now; +# ... even though SWD ignores all except TAPID, and +# JTAG shouldn't need anything more then irlen. (and TAPID). +swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ + -expected-id $_CPUTAPID -ignore-version +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # default to 2K working area + set _WORKAREASIZE 0x800 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# 8K working area at base of ram, not backed up +# +# NOTE: you may need or want to reconfigure the work area; +# some parts have just 6K, and you may want to use other +# addresses (at end of mem not beginning) or back it up. +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE + +# JTAG speed ... slow enough to work with a 12 MHz RC oscillator; +# LM3S parts don't support RTCK +# +# NOTE: this may be increased by a reset-init handler, after it +# configures and enables the PLL. Or you might need to decrease +# this, if you're using a slower clock. +adapter speed 500 + +source [find mem_helper.tcl] + +proc reset_peripherals {family} { + + source [find chip/ti/lm3s/lm3s.tcl] + + echo "Resetting Core Peripherals" + + # Disable the PLL and the system clock divider (nop if disabled) + mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV + mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 + + # RCC and RCC2 to their reset values + mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}] + mww $SYSCTL_RCC2 0x07806810 + mww $SYSCTL_RCC 0x078e3ad1 + + # Reset the deep sleep clock configuration register + mww $SYSCTL_DSLPCLKCFG 0x07800000 + + # Reset the clock gating registers + mww $SYSCTL_RCGC0 0x00000040 + mww $SYSCTL_RCGC1 0 + mww $SYSCTL_RCGC2 0 + mww $SYSCTL_SCGC0 0x00000040 + mww $SYSCTL_SCGC1 0 + mww $SYSCTL_SCGC2 0 + mww $SYSCTL_DCGC0 0x00000040 + mww $SYSCTL_DCGC1 0 + mww $SYSCTL_DCGC2 0 + + # Reset the remaining SysCtl registers + mww $SYSCTL_PBORCTL 0 + mww $SYSCTL_IMC 0 + mww $SYSCTL_GPIOHBCTL 0 + mww $SYSCTL_MOSCCTL 0 + mww $SYSCTL_PIOSCCAL 0 + mww $SYSCTL_I2SMCLKCFG 0 + + # Reset the peripherals + mww $SYSCTL_SRCR0 0xffffffff + mww $SYSCTL_SRCR1 0xffffffff + mww $SYSCTL_SRCR2 0xffffffff + mww $SYSCTL_SRCR0 0 + mww $SYSCTL_SRCR1 0 + mww $SYSCTL_SRCR2 0 + + # Clear any pending SysCtl interrupts + mww $SYSCTL_MISC 0xffffffff + + # Wait for any pending flash operations to complete + while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 } + + # Reset the flash controller registers + mww $FLASH_FMA 0 + mww $FLASH_FCIM 0 + mww $FLASH_FCMISC 0xffffffff + mww $FLASH_FWBVAL 0 +} + +$_TARGETNAME configure -event reset-start { + adapter speed 500 + + # + # When nRST is asserted on most Stellaris devices, it clears some of + # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong; + # and OpenOCD depends on those TRMs. So we won't use SRST on those + # chips. (Only power-on reset should affect debug state, beyond a + # few specified bits; not the chip's nRST input, wired to SRST.) + # + # REVISIT current errata specs don't seem to cover this issue. + # Do we have more details than this email? + # https://lists.berlios.de/pipermail + # /openocd-development/2008-August/003065.html + # + + global _DEVICECLASS + + if {$_DEVICECLASS != 0xff} { + set device_class $_DEVICECLASS + } else { + set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}] + } + + if {$device_class == 0 || $device_class == 1 || + $device_class == 3 || $device_class == 5 || $device_class == 0xa} { + if {![using_hla]} { + # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ + cortex_m reset_config sysresetreq + } + } else { + if {![using_hla]} { + # Tempest and Firestorm default to using NVIC VECTRESET + # peripherals will need resetting manually, see proc reset_peripherals + cortex_m reset_config vectreset + } + # reset peripherals, based on code in + # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf + reset_peripherals $device_class + } +} + +# flash configuration ... autodetects sizes, autoprobed +flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/stm32c0x.cfg b/openocd-win/openocd/scripts/target/stm32c0x.cfg new file mode 100644 index 0000000..d015120 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32c0x.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32c0x family +# +# stm32c0 devices support SWD transports only. +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32c0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 6kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1800 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +# reasonable default +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable DBGMCU clock + # RCC_APB1ENR |= DBGMCUEN + mmw 0x4002103C 0x08000000 0 + + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} diff --git a/openocd-win/openocd/scripts/target/stm32f0x.cfg b/openocd-win/openocd/scripts/target/stm32f0x.cfg new file mode 100644 index 0000000..5b8954e --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f0x.cfg @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f0x family + +# +# stm32 devices support SWD transports only. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0091 + # Section 29.5.3 + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME + +# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter speed 1000 + +adapter srst delay 100 + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32f0x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter speed 1000 +} + +proc stm32f0x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP + + # Stop watchdog counters during halt + mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f0x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 6 (48 MHz) + mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON + mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter speed 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init } diff --git a/openocd-win/openocd/scripts/target/stm32f1x.cfg b/openocd-win/openocd/scripts/target/stm32f1x.cfg new file mode 100644 index 0000000..53e81a5 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f1x.cfg @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f1x family + +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f1x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 4kB (as found on some STM32F100s) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0008 Section 26.6.3 + set _CPUTAPID 0x3ba00477 + } { + # this is the SW-DP tap id not the jtag tap id + set _CPUTAPID 0x1ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP | + # DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000307 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32f2x.cfg b/openocd-win/openocd/scripts/target/stm32f2x.cfg new file mode 100644 index 0000000..f475826 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f2x.cfg @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f2x family + +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f2x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0033 + # Section 32.6.3 - corresponds to Cortex-M3 r2p0 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32f3x.cfg b/openocd-win/openocd/scripts/target/stm32f3x.cfg new file mode 100644 index 0000000..aa978d9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f3x.cfg @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f3x family + +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f3x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter speed 1000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0316 + # Section 29.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32f3x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter speed 1000 +} + +proc stm32f3x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + + # Stop watchdog counters during halt + mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f3x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 8 (64 MHz) + mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON + mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter speed 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init } + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xe0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32f4x.cfg b/openocd-win/openocd/scripts/target/stm32f4x.cfg new file mode 100644 index 0000000..35d8275 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f4x.cfg @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f4x family + +# +# stm32f4 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f4x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 32kB (Available RAM in smallest device STM32F410) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0090 + # Section 38.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { + targets $_chipname.cpu + + if { [$_chipname.tpiu cget -protocol] eq "sync" } { + switch [$_chipname.tpiu cget -port-width] { + 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 + mmw 0xE0042004 0x00000060 0x000000c0 + mmw 0x40021020 0x00000000 0x0000ff00 + mmw 0x40021000 0x000000a0 0x000000f0 + mmw 0x40021008 0x000000f0 0x00000000 + } + 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 + mmw 0xE0042004 0x000000a0 0x000000c0 + mmw 0x40021020 0x00000000 0x000fff00 + mmw 0x40021000 0x000002a0 0x000003f0 + mmw 0x40021008 0x000003f0 0x00000000 + } + 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 + mmw 0xE0042004 0x000000e0 0x000000c0 + mmw 0x40021020 0x00000000 0x0fffff00 + mmw 0x40021000 0x00002aa0 0x00003ff0 + mmw 0x40021008 0x00003ff0 0x00000000 + } + } + } else { + # Set TRACE_IOEN; TRACE_MODE to async + mmw 0xE0042004 0x00000020 0x000000c0 + } +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" + +$_TARGETNAME configure -event reset-init { + # Configure PLL to boost clock to HSI x 4 (64 MHz) + mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P) + mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency) + mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON + sleep 10 ;# Wait for PLL to lock + mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2 + mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL + + # Boost JTAG frequency + adapter speed 8000 +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed since CPU speed will slow down to 16MHz with the reset + adapter speed 2000 +} diff --git a/openocd-win/openocd/scripts/target/stm32f7x.cfg b/openocd-win/openocd/scripts/target/stm32f7x.cfg new file mode 100644 index 0000000..3782b9a --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32f7x.cfg @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32f7x family + +# +# stm32f7 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f7x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 128kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x20000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0385 + # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0 + set _CPUTAPID 0x5ba00477 + } { + set _CPUTAPID 0x5ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME + +# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and +# also address 0x00200000 via the ITCM. The former mapping is read-write in +# hardware, while the latter is read-only. By presenting an alias, we +# accomplish two things: +# (1) We allow writing at 0x00200000 (because the alias acts identically to the +# original bank), which allows code intended to run from that address to +# also be linked for loading at that address, simplifying linking. +# (2) We allow the proper memory map to be delivered to GDB, which will cause +# it to use hardware breakpoints at the 0x00200000 mapping (correctly +# identifying it as Flash), which it would otherwise not do. Configuring +# the Flash via ITCM alias as virtual +flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 +} + +# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +# Use hardware reset. +# +# This target is compatible with connect_assert_srst, which may be set in a +# board file. +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" + +$_TARGETNAME configure -event reset-init { + # If the HSE was previously enabled and the external clock source + # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be + # properly switched back to HSI. This situation persists even over a system + # reset, including a pin reset via SRST. However, activating the clock + # security system will detect the problem and clear HSERDY to 0, which in + # turn allows the PLL to switch back to HSI properly. Since we just came + # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must + # have happened; in that case, activate the clock security system to clear + # HSERDY. + if {[mrw 0x40023800] & 0x00020000} { + mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON + sleep 10 ;# Wait for CSS to fire, if it wants to + mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON + mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC + sleep 1 ;# Wait for CSSF to clear + } + + # If the clock security system fired, it will pend an NMI. A pending NMI + # will cause a bad time for any subsequent executing code, such as a + # programming algorithm. + if {[mrw 0xE000ED04] & 0x80000000} { + # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be + # cleared by any normal means (such as ICSR or NVIC). It can only be + # cleared by entering the NMI handler or by resetting the processor. + echo "[target current]: Clock security system generated NMI. Clearing." + + # Keep the old DEMCR value. + set old [mrw 0xE000EDFC] + + # Enable vector catch on reset. + mww 0xE000EDFC 0x01000001 + + # Issue local reset via AIRCR. + mww 0xE000ED0C 0x05FA0001 + + # Restore old DEMCR value. + mww 0xE000EDFC $old + } + + # Configure PLL to boost clock to HSI x 10 (160 MHz) + mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) + mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency) + mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON + sleep 10 ;# Wait for PLL to lock + mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2) + mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL + + # Boost SWD frequency + # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo + # suffers from DAP WAITs + if {[using_jtag]} { + [[target current] cget -dap] memaccess 16 + } { + adapter speed 8000 + } +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed since CPU speed will slow down to 16MHz with the reset + adapter speed 2000 +} diff --git a/openocd-win/openocd/scripts/target/stm32g0x.cfg b/openocd-win/openocd/scripts/target/stm32g0x.cfg new file mode 100644 index 0000000..b6d9a22 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32g0x.cfg @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32g0x family + +# +# stm32g0 devices support SWD transports only. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32g0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Section 37.5.5 - corresponds to Cortex-M0+ + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +# reasonable default +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32g0x_default_reset_start {} { + # Reset clock is HSI16 (16 MHz) + adapter speed 2000 +} + +proc stm32g0x_default_examine_end {} { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} + +proc stm32g0x_default_reset_init {} { + # Increase clock to 64 Mhz + mmw 0x40022000 0x00000002 0x00000005 ;# FLASH_ACR: Latency = 2 + mww 0x4002100C 0x30000802 ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2 + mmw 0x40021000 0x01000000 0x00000000 ;# RCC_CR |= PLLON + mmw 0x40021008 0x00000002 0x00000005 ;# RCC_CFGR: SW=PLLRCLK + + # Boost JTAG frequency + adapter speed 4000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init } diff --git a/openocd-win/openocd/scripts/target/stm32g4x.cfg b/openocd-win/openocd/scripts/target/stm32g4x.cfg new file mode 100644 index 0000000..39ed1e3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32g4x.cfg @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32g4x family + +# +# stm32g4 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32g4x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# Smallest current target has 32kB ram, use 16kB by default to avoid surprises +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0440 + # Section 46.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 +} + +# reasonable default +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event reset-init { + # CPU comes out of reset with HSION | HSIRDY. + # Use HSI 16 MHz clock, compliant even with VOS == 2. + # 1 WS compliant with VOS == 2 and 16 MHz. + mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1 + mmw 0x40021000 0x00000100 0x00000000 ;# RCC_CR |= HSION + mmw 0x40021008 0x00000001 0x00000002 ;# RCC_CFGR: SW=HSI16 +} + +$_TARGETNAME configure -event reset-start { + # Reset clock is HSI (16 MHz) + adapter speed 2000 +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32h7x.cfg b/openocd-win/openocd/scripts/target/stm32h7x.cfg new file mode 100644 index 0000000..5aae938 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32h7x.cfg @@ -0,0 +1,308 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32h7x family + +# +# stm32h7 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32h7x +} + +if { [info exists DUAL_BANK] } { + set $_CHIPNAME.DUAL_BANK $DUAL_BANK + unset DUAL_BANK +} else { + set $_CHIPNAME.DUAL_BANK 0 +} + +if { [info exists DUAL_CORE] } { + set $_CHIPNAME.DUAL_CORE $DUAL_CORE + unset DUAL_CORE +} else { + set $_CHIPNAME.DUAL_CORE 0 +} + +# Issue a warning when hla is used, and fallback to single core configuration +if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } { + echo "Warning : hla does not support multicore debugging" + set $_CHIPNAME.DUAL_CORE 0 +} + +if { [info exists USE_CTI] } { + set $_CHIPNAME.USE_CTI $USE_CTI + unset USE_CTI +} else { + set $_CHIPNAME.USE_CTI 0 +} + +# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0 +if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } { + echo "Warning : could not use CTI with a single core device, CTI is disabled" + set $_CHIPNAME.USE_CTI 0 +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +if {![using_hla]} { + # STM32H7 provides an APB-AP at access port 2, which allows the access to + # the debug and trace features on the system APB System Debug Bus (APB-D). + target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 + swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000 + tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000 +} + +target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 + +$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0 + +if {[set $_CHIPNAME.DUAL_BANK]} { + flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0 +} + +if {[set $_CHIPNAME.DUAL_CORE]} { + target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 + + $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + + flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1 + + if {[set $_CHIPNAME.DUAL_BANK]} { + flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1 + } +} + +# Make sure that cpu0 is selected +targets $_CHIPNAME.cpu0 + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000 +} else { + if { [info exists OCTOSPI1] && $OCTOSPI1 } { + set a [llength [flash list]] + set _OCTOSPINAME1 $_CHIPNAME.octospi1 + flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000 + } + if { [info exists OCTOSPI2] && $OCTOSPI2 } { + set b [llength [flash list]] + set _OCTOSPINAME2 $_CHIPNAME.octospi2 + flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000 + } +} + +# Clock after reset is HSI at 64 MHz, no need of PLL +adapter speed 1800 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +# use hardware reset +# +# The STM32H7 does not support connect_assert_srst mode because the AXI is +# unavailable while SRST is asserted, and that is used to access the DBGMCU +# component at 0x5C001000 in the examine-end event handler. +# +# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead +# of the default AP0, and that works with SRST asserted; however, nonzero AP +# usage does not work with HLA, so is not done by default. That change could be +# made in a local configuration file if connect_assert_srst mode is needed for +# a specific application and a non-HLA adapter is in use. +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq + + if {[set $_CHIPNAME.DUAL_CORE]} { + $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq + } + + # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal + # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 + # makes the data access cacheable. This allows reading and writing data in the + # CPU cache from the debugger, which is far more useful than going straight to + # RAM when operating on typical variables, and is generally no worse when + # operating on special memory locations. + $_CHIPNAME.dap apcsw 0x08000000 0x08000000 +} + +$_CHIPNAME.cpu0 configure -event examine-end { + # Enable D3 and D1 DBG clocks + # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN + stm32h7x_dbgmcu_mmw 0x004 0x00600000 0 + + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain + stm32h7x_dbgmcu_mmw 0x004 0x00000007 0 + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain + stm32h7x_dbgmcu_mmw 0x004 0x00000038 0 + + # Stop watchdog counters during halt + # DBGMCU_APB3FZ1 |= WWDG1 + stm32h7x_dbgmcu_mmw 0x034 0x00000040 0 + # DBGMCU_APB1LFZ1 |= WWDG2 + stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0 + # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2 + stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0 + + # Enable clock for tracing + # DBGMCU_CR |= TRACECLKEN + stm32h7x_dbgmcu_mmw 0x004 0x00100000 0 + + # RM0399 (id 0x450) M7+M4 with SWO Funnel + # RM0433 (id 0x450) M7 with SWO Funnel + # RM0455 (id 0x480) M7 without SWO Funnel + # RM0468 (id 0x483) M7 without SWO Funnel + # Enable CM7 and CM4 slave ports in SWO trace Funnel + # Works ok also on devices single core and without SWO funnel + # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF + # SWTF_CTRL |= ENS0 | ENS1 + stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0 +} + +$_CHIPNAME.cpu0 configure -event reset-init { + # Clock after reset is HSI at 64 MHz, no need of PLL + adapter speed 4000 +} + +# get _CHIPNAME from current target +proc stm32h7x_get_chipname {} { + set t [target current] + set sep [string last "." $t] + if {$sep == -1} { + return $t + } + return [string range $t 0 [expr {$sep - 1}]] +} + +if {[set $_CHIPNAME.DUAL_CORE]} { + $_CHIPNAME.cpu1 configure -event examine-end { + set _CHIPNAME [stm32h7x_get_chipname] + global $_CHIPNAME.USE_CTI + + # Stop watchdog counters during halt + # DBGMCU_APB3FZ2 |= WWDG1 + stm32h7x_dbgmcu_mmw 0x038 0x00000040 0 + # DBGMCU_APB1LFZ2 |= WWDG2 + stm32h7x_dbgmcu_mmw 0x040 0x00000800 0 + # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2 + stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0 + + if {[set $_CHIPNAME.USE_CTI]} { + stm32h7x_cti_start + } + } +} + +# like mrw, but with target selection +proc stm32h7x_mrw {used_target reg} { + return [$used_target read_memory $reg 32 1] +} + +# like mmw, but with target selection +proc stm32h7x_mmw {used_target reg setbits clearbits} { + set old [stm32h7x_mrw $used_target $reg] + set new [expr {($old & ~$clearbits) | $setbits}] + $used_target mww $reg $new +} + +# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base +# this procedure will use the mem_ap on AP2 whenever possible +proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { + # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address + if {![using_hla]} { + set _CHIPNAME [stm32h7x_get_chipname] + set used_target $_CHIPNAME.ap2 + set reg_addr [expr {0xE00E1000 + $reg_offset}] + } { + set used_target [target current] + set reg_addr [expr {0x5C001000 + $reg_offset}] + } + + stm32h7x_mmw $used_target $reg_addr $setbits $clearbits +} + +if {[set $_CHIPNAME.USE_CTI]} { + # create CTI instances for both cores + cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000 + cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000 + + $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all } + $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all } + + $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all } + $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all } + + proc stm32h7x_cti_start {} { + set _CHIPNAME [stm32h7x_get_chipname] + + # Configure Cores' CTIs to halt each other + # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0 + $_CHIPNAME.cti0 write INEN0 0x1 + $_CHIPNAME.cti0 write OUTEN0 0x1 + $_CHIPNAME.cti1 write INEN0 0x1 + $_CHIPNAME.cti1 write OUTEN0 0x1 + + # enable CTIs + $_CHIPNAME.cti0 enable on + $_CHIPNAME.cti1 enable on + } + + proc stm32h7x_cti_stop {} { + set _CHIPNAME [stm32h7x_get_chipname] + + $_CHIPNAME.cti0 enable off + $_CHIPNAME.cti1 enable off + } + + proc stm32h7x_cti_prepare_restart_all {} { + stm32h7x_cti_prepare_restart cti0 + stm32h7x_cti_prepare_restart cti1 + } + + proc stm32h7x_cti_prepare_restart {cti} { + set _CHIPNAME [stm32h7x_get_chipname] + + # Acknowlodge EDBGRQ at TRIGOUT0 + $_CHIPNAME.$cti write INACK 0x01 + $_CHIPNAME.$cti write INACK 0x00 + } +} diff --git a/openocd-win/openocd/scripts/target/stm32h7x_dual_bank.cfg b/openocd-win/openocd/scripts/target/stm32h7x_dual_bank.cfg new file mode 100644 index 0000000..41a4773 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32h7x_dual_bank.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32h7x family (dual flash bank) + +# STM32H7xxxI 2Mo have a dual bank flash. +set DUAL_BANK 1 + +source [find target/stm32h7x.cfg] diff --git a/openocd-win/openocd/scripts/target/stm32l0.cfg b/openocd-win/openocd/scripts/target/stm32l0.cfg new file mode 100644 index 0000000..b4bdb18 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l0.cfg @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# M0+ devices only have SW-DP, but swj-dp code works, just don't +# set any jtag related features +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l0 +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 2kB (max ram on smallest part) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x800 +} + +# JTAG speed should be <= F_CPU/6. +# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz +adapter speed 300 + +adapter srst delay 100 + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # Arm, m0+, non-multidrop. + # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32l0_enable_HSI16 {} { + # Enable HSI16 as clock source + echo "STM32L0: Enabling HSI16" + + # Set HSI16ON in RCC_CR (leave MSI enabled) + mmw 0x40021000 0x00000101 0 + + # Set HSI16 as SYSCLK (RCC_CFGR) + mmw 0x4002100c 0x00000001 0 + + # Wait until System clock switches to HSI16 + while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { } + + # Increase speed + adapter speed 2500 +} + +$_TARGETNAME configure -event reset-init { + stm32l0_enable_HSI16 +} + +$_TARGETNAME configure -event reset-start { + adapter speed 300 +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0x40015804 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} diff --git a/openocd-win/openocd/scripts/target/stm32l0_dual_bank.cfg b/openocd-win/openocd/scripts/target/stm32l0_dual_bank.cfg new file mode 100644 index 0000000..ff3cb90 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l0_dual_bank.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/stm32l0.cfg] + +# Add the second flash bank. +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/stm32l1.cfg b/openocd-win/openocd/scripts/target/stm32l1.cfg new file mode 100644 index 0000000..53d9076 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l1.cfg @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# stm32l1 devices support both JTAG and SWD transports. +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l1 +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 10kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2800 +} + +# JTAG speed should be <= F_CPU/6. +# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz +adapter speed 300 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0038 + # Section 30.6.3 - corresponds to Cortex-M3 r2p0 + set _CPUTAPID 0x4ba00477 + } else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32l_enable_HSI {} { + # Enable HSI as clock source + echo "STM32L: Enabling HSI" + + # Set HSION in RCC_CR + mmw 0x40023800 0x00000101 0 + + # Set HSI as SYSCLK + mmw 0x40023808 0x00000001 0 + + # Increase JTAG speed + adapter speed 2000 +} + +$_TARGETNAME configure -event reset-init { + stm32l_enable_HSI +} + +$_TARGETNAME configure -event reset-start { + adapter speed 300 +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32l1x_dual_bank.cfg b/openocd-win/openocd/scripts/target/stm32l1x_dual_bank.cfg new file mode 100644 index 0000000..deefdb4 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l1x_dual_bank.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/stm32l1.cfg] + +# The stm32l1x 384kb have a dual bank flash. +# Let's add a definition for the second bank here. + +# Add the second flash bank. +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/stm32l4x.cfg b/openocd-win/openocd/scripts/target/stm32l4x.cfg new file mode 100644 index 0000000..9a69673 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l4x.cfg @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32l4x family + +# +# stm32l4 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l4x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 40kB (Available RAM in smallest device STM32L412) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0xa000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0351 + # Section 44.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 +} else { + if { [info exists OCTOSPI1] && $OCTOSPI1 } { + set a [llength [flash list]] + set _OCTOSPINAME1 $_CHIPNAME.octospi1 + flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 + } + if { [info exists OCTOSPI2] && $OCTOSPI2 } { + set b [llength [flash list]] + set _OCTOSPINAME2 $_CHIPNAME.octospi2 + flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400 + } +} + +# Common knowledges tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://openocd.zylin.com/#/c/3366/ +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { + targets $_chipname.cpu + + if { [$_chipname.tpiu cget -protocol] eq "sync" } { + switch [$_chipname.tpiu cget -port-width] { + 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 + mmw 0xE0042004 0x00000060 0x000000c0 + mmw 0x48001020 0x00000000 0x0000ff00 + mmw 0x48001000 0x000000a0 0x000000f0 + mmw 0x48001008 0x000000f0 0x00000000 + } + 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 + mmw 0xE0042004 0x000000a0 0x000000c0 + mmw 0x48001020 0x00000000 0x000fff00 + mmw 0x48001000 0x000002a0 0x000003f0 + mmw 0x48001008 0x000003f0 0x00000000 + } + 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 + mmw 0xE0042004 0x000000e0 0x000000c0 + mmw 0x48001020 0x00000000 0x0fffff00 + mmw 0x48001000 0x00002aa0 0x00003ff0 + mmw 0x48001008 0x00003ff0 0x00000000 + } + } + } else { + # Set TRACE_IOEN; TRACE_MODE to async + mmw 0xE0042004 0x00000020 0x000000c0 + } +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" + +$_TARGETNAME configure -event reset-init { + # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz). + # Use MSI 24 MHz clock, compliant even with VOS == 2. + # 3 WS compliant with VOS == 2 and 24 MHz. + mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency) + mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9 + + # Boost JTAG frequency + adapter speed 4000 +} + +$_TARGETNAME configure -event reset-start { + # Reset clock is MSI (4 MHz) + adapter speed 500 +} diff --git a/openocd-win/openocd/scripts/target/stm32l5x.cfg b/openocd-win/openocd/scripts/target/stm32l5x.cfg new file mode 100644 index 0000000..c43b699 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32l5x.cfg @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32l5x family +# stm32l5x devices support both JTAG and SWD transports. + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l5x +} + +source [find target/stm32x5x_common.cfg] + +proc stm32l5x_clock_config {} { + set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}] + # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL + # RCC_APB1ENR1 = PWREN + mww [expr {0x40021058 + $offset}] 0x10000000 + # delay for register clock enable (read back reg) + mrw [expr {0x40021058 + $offset}] + # PWR_CR1 : VOS Range 0 + mww [expr {0x40007000 + $offset}] 0 + # while (PWR_SR2 & VOSF) + while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {} + # FLASH_ACR : 5 WS for 110 MHz HCLK + mww 0x40022000 0x00000005 + # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz + # fVCO = 4 x 55 /1 = 220 + # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz + mww [expr {0x4002100C + $offset}] 0x01003711 + # RCC_CR |= PLLON + mmw [expr {0x40021000 + $offset}] 0x01000000 0 + # while !(RCC_CR & PLLRDY) + while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {} + # RCC_CFGR |= SW_PLL + mmw [expr {0x40021008 + $offset}] 0x00000003 0 + # while ((RCC_CFGR & SWS) != PLL) + while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {} +} + +$_TARGETNAME configure -event reset-init { + stm32l5x_clock_config + # Boost JTAG frequency + adapter speed 4000 +} diff --git a/openocd-win/openocd/scripts/target/stm32mp13x.cfg b/openocd-win/openocd/scripts/target/stm32mp13x.cfg new file mode 100644 index 0000000..bcf25c9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32mp13x.cfg @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32MP13x (Single Cortex-A7) +# http://www.st.com/stm32mp1 + +# HLA does not support custom CSW nor AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"." + shutdown +} + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32mp13x +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } else { + set _CPUTAPID 0x6ba02477 + } +} + +# Chip Level TAP Controller, only in jtag mode +if { [info exists CLCTAPID] } { + set _CLCTAPID $CLCTAPID +} else { + set _CLCTAPID 0x06501041 +} + +swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 +if { [using_jtag] } { + jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack + +# NOTE: keep ap-num and dbgbase to speed-up examine after reset +# NOTE: do not change the order of target create +target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1 +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 + +$_CHIPNAME.cpu cortex_a maskisr on +$_CHIPNAME.cpu cortex_a dacrfixup on + +# interface does not work while srst is asserted +# this is target specific, valid for every board +# srst resets the debug unit, behavior equivalent to "srst_pulls_trst" +reset_config srst_gates_jtag srst_pulls_trst + +adapter speed 5000 +adapter srst pulse_width 200 +# bootrom has an internal timeout of 1 second for detecting the boot flash. +# wait at least 1 second to guarantee we are out of bootrom +adapter srst delay 1100 + +add_help_text axi_secure "Set secure mode for following AXI accesses" +proc axi_secure {} { + $::_CHIPNAME.dap apsel 0 + $::_CHIPNAME.dap apcsw 0x10006000 +} + +add_help_text axi_nsecure "Set non-secure mode for following AXI accesses" +proc axi_nsecure {} { + $::_CHIPNAME.dap apsel 0 + $::_CHIPNAME.dap apcsw 0x30006000 +} + +axi_secure + +proc dbgmcu_enable_debug {} { + # keep clock enabled in low-power + ## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004} + # freeze watchdog 1 and 2 on core halted + catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004} + catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008} +} + +proc toggle_cpu_dbg_claim0 {} { + # toggle CPU0 DBG_CLAIM[0] + $::_CHIPNAME.ap1 mww 0xe00d0fa0 1 + $::_CHIPNAME.ap1 mww 0xe00d0fa4 1 +} + +# FIXME: most of handlers below will be removed once reset framework get merged +$_CHIPNAME.ap1 configure -event reset-deassert-pre { + adapter deassert srst deassert trst + catch {dap init} + catch {$::_CHIPNAME.dap apid 1} +} +$_CHIPNAME.cpu configure -event reset-deassert-pre {$::_CHIPNAME.cpu arp_examine} +$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug} +$_CHIPNAME.ap1 configure -event examine-start {dap init} +$_CHIPNAME.ap1 configure -event examine-end {dbgmcu_enable_debug} diff --git a/openocd-win/openocd/scripts/target/stm32mp15x.cfg b/openocd-win/openocd/scripts/target/stm32mp15x.cfg new file mode 100644 index 0000000..bcdda73 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32mp15x.cfg @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4) +# http://www.st.com/stm32mp1 + +# HLA does not support multi-cores nor custom CSW nor AP other than 0 +if { [using_hla] } { + echo "ERROR: HLA transport cannot work with this target." + echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"." + shutdown +} + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32mp15x +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } else { + set _CPUTAPID 0x6ba02477 + } +} + +# Chip Level TAP Controller, only in jtag mode +if { [info exists CLCTAPID] } { + set _CLCTAPID $CLCTAPID +} else { + set _CLCTAPID 0x06500041 +} + +swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 +if { [using_jtag] } { + jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack + +# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1 +# so defer-examine it until the reset framework get merged +# NOTE: keep ap-num and dbgbase to speed-up examine after reset +# NOTE: do not change the order of target create +target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1 +target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 +target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0 +target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 +target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 +target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine + +targets $_CHIPNAME.cpu0 + +target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1 +$_CHIPNAME.cpu0 cortex_a maskisr on +$_CHIPNAME.cpu1 cortex_a maskisr on +$_CHIPNAME.cpu0 cortex_a dacrfixup on +$_CHIPNAME.cpu1 cortex_a dacrfixup on + +cti create $_CHIPNAME.cti.sys -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000 +cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000 +cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000 +cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000 + +swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000 + +# interface does not work while srst is asserted +# this is target specific, valid for every board +# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires +# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the +# debug unit, behavior equivalent to "srst_pulls_trst" +reset_config srst_gates_jtag srst_pulls_trst + +adapter speed 5000 +adapter srst pulse_width 200 +# bootrom has an internal timeout of 1 second for detecting the boot flash. +# wait at least 1 second to guarantee we are out of bootrom +adapter srst delay 1100 + +add_help_text axi_secure "Set secure mode for following AXI accesses" +proc axi_secure {} { + $::_CHIPNAME.dap apsel 0 + $::_CHIPNAME.dap apcsw 0x10006000 +} + +add_help_text axi_nsecure "Set non-secure mode for following AXI accesses" +proc axi_nsecure {} { + $::_CHIPNAME.dap apsel 0 + $::_CHIPNAME.dap apcsw 0x30006000 +} + +axi_secure + +proc dbgmcu_enable_debug {} { + # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible + catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007} + # freeze watchdog 1 and 2 on cores halted + catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004} + catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008} +} + +proc toggle_cpu0_dbg_claim0 {} { + # toggle CPU0 DBG_CLAIM[0] + $::_CHIPNAME.ap1 mww 0xe00d0fa0 1 + $::_CHIPNAME.ap1 mww 0xe00d0fa4 1 +} + +proc detect_cpu1 {} { + set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1] + set dual_core [expr {$cpu1_prsr & 1}] + if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine} +} + +proc rcc_enable_traceclk {} { + $::_CHIPNAME.ap2 mww 0x5000080c 0x301 +} + +# FIXME: most of handler below will be removed once reset framework get merged +$_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}} +$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk} +$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine} +$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer} +$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0} +$_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}} +$_CHIPNAME.ap1 configure -event examine-start {dap init} +$_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug} +$_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1} +$_CHIPNAME.ap2 configure -event examine-end {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine} diff --git a/openocd-win/openocd/scripts/target/stm32u5x.cfg b/openocd-win/openocd/scripts/target/stm32u5x.cfg new file mode 100644 index 0000000..44b51e2 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32u5x.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32u5x family +# stm32u5x devices support both JTAG and SWD transports. + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32u5x +} + +source [find target/stm32x5x_common.cfg] + +proc stm32u5x_clock_config {} { + set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}] + # MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL + + # Enable voltage range 1 for frequency above 100 Mhz + # RCC_AHB3ENR = PWREN + mww [expr {0x46020C94 + $offset}] 0x00000004 + # delay for register clock enable (read back reg) + mrw [expr {0x46020C94 + $offset}] + # PWR_VOSR : VOS Range 1 + mmw [expr {0x4602080C + $offset}] 0x00030000 0 + # while !(PWR_VOSR & VOSRDY) + while {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {} + # FLASH_ACR : 4 WS for 160 MHz HCLK + mww [expr {0x40022000 + $offset}] 0x00000004 + # RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz + # PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8 + mww [expr {0x46020C28 + $offset}] 0x00040009 + # Enable EPOD Booster + mmw [expr {0x4602080C + $offset}] 0x00040000 0 + # while !(PWR_VOSR & BOOSTRDY) + while {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {} + # RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80 + # fVCO = 4 x 80 /1 = 320 + # SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz + mww [expr {0x46020C34 + $offset}] 0x0101024F + # RCC_CR |= PLL1ON + mmw [expr {0x46020C00 + $offset}] 0x01000000 0 + # while !(RCC_CR & PLL1RDY) + while {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {} + # RCC_CFGR1 |= SW_PLL + mmw [expr {0x46020C1C + $offset}] 0x00000003 0 + # while ((RCC_CFGR1 & SWS) != PLL) + while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {} +} + +$_TARGETNAME configure -event reset-init { + stm32u5x_clock_config + # Boost JTAG frequency + adapter speed 4000 +} diff --git a/openocd-win/openocd/scripts/target/stm32w108xx.cfg b/openocd-win/openocd/scripts/target/stm32w108xx.cfg new file mode 100644 index 0000000..e6a62e8 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32w108xx.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Target configuration for the ST STM32W108xx chips +# +# Processor: ARM Cortex-M3 +# Date: 2013-06-09 +# Author: Giuseppe Barba <giuseppe.barba@gmail.com> + +# +# stm32 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] == 0 } { + set _CHIPNAME stm32w108 +} else { + set _CHIPNAME $CHIPNAME +} + +# Work-area is a space in RAM used for flash programming +# By default use 8kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x3ba00477 + } { + set _CPUTAPID 0x1ba01477 + } +} + +set _ENDIAN little + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID + jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID + } else { + set _BSTAPID_1 0x169a862b + set _BSTAPID_2 0x269a862b + jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \ + -expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2 + } +} +# +# Set Target +# +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + + +# Use the flash driver from the EM357 +set _FLASHNAME $_CHIPNAME.flash + +# 64k (0x10000) of flash +flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME + +reset_config srst_nogate + +if {![using_hla]} { + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/stm32wbx.cfg b/openocd-win/openocd/scripts/target/stm32wbx.cfg new file mode 100644 index 0000000..737b144 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32wbx.cfg @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32wbx family + +# +# stm32wb devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32wbx +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x6ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +# Common knowledges tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://openocd.zylin.com/#/c/3366/ +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event reset-init { + # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz. + # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1. + # 2 WS compliant with VOS=Range1 and 24 MHz. + mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency) + mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz + # Boost JTAG frequency + adapter speed 4000 +} + +$_TARGETNAME configure -event reset-start { + # Reset clock is MSI (4 MHz) + adapter speed 500 +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE004203C 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0xE0042004 0x00000020 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32wlx.cfg b/openocd-win/openocd/scripts/target/stm32wlx.cfg new file mode 100644 index 0000000..39c897f --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32wlx.cfg @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32wlx family + +# +# stm32wl devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32wlx +} + +if { [info exists DUAL_CORE] } { + set $_CHIPNAME.DUAL_CORE $DUAL_CORE + unset DUAL_CORE +} else { + set $_CHIPNAME.DUAL_CORE 0 +} + +if { [info exists WKUP_CM0P] } { + set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P + unset WKUP_CM0P +} else { + set $_CHIPNAME.WKUP_CM0P 0 +} + +# Issue a warning when hla is used, and fallback to single core configuration +if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } { + echo "Warning : hla does not support multicore debugging" + set $_CHIPNAME.DUAL_CORE 0 + set $_CHIPNAME.WKUP_CM0P 0 +} + +# setup the Work-area start address and size +# Work-area is a space in RAM used for flash programming + +# Memory map for known devices: +# STM32WL x5JC x5JB x5J8 +# FLASH 256 128 64 +# SRAM1 32 16 0 +# SRAM2 32 32 20 + +# By default use 8kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +# Use SRAM2 as work area (some devices do not have SRAM1): +set WORKAREASTART_CM4 0x20008000 +set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}] + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x6ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap + +$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0 +flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq +} + +$_CHIPNAME.cpu0 configure -event reset-init { + # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz. + # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1. + # 2 WS compliant with VOS=Range1 and 24 MHz. + mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency) + mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz + # Boost JTAG frequency + adapter speed 4000 +} + +$_CHIPNAME.cpu0 configure -event reset-start { + # Reset clock is MSI (4 MHz) + adapter speed 500 +} + +$_CHIPNAME.cpu0 configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE004203C 0x00001800 0 + + set _CHIPNAME [stm32wlx_get_chipname] + global $_CHIPNAME.WKUP_CM0P + + if {[set $_CHIPNAME.WKUP_CM0P]} { + stm32wlx_wkup_cm0p + } +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +if {[set $_CHIPNAME.DUAL_CORE]} { + target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 + + $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0 + + flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1 + flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1 + + if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq + } + + proc stm32wlx_wkup_cm0p {} { + set _CHIPNAME [stm32wlx_get_chipname] + + # enable CPU2 boot after reset and after wakeup from Stop or Standby mode + # PWR_CR4 |= C2BOOT + stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0 + } +} + +# get _CHIPNAME from current target +proc stm32wlx_get_chipname {} { + set t [target current] + set sep [string last "." $t] + if {$sep == -1} { + return $t + } + return [string range $t 0 [expr {$sep - 1}]] +} + +# like mrw, but with target selection +proc stm32wlx_mrw {used_target reg} { + return [$used_target read_memory $reg 32 1] +} + +# like mmw, but with target selection +proc stm32wlx_mmw {used_target reg setbits clearbits} { + set old [stm32wlx_mrw $used_target $reg] + set new [expr {($old & ~$clearbits) | $setbits}] + $used_target mww $reg $new +} + +# Make sure that cpu0 is selected +targets $_CHIPNAME.cpu0 + +# Common knowledges tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://openocd.zylin.com/#/c/3366/ +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate diff --git a/openocd-win/openocd/scripts/target/stm32x5x_common.cfg b/openocd-win/openocd/scripts/target/stm32x5x_common.cfg new file mode 100644 index 0000000..fb3aeb1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32x5x_common.cfg @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# common script for stm32l5x and stm32u5x families + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers + # STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers + # Corresponds to Cortex®-M33 JTAG debug port ID code + set _CPUTAPID 0x0ba04477 + } { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x0be12477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +# use non-secure RAM by default +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# create sec/ns flash and otp memories (sizes will be probed) +flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME + +# Common knowledge tells JTAG speed should be <= F_CPU/6. +# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on +# the safe side. +# +# Note that there is a pretty wide band where things are +# more or less stable, see http://review.openocd.org/3366 +adapter speed 500 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {[using_hla]} { + echo "Warn : The selected adapter does not support debugging this device in secure mode" +} else { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32x5x_is_secure {} { + # read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16) + set DSCSR [mrw 0xE000EE08] + return [expr {($DSCSR & (1 << 16)) != 0}] +} + +proc stm32x5x_ahb_ap_non_secure_access {} { + # in HLA mode, non-secure debugging is possible without changing the AP CSW + if {![using_hla]} { + # SPROT=1=Non Secure access, Priv=1 + [[target current] cget -dap] apcsw 0x4B000000 0x4F000000 + } +} + +proc stm32x5x_ahb_ap_secure_access {} { + if {![using_hla]} { + # SPROT=0=Secure access, Priv=1 + [[target current] cget -dap] apcsw 0x0B000000 0x4F000000 + } +} + +$_TARGETNAME configure -event reset-start { + # Reset clock is MSI (4 MHz) + adapter speed 480 +} + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0xE0044004 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0044008 0x00001800 0 +} + +$_TARGETNAME configure -event halted { + set secure [stm32x5x_is_secure] + + if {$secure} { + set secure_str "Secure" + stm32x5x_ahb_ap_secure_access + } else { + set secure_str "Non-Secure" + stm32x5x_ahb_ap_non_secure_access + } + + # print the secure state only when it changes + set _TARGETNAME [target current] + global $_TARGETNAME.secure + + if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} { + echo "CPU in $secure_str state" + # update saved security state + set $_TARGETNAME.secure $secure + } +} + +$_TARGETNAME configure -event gdb-flash-erase-start { + set use_secure_workarea 0 + # check if FLASH_OPTR.TZEN is enabled + set FLASH_OPTR [mrw 0x40022040] + if {[expr {$FLASH_OPTR & 0x80000000}] == 0} { + echo "TZEN option bit disabled" + stm32x5x_ahb_ap_non_secure_access + } else { + stm32x5x_ahb_ap_secure_access + echo "TZEN option bit enabled" + + # check if FLASH_OPTR.RDP is not Level 0.5 + if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} { + set use_secure_workarea 1 + } + } + + set _TARGETNAME [target current] + set workarea_addr [$_TARGETNAME cget -work-area-phys] + echo "workarea_addr $workarea_addr" + + if {$use_secure_workarea} { + set workarea_addr [expr {$workarea_addr | 0x10000000}] + } else { + set workarea_addr [expr {$workarea_addr & ~0x10000000}] + } + + $_TARGETNAME configure -work-area-phys $workarea_addr +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + + # Set TRACE_EN and TRACE_IOEN in DBGMCU_CR + # Leave TRACE_MODE untouched (defaults to async). + # When using sync change this value accordingly to configure trace pins + # assignment + mmw 0xE0044004 0x00000030 0 +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/openocd-win/openocd/scripts/target/stm32xl.cfg b/openocd-win/openocd/scripts/target/stm32xl.cfg new file mode 100644 index 0000000..ad68f3a --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm32xl.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32xl family (dual flash bank) +source [find target/stm32f1x.cfg] + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/stm8l.cfg b/openocd-win/openocd/scripts/target/stm8l.cfg new file mode 100644 index 0000000..583a2a4 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l.cfg @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm8l family + +# +# stm8 devices support SWIM transports only. +# + +transport select swim + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm8l +} + +# Work-area is a space in RAM used for flash programming +# By default use 1kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists FLASHSTART] } { + set _FLASHSTART $FLASHSTART +} else { + set _FLASHSTART 0x8000 +} + +if { [info exists FLASHEND] } { + set _FLASHEND $FLASHEND +} else { + set _FLASHEND 0xffff +} + +if { [info exists EEPROMSTART] } { + set _EEPROMSTART $EEPROMSTART +} else { + set _EEPROMSTART 0x4000 +} + +if { [info exists EEPROMEND] } { + set _EEPROMEND $EEPROMEND +} else { + set _EEPROMEND 0x43ff +} + +if { [info exists OPTIONSTART] } { + set _OPTIONSTART $OPTIONSTART +} else { + set _OPTIONSTART 0x4800 +} + +if { [info exists OPTIONEND] } { + set _OPTIONEND $OPTIONEND +} else { + set _OPTIONEND 0x487f +} + +if { [info exists BLOCKSIZE] } { + set _BLOCKSIZE $BLOCKSIZE +} else { + set _BLOCKSIZE 0x80 +} + +swim newtap $_CHIPNAME cpu + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu + +$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1 +$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND +$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE + +# Uncomment this line to enable interrupts while instruction step +#$_TARGETNAME configure -enable_step_irq + +# Set stm8l type +$_TARGETNAME configure -enable_stm8l + +# Set high speed +adapter speed 800 +# Set low speed +#adapter speed 363 + +reset_config srst_only + +#uncomment this line to connect under reset +#reset_config srst_nogate connect_assert_srst diff --git a/openocd-win/openocd/scripts/target/stm8l151x2.cfg b/openocd-win/openocd/scripts/target/stm8l151x2.cfg new file mode 100644 index 0000000..db88c71 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l151x2.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x2 +# Supported Devices: +# STM8L151C2 +# STM8L151F2 +# STM8L151G2 +# STM8L151K2 + +# 1kB RAM +# Start 0x0000 +# End 0x03ff +set WORKAREASIZE 1024 + +# 4kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0x8fff + +# 256B EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x10ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x487f + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8l151x3.cfg b/openocd-win/openocd/scripts/target/stm8l151x3.cfg new file mode 100644 index 0000000..fe904b4 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l151x3.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x3 +# Supported Devices: +# STM8L151C3 +# STM8L151F3 +# STM8L151G3 +# STM8L151K3 + +# 1kB RAM +# Start 0x0000 +# End 0x03ff +set WORKAREASIZE 1024 + +# 8kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0x9fff + +# 256B EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x10ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x487f + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8l152.cfg b/openocd-win/openocd/scripts/target/stm8l152.cfg new file mode 100644 index 0000000..033b826 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l152.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg' +echo ' using stm8l152.cfg for backwards compatability' + +set EEPROMSTART 0x1000 +set EEPROMEND 0x13ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8l15xx4.cfg b/openocd-win/openocd/scripts/target/stm8l15xx4.cfg new file mode 100644 index 0000000..4438193 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l15xx4.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x4/STM8L152x4 +# Supported Devices: +# STM8L151C4 +# STM8L151G4 +# STM8L151K4 +# STM8L152C4 +# STM8L152K4 + +# 2kB RAM +# Start 0x0000 +# End 0x07ff +set WORKAREASIZE 2048 + +# 16kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0xbfff + +# 1kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x13ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8l15xx6.cfg b/openocd-win/openocd/scripts/target/stm8l15xx6.cfg new file mode 100644 index 0000000..5243295 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l15xx6.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x6/STM8L152x6 +# Supported Devices: +# STM8L151C6 +# STM8L151G6 +# STM8L151K6 +# STM8L151R6 +# STM8L152C6 +# STM8L152K6 +# STM8L152R6 + +# 2kB RAM +# Start 0x0000 +# End 0x07ff +set WORKAREASIZE 2048 + +# 32kB Flash +set FLASHSTART 0x8000 +set FLASHEND 0xffff + +# 1kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x13ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8l15xx8.cfg b/openocd-win/openocd/scripts/target/stm8l15xx8.cfg new file mode 100644 index 0000000..e354827 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8l15xx8.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Config script for STM8L151x8/STM8L152x8 +# Supported Devices: +# STM8L151C8 +# STM8L151M8 +# STM8L151R8 +# STM8L152C8 +# STM8L152K8 +# STM8L152M8 +# STM8L152R8 + +# 4kB RAM +# Start 0x0000 +# End 0x0fff +set WORKAREASIZE 4096 + +# 64kB Flash +set FLASHSTART 0x08000 +set FLASHEND 0x17fff + +# 2kB EEPROM +set EEPROMSTART 0x1000 +set EEPROMEND 0x17ff + +set OPTIONSTART 0x4800 +set OPTIONEND 0x48ff + +proc stm8_reset_rop {} { + mwb 0x4800 0xaa + mwb 0x4800 0xaa + reset halt +} + +source [find target/stm8l.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8s.cfg b/openocd-win/openocd/scripts/target/stm8s.cfg new file mode 100644 index 0000000..01e50d0 --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8s.cfg @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm8s family + +# +# stm8 devices support SWIM transports only. +# + +transport select swim + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm8s +} + +# Work-area is a space in RAM used for flash programming +# By default use 1kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists FLASHSTART] } { + set _FLASHSTART $FLASHSTART +} else { + set _FLASHSTART 0x8000 +} + +if { [info exists FLASHEND] } { + set _FLASHEND $FLASHEND +} else { + set _FLASHEND 0xffff +} + +if { [info exists EEPROMSTART] } { + set _EEPROMSTART $EEPROMSTART +} else { + set _EEPROMSTART 0x4000 +} + +if { [info exists EEPROMEND] } { + set _EEPROMEND $EEPROMEND +} else { + set _EEPROMEND 0x43ff +} + +if { [info exists OPTIONSTART] } { + set _OPTIONSTART $OPTIONSTART +} else { + set _OPTIONSTART 0x4800 +} + +if { [info exists OPTIONEND] } { + set _OPTIONEND $OPTIONEND +} else { + set _OPTIONEND 0x487f +} + +if { [info exists BLOCKSIZE] } { + set _BLOCKSIZE $BLOCKSIZE +} else { + set _BLOCKSIZE 0x80 +} + +swim newtap $_CHIPNAME cpu + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu + +$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1 +$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND +$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE + +# Uncomment this line to enable interrupts while instruction step +#$_TARGETNAME configure -enable_step_irq + +# Set high speed +adapter speed 800 +# Set low speed +#adapter speed 363 + +reset_config srst_only + +# uncomment this line to connect under reset +#reset_config srst_nogate connect_assert_srst diff --git a/openocd-win/openocd/scripts/target/stm8s003.cfg b/openocd-win/openocd/scripts/target/stm8s003.cfg new file mode 100644 index 0000000..60f5c3c --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8s003.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#config script for STM8S003 + +set FLASHEND 0x9FFF +set BLOCKSIZE 0x40 + +proc stm8_reset_rop {} { + mwb 0x4800 0x00 + reset halt +} + +source [find target/stm8s.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8s103.cfg b/openocd-win/openocd/scripts/target/stm8s103.cfg new file mode 100644 index 0000000..41350cb --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8s103.cfg @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#config script for STM8S103 + +set FLASHEND 0x9FFF +set EEPROMEND 0x427F +set OPTIONEND 0x480A +set BLOCKSIZE 0x40 + +proc stm8_reset_rop {} { + mwb 0x4800 0x00 + reset halt +} + +source [find target/stm8s.cfg] diff --git a/openocd-win/openocd/scripts/target/stm8s105.cfg b/openocd-win/openocd/scripts/target/stm8s105.cfg new file mode 100644 index 0000000..6af491e --- /dev/null +++ b/openocd-win/openocd/scripts/target/stm8s105.cfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#config script for STM8S105 + +proc stm8_reset_rop {} { + mwb 0x4800 0x00 + reset halt +} + +source [find target/stm8s.cfg] diff --git a/openocd-win/openocd/scripts/target/str710.cfg b/openocd-win/openocd/scripts/target/str710.cfg new file mode 100644 index 0000000..ff89717 --- /dev/null +++ b/openocd-win/openocd/scripts/target/str710.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#start slow, speed up after reset +adapter speed 10 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str710 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-start { adapter speed 10 } +$_TARGETNAME configure -event reset-init { + adapter speed 6000 + +# Because the hardware cannot be interrogated for the protection state +# of sectors, initialize all the sectors to be unprotected. The initial +# state is reflected by the driver, too. + flash protect 0 0 last off + flash protect 1 0 last off +} +$_TARGETNAME configure -event gdb-flash-erase-start { + flash protect 0 0 7 off + flash protect 1 0 1 off +} + +$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank str7x <base> <size> 0 0 <target#> <variant> +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x diff --git a/openocd-win/openocd/scripts/target/str730.cfg b/openocd-win/openocd/scripts/target/str730.cfg new file mode 100644 index 0000000..57681f9 --- /dev/null +++ b/openocd-win/openocd/scripts/target/str730.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#STR730 CPU + +adapter speed 3000 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str730 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +#jtag nTRST and nSRST delay +adapter srst delay 500 +jtag_ntrst_delay 500 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 + +$_TARGETNAME configure -event reset-start { adapter speed 10 } +$_TARGETNAME configure -event reset-init { + adapter speed 3000 + +# Because the hardware cannot be interrogated for the protection state +# of sectors, initialize all the sectors to be unprotected. The initial +# state is reflected by the driver, too. + flash protect 0 0 last off +} +$_TARGETNAME configure -event gdb-flash-erase-start { + flash protect 0 0 7 off +} + +$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base> <size> <chip_width> <bus_width> +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x diff --git a/openocd-win/openocd/scripts/target/str750.cfg b/openocd-win/openocd/scripts/target/str750.cfg new file mode 100644 index 0000000..5af7b74 --- /dev/null +++ b/openocd-win/openocd/scripts/target/str750.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#STR750 CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str750 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4f1f0041 +} + +# jtag speed +adapter speed 10 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +#jtag nTRST and nSRST delay +adapter srst delay 500 +jtag_ntrst_delay 500 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 + +$_TARGETNAME configure -event reset-start { adapter speed 10 } +$_TARGETNAME configure -event reset-init { + adapter speed 3000 + + init_smi +# Because the hardware cannot be interrogated for the protection state +# of sectors, initialize all the sectors to be unprotected. The initial +# state is reflected by the driver, too. + flash protect 0 0 last off + flash protect 1 0 last off +} +$_TARGETNAME configure -event gdb-flash-erase-start { + flash protect 0 0 7 off + flash protect 1 0 1 off +} + +$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base> <size> <chip_width> <bus_width> +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x + +# Serial NOR on SMI CS0. +set _FLASHNAME $_CHIPNAME.snor +flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME + +source [find mem_helper.tcl] + +proc init_smi {} { + mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs + mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit + mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1 +} diff --git a/openocd-win/openocd/scripts/target/str912.cfg b/openocd-win/openocd/scripts/target/str912.cfg new file mode 100644 index 0000000..3167b40 --- /dev/null +++ b/openocd-win/openocd/scripts/target/str912.cfg @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for str9 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed. We need to stick to 16kHz until we've finished reset. +adapter speed 16 + +adapter srst delay 100 +jtag_ntrst_delay 100 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst + +if { [info exists FLASHTAPID] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0x04570041 +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # possible values: 0x1457f041, 0x2457f041 + # we ignore version in check below + set _BSTAPID 0x1457f041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-start { adapter speed 16 } + +$_TARGETNAME configure -event reset-init { + # We can increase speed now that we know the target is halted. + #adapter speed 3000 + + # -- Enable 96K RAM + # PFQBC enabled / DTCM & AHB wait-states disabled + mww 0x5C002034 0x0191 + + str9x flash_config 0 4 2 0 0x80000 + flash protect 0 0 7 off +} + +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 + +#flash bank str9x <base> <size> 0 0 <target#> <variant> +set _FLASHNAME $_CHIPNAME.flash0 +flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME diff --git a/openocd-win/openocd/scripts/target/swj-dp.tcl b/openocd-win/openocd/scripts/target/swj-dp.tcl new file mode 100644 index 0000000..f2b233f --- /dev/null +++ b/openocd-win/openocd/scripts/target/swj-dp.tcl @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ARM Debug Interface V5 (ADI_V5) utility +# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since +# SW-DP and JTAG-DP targets don't need to switch based +# on which transport is active. +# +# declare a JTAG or SWD Debug Access Point (DAP) +# based on the transport in use with this session. +# You can't access JTAG ops when SWD is active, etc. + +# params are currently what "jtag newtap" uses +# because OpenOCD internals are still strongly biased +# to JTAG .... but for SWD, "irlen" etc are ignored, +# and the internals work differently + +# for now, ignore non-JTAG and non-SWD transports +# (e.g. initial flash programming via SPI or UART) + +# split out "chip" and "tag" so we can someday handle +# them more uniformly irlen too...) + +if [catch {transport select}] { + echo "Error: unable to select a session transport. Can't continue." + shutdown +} + +proc swj_newdap {chip tag args} { + if [using_jtag] { + eval jtag newtap $chip $tag $args + } elseif [using_swd] { + eval swd newdap $chip $tag $args + } else { + echo "Error: transport '[ transport select ]' not supported by swj_newdap" + shutdown + } +} diff --git a/openocd-win/openocd/scripts/target/swm050.cfg b/openocd-win/openocd/scripts/target/swm050.cfg new file mode 100644 index 0000000..6cc5f6d --- /dev/null +++ b/openocd-win/openocd/scripts/target/swm050.cfg @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Synwit SWM050 + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME swm050 +} +set _CHIPSERIES swm050 + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x400 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME + +adapter speed 1000 + +$_TARGETNAME configure -event reset-init { + # Stop the watchdog, just to be safe + mww 0x40019000 0x00 + # Set clock divider value to 1 + mww 0x400F0000 0x01 + # Set system clock to 18Mhz + mww 0x400F0008 0x00 +} + +# SWM050 (Cortex-M0 core) supports SYSRESETREQ +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} diff --git a/openocd-win/openocd/scripts/target/test_reset_syntax_error.cfg b/openocd-win/openocd/scripts/target/test_reset_syntax_error.cfg new file mode 100644 index 0000000..7ef5914 --- /dev/null +++ b/openocd-win/openocd/scripts/target/test_reset_syntax_error.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Test script to check that syntax error in reset +# script is reported properly. + +# at91eb40a target + +#jtag scan chain +set _CHIPNAME syntaxtest +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf + +#target configuration +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -event reset-init { + + syntax error +} diff --git a/openocd-win/openocd/scripts/target/test_syntax_error.cfg b/openocd-win/openocd/scripts/target/test_syntax_error.cfg new file mode 100644 index 0000000..2d5da7f --- /dev/null +++ b/openocd-win/openocd/scripts/target/test_syntax_error.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This script tests a syntax error in the startup +# config script + +syntax error here diff --git a/openocd-win/openocd/scripts/target/ti-ar7.cfg b/openocd-win/openocd/scripts/target/ti-ar7.cfg new file mode 100644 index 0000000..28b6cf7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti-ar7.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments AR7 SOC - used in many adsl modems. +# http://www.linux-mips.org/wiki/AR7 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ti-ar7 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0000100f +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu + +# use onboard 4k sram as working area +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000 diff --git a/openocd-win/openocd/scripts/target/ti-cjtag.cfg b/openocd-win/openocd/scripts/target/ti-cjtag.cfg new file mode 100644 index 0000000..97111f1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti-cjtag.cfg @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# A start sequence to change from cJTAG to 4-pin JTAG +# This is needed for CC2538 and CC26xx to be able to communicate through JTAG +# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information. +proc ti_cjtag_to_4pin_jtag {jrc} { + # Bypass + runtest 20 + irscan $jrc 0x3f -endstate RUN/IDLE + # Two zero bit scans and a one bit drshift + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + + # A two bit drhift and a 9 bit drshift + pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE + pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE + pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE + + # Bypass + irscan $jrc 0x3f -endstate RUN/IDLE + + # Set ICEPick IDCODE in data register + irscan $jrc 0x04 -endstate RUN/IDLE +} diff --git a/openocd-win/openocd/scripts/target/ti_calypso.cfg b/openocd-win/openocd/scripts/target/ti_calypso.cfg new file mode 100644 index 0000000..9083336 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_calypso.cfg @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# TI Calypso (lite) G2 C035 Digital Base Band chip +# +# ARM7TDMIE + DSP subchip (S28C128) +# +# 512K SRAM Calypso +# 256K SRAM Calypso lite +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME calypso +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3100e02f +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +adapter speed 1000 + +reset_config trst_and_srst + +jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8 +jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# target + +set _TARGETNAME $_CHIPNAME.arm +target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME + +# workarea + +$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1 + +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable + +$_TARGETNAME configure -event examine-start { + irscan calypso.arm 0x0b -endstate DRPAUSE + drscan calypso.arm 2 2 -endstate RUN/IDLE +} diff --git a/openocd-win/openocd/scripts/target/ti_cc13x0.cfg b/openocd-win/openocd/scripts/target/ti_cc13x0.cfg new file mode 100644 index 0000000..f1c43a6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc13x0.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC13x0 - ARM Cortex-M3 +# +# http://www.ti.com +# + +set CHIPNAME cc13x0 +set JRC_TAPID 0x0B9BE02F +set WORKAREASIZE 0x4000 + +source [find target/ti_cc26x0.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_cc13x2.cfg b/openocd-win/openocd/scripts/target/ti_cc13x2.cfg new file mode 100644 index 0000000..c850816 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc13x2.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC13x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc13x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_cc26x0.cfg b/openocd-win/openocd/scripts/target/ti_cc26x0.cfg new file mode 100644 index 0000000..b9ccf31 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc26x0.cfg @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC26x0 - ARM Cortex-M3 +# +# http://www.ti.com +# + +source [find target/icepick.cfg] +source [find target/ti-cjtag.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc26x0 +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4BA00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# +# ICEpick-C (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0B99A02F +} +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version +jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG +jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME + +cortex_m reset_config vectreset diff --git a/openocd-win/openocd/scripts/target/ti_cc26x2.cfg b/openocd-win/openocd/scripts/target/ti_cc26x2.cfg new file mode 100644 index 0000000..62c91c3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc26x2.cfg @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC26x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc26x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_cc3220sf.cfg b/openocd-win/openocd/scripts/target/ti_cc3220sf.cfg new file mode 100644 index 0000000..cf43363 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc3220sf.cfg @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC3220SF - ARM Cortex-M4 +# +# http://www.ti.com/CC3220SF +# + +source [find target/swj-dp.tcl] +source [find target/icepick.cfg] +source [find target/ti_cc32xx.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME + +# +# On CC32xx family of devices, sysreqreset is disabled, and vectreset is +# blocked by the boot loader (stops in a while(1) statement). srst reset can +# leave the target in a state that prevents debug. The following uses the +# soft_reset_halt command to reset and halt the target. Then the PC and stack +# are initialized from internal flash. This allows for a more reliable reset, +# but with two caveats: it only works for the SF variant that has internal +# flash, and it only resets the CPU and not any peripherals. +# + +proc ocd_process_reset_inner { MODE } { + + soft_reset_halt + + # Initialize MSP, PSP, and PC from vector table at flash 0x01000800 + set boot [read_memory 0x01000800 32 2] + + reg msp [lindex $boot 0] + reg psp [lindex $boot 0] + reg pc [lindex $boot 1] + + if { 0 == [string compare $MODE run ] } { + resume + } + + cc32xx.cpu invoke-event reset-end +} diff --git a/openocd-win/openocd/scripts/target/ti_cc32xx.cfg b/openocd-win/openocd/scripts/target/ti_cc32xx.cfg new file mode 100644 index 0000000..9eb03eb --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_cc32xx.cfg @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments CC32xx - ARM Cortex-M4 +# +# http://www.ti.com/product/CC3200 +# http://www.ti.com/product/CC3220 +# + +source [find target/swj-dp.tcl] +source [find target/icepick.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc32xx +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + if {[using_jtag]} { + set _DAP_TAPID 0x4BA00477 + } else { + set _DAP_TAPID 0x2BA01477 + } +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable + jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" +} else { + swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +} + +# +# ICEpick-C (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0B97C02F +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version + jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +} + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/ti_dm355.cfg b/openocd-win/openocd/scripts/target/ti_dm355.cfg new file mode 100644 index 0000000..4292373 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_dm355.cfg @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments DaVinci family: TMS320DM355 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dm355 +} + +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + +source [find target/icepick.cfg] + +# +# Also note: when running without RTCK before the PLLs are set up, you +# may need to slow the JTAG clock down quite a lot (under 2 MHz). +# + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 +jtag configure $_CHIPNAME.etb -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 1" + +# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07926001 +} +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 +jtag configure $_CHIPNAME.arm -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# Primary TAP: ICEpick (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b73b02f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ + +# various symbol definitions, to avoid hard-wiring addresses +# and enable some sharing of DaVinci-family utility code +global dm355 +set dm355 [ dict create ] + +# Physical addresses for controllers and memory +# (Some of these are valid for many DaVinci family chips) +dict set dm355 sram0 0x00010000 +dict set dm355 sram1 0x00014000 +dict set dm355 sysbase 0x01c40000 +dict set dm355 pllc1 0x01c40800 +dict set dm355 pllc2 0x01c40c00 +dict set dm355 psc 0x01c41000 +dict set dm355 gpio 0x01c67000 +dict set dm355 a_emif 0x01e10000 +dict set dm355 a_emif_cs0 0x02000000 +dict set dm355 a_emif_cs1 0x04000000 +dict set dm355 ddr_emif 0x20000000 +dict set dm355 ddr 0x80000000 +dict set dm355 uart0 0x01c20000 +dict set dm355 uart1 0x01c20400 +dict set dm355 uart2 0x01e06000 + +source [find target/davinci.cfg] + +################ +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) +# and the ETB memory (4K) are other options, while trace is unused. +set _TARGETNAME $_CHIPNAME.arm + +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME + +# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, +# and that the work area is used only with a kernel mmu context ... +$_TARGETNAME configure \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ + -work-area-phys [dict get $dm355 sram1] \ + -work-area-size 0x4000 \ + -work-area-backup 0 + +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +adapter speed 1500 +$_TARGETNAME configure -event "reset-start" { adapter speed 1500 } + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/ti_dm365.cfg b/openocd-win/openocd/scripts/target/ti_dm365.cfg new file mode 100644 index 0000000..e19efd7 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_dm365.cfg @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments DaVinci family: TMS320DM365 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dm365 +} + +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + +source [find target/icepick.cfg] + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 +jtag configure $_CHIPNAME.etb -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 1" + +# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x0792602f +} +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 +jtag configure $_CHIPNAME.arm -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# Primary TAP: ICEpick (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b83e02f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ + +# various symbol definitions, to avoid hard-wiring addresses +# and enable some sharing of DaVinci-family utility code +global dm365 +set dm365 [ dict create ] + +# Physical addresses for controllers and memory +# (Some of these are valid for many DaVinci family chips) +dict set dm365 sram0 0x00010000 +dict set dm365 sram1 0x00014000 +dict set dm365 sysbase 0x01c40000 +dict set dm365 pllc1 0x01c40800 +dict set dm365 pllc2 0x01c40c00 +dict set dm365 psc 0x01c41000 +dict set dm365 gpio 0x01c67000 +dict set dm365 a_emif 0x01d10000 +dict set dm365 a_emif_cs0 0x02000000 +dict set dm365 a_emif_cs1 0x04000000 +dict set dm365 ddr_emif 0x20000000 +dict set dm365 ddr 0x80000000 + +source [find target/davinci.cfg] + +################ +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K) +# and the ETB memory (4K) are other options, while trace is unused. +set _TARGETNAME $_CHIPNAME.arm + +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME + +# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, +# and that the work area is used only with a kernel mmu context ... +$_TARGETNAME configure \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ + -work-area-phys [dict get $dm365 sram1] \ + -work-area-size 0x4000 \ + -work-area-backup 0 + +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +adapter speed 1500 +$_TARGETNAME configure -event "reset-start" { adapter speed 1500 } + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/ti_dm6446.cfg b/openocd-win/openocd/scripts/target/ti_dm6446.cfg new file mode 100644 index 0000000..8938234 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_dm6446.cfg @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments DaVinci family: TMS320DM6446 +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dm6446 +} + +# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled* +# after JTAG reset until ICEpick is used to route them in. +set EMU01 "-disable" + +# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without +# needing any ICEpick interaction. +#set EMU01 "-enable" + +source [find target/icepick.cfg] + +# Subsidiary TAP: unknown ... must enable via ICEpick +jtag newtap $_CHIPNAME unknown -irlen 8 -disable +jtag configure $_CHIPNAME.unknown -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 3" + +# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick +jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable +jtag configure $_CHIPNAME.dsp -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 2" + +# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer +if { [info exists ETB_TAPID] } { + set _ETB_TAPID $ETB_TAPID +} else { + set _ETB_TAPID 0x2b900f0f +} +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01 +jtag configure $_CHIPNAME.etb -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 1" + +# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM. +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07926001 +} +jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01 +jtag configure $_CHIPNAME.arm -event tap-enable \ + "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0b70002f +} +jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID + +jtag configure $_CHIPNAME.jrc -event setup \ + "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm" + +################ +# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K) +# and the ETB memory (4K) are other options, while trace is unused. +# Little-endian; use the OpenOCD default. +set _TARGETNAME $_CHIPNAME.arm + +target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000 + +# be absolutely certain the JTAG clock will work with the worst-case +# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns +# on the PLL and starts using it. OK to speed up after clock setup. +adapter speed 1500 +$_TARGETNAME configure -event "reset-start" { adapter speed 1500 } + +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable + +# trace setup +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb diff --git a/openocd-win/openocd/scripts/target/ti_k3.cfg b/openocd-win/openocd/scripts/target/ti_k3.cfg new file mode 100644 index 0000000..f0881cd --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_k3.cfg @@ -0,0 +1,370 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# +# Texas Instruments K3 devices: +# * AM654x: https://www.ti.com/lit/pdf/spruid7 +# Has 4 ARMV8 Cores and 2 R5 Cores and an M3 +# * J721E: https://www.ti.com/lit/pdf/spruil1 +# Has 2 ARMV8 Cores and 6 R5 Cores and an M3 +# * J7200: https://www.ti.com/lit/pdf/spruiu1 +# Has 2 ARMV8 Cores and 4 R5 Cores and an M3 +# * J721S2: https://www.ti.com/lit/pdf/spruj28 +# Has 2 ARMV8 Cores and 6 R5 Cores and an M4F +# * AM642: https://www.ti.com/lit/pdf/spruim2 +# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 +# * AM625: https://www.ti.com/lit/pdf/spruiv7a +# Has 4 ARMV8 Cores and 1 R5 Core and an M4F +# * AM62a7: https://www.ti.com/lit/pdf/spruj16a +# Has 4 ARMV8 Cores and 2 R5 Cores +# + +source [find target/swj-dp.tcl] + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc am654 +} + +# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug +if { [info exists V8_SMP_DEBUG] } { + set _v8_smp_debug $V8_SMP_DEBUG +} else { + set _v8_smp_debug 0 +} + +# Common Definitions + +# System Controller is the very first processor - all current SoCs have it. +set CM3_CTIBASE {0x3C016000} + +# sysctrl power-ap unlock offsets +set _sysctrl_ap_unlock_offsets {0xf0 0x44} + +# All the ARMV8s are the next processors. +# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1 +set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000} +set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000} + +# And we add up the R5s +# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1 +set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000} +set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000} +set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} + +# Finally an General Purpose(GP) MCU +set CM4_CTIBASE {0x20001000} + +# General Purpose MCU (M4) may be present on some very few SoCs +set _gp_mcu_cores 0 +# General Purpose MCU power-ap unlock offsets +set _gp_mcu_ap_unlock_offsets {0xf0 0x60} + +# Set configuration overrides for each SOC +switch $_soc { + am654 { + set _CHIPNAME am654 + set _K3_DAP_TAPID 0x0bb5a02f + + # AM654 has 2 clusters of 2 A53 cores each. + set _armv8_cpu_name a53 + set _armv8_cores 4 + + # AM654 has 1 cluster of 2 R5s cores. + set _r5_cores 2 + set R5_NAMES {mcu_r5.0 mcu_r5.1} + + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x50} + } + am642 { + set _CHIPNAME am642 + set _K3_DAP_TAPID 0x0bb3802f + + # AM642 has 1 clusters of 2 A53 cores each. + set _armv8_cpu_name a53 + set _armv8_cores 2 + set ARMV8_DBGBASE {0x90010000 0x90110000} + set ARMV8_CTIBASE {0x90020000 0x90120000} + + # AM642 has 2 cluster of 2 R5s cores. + set _r5_cores 4 + set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} + set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000} + set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000} + + # M4 processor + set _gp_mcu_cores 1 + } + am625 { + set _CHIPNAME am625 + set _K3_DAP_TAPID 0x0bb7e02f + + # AM625 has 1 clusters of 4 A53 cores. + set _armv8_cpu_name a53 + set _armv8_cores 4 + set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000} + set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000} + + # AM625 has 1 cluster of 1 R5s core. + set _r5_cores 1 + set R5_NAMES {main0_r5.0} + set R5_DBGBASE {0x9d410000} + set R5_CTIBASE {0x9d418000} + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + + # M4 processor + set _gp_mcu_cores 1 + set _gp_mcu_ap_unlock_offsets {0xf0 0x7c} + + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x740002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 10 + # Emulated AP description + set _dmem_emu_base_address 0x760000000 + set _dmem_emu_base_address_map_to 0x1d500000 + set _dmem_emu_ap_list 1 + } + am62a7 { + set _CHIPNAME am62a7 + set _K3_DAP_TAPID 0x0bb8d02f + + # AM62a7 has 1 clusters of 4 A53 cores. + set _armv8_cpu_name a53 + set _armv8_cores 4 + set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000} + set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000} + + # AM62a7 has 2 cluster of 1 R5s core. + set _r5_cores 2 + set R5_NAMES {main0_r5.0 mcu0_r5.0} + set R5_DBGBASE {0x9d410000 0x9d810000} + set R5_CTIBASE {0x9d418000 0x9d818000} + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + } + j721e { + set _CHIPNAME j721e + set _K3_DAP_TAPID 0x0bb6402f + # J721E has 1 cluster of 2 A72 cores. + set _armv8_cpu_name a72 + set _armv8_cores 2 + + # J721E has 3 clusters of 2 R5 cores each. + set _r5_cores 6 + + # Setup DMEM access descriptions + # DAPBUS (Debugger) description + set _dmem_base_address 0x4c40002000 + set _dmem_ap_address_offset 0x100 + set _dmem_max_aps 8 + # Emulated AP description + set _dmem_emu_base_address 0x4c60000000 + set _dmem_emu_base_address_map_to 0x1d600000 + set _dmem_emu_ap_list 1 + } + j7200 { + set _CHIPNAME j7200 + set _K3_DAP_TAPID 0x0bb6d02f + + # J7200 has 1 cluster of 2 A72 cores. + set _armv8_cpu_name a72 + set _armv8_cores 2 + + # J7200 has 2 clusters of 2 R5 cores each. + set _r5_cores 4 + set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000} + set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000} + + # M3 CTI base + set CM3_CTIBASE {0x20001000} + } + j721s2 { + set _CHIPNAME j721s2 + set _K3_DAP_TAPID 0x0bb7502f + + # J721s2 has 1 cluster of 2 A72 cores. + set _armv8_cpu_name a72 + set _armv8_cores 2 + + # J721s2 has 3 clusters of 2 R5 cores each. + set _r5_cores 6 + + # sysctrl CTI base + set CM3_CTIBASE {0x20001000} + # Sysctrl power-ap unlock offsets + set _sysctrl_ap_unlock_offsets {0xf0 0x78} + + # M4 processor + set _gp_mcu_cores 1 + set _gp_mcu_ap_unlock_offsets {0xf0 0x7c} + } + default { + echo "'$_soc' is invalid!" + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu + +set _CTINAME $_CHIPNAME.cti + +# sysctrl is always present +cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] +target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine +$_TARGETNAME.sysctrl configure -event reset-assert { } + +proc sysctrl_up {} { + # To access sysctrl, we need to enable the JTAG access for the same. + # Ensure Power-AP unlocked + $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000 + $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098 + + $::_TARGETNAME.sysctrl arp_examine +} + +$_TARGETNAME.sysctrl configure -event gdb-attach { + sysctrl_up + # gdb-attach default rule + halt 1000 +} + +proc _cpu_no_smp_up {} { + set _current_target [target current] + set _current_type [$_current_target cget -type] + + $_current_target arp_examine + $_current_target $_current_type dbginit +} + +proc _armv8_smp_up {} { + for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } { + $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine + $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit + $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on + } + # Set Default target as core 0 + targets $::_TARGETNAME.$::_armv8_cpu_name.0 +} + +set _v8_smp_targets "" + +for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { + + cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $ARMV8_CTIBASE $_core] + + target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine + + set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core" + + if { $_v8_smp_debug == 0 } { + $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach { + _cpu_no_smp_up + # gdb-attach default rule + halt 1000 + } + } else { + $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach { + _armv8_smp_up + # gdb-attach default rule + halt 1000 + } + } +} + +# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs +set _armv8_up_cmd "$_armv8_cpu_name"_up +# Available if V8_SMP_DEBUG is set to non-zero value +set _armv8_smp_cmd "$_armv8_cpu_name"_smp + +if { $_v8_smp_debug == 0 } { + proc $_armv8_up_cmd { args } { + foreach _core $args { + targets $_core + _cpu_no_smp_up + } + } +} else { + proc $_armv8_smp_cmd { args } { + _armv8_smp_up + } + # Declare SMP + target smp $:::_v8_smp_targets +} + +for { set _core 0 } { $_core < $_r5_cores } { incr _core } { + set _r5_name [lindex $R5_NAMES $_core] + cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $R5_CTIBASE $_core] + + # inactive core examination will fail - wait till startup of additional core + target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine + + $_TARGETNAME.$_r5_name configure -event gdb-attach { + _cpu_no_smp_up + # gdb-attach default rule + halt 1000 + } +} + +proc r5_up { args } { + foreach _core $args { + targets $_core + _cpu_no_smp_up + } +} + +if { $_gp_mcu_cores != 0 } { + cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] + target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + $_TARGETNAME.gp_mcu configure -event reset-assert { } + + proc gp_mcu_up {} { + # To access GP MCU, we need to enable the JTAG access for the same. + # Ensure Power-AP unlocked + $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000 + $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098 + + $::_TARGETNAME.gp_mcu arp_examine + } + + $_TARGETNAME.gp_mcu configure -event gdb-attach { + gp_mcu_up + # gdb-attach default rule + halt 1000 + } +} + +# In case of DMEM access, configure the dmem adapter with offsets from above. +if { 0 == [string compare [adapter name] dmem ] } { + if { [info exists _dmem_base_address] } { + # DAPBUS (Debugger) description + dmem base_address $_dmem_base_address + dmem ap_address_offset $_dmem_ap_address_offset + dmem max_aps $_dmem_max_aps + + # The following are the details of APs to be emulated for direct address access. + # Debug Config (Debugger) description + dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to + dmem emu_ap_list $_dmem_emu_ap_list + # We are going local bus, so speed is really dummy here. + adapter speed 2500 + } else { + puts "ERROR: ${SOC} data is missing to support dmem access!" + } +} diff --git a/openocd-win/openocd/scripts/target/ti_msp432.cfg b/openocd-win/openocd/scripts/target/ti_msp432.cfg new file mode 100644 index 0000000..8a90b98 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_msp432.cfg @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz +# +# http://www.ti.com/MSP432 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME msp432 +} + +if { [info exists CPUTAPID] } { + set _DAP_TAPID $CPUTAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists DAP_SWD_ID] } { + set _DAP_SWD_ID $DAP_SWD_ID +} else { + set _DAP_SWD_ID 0x2ba01477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _DAP_ID $_DAP_TAPID +} else { + set _DAP_ID $_DAP_SWD_ID +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME + +cortex_m reset_config sysresetreq diff --git a/openocd-win/openocd/scripts/target/ti_rm4x.cfg b/openocd-win/openocd/scripts/target/ti_rm4x.cfg new file mode 100644 index 0000000..715aa5b --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_rm4x.cfg @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find target/ti_tms570.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_tms570.cfg b/openocd-win/openocd/scripts/target/ti_tms570.cfg new file mode 100644 index 0000000..18e0d82 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_tms570.cfg @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter speed 1500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME tms570 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN big +} + +# TMS570 has an ICEpick-C on which we need the router commands. +source [find target/icepick.cfg] + +# Main DAP +# DAP_TAPID should be set before source-ing this file +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version +jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" + +# ICEpick-C (JTAG route controller) +# JRC_TAPID should be set before source-ing this file +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} + +set _JRC_TAPID2 0x0B7B302F +set _JRC_TAPID3 0x0B95502F +set _JRC_TAPID4 0x0B97102F +set _JRC_TAPID5 0x0D8A002F +set _JRC_TAPID6 0x0B8A002F + + +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \ + -expected-id $_JRC_TAPID \ + -expected-id $_JRC_TAPID2 \ + -expected-id $_JRC_TAPID3 \ + -expected-id $_JRC_TAPID4 \ + -expected-id $_JRC_TAPID5 \ + -expected-id $_JRC_TAPID6 \ + -ignore-version +jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100" + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Cortex-R4 target +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \ + -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000 + +# TMS570 uses quirky BE-32 mode +$_CHIPNAME.dap ti_be_32_quirks 1 + +$_TARGETNAME configure -event "reset-assert" { + global _CHIPNAME + + # assert warm system reset through ICEPick + icepick_c_wreset $_CHIPNAME.jrc +} diff --git a/openocd-win/openocd/scripts/target/ti_tms570lc43xx.cfg b/openocd-win/openocd/scripts/target/ti_tms570lc43xx.cfg new file mode 100644 index 0000000..ffda989 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_tms570lc43xx.cfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +set DAP_TAPID 0x0B95A02F +set JRC_TAPID 0x0B95A02F + +source [find target/ti_tms570.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_tms570ls20xxx.cfg b/openocd-win/openocd/scripts/target/ti_tms570ls20xxx.cfg new file mode 100644 index 0000000..cc2bbd6 --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_tms570ls20xxx.cfg @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TMS570LS20216, TMS570LS20206, TMS570LS10216 +# TMS570LS10206, TMS570LS10116, TMS570LS10106 +set DAP_TAPID 0x0B7B302F +set JRC_TAPID 0x0B7B302F + +source [find target/ti_tms570.cfg] diff --git a/openocd-win/openocd/scripts/target/ti_tms570ls3137.cfg b/openocd-win/openocd/scripts/target/ti_tms570ls3137.cfg new file mode 100644 index 0000000..ebe2cfc --- /dev/null +++ b/openocd-win/openocd/scripts/target/ti_tms570ls3137.cfg @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# TMS570LS3137 +set DAP_TAPID 0x0B8A002F +set JRC_TAPID 0x0B8A002F + +source [find target/ti_tms570.cfg] diff --git a/openocd-win/openocd/scripts/target/tmpa900.cfg b/openocd-win/openocd/scripts/target/tmpa900.cfg new file mode 100644 index 0000000..b7ec689 --- /dev/null +++ b/openocd-win/openocd/scripts/target/tmpa900.cfg @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Toshiba TMPA900 +###################################### + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME tmpa900 +} + +# Toshiba TMPA900 series MCUs are always little endian as per datasheet. +set _ENDIAN little + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926031 +} + +#TMPA900 has following IDs: +# CP15.0 register 0x41069265 +# CP15.1 register 0x1d152152 +# ARM core 0x07926031 + + +# +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst +adapter srst delay 20 +jtag_ntrst_delay 20 + +###################### +# Target configuration +###################### + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +# Internal RAM-0 (16kB): 0xf8004000 +# Internal RAM-1 (8kB): 0xf8008000 + +# Use internal RAM-0 and RAM-1 as working area (24kB total). +$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \ +-work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/tmpa910.cfg b/openocd-win/openocd/scripts/target/tmpa910.cfg new file mode 100644 index 0000000..276d1ad --- /dev/null +++ b/openocd-win/openocd/scripts/target/tmpa910.cfg @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +###################################### +# Target: Toshiba TMPA910 +###################################### + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME tmpa910 +} + +# Toshiba TMPA910 series MCUs are always little endian as per datasheet. +set _ENDIAN little + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926031 +} + +#TMPA910 has following IDs: +# CP15.0 register 0x41069265 +# CP15.1 register 0x1d152152 +# ARM core 0x07926031 + + +# +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst +adapter srst delay 20 +jtag_ntrst_delay 20 + +###################### +# Target configuration +###################### + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME + +# Internal RAM-0 (16kB): 0xf8004000 +# Internal RAM-1 (16kB): 0xf8008000 +# Internal RAM-2 (16kB): 0xf800c000 + +# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total). +$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \ +-work-area-backup 0 diff --git a/openocd-win/openocd/scripts/target/tnetc4401.cfg b/openocd-win/openocd/scripts/target/tnetc4401.cfg new file mode 100644 index 0000000..6a24980 --- /dev/null +++ b/openocd-win/openocd/scripts/target/tnetc4401.cfg @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based) +# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems. +# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf +transport select jtag +set _TARGETNAME tnetc4401 +set _CPUTAPID 0x0000100f +jtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID +target create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big + +# May need to halt manually before calling reset init +$_TARGETNAME configure -event reset-init { + halt + echo "Attempting to disable watchdog..." + mwb phys 0xa8610b00 0 256 + halt + wait_halt +} diff --git a/openocd-win/openocd/scripts/target/u8500.cfg b/openocd-win/openocd/scripts/target/u8500.cfg new file mode 100644 index 0000000..417fdd1 --- /dev/null +++ b/openocd-win/openocd/scripts/target/u8500.cfg @@ -0,0 +1,326 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Copyright (C) ST-Ericsson SA 2011 +# Author : michel.jaouen@stericsson.com +# U8500 target + +proc mmu_off {} { + set cp [arm mrc 15 0 1 0 0] + set cp [expr {$cp & ~1}] + arm mcr 15 0 1 0 0 $cp +} + +proc mmu_on {} { + set cp [arm mrc 15 0 1 0 0] + set cp [expr {$cp | 1}] + arm mcr 15 0 1 0 0 $cp +} + +proc ocd_gdb_restart {target_id} { + global _TARGETNAME_1 + global _SMP + targets $_TARGETNAME_1 + if { $_SMP == 1 } { + cortex_a smp off + } + rst_run + halt + if { $_SMP == 1 } { + cortex_a smp on + } +} + +proc smp_reg {} { + global _TARGETNAME_1 + global _TARGETNAME_2 + targets $_TARGETNAME_1 + echo "$_TARGETNAME_1" + set pc1 [reg pc] + set stck1 [reg sp_svc] + targets $_TARGETNAME_2 + echo "$_TARGETNAME_1" + set pc2 [reg pc] + set stck2 [reg sp_svc] +} + + +proc u8500_tapenable {chip val} { + echo "JTAG tap enable $chip" +} + + +proc pwrsts { } { + global _CHIPNAME + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 0 + set pwrsts [drscan $_CHIPNAME.jrc 16 0] + echo "pwrsts ="$pwrsts + set a9 [expr "0x$pwrsts & 0xc"] + set ape [expr "0x$pwrsts & 0x3"] + if {[string equal "0" $ape]} { + echo "ape off" + } else { + echo "ape on" + } + echo "$a9" + switch $a9 { + 4 { + echo "A9 in retention" + } + 8 { + echo "A9 100% DVFS" + } + c { + echo "A9 50% DVFS" + } + } +} + +proc poll_pwrsts { } { + global _CHIPNAME + set result 1 + set i 0 + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 0 + set pwrsts [drscan $_CHIPNAME.jrc 16 0] + set pwrsts [expr "0x$pwrsts & 0xc"] + while {[string equal "4" $pwrsts] && $i<20} { + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 0; + set pwrsts [drscan $_CHIPNAME.jrc 16 0] + set pwrsts [expr "0x$pwrsts & 0xc"] + if {![string equal "4" $pwrsts]} { + set result 1 + } else { + set result 0 + sleep 200 + echo "loop $i" + } + incr i + } + return $result +} + +proc halt_ { } { + if {[poll_pwrsts]==1} { + halt + } else { + echo "halt failed : target in retention" + } +} + + +proc u8500_dapenable {chip} { +} + +proc u8500_tapdisable {chip val} { + echo "JTAG tap disable $chip" +} + + +proc enable_apetap {} { + global _CHIPNAME + global _TARGETNAME_2 + global _TARGETNAME_1 + poll off + irscan $_CHIPNAME.jrc 0x3e + drscan $_CHIPNAME.jrc 8 0xcf + jtag tapenable $_CHIPNAME.dap + irscan $_CHIPNAME.jrc 0x6 + drscan $_CHIPNAME.jrc 32 0 + irscan $_CHIPNAME.jrc 0x6 + drscan $_CHIPNAME.jrc 32 0 + set status [$_TARGETNAME_1 curstate] + if {[string equal "unknown" $status]} { + $_TARGETNAME_1 arp_examine + cache_config l2x 0xa0412000 8 + } + + set status [$_TARGETNAME_2 curstate] + if {[string equal "unknown" $status]} { + $_TARGETNAME_2 arp_examine + } + } + +tcl_port 5555 +telnet_port 4444 +gdb_port 3333 + +if { [info exists CHIPNAME] } { +global _CHIPNAME + set _CHIPNAME $CHIPNAME +} else { +global _CHIPNAME + set _CHIPNAME u8500 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + + + +# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT, +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable \ + "u8500_dapenable $_CHIPNAME.cpu" +jtag configure $_CHIPNAME.cpu -event tap-disable \ + "u8500_tapdisable $_CHIPNAME.cpu 0xc0" + + +#CLTAPC TAP JRC equivalent +if { [info exists CLTAPC_ID] } { + set _CLTAPC_ID $CLTAPC_ID +} else { + set _CLTAPC_ID 0x22286041 +} +jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version + + +if { ![info exists TARGETNAME_1] } { +global _TARGETNAME_1 +set _TARGETNAME_1 $_CHIPNAME.cpu1 +} else { +global _TARGETNAME_1 +set _TARGETNAME_1 $TARGETNAME_1 +} + +if { [info exists DAP_DBG1] } { + set _DAP_DBG1 $DAP_DBG1 +} else { + set _DAP_DBG1 0x801A8000 +} +if { [info exists DAP_DBG2] } { + set _DAP_DBG2 $DAP_DBG2 +} else { + set _DAP_DBG2 0x801AA000 +} + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux + + +if { ![info exists TARGETNAME_2] } { +global _TARGETNAME_2 +set _TARGETNAME_2 $_CHIPNAME.cpu2 +} else { +global _TARGETNAME_2 +set _TARGETNAME_2 $TARGETNAME_2 +} + +target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux + + +if {![info exists SMP]} { +global _SMP +set _SMP 1 +} else { +global _SMP +set _SMP $SMP +} +global SMP +if { $_SMP == 1} { +target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1 +} + + + + +proc secsts1 { } { + global _CHIPNAME + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 4 + set secsts1 [drscan $_CHIPNAME.jrc 16 0] + echo "secsts1 ="$secsts1 + set secsts1 [expr "0x$secsts1 & 0x4"] + if {![string equal "4" $secsts1]} { + echo "APE target secured" + } else { + echo "APE target not secured" + } +} + +proc att { } { + global _CHIPNAME + jtag arp_init + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 4 + set secsts1 [drscan $_CHIPNAME.jrc 16 0] + echo "secsts1 ="$secsts1 + set secsts1 [expr "0x$secsts1 & 0x4"] + if {[string equal "4" $secsts1]} { + if {[poll_pwrsts]==1} { + enable_apetap + } else { + echo "target in retention" + } + } else { + echo "target secured" + } + +} + + + +proc rst_run { } { + global _CHIPNAME + global _TARGETNAME_2 + global _TARGETNAME_1 + set status [$_TARGETNAME_1 curstate] + if {[string equal "halted" $status]} { + resume + targets $_TARGETNAME_1 + } + set status [$_TARGETNAME_2 curstate] + if {[string equal "halted" $status]} { + resume + targets $_TARGETNAME_2 + } + poll off + jtag arp_init + reset + sleep 20 + irscan $_CHIPNAME.jrc 0x3a + drscan $_CHIPNAME.jrc 4 4 + set secsts1 [drscan $_CHIPNAME.jrc 16 0] + echo "secsts1 ="$secsts1 + set secsts1 [expr "0x$secsts1 & 0x4"] + while {![string equal "4" $secsts1]} { + irscan u8500.jrc 0x3a + drscan u8500.jrc 4 4 + set secsts1 [drscan $_CHIPNAME.jrc 16 0] + echo "secsts1 ="$secsts1 + set secsts1 [expr "0x$secsts1 & 0x4"] + } + echo "ape debugable" + enable_apetap + poll on + targets $_TARGETNAME_1 + dap apsel 1 +} + +if {![info exists MAXSPEED]} { +global _MAXSPEED +set _MAXSPEED 15000 +} else { +global _MAXSPEED +set _MAXSPEED $MAXSPEED +} +global _MAXSPEED +adapter speed $_MAXSPEED + + +gdb_breakpoint_override hard +set mem inaccessible-by-default-off + +jtag_ntrst_delay 100 +reset_config trst_and_srst combined diff --git a/openocd-win/openocd/scripts/target/vd_aarch64.cfg b/openocd-win/openocd/scripts/target/vd_aarch64.cfg new file mode 100644 index 0000000..619134a --- /dev/null +++ b/openocd-win/openocd/scripts/target/vd_aarch64.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# Arm v8 64b Cortex A + +if {![info exists _CORES]} { + set _CORES 1 +} +if {![info exists _CHIPNAME]} { + set _CHIPNAME aarch64 +} +set _TARGETNAME $_CHIPNAME.cpu +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80810000 0x80910000} +set CTIBASE {0x80820000 0x80920000} + +dap create $_CHIPNAME.dap -chain-position $_TARGETNAME +$_CHIPNAME.dap apsel 1 + +for { set _core 0 } { $_core < $_CORES } { incr _core } \ +{ + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core] + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + set _smp_command "target smp $_TARGETNAME.$_core" + } + eval $_command +} +eval $_smp_command + +# default target is core 0 +targets $_TARGETNAME.0 diff --git a/openocd-win/openocd/scripts/target/vd_cortex_m.cfg b/openocd-win/openocd/scripts/target/vd_cortex_m.cfg new file mode 100644 index 0000000..4d7b0df --- /dev/null +++ b/openocd-win/openocd/scripts/target/vd_cortex_m.cfg @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# ARM Cortex M + +if {![info exists _CHIPNAME]} { + set _CHIPNAME cortex_m +} +set _TARGETNAME $_CHIPNAME.cpu + +dap create $_CHIPNAME.dap -chain-position $_TARGETNAME + +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap diff --git a/openocd-win/openocd/scripts/target/vd_riscv.cfg b/openocd-win/openocd/scripts/target/vd_riscv.cfg new file mode 100644 index 0000000..f08cb1a --- /dev/null +++ b/openocd-win/openocd/scripts/target/vd_riscv.cfg @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# RISCV core + +if {![info exists _HARTID]} { + set _HARTID 0x00 +} +if {![info exists _CHIPNAME]} { + set _CHIPNAME riscv +} +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 +riscv set_mem_access sysbus progbuf diff --git a/openocd-win/openocd/scripts/target/vybrid_vf6xx.cfg b/openocd-win/openocd/scripts/target/vybrid_vf6xx.cfg new file mode 100644 index 0000000..776c16b --- /dev/null +++ b/openocd-win/openocd/scripts/target/vybrid_vf6xx.cfg @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Freescale Vybrid VF610 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME vf610 +} + +if { [info exists A5_JTAG_TAPID] } { + set _A5_JTAG_TAPID $A5_JTAG_TAPID +} else { + set _A5_JTAG_TAPID 0x4BA00477 +} + +if { [info exists A5_SWD_TAPID] } { + set _A5_SWD_TAPID $A5_SWD_TAPID +} else { + set _A5_SWD_TAPID 0x3BA02477 +} + +if { [using_jtag] } { + set _A5_TAPID $_A5_JTAG_TAPID +} else { + set _A5_TAPID $_A5_SWD_TAPID +} + +source [find target/swj-dp.tcl] + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000 +target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/xilinx_zynqmp.cfg b/openocd-win/openocd/scripts/target/xilinx_zynqmp.cfg new file mode 100644 index 0000000..9734a18 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xilinx_zynqmp.cfg @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# target configuration for +# Xilinx ZynqMP (UltraScale+ / A53) +# +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME uscale +} + +# +# DAP tap (Quard core A53) +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap + +# +# PS tap (UltraScale+) +# +if { [info exists PS_TAPID] } { + set _PS_TAPID $PS_TAPID + jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID +} else { + # FPGA Programmable logic. Values take from Table 39-1 in UG1085: + jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \ + -expected-id 0x04711093 \ + -expected-id 0x04710093 \ + -expected-id 0x04721093 \ + -expected-id 0x04720093 \ + -expected-id 0x04739093 \ + -expected-id 0x04730093 \ + -expected-id 0x04738093 \ + -expected-id 0x04740093 \ + -expected-id 0x04750093 \ + -expected-id 0x04759093 \ + -expected-id 0x04758093 +} + +set jtag_configured 0 + +jtag configure $_CHIPNAME.ps -event setup { + global _CHIPNAME + global jtag_configured + + if { $jtag_configured == 0 } { + # add the DAP tap to the chain + # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924 + irscan $_CHIPNAME.ps 0x824 + drscan $_CHIPNAME.ps 32 0x00000003 + runtest 100 + + # setup event will be re-entered through jtag arp_init + # break the recursion + set jtag_configured 1 + # re-initialized the jtag chain + jtag arp_init + } +} + +set _TARGETNAME $_CHIPNAME.a53 +set _CTINAME $_CHIPNAME.cti +set _smp_command "" + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set _cores 4 + +for { set _core 0 } { $_core < $_cores } { incr _core } { + + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \ + -baseaddr [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + set _command "$_command -rtos hwthread" + set _smp_command "target smp $_TARGETNAME.$_core" + } + + eval $_command +} + +target create uscale.axi mem_ap -dap uscale.dap -ap-num 0 + +eval $_smp_command +targets $_TARGETNAME.0 + +proc core_up { args } { + global _TARGETNAME + foreach core $args { + $_TARGETNAME.$core arp_examine + } +} diff --git a/openocd-win/openocd/scripts/target/xmc1xxx.cfg b/openocd-win/openocd/scripts/target/xmc1xxx.cfg new file mode 100644 index 0000000..cafd032 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xmc1xxx.cfg @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz) +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xmc1000 +} + +# +# Only SWD and SPD supported +# +source [find target/swj-dp.tcl] + +if { [info exists CPUTAPID] } { + set _CPU_SWD_TAPID $CPUTAPID +} else { + set _CPU_SWD_TAPID 0x0BB11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 \ + -work-area-size $_WORKAREASIZE \ + -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME + +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/xmc4xxx.cfg b/openocd-win/openocd/scripts/target/xmc4xxx.cfg new file mode 100644 index 0000000..0e28494 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xmc4xxx.cfg @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz) +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xmc4000 +} + +source [find target/swj-dp.tcl] + +# +# SWJ-DP +# +if { [info exists CPU_JTAG_TAPID] } { + set _CPU_JTAG_TAPID $CPU_JTAG_TAPID +} else { + set _CPU_JTAG_TAPID 0x4BA00477 +} + +# +# SW_DP +# +if { [info exists CPU_SWD_TAPID] } { + set _CPU_SWD_TAPID $CPU_SWD_TAPID +} else { + set _CPU_SWD_TAPID 0x2BA01477 +} + +if { [using_jtag] } { + set _CPU_TAPID $_CPU_JTAG_TAPID +} else { + set _CPU_TAPID $_CPU_SWD_TAPID +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +# Work-area is a space in RAM used for flash programming +# By default use 16 kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME + +if { ![using_hla] } { + cortex_m reset_config sysresetreq +} + +adapter speed 1000 diff --git a/openocd-win/openocd/scripts/target/xmos_xs1-xau8a-10_arm.cfg b/openocd-win/openocd/scripts/target/xmos_xs1-xau8a-10_arm.cfg new file mode 100644 index 0000000..60fe9ad --- /dev/null +++ b/openocd-win/openocd/scripts/target/xmos_xs1-xau8a-10_arm.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz +# +# http://www.xmos.com/products/silicon/xcore-xa/xa-series +# + +if { ![info exists CHIPNAME] } { + set CHIPNAME xcorexa +} + +if { ![info exists WORKAREASIZE] } { + # XS1-XAU8A-10-FB265: 128 KB SRAM + set WORKAREASIZE 0x20000 +} + +source [find target/efm32.cfg] diff --git a/openocd-win/openocd/scripts/target/xtensa-core-esp32.cfg b/openocd-win/openocd/scripts/target/xtensa-core-esp32.cfg new file mode 100644 index 0000000..9a70072 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa-core-esp32.cfg @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x400D0000 0x330000 +xtensa xtmem irom 0x40000000 0x64F00 +xtensa xtmem iram 0x40070000 0x30000 +xtensa xtmem iram 0x400C0000 0x2000 +xtensa xtmem drom 0x3F400000 0x800000 +xtensa xtmem drom 0x3FF90000 0x10000 +xtensa xtmem dram 0x3FFAE000 0x52000 +xtensa xtmem dram 0x3FF80000 0x2000 +xtensa xtmem dram 0x3F800000 0x400000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3FF00000 0x71000 +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 1 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 173 +xtensa xtregfmt contiguous 105 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg expstate 0x03e6 +xtensa xtreg f64r_lo 0x03ea +xtensa xtreg f64r_hi 0x03eb +xtensa xtreg f64s 0x03ec +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/openocd-win/openocd/scripts/target/xtensa-core-esp32s2.cfg b/openocd-win/openocd/scripts/target/xtensa-core-esp32s2.cfg new file mode 100644 index 0000000..b38cb1d --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa-core-esp32s2.cfg @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S2 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x40080000 0x780000 +xtensa xtmem irom 0x40000000 0x20000 +xtensa xtmem iram 0x40020000 0x50000 +xtensa xtmem iram 0x40070000 0x2000 +xtensa xtmem drom 0x3F000000 0x400000 +xtensa xtmem drom 0x3F4D3FFC 0xAAC004 +xtensa xtmem drom 0x3FFA0000 0x10000 +xtensa xtmem dram 0x3FFB0000 0x50000 +xtensa xtmem dram 0x3FF9E000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3F500000 0xA80000 +xtensa xtmem dram 0x3F400000 0xD3FFC +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 0 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 171 +xtensa xtregfmt contiguous 73 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg gpio_out 0x0300 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg pwrctl 0x2014 +xtensa xtreg pwrstat 0x2015 +xtensa xtreg eristat 0x2016 +xtensa xtreg cs_itctrl 0x2017 +xtensa xtreg cs_claimset 0x2018 +xtensa xtreg cs_claimclr 0x2019 +xtensa xtreg cs_lockaccess 0x201a +xtensa xtreg cs_lockstatus 0x201b +xtensa xtreg cs_authstatus 0x201c +xtensa xtreg fault_info 0x202b +xtensa xtreg trax_id 0x202c +xtensa xtreg trax_control 0x202d +xtensa xtreg trax_status 0x202e +xtensa xtreg trax_data 0x202f +xtensa xtreg trax_address 0x2030 +xtensa xtreg trax_pctrigger 0x2031 +xtensa xtreg trax_pcmatch 0x2032 +xtensa xtreg trax_delay 0x2033 +xtensa xtreg trax_memstart 0x2034 +xtensa xtreg trax_memend 0x2035 +xtensa xtreg pmg 0x2043 +xtensa xtreg pmpc 0x2044 +xtensa xtreg pm0 0x2045 +xtensa xtreg pm1 0x2046 +xtensa xtreg pmctrl0 0x2047 +xtensa xtreg pmctrl1 0x2048 +xtensa xtreg pmstat0 0x2049 +xtensa xtreg pmstat1 0x204a +xtensa xtreg ocdid 0x204b +xtensa xtreg ocd_dcrclr 0x204c +xtensa xtreg ocd_dcrset 0x204d +xtensa xtreg ocd_dsr 0x204e +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/openocd-win/openocd/scripts/target/xtensa-core-esp32s3.cfg b/openocd-win/openocd/scripts/target/xtensa-core-esp32s3.cfg new file mode 100644 index 0000000..b3f20e3 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa-core-esp32s3.cfg @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S3 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options + +# Memory Options +xtensa xtmem irom 0x42000000 0x2000000 +xtensa xtmem irom 0x40000000 0x60000 +xtensa xtmem iram 0x40370000 0x70000 +xtensa xtmem iram 0x600FE000 0x2000 +xtensa xtmem drom 0x3C000000 0x1000000 +xtensa xtmem drom 0x3FF00000 0x20000 +xtensa xtmem dram 0x3FC88000 0x78000 +xtensa xtmem dram 0x600FE000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x60000000 0x10000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 0x4000 +xtensa xtopt tracememrev 0 +xtensa xtopt perfcount 2 + + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 228 +xtensa xtregfmt contiguous 128 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg gpio_out 0x030c +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 +xtensa xtreg accx_0 0x0300 +xtensa xtreg accx_1 0x0301 +xtensa xtreg qacc_h_0 0x0302 +xtensa xtreg qacc_h_1 0x0303 +xtensa xtreg qacc_h_2 0x0304 +xtensa xtreg qacc_h_3 0x0305 +xtensa xtreg qacc_h_4 0x0306 +xtensa xtreg qacc_l_0 0x0307 +xtensa xtreg qacc_l_1 0x0308 +xtensa xtreg qacc_l_2 0x0309 +xtensa xtreg qacc_l_3 0x030a +xtensa xtreg qacc_l_4 0x030b +xtensa xtreg sar_byte 0x030d +xtensa xtreg fft_bit_width 0x030e +xtensa xtreg ua_state_0 0x030f +xtensa xtreg ua_state_1 0x0310 +xtensa xtreg ua_state_2 0x0311 +xtensa xtreg ua_state_3 0x0312 +xtensa xtreg q0 0x1008 +xtensa xtreg q1 0x1009 +xtensa xtreg q2 0x100a +xtensa xtreg q3 0x100b +xtensa xtreg q4 0x100c +xtensa xtreg q5 0x100d +xtensa xtreg q6 0x100e +xtensa xtreg q7 0x100f +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg pwrctl 0x2028 +xtensa xtreg pwrstat 0x2029 +xtensa xtreg eristat 0x202a +xtensa xtreg cs_itctrl 0x202b +xtensa xtreg cs_claimset 0x202c +xtensa xtreg cs_claimclr 0x202d +xtensa xtreg cs_lockaccess 0x202e +xtensa xtreg cs_lockstatus 0x202f +xtensa xtreg cs_authstatus 0x2030 +xtensa xtreg fault_info 0x203f +xtensa xtreg trax_id 0x2040 +xtensa xtreg trax_control 0x2041 +xtensa xtreg trax_status 0x2042 +xtensa xtreg trax_data 0x2043 +xtensa xtreg trax_address 0x2044 +xtensa xtreg trax_pctrigger 0x2045 +xtensa xtreg trax_pcmatch 0x2046 +xtensa xtreg trax_delay 0x2047 +xtensa xtreg trax_memstart 0x2048 +xtensa xtreg trax_memend 0x2049 +xtensa xtreg pmg 0x2057 +xtensa xtreg pmpc 0x2058 +xtensa xtreg pm0 0x2059 +xtensa xtreg pm1 0x205a +xtensa xtreg pmctrl0 0x205b +xtensa xtreg pmctrl1 0x205c +xtensa xtreg pmstat0 0x205d +xtensa xtreg pmstat1 0x205e +xtensa xtreg ocdid 0x205f +xtensa xtreg ocd_dcrclr 0x2060 +xtensa xtreg ocd_dcrset 0x2061 +xtensa xtreg ocd_dsr 0x2062 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f diff --git a/openocd-win/openocd/scripts/target/xtensa-core-nxp_rt600.cfg b/openocd-win/openocd/scripts/target/xtensa-core-nxp_rt600.cfg new file mode 100644 index 0000000..abd961e --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa-core-nxp_rt600.cfg @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target + + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 32 +xtensa xtopt windowed 1 + + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 4 +xtensa xtopt excmlevel 2 + + +# Cache Options +xtensa xtmem icache 256 32768 4 +xtensa xtmem dcache 256 65536 4 1 + + +# Memory Options +xtensa xtmem iram 0x24020000 65536 +xtensa xtmem dram 0x24000000 65536 +xtensa xtmem sram 0x00000000 603979776 + + +# Memory Protection/Translation Options + + +# Debug Options +xtensa xtopt debuglevel 4 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 + + +# Core Registers +xtensa xtregs 208 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg prefctl 0x0228 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg expstate 0x03e6 +xtensa xtreg f64r_lo 0x03ea +xtensa xtreg f64r_hi 0x03eb +xtensa xtreg f64s 0x03ec +xtensa xtreg ae_ovf_sar 0x03f0 +xtensa xtreg ae_bithead 0x03f1 +xtensa xtreg ae_ts_fts_bu_bp 0x03f2 +xtensa xtreg ae_cw_sd_no 0x03f3 +xtensa xtreg ae_cbegin0 0x03f6 +xtensa xtreg ae_cend0 0x03f7 +xtensa xtreg ae_cbegin1 0x03f8 +xtensa xtreg ae_cend1 0x03f9 +xtensa xtreg aed0 0x1010 +xtensa xtreg aed1 0x1011 +xtensa xtreg aed2 0x1012 +xtensa xtreg aed3 0x1013 +xtensa xtreg aed4 0x1014 +xtensa xtreg aed5 0x1015 +xtensa xtreg aed6 0x1016 +xtensa xtreg aed7 0x1017 +xtensa xtreg aed8 0x1018 +xtensa xtreg aed9 0x1019 +xtensa xtreg aed10 0x101a +xtensa xtreg aed11 0x101b +xtensa xtreg aed12 0x101c +xtensa xtreg aed13 0x101d +xtensa xtreg aed14 0x101e +xtensa xtreg aed15 0x101f +xtensa xtreg u0 0x1020 +xtensa xtreg u1 0x1021 +xtensa xtreg u2 0x1022 +xtensa xtreg u3 0x1023 +xtensa xtreg aep0 0x1024 +xtensa xtreg aep1 0x1025 +xtensa xtreg aep2 0x1026 +xtensa xtreg aep3 0x1027 +xtensa xtreg fcr_fsr 0x1029 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg pwrctl 0x2024 +xtensa xtreg pwrstat 0x2025 +xtensa xtreg eristat 0x2026 +xtensa xtreg cs_itctrl 0x2027 +xtensa xtreg cs_claimset 0x2028 +xtensa xtreg cs_claimclr 0x2029 +xtensa xtreg cs_lockaccess 0x202a +xtensa xtreg cs_lockstatus 0x202b +xtensa xtreg cs_authstatus 0x202c +xtensa xtreg pmg 0x203b +xtensa xtreg pmpc 0x203c +xtensa xtreg pm0 0x203d +xtensa xtreg pm1 0x203e +xtensa xtreg pmctrl0 0x203f +xtensa xtreg pmctrl1 0x2040 +xtensa xtreg pmstat0 0x2041 +xtensa xtreg pmstat1 0x2042 +xtensa xtreg ocdid 0x2043 +xtensa xtreg ocd_dcrclr 0x2044 +xtensa xtreg ocd_dcrset 0x2045 +xtensa xtreg ocd_dsr 0x2046 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg b0 0x0010 +xtensa xtreg b1 0x0011 +xtensa xtreg b2 0x0012 +xtensa xtreg b3 0x0013 +xtensa xtreg b4 0x0014 +xtensa xtreg b5 0x0015 +xtensa xtreg b6 0x0016 +xtensa xtreg b7 0x0017 +xtensa xtreg b8 0x0018 +xtensa xtreg b9 0x0019 +xtensa xtreg b10 0x001a +xtensa xtreg b11 0x001b +xtensa xtreg b12 0x001c +xtensa xtreg b13 0x001d +xtensa xtreg b14 0x001e +xtensa xtreg b15 0x001f +xtensa xtreg psintlevel 0x2006 +xtensa xtreg psum 0x2007 +xtensa xtreg pswoe 0x2008 +xtensa xtreg psexcm 0x2009 +xtensa xtreg pscallinc 0x200a +xtensa xtreg psowb 0x200b +xtensa xtreg acc 0x200c +xtensa xtreg dbnum 0x2011 +xtensa xtreg ae_overflow 0x2014 +xtensa xtreg ae_sar 0x2015 +xtensa xtreg ae_cwrap 0x2016 +xtensa xtreg ae_bitptr 0x2017 +xtensa xtreg ae_bitsused 0x2018 +xtensa xtreg ae_tablesize 0x2019 +xtensa xtreg ae_first_ts 0x201a +xtensa xtreg ae_nextoffset 0x201b +xtensa xtreg ae_searchdone 0x201c +xtensa xtreg roundmode 0x201d +xtensa xtreg invalidflag 0x201e +xtensa xtreg divzeroflag 0x201f +xtensa xtreg overflowflag 0x2020 +xtensa xtreg underflowflag 0x2021 +xtensa xtreg inexactflag 0x2022 diff --git a/openocd-win/openocd/scripts/target/xtensa-core-xt8.cfg b/openocd-win/openocd/scripts/target/xtensa-core-xt8.cfg new file mode 100644 index 0000000..e544d78 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa-core-xt8.cfg @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa xt8 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 32 +xtensa xtopt windowed 1 + + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 3 +xtensa xtopt excmlevel 1 + + +# Cache Options +xtensa xtmem icache 16 1024 1 +xtensa xtmem dcache 16 1024 1 1 + + +# Memory Options +xtensa xtmem iram 0x40000000 1048576 +xtensa xtmem dram 0x3ff00000 262144 +xtensa xtmem srom 0x50000000 131072 +xtensa xtmem sram 0x60000000 4194304 + + +# Memory Protection/Translation Options + + +# Debug Options +xtensa xtopt debuglevel 3 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 + + +# Core Registers +xtensa xtregs 127 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg expstate 0x03e6 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg pwrctl 0x200f +xtensa xtreg pwrstat 0x2010 +xtensa xtreg eristat 0x2011 +xtensa xtreg cs_itctrl 0x2012 +xtensa xtreg cs_claimset 0x2013 +xtensa xtreg cs_claimclr 0x2014 +xtensa xtreg cs_lockaccess 0x2015 +xtensa xtreg cs_lockstatus 0x2016 +xtensa xtreg cs_authstatus 0x2017 +xtensa xtreg fault_info 0x2026 +xtensa xtreg trax_id 0x2027 +xtensa xtreg trax_control 0x2028 +xtensa xtreg trax_status 0x2029 +xtensa xtreg trax_data 0x202a +xtensa xtreg trax_address 0x202b +xtensa xtreg trax_pctrigger 0x202c +xtensa xtreg trax_pcmatch 0x202d +xtensa xtreg trax_delay 0x202e +xtensa xtreg trax_memstart 0x202f +xtensa xtreg trax_memend 0x2030 +xtensa xtreg pmg 0x203e +xtensa xtreg pmpc 0x203f +xtensa xtreg pm0 0x2040 +xtensa xtreg pm1 0x2041 +xtensa xtreg pmctrl0 0x2042 +xtensa xtreg pmctrl1 0x2043 +xtensa xtreg pmstat0 0x2044 +xtensa xtreg pmstat1 0x2045 +xtensa xtreg ocdid 0x2046 +xtensa xtreg ocd_dcrclr 0x2047 +xtensa xtreg ocd_dcrset 0x2048 +xtensa xtreg ocd_dsr 0x2049 +xtensa xtreg psintlevel 0x2003 +xtensa xtreg psum 0x2004 +xtensa xtreg pswoe 0x2005 +xtensa xtreg psexcm 0x2006 +xtensa xtreg pscallinc 0x2007 +xtensa xtreg psowb 0x2008 diff --git a/openocd-win/openocd/scripts/target/xtensa.cfg b/openocd-win/openocd/scripts/target/xtensa.cfg new file mode 100644 index 0000000..101e135 --- /dev/null +++ b/openocd-win/openocd/scripts/target/xtensa.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Target Support for Xtensa Processors +# + +set xtensa_ids { 0x120034e5 0x120134e5 + 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5 + 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5 + 0x20b034e5 } +set expected_xtensa_ids {} +foreach i $xtensa_ids { + lappend expected_xtensa_ids -expected-id $i +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xtensa +} + +if { [info exists CPUTAPID] } { + set _CPUTAPARGLIST "-expected-id $CPUTAPID" +} else { + set _CPUTAPARGLIST [join $expected_xtensa_ids] +} + +set _TARGETNAME $_CHIPNAME +set _CPU0NAME cpu +set _TAPNAME $_CHIPNAME.$_CPU0NAME + +if { [info exists XTENSA_DAP] } { + source [find target/swj-dp.tcl] + # SWD mode ignores the -irlen parameter + eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + + set _TARGETNAME $_CHIPNAME.cpu + if { [info exists XTENSA_DAP_BASE] } { + # Specify fixed offset for accessing XDM via APB behind a DAP interface + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE + } else { + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap + } +} else { + # JTAG direct (without DAP) + eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST + target create $_TARGETNAME xtensa -chain-position $_TAPNAME +} + +$_TARGETNAME configure -event reset-assert-post { soft_reset_halt } + +gdb_report_register_access_error enable diff --git a/openocd-win/openocd/scripts/target/zynq_7000.cfg b/openocd-win/openocd/scripts/target/zynq_7000.cfg new file mode 100644 index 0000000..f5b4478 --- /dev/null +++ b/openocd-win/openocd/scripts/target/zynq_7000.cfg @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Xilinx Zynq-7000 All Programmable SoC +# +# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm +# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip +# +# 0x03736093 XQ7Z100 XC7Z100I XC7Z100 +# 0x03731093 XQ7Z045 XC7Z045I XC7Z045 +# 0x0372c093 XQ7Z030 XC7Z030I XC7Z030 XA7Z030 +# 0x03727093 XQ7Z020 XC7Z020I XC7Z020 XA7Z020 +# 0x03732093 XC7Z035I XC7Z035 +# 0x0373b093 XC7Z015I XC7Z015 +# 0x03728093 XC7Z014S +# 0x0373c093 XC7Z012S +# 0x03722093 XC7Z010I XC7Z010 XA7Z010 +# 0x03723093 XC7Z007S + +set _CHIPNAME zynq +set _TARGETNAME $_CHIPNAME.cpu + +jtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \ + -expected-id 0x03723093 \ + -expected-id 0x03722093 \ + -expected-id 0x0373c093 \ + -expected-id 0x03728093 \ + -expected-id 0x0373B093 \ + -expected-id 0x03732093 \ + -expected-id 0x03727093 \ + -expected-id 0x0372C093 \ + -expected-id 0x03731093 \ + -expected-id 0x03736093 + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477 + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x80090000 +target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x80092000 +target smp ${_TARGETNAME}0 ${_TARGETNAME}1 + +adapter speed 1000 + +${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" +${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" + +pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart +virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23 + +set XC7_JSHUTDOWN 0x0d +set XC7_JPROGRAM 0x0b +set XC7_JSTART 0x0c +set XC7_BYPASS 0x3f + +proc zynqpl_program {tap} { + echo "DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'" + global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS + irscan $tap $XC7_JSHUTDOWN + irscan $tap $XC7_JPROGRAM + runtest 60000 + #JSTART prevents this from working... + #irscan $tap $XC7_JSTART + runtest 2000 + irscan $tap $XC7_BYPASS + runtest 2000 +} diff --git a/openocd-win/openocd/scripts/target/к1879xб1я.cfg b/openocd-win/openocd/scripts/target/к1879xб1я.cfg new file mode 100644 index 0000000..8dd330d --- /dev/null +++ b/openocd-win/openocd/scripts/target/к1879xб1я.cfg @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# СБИС К1879ХБ1Я +# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/ + +adapter speed 1000 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME к1879хб1я +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists DSP_TAPID] } { + set _DSP_TAPID $DSP_TAPID +} else { + set _DSP_TAPID 0x2b900f0f +} + +jtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID + +if { [info exists CPU_TAPID] } { + set _CPU_TAPID $CPU_TAPID +} else { + set _CPU_TAPID 0x07b76f0f +} + +jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID + +set _TARGETNAME $_CHIPNAME.arm +target create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm diff --git a/openocd-win/openocd/scripts/test/selftest.cfg b/openocd-win/openocd/scripts/test/selftest.cfg new file mode 100644 index 0000000..10efb0c --- /dev/null +++ b/openocd-win/openocd/scripts/test/selftest.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>" + +proc selftest {tmpfile address size} { + + for {set i 0} {$i < $size } {set i [expr {$i+4}]} { + mww [expr {$address+$i}] $i + } + + for {set i 0} {$i < 10 } {set i [expr {$i+1}]} { + echo "Test iteration $i" + dump_image $tmpfile $address $size + verify_image $tmpfile $address bin + load_image $tmpfile $address bin + } + +} diff --git a/openocd-win/openocd/scripts/test/syntax1.cfg b/openocd-win/openocd/scripts/test/syntax1.cfg new file mode 100644 index 0000000..7735ee9 --- /dev/null +++ b/openocd-win/openocd/scripts/test/syntax1.cfg @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +adapter srst delay 200 +jtag_ntrst_delay 200 + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config trst_and_srst srst_pulls_trst + +#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough +adapter assert trst assert srst +adapter deassert trst deassert srst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f + +#target configuration +#daemon_startup reset + +set _TARGETNAME [format "%s.cpu" lpc2148] +target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-backup 0 + +$_TARGETNAME configure -event reset-init { +soft_reset_halt +mvb 0xE01FC040 0x01 +} + + + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 diff --git a/openocd-win/openocd/scripts/tools/firmware-recovery.tcl b/openocd-win/openocd/scripts/tools/firmware-recovery.tcl new file mode 100644 index 0000000..6a328cd --- /dev/null +++ b/openocd-win/openocd/scripts/tools/firmware-recovery.tcl @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "\n\nFirmware recovery helpers" +echo "Use -c firmware_help to get help\n" + +set known_boards { + "asus-rt-n16 ASUS RT-N16" + "asus-rt-n66u ASUS RT-N66U" + "linksys-wag200g Linksys WAG200G" + "linksys-wrt54gl Linksys WRT54GL v1.1" + "netgear-dg834v3 Netgear DG834G v3" + "tp-link_tl-mr3020 TP-LINK TL-MR3020" + "bt-homehubv1 BT HomeHub v1" +} + +proc firmware_help { } { + echo " +Your OpenOCD command should look like this: +openocd -f interface/<jtag adapter>.cfg -f tools/firmware-recovery.tcl -c \"<commands>*; shutdown\" + +Where: +<jtag adapter> is one of the supported devices, e.g. ftdi/jtagkey2 +<commands> are firmware-recovery commands separated by semicolon + +Supported commands: +firmware_help get this help +list_boards list known boards and exit +board <name> select board you work with +list_partitions list partitions of the currently selected board +dump_part <name> <filename> save partition's contents to a file +erase_part <name> erase the given partition +flash_part <name> <filename> erase, flash and verify the given partition +ram_boot <filename> load binary file to RAM and run it +adapter speed <freq> set JTAG clock frequency in kHz + +For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run: +openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\ + -c \"board asus-rt-n16; erase_part nvram; flash_part CFE cfe-n16.bin; shutdown\" +\n\n" + shutdown +} + +# set default, can be overridden later +adapter speed 1000 + +proc get_partition { name } { + global partition_list + dict get $partition_list $name +} + +proc partition_desc { name } { lindex [get_partition $name] 0 } +proc partition_start { name } { lindex [get_partition $name] 1 } +proc partition_size { name } { lindex [get_partition $name] 2 } + +proc list_boards { } { + global known_boards + echo "List of the supported boards:\n" + echo "Board name\t\tDescription" + echo "-----------------------------------" + foreach i $known_boards { + echo $i + } + echo "\n\n" +} + +proc board { name } { + script [find board/$name.cfg] +} + +proc list_partitions { } { + global partition_list + set fstr "%-16s%-14s%-14s%s" + echo "\nThe currently selected board is known to have these partitions:\n" + echo [format $fstr Name Start Size Description] + echo "-------------------------------------------------------" + for {set i 0} {$i < [llength $partition_list]} {incr i 2} { + set key [lindex $partition_list $i] + echo [format $fstr $key [partition_start $key] [partition_size $key] [partition_desc $key]] + } + echo "\n\n" +} + +# Magic to work with any targets, including semi-functional +proc prepare_target { } { + init + catch {halt} + catch {reset init} + catch {halt} +} + +proc dump_part { name filename } { + prepare_target + dump_image $filename [partition_start $name] [partition_size $name] +} + +proc erase_part { name } { + prepare_target + flash erase_address [partition_start $name] [partition_size $name] +} + +proc flash_part { name filename } { + prepare_target + flash write_image erase $filename [partition_start $name] bin + echo "Verifying:" + verify_image $filename [partition_start $name] +} + +proc ram_boot { filename } { + global ram_boot_address + prepare_target + load_image $filename $ram_boot_address bin + resume $ram_boot_address +} + +echo "" diff --git a/openocd-win/openocd/scripts/tools/memtest.tcl b/openocd-win/openocd/scripts/tools/memtest.tcl new file mode 100644 index 0000000..f70f950 --- /dev/null +++ b/openocd-win/openocd/scripts/tools/memtest.tcl @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Algorithms by Michael Barr, released into public domain +# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser + +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] + +proc runAllMemTests { baseAddress nBytes } { + memTestDataBus $baseAddress + memTestAddressBus $baseAddress $nBytes + memTestDevice $baseAddress $nBytes +} + +#*********************************************************************************** +# * +# * Function: memTestDataBus() +# * +# * Description: Test the data bus wiring in a memory region by +# * performing a walking 1's test at a fixed address +# * within that region. The address (and hence the +# * memory region) is selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * Notes: +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first pattern that failed. +# * +#*********************************************************************************** +proc memTestDataBus { address } { + echo "Running memTestDataBus" + + for {set i 0} {$i < 32} {incr i} { + # Shift bit + set pattern [expr {1 << $i}] + + # Write pattern to memory + memwrite32 $address $pattern + + # Read pattern from memory + set data [memread32 $address] + + if {$data != $pattern} { + echo "FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data" + return $pattern + } + } +} + +#*********************************************************************************** +# * +# * Function: memTestAddressBus() +# * +# * Description: Perform a walking 1's test on the relevant bits +# * of the address and check for aliasing. This test +# * will find single-bit address failures such as stuck +# * -high, stuck-low, and shorted pins. The base address +# * and size of the region are selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * +# * Notes: For best results, the selected base address should +# * have enough LSB 0's to guarantee single address bit +# * changes. For example, to test a 64-Kbyte region, +# * select a base address on a 64-Kbyte boundary. Also, +# * select the region size as a power-of-two--if at all +# * possible. +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first address at which an +# * aliasing problem was uncovered. By examining the +# * contents of memory, it may be possible to gather +# * additional information about the problem. +# * +#*********************************************************************************** +proc memTestAddressBus { baseAddress nBytes } { + set addressMask [expr {$nBytes - 1}] + set pattern 0xAAAAAAAA + set antipattern 0x55555555 + + echo "Running memTestAddressBus" + + echo "addressMask: [convertToHex $addressMask]" + + echo "memTestAddressBus: Writing the default pattern at each of the power-of-two offsets..." + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}] } { + set addr [expr {$baseAddress + $offset}] + memwrite32 $addr $pattern + } + + echo "memTestAddressBus: Checking for address bits stuck high..." + memwrite32 $baseAddress $antipattern + + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + + if {$data != $pattern} { + echo "FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]" + return $pattern + } + } + + echo "memTestAddressBus: Checking for address bits stuck low or shorted..." + memwrite32 $baseAddress $pattern + for {set testOffset 32} {[expr {$testOffset & $addressMask}] != 0} {set testOffset [expr {$testOffset << 1}] } { + set addr [expr {$baseAddress + $testOffset}] + memwrite32 $addr $antipattern + + set data [memread32 $baseAddress] + if {$data != $pattern} { + echo "FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]" + return $pattern + } + + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $baseAddress] + + if {(($data != $pattern) && ($offset != $testOffset))} { + echo "FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]" + return $pattern + } + } + set addr [expr {$baseAddress + $testOffset}] + memwrite32 $addr $pattern + } +} + +#*********************************************************************************** +# * +# * Function: memTestDevice() +# * +# * Description: Test the integrity of a physical memory device by +# * performing an increment/decrement test over the +# * entire region. In the process every storage bit +# * in the device is tested as zero and as one. The +# * base address and the size of the region are +# * selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * Notes: +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first address at which an +# * incorrect value was read back. By examining the +# * contents of memory, it may be possible to gather +# * additional information about the problem. +# * +#*********************************************************************************** +proc memTestDevice { baseAddress nBytes } { + echo "Running memTestDevice" + + echo "memTestDevice: Filling memory with a known pattern..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + memwrite32 [expr {$baseAddress + $offset}] $pattern + } + + echo "memTestDevice: Checking each location and inverting it for the second pass..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + + if {$data != $pattern} { + echo "FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]" + return $pattern + } + + set antiPattern [expr {~$pattern}] + memwrite32 [expr {$baseAddress + $offset}] $antiPattern + } + + echo "memTestDevice: Checking each location for the inverted pattern and zeroing it..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + set antiPattern [expr {~$pattern & ((1<<32) - 1)}] + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + set dataHex [convertToHex $data] + set antiPatternHex [convertToHex $antiPattern] + if {$dataHex != $antiPatternHex} { + echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset" + return $pattern + } + } +} + +proc convertToHex { value } { + format 0x%08x $value +} diff --git a/openocd-win/openocd/scripts/tools/test_cpu_speed.tcl b/openocd-win/openocd/scripts/tools/test_cpu_speed.tcl new file mode 100644 index 0000000..f1a3fb3 --- /dev/null +++ b/openocd-win/openocd/scripts/tools/test_cpu_speed.tcl @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Description: +# Measure the CPU clock frequency of an ARM Cortex-M based device. +# +# Return: +# The CPU clock frequency in Hz. A negative value indicates that the loop +# counter was saturated. +# +# Note: +# You may need to adapt the number of cycles for your device. +# +add_help_text cortex_m_test_cpu_speed "Measure the CPU clock frequency of an ARM Cortex-M based device" +add_usage_text cortex_m_test_cpu_speed {address [timeout [cycles_per_loop]]} +proc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } { + set loop_counter_start 0xffffffff + + halt + + # Backup registers and memory. + set backup_regs [get_reg -force {pc r0 xpsr}] + set backup_mem [read_memory $address 16 3] + + # We place the following code at the given address to measure the + # CPU clock frequency: + # + # 3801: subs r0, #1 + # d1fd: bne #-2 + # e7fe: b #-4 + write_memory $address 16 {0x3801 0xd1fd 0xe7fe} + + set_reg "pc $address r0 $loop_counter_start" + resume + sleep $timeout + halt + + # Get the loop counter value from register r0. + set loop_counter_end [dict values [get_reg r0]] + set loop_counter_diff [expr {$loop_counter_start - $loop_counter_end}] + + # Restore registers and memory. + set_reg $backup_regs + write_memory $address 16 $backup_mem + + if { [expr {$loop_counter_end == 0}] } { + return -1 + } + + return [expr {double($loop_counter_diff) * $cycles_per_loop / $timeout * 1000}] +} diff --git a/unbrick-toolkit/OpenOCD/bitsbytes.tcl b/unbrick-toolkit/OpenOCD/bitsbytes.tcl new file mode 100644 index 0000000..03d758e --- /dev/null +++ b/unbrick-toolkit/OpenOCD/bitsbytes.tcl @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +#---------------------------------------- +# Purpose - Create some $BIT variables +# Create $K and $M variables +# and some bit field extraction variables. +# Create helper variables ... +# BIT0.. BIT31 + +for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} { + set vn [format "BIT%d" $x] + global $vn + set $vn [expr {1 << $x}] +} + +# Create K bytes values +# __1K ... to __2048K +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { + set vn [format "__%dK" $x] + global $vn + set $vn [expr {1024 * $x}] +} + +# Create M bytes values +# __1M ... to __2048K +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { + set vn [format "__%dM" $x] + global $vn + set $vn [expr {1024 * 1024 * $x}] +} + +proc create_mask { MSB LSB } { + return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}] +} + +# Cut Bits $MSB to $LSB out of this value. +# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16] +# Result: 0x02340000 + +proc extract_bitfield { VALUE MSB LSB } { + return [expr {[create_mask $MSB $LSB] & $VALUE}] +} + + +# Cut bits $MSB to $LSB out of this value +# and shift (normalize) them down to bit 0. +# +# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16] +# Result: 0x00000234 +# +proc normalize_bitfield { VALUE MSB LSB } { + return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}] +} + +proc show_normalize_bitfield { VALUE MSB LSB } { + set m [create_mask $MSB $LSB] + set mr [expr {$VALUE & $m}] + set sr [expr {$mr >> $LSB}] + echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr] + return $sr +} diff --git a/unbrick-toolkit/OpenOCD/bootloader.bin b/unbrick-toolkit/OpenOCD/bootloader.bin new file mode 100644 index 0000000..11fdf1d Binary files /dev/null and b/unbrick-toolkit/OpenOCD/bootloader.bin differ diff --git a/unbrick-toolkit/OpenOCD/interface/stlink-dap.cfg b/unbrick-toolkit/OpenOCD/interface/stlink-dap.cfg new file mode 100644 index 0000000..99c81c1 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/interface/stlink-dap.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# +# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect" +# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect" +# +# SWIM transport is natively supported +# + +adapter driver st-link +st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# transport select dapdirect_jtag +# transport select dapdirect_swd +# transport select swim + +# Optionally specify the serial number of usb device +# e.g. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/unbrick-toolkit/OpenOCD/interface/stlink-v1.cfg b/unbrick-toolkit/OpenOCD/interface/stlink-v1.cfg new file mode 100644 index 0000000..96ed088 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/interface/stlink-v1.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/unbrick-toolkit/OpenOCD/interface/stlink-v2-1.cfg b/unbrick-toolkit/OpenOCD/interface/stlink-v2-1.cfg new file mode 100644 index 0000000..d2baad4 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/interface/stlink-v2-1.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/unbrick-toolkit/OpenOCD/interface/stlink-v2.cfg b/unbrick-toolkit/OpenOCD/interface/stlink-v2.cfg new file mode 100644 index 0000000..400411e --- /dev/null +++ b/unbrick-toolkit/OpenOCD/interface/stlink-v2.cfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg" +source [find interface/stlink.cfg] diff --git a/unbrick-toolkit/OpenOCD/interface/stlink.cfg b/unbrick-toolkit/OpenOCD/interface/stlink.cfg new file mode 100644 index 0000000..8578bf2 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/interface/stlink.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit +# debugger/programmer +# + +adapter driver hla +hla_layout stlink +hla_device_desc "ST-LINK" +hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757 + +# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 +# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 +# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial +# number reset issues. +# eg. +# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" diff --git a/unbrick-toolkit/OpenOCD/k5_v2.01.27_fw.bin b/unbrick-toolkit/OpenOCD/k5_v2.01.27_fw.bin new file mode 100644 index 0000000..0c6eebb Binary files /dev/null and b/unbrick-toolkit/OpenOCD/k5_v2.01.27_fw.bin differ diff --git a/unbrick-toolkit/OpenOCD/libusb0.dll b/unbrick-toolkit/OpenOCD/libusb0.dll new file mode 100644 index 0000000..28122e1 Binary files /dev/null and b/unbrick-toolkit/OpenOCD/libusb0.dll differ diff --git a/unbrick-toolkit/OpenOCD/mem_helper.tcl b/unbrick-toolkit/OpenOCD/mem_helper.tcl new file mode 100644 index 0000000..0229d54 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/mem_helper.tcl @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Helper for common memory read/modify/write procedures + +# mrw: "memory read word", returns value of $reg +proc mrw {reg} { + return [read_memory $reg 32 1] +} + +add_usage_text mrw "address" +add_help_text mrw "Returns value of word in memory." + +# mrh: "memory read halfword", returns value of $reg +proc mrh {reg} { + return [read_memory $reg 16 1] +} + +add_usage_text mrh "address" +add_help_text mrh "Returns value of halfword in memory." + +# mrb: "memory read byte", returns value of $reg +proc mrb {reg} { + return [read_memory $reg 8 1] +} + +add_usage_text mrb "address" +add_help_text mrb "Returns value of byte in memory." + +# mmw: "memory modify word", updates value of $reg +# $reg <== ((value & ~$clearbits) | $setbits) +proc mmw {reg setbits clearbits} { + set old [mrw $reg] + set new [expr {($old & ~$clearbits) | $setbits}] + mww $reg $new +} + +add_usage_text mmw "address setbits clearbits" +add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;" diff --git a/unbrick-toolkit/OpenOCD/memory.tcl b/unbrick-toolkit/OpenOCD/memory.tcl new file mode 100644 index 0000000..b111749 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/memory.tcl @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# MEMORY +# +# All Memory regions have two components. +# (1) A count of regions, in the form N_NAME +# (2) An array within info about each region. +# +# The ARRAY +# +# <NAME>( RegionNumber , ATTRIBUTE ) +# +# Where <NAME> is one of: +# +# N_FLASH & FLASH (internal memory) +# N_RAM & RAM (internal memory) +# N_MMREGS & MMREGS (for memory mapped registers) +# N_XMEM & XMEM (off chip memory, ie: flash on cs0, sdram on cs2) +# or N_UNKNOWN & UNKNOWN for things that do not exist. +# +# We have 1 unknown region. +set N_UNKNOWN 1 +# All MEMORY regions must have these attributes +# CS - chip select (if internal, use -1) +set UNKNOWN(0,CHIPSELECT) -1 +# BASE - base address in memory +set UNKNOWN(0,BASE) 0 +# LEN - length in bytes +set UNKNOWN(0,LEN) $CPU_MAX_ADDRESS +# HUMAN - human name of the region +set UNKNOWN(0,HUMAN) "unknown" +# TYPE - one of: +# flash, ram, mmr, unknown +# For harvard arch: +# iflash, dflash, iram, dram +set UNKNOWN(0,TYPE) "unknown" +# RWX - access ablity +# unix style chmod bits +# 0 - no access +# 1 - execute +# 2 - write +# 4 - read +# hence: 7 - readwrite execute +set RWX_NO_ACCESS 0 +set RWX_X_ONLY $BIT0 +set RWX_W_ONLY $BIT1 +set RWX_R_ONLY $BIT2 +set RWX_RW [expr {$RWX_R_ONLY + $RWX_W_ONLY}] +set RWX_R_X [expr {$RWX_R_ONLY + $RWX_X_ONLY}] +set RWX_RWX [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}] +set UNKNOWN(0,RWX) $RWX_NO_ACCESS + +# WIDTH - access width +# 8,16,32 [0 means ANY] +set ACCESS_WIDTH_NONE 0 +set ACCESS_WIDTH_8 $BIT0 +set ACCESS_WIDTH_16 $BIT1 +set ACCESS_WIDTH_32 $BIT2 +set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}] +set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE + +proc iswithin { ADDRESS BASE LEN } { + return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}] +} + +proc address_info { ADDRESS } { + + foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } { + if { info exists $WHERE } { + set lmt [set N_[set WHERE]] + for { set region 0 } { $region < $lmt } { incr region } { + if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } { + return "$WHERE $region"; + } + } + } + } + + # Return the 'unknown' + return "UNKNOWN 0" +} + +proc memread32 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] { + return $foo + } else { + error "memread32: $msg" + } +} + +proc memread16 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] { + return $foo + } else { + error "memread16: $msg" + } +} + +proc memread8 {ADDR} { + if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] { + return $foo + } else { + error "memread8: $msg" + } +} + +proc memwrite32 {ADDR DATA} { + if ![ catch { write_memory $ADDR 32 $DATA } msg ] { + return $DATA + } else { + error "memwrite32: $msg" + } +} + +proc memwrite16 {ADDR DATA} { + if ![ catch { write_memory $ADDR 16 $DATA } msg ] { + return $DATA + } else { + error "memwrite16: $msg" + } +} + +proc memwrite8 {ADDR DATA} { + if ![ catch { write_memory $ADDR 8 $DATA } msg ] { + return $DATA + } else { + error "memwrite8: $msg" + } +} + +proc memread32_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] { + return $foo + } else { + error "memread32: $msg" + } +} + +proc memread16_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] { + return $foo + } else { + error "memread16: $msg" + } +} + +proc memread8_phys {ADDR} { + if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] { + return $foo + } else { + error "memread8: $msg" + } +} + +proc memwrite32_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite32: $msg" + } +} + +proc memwrite16_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite16: $msg" + } +} + +proc memwrite8_phys {ADDR DATA} { + if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] { + return $DATA + } else { + error "memwrite8: $msg" + } +} diff --git a/unbrick-toolkit/OpenOCD/mmr_helpers.tcl b/unbrick-toolkit/OpenOCD/mmr_helpers.tcl new file mode 100644 index 0000000..5c37fcf --- /dev/null +++ b/unbrick-toolkit/OpenOCD/mmr_helpers.tcl @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +proc proc_exists { NAME } { + set n [info commands $NAME] + set l [string length $n] + return [expr {$l != 0}] +} + +# Give: REGISTER name - must be a global variable. +proc show_mmr32_reg { NAME } { + + global $NAME + # we want $($NAME) + set a [set [set NAME]] + + if ![catch { set v [memread32 $a] } msg ] { + echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v] + + # Was a helper defined? + set fn show_${NAME}_helper + if [ proc_exists $fn ] { + # Then call it + $fn $NAME $a $v + } + return $v; + } else { + error [format "%s (%s)" $msg $NAME ] + } +} + + +# Give: NAMES - an array of names accessible +# in the callers symbol-scope. +# VAL - the bits to display. + +proc show_mmr32_bits { NAMES VAL } { + + upvar $NAMES MYNAMES + + set w 5 + foreach {IDX N} $MYNAMES { + set l [string length $N] + if { $l > $w } { set w $l } + } + + for { set x 24 } { $x >= 0 } { incr x -8 } { + echo -n " " + for { set y 7 } { $y >= 0 } { incr y -1 } { + set s $MYNAMES([expr {$x + $y}]) + echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ] + } + echo "" + + echo -n " " + for { set y 7 } { $y >= 0 } { incr y -1 } { + echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""] + } + echo "" + } +} + + +proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } { + set width [expr {(($MSB - $LSB + 1) + 7) / 4}] + set nval [show_normalize_bitfield $VAL $MSB $LSB ] + set name0 [lindex $FIELDVALUES 0 ] + if [ string compare $name0 _NUMBER_ ] { + set sval [lindex $FIELDVALUES $nval] + } else { + set sval "" + } + echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ] +} + +# Give: ADDR - address of the register. +# BIT - bit's number. + +proc get_mmr_bit { ADDR BIT } { + set val [memread32 $ADDR] + set bit_val [expr {$val & [expr {1 << $BIT}]}] + return $bit_val +} + + +# Give: ADDR - address of the register. +# MSB - MSB bit's number. +# LSB - LSB bit's number. + +proc get_mmr_bitfield { ADDR MSB LSB } { + set rval [memread32 $ADDR] + return normalize_bitfield $rval $MSB $LSB +} diff --git a/unbrick-toolkit/OpenOCD/openocd.exe b/unbrick-toolkit/OpenOCD/openocd.exe new file mode 100644 index 0000000..73888f5 Binary files /dev/null and b/unbrick-toolkit/OpenOCD/openocd.exe differ diff --git a/unbrick-toolkit/OpenOCD/target/dp32g030.cfg b/unbrick-toolkit/OpenOCD/target/dp32g030.cfg new file mode 100644 index 0000000..9f279f1 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/target/dp32g030.cfg @@ -0,0 +1,340 @@ +#OpenOCD script for Action Dynamic DP32G030 ARM Cortex M0 CPU (UV-5R, UV-k5 Ham HTs) +#For use with cheap ST-Link USB debug probe +source target/swj-dp.tcl + +set _CHIP_NAME DP32G0xx +set _ENDIAN little +set _WORKAREASIZE 0x1000 +set _FLASH_SIZE 0x10000 +set _CPUTAPID 0x0BB11477 +set _TARGETNAME $_CHIP_NAME.cpu +set _FLASHNAME $_CHIP_NAME.flash +set _SECTOR_SIZE 512 +set _MASKING_CFG 2 ;#1:2kB, 2:4kB, 3:8kB + +adapter speed 960 +adapter srst delay 100 +reset_config srst_nogate + +# Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan +swj_newdap $_CHIP_NAME cpu -expected-id $_CPUTAPID -enable + +# Create the DAP instance, this must be explicitly created according to the OpenOCD docs +dap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu + +# Set up the GDB target for the CPU +target create $_CHIP_NAME.cpu cortex_m -endian $_ENDIAN -dap $_CHIP_NAME.dap +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Declare internal bank +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME + +proc check_readiness {} { + while {[read_memory 0x4006F014 32 1] & 0x2} {} +} + +proc rom_mask_off {} { + echo "\nChecking ROM masking" + check_readiness + set status [read_memory 0x4006F020 32 1] + if {($status & 0x3) != 0} { + echo [format "\nROM masking is set to 0b%03b. Unsetting..." $status] + write_memory 0x4006F020 32 [expr {[read_memory 0x4006F020 32 1] & 0x3}] + check_readiness + write_memory 0x4006F020 32 0 + check_readiness + write_memory 0x4006F020 32 4 + } + return [read_memory 0x4006F020 32 1] +} + +proc rom_mask_on {} { + global _MASKING_CFG + echo "\nChecking ROM masking" + check_readiness + set status [read_memory 0x4006F020 32 1] + if {($status & 0x3) != $_MASKING_CFG} { + echo [format "\nROM masking is set to 0b%03b. Setting ON..." $status] + write_memory 0x4006F020 32 [expr {[read_memory 0x4006F020 32 1] & 0x3}] + check_readiness + write_memory 0x4006F020 32 $_MASKING_CFG + check_readiness + write_memory 0x4006F020 32 [expr {4 | $_MASKING_CFG}] + } + return [read_memory 0x4006F020 32 1] +} + +proc unlock_rom {} { + write_memory 0x4006F01c 32 0xAA + check_readiness +} + +proc lock_rom {} { + write_memory 0x4006F018 32 0x55 + check_readiness +} + +proc select_region {target_r} { + #Region 0 is main user ROM area, 1 is NVRAM area + write_memory 0x4006F000 32 [expr {(0x31 & [read_memory 0x4006F000 32 1]) | (($target_r & 0x1) << 1)}] + check_readiness +} + +proc wipe_sector_range {st_sec sec_count} { + set last [expr {$st_sec + $sec_count}] + set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}] + write_memory 0x4006F000 32 [expr {$reg | 0x8}] ;#set writing mode ERASE + + for {set i $st_sec} {$i < $last} {incr i} { + check_readiness + echo -n [format "\rErasing sector 0x%02x = offset 0x%04x" [expr {$i}] [expr {$i*512}] ] + write_memory 0x4006F004 32 [expr {$i << 7}] ;#set address in flash + write_memory 0x4006F010 32 0x01 ;#do it + } + check_readiness + write_memory 0x4006F000 32 $reg +} + +proc wipe_rom {} { + #This will wipe everything including bootloader + global _SECTOR_SIZE + global _FLASH_SIZE + unlock_rom + select_region 0 + if {[rom_mask_off] != 4} { + echo "\nROM Masking failed to disable!" + close $fd + return + } + wipe_sector_range 0 [expr {$_FLASH_SIZE / $_SECTOR_SIZE}] +} + +proc write_image {filename offset} { + global _SECTOR_SIZE + global _FLASH_SIZE + set fs [file size $filename] + set fd [open $filename "rb"] + set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}] + write_memory 0x4006F000 32 [expr {$reg | 0x4}] ;#set writing mode PROGRAM + while {![eof $fd]} { + if {($offset+4) > $_FLASH_SIZE} { + echo "\nData exceeds main storage capacity!" + write_memory 0x4006F000 32 $reg + lock_rom + close $fd + return + } + check_readiness + set data [read $fd 4] + set data $data[string repeat \xFF [expr {4-[string length $data]}]] ;#padding + binary scan $data i i_data + write_memory 0x4006F004 32 [expr {($offset>>2)+0xC000}] ;#set destination offset + write_memory 0x4006F008 32 $i_data ;#set word + write_memory 0x4006F010 32 0x01 ;#set OPSTART=1 + while {([read_memory 0x4006F014 32 1] & 4) == 0} {} + echo -n [format "\rProgrammed up to 0x%04x (FLASH_ADDR=0x%04x)" $offset [expr {($offset>>2)+0xC000}]] + incr offset 4 + } + check_readiness + write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF +} + +proc flash_blocks {filename address nblocks offset} { + #Intended for speed. Due to tight timings, sometimes it works, sometimes it does not. Needs clocks adjusting there. + global _SECTOR_SIZE + global _FLASH_SIZE + + if {($nblocks != 0) & [expr {$nblocks & 1}]} { + set nblocks [expr {$nblocks + 1}] + } + set addr [expr {$_SECTOR_SIZE * ($address >> 9)}] + set fs [expr {((($_SECTOR_SIZE*$nblocks)/2 + $_SECTOR_SIZE-1)&(0x10000000-$_SECTOR_SIZE))}] + set fd [open $filename "rb"] + + read $fd $addr + set addr [expr {$addr + $offset}] ;#apply ROM offset + set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}] + + echo -n [format "\tWiping %02d sectors, starting at %02d " [expr {$nblocks / 2}] [expr {$addr >> 9}]] + + wipe_sector_range [expr {$addr >> 9}] [expr {$nblocks / 2}] ;#wipe related sectors + echo "\nRegion cleared OK" + + echo [format "%02d bytes to push" $fs]; ##DEBUG + write_memory 0x4006F000 32 [expr {$reg | 0x4}] ;#set writing mode PROGRAM + + while {$fs > 0} { + write_memory 0x4006F004 32 [expr {0xC000+(($addr)>>2)}] ;#set block starting offset + set i_buffer {} + for {set blk 0} {$blk < $_SECTOR_SIZE/2} {incr blk 4} { + set data [read $fd 4] + set data $data[string repeat \xFF [expr {4-[string length $data]}]] ;#padding to desired ending block + if {($addr+$_SECTOR_SIZE/2) >= $_FLASH_SIZE} { + echo [format "\nMain firmware image upper boundary reached (%d)!" $addr] + write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF + close $fd + return + } + binary scan $data i i_data + lappend i_buffer [expr {$i_data & 0xFFFFFFFF}] + incr fs -4 + } + echo [format "\nWriting at offset 0x%04x" [expr {$addr}]] + ##for {set bi 0} {$bi < 64} {incr bi} {echo -n [format "%08x" [lindex $i_buffer $bi]]}; #DEBUG + write_memory 0x4006F008 32 [lindex $i_buffer 0] ;#prepare 1st word: we need to be quick beyond this point + check_readiness + write_memory 0x4006F010 32 0x01 + for {set bi 1} {$bi < 64} {incr bi} {while {([read_memory 0x4006F014 32 1] & 0x4) == 4} {write_memory 0x4006F008 32 [lindex $i_buffer $bi]}} + check_readiness + incr addr $_SECTOR_SIZE/2 ;# Next block + } + write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF + echo [format "\nLast write was 0x%08x " [lindex $i_buffer 63]] + close $fd + return +} + +proc toggle_pin_gpioa {pin} { + write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] ^(1<<$pin) }] +} + +proc toggle_pin_gpiob {pin} { + write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] ^(1<<$pin) }] +} + +proc toggle_pin_gpioc {pin} { + write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] ^(1<<$pin) }] +} + +proc set_pin_gpioa {pin value} { + if {$value == 0} { + write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] &~(1<<$pin) }] + } else { + write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] |(1<<$pin) }] + } +} + +proc set_pin_gpiob {pin value} { + if {$value == 0} { + write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] &~(1<<$pin) }] + } else { + write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] |(1<<$pin) }] + } +} + +proc set_pin_gpioc {pin value} { + if {$value == 0} { + write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] &~(1<<$pin) }] + } else { + write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] |(1<<$pin) }] + } +} + +##Quansheng UVK5-specific snippets + +proc uv_fastflash_bl {filename} { + write_memory 0x4006F024 32 0x4E02A300 ;#force stock timings, just in case + write_memory 0x4006F028 32 0x210360 + write_memory 0x4006F000 32 0x1 + check_readiness + select_region 0 + if {[rom_mask_off] != 4} { + echo "\nROM Masking failed to disable!" + close $fd + return + } + reset halt + unlock_rom + + flash_blocks $filename 0 16 0 + + #just relock flashROM + lock_rom +} + +proc uv_fastflash_fw {filename} { + #Make sure bootloader is hidden + if {[rom_mask_on] != 6} { + echo "\nROM Masking failed to enable!" + close $fd + return + } + reset halt + unlock_rom + + flash_blocks $filename 0 [expr {[file size $filename] >> 8}] 0 + reset + echo "\nCPU reset: Transceiver should boot now." +} + +proc uv_flash_bl {filename} { + #Securely rewrites bootloader (slowly) + + if {[file size $filename] > 0x1000} { + echo [format "Bootloader image is too large to fit!] + return + } + select_region 0 + if {[rom_mask_off] != 4} { + echo "\nROM Masking failed to disable!" + return + } + reset halt + unlock_rom + + wipe_sector_range 0 8 + echo "\nRegion cleared OK" + + write_image $filename 0 + + if {[rom_mask_on] != 6} { + echo "\nROM Masking failed to enable!" + lock_rom + return + } + #relock flashROM, in case conventional method for fw is preferred + lock_rom + echo "\nBootloader code programmed.\nYou can use uv_flash_fw to program main firmware, or just use stock tool to do it." +} + +proc uv_flash_fw {filename} { + #Securely rewrites main firmware (slowly) + + select_region 0 + #Make sure bootloader is hidden + if {[rom_mask_on] != 6} { + echo "\nROM Masking failed to enable!" + return + } + reset halt + unlock_rom + + wipe_sector_range 0 120 + echo "\nRegion cleared OK" + + write_image $filename 0 + + #relock flashROM, then reset CPU + lock_rom + reset + echo "\nCPU reset: Transceiver should boot now." +} + +proc uv_flashlight_toggle {} { + toggle_pin_gpioc 3 ;# toggles PORTC.3 +} + +proc uv_flashlight_on {} { + set_pin_gpioc 3 1 ;# set PORTC.3 high +} + +proc uv_flashlight_off {} { + set_pin_gpioc 3 0 ;# set PORTC.3 to low +} + +proc uv_backlight_toggle {} { + toggle_pin_gpiob 6 ;# toggles PORTB.6 +} + +init +#reset halt diff --git a/unbrick-toolkit/OpenOCD/target/swj-dp-legacy.tcl b/unbrick-toolkit/OpenOCD/target/swj-dp-legacy.tcl new file mode 100644 index 0000000..1d274cb --- /dev/null +++ b/unbrick-toolkit/OpenOCD/target/swj-dp-legacy.tcl @@ -0,0 +1,34 @@ +# ARM Debug Interface V5 (ADI_V5) utility +# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since +# SW-DP and JTAG-DP targets don't need to switch based +# on which transport is active. +# +# declare a JTAG or SWD Debug Access Point (DAP) +# based on the transport in use with this session. +# You can't access JTAG ops when SWD is active, etc. + +# params are currently what "jtag newtap" uses +# because OpenOCD internals are still strongly biased +# to JTAG .... but for SWD, "irlen" etc are ignored, +# and the internals work differently + +# for now, ignore non-JTAG and non-SWD transports +# (e.g. initial flash programming via SPI or UART) + +# split out "chip" and "tag" so we can someday handle +# them more uniformly irlen too...) + +if [catch {transport select}] { + echo "Error: unable to select a session transport. Can't continue." + shutdown +} + +proc swj_newdap {chip tag args} { + if [using_hla] { + eval hla newtap $chip $tag $args + } elseif [using_jtag] { + eval jtag newtap $chip $tag $args + } elseif [using_swd] { + eval swd newdap $chip $tag $args + } +} diff --git a/unbrick-toolkit/OpenOCD/target/swj-dp.tcl b/unbrick-toolkit/OpenOCD/target/swj-dp.tcl new file mode 100644 index 0000000..f2b233f --- /dev/null +++ b/unbrick-toolkit/OpenOCD/target/swj-dp.tcl @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# ARM Debug Interface V5 (ADI_V5) utility +# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since +# SW-DP and JTAG-DP targets don't need to switch based +# on which transport is active. +# +# declare a JTAG or SWD Debug Access Point (DAP) +# based on the transport in use with this session. +# You can't access JTAG ops when SWD is active, etc. + +# params are currently what "jtag newtap" uses +# because OpenOCD internals are still strongly biased +# to JTAG .... but for SWD, "irlen" etc are ignored, +# and the internals work differently + +# for now, ignore non-JTAG and non-SWD transports +# (e.g. initial flash programming via SPI or UART) + +# split out "chip" and "tag" so we can someday handle +# them more uniformly irlen too...) + +if [catch {transport select}] { + echo "Error: unable to select a session transport. Can't continue." + shutdown +} + +proc swj_newdap {chip tag args} { + if [using_jtag] { + eval jtag newtap $chip $tag $args + } elseif [using_swd] { + eval swd newdap $chip $tag $args + } else { + echo "Error: transport '[ transport select ]' not supported by swj_newdap" + shutdown + } +} diff --git a/unbrick-toolkit/OpenOCD/tools/memtest.tcl b/unbrick-toolkit/OpenOCD/tools/memtest.tcl new file mode 100644 index 0000000..f70f950 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/tools/memtest.tcl @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Algorithms by Michael Barr, released into public domain +# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser + +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] + +proc runAllMemTests { baseAddress nBytes } { + memTestDataBus $baseAddress + memTestAddressBus $baseAddress $nBytes + memTestDevice $baseAddress $nBytes +} + +#*********************************************************************************** +# * +# * Function: memTestDataBus() +# * +# * Description: Test the data bus wiring in a memory region by +# * performing a walking 1's test at a fixed address +# * within that region. The address (and hence the +# * memory region) is selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * Notes: +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first pattern that failed. +# * +#*********************************************************************************** +proc memTestDataBus { address } { + echo "Running memTestDataBus" + + for {set i 0} {$i < 32} {incr i} { + # Shift bit + set pattern [expr {1 << $i}] + + # Write pattern to memory + memwrite32 $address $pattern + + # Read pattern from memory + set data [memread32 $address] + + if {$data != $pattern} { + echo "FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data" + return $pattern + } + } +} + +#*********************************************************************************** +# * +# * Function: memTestAddressBus() +# * +# * Description: Perform a walking 1's test on the relevant bits +# * of the address and check for aliasing. This test +# * will find single-bit address failures such as stuck +# * -high, stuck-low, and shorted pins. The base address +# * and size of the region are selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * +# * Notes: For best results, the selected base address should +# * have enough LSB 0's to guarantee single address bit +# * changes. For example, to test a 64-Kbyte region, +# * select a base address on a 64-Kbyte boundary. Also, +# * select the region size as a power-of-two--if at all +# * possible. +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first address at which an +# * aliasing problem was uncovered. By examining the +# * contents of memory, it may be possible to gather +# * additional information about the problem. +# * +#*********************************************************************************** +proc memTestAddressBus { baseAddress nBytes } { + set addressMask [expr {$nBytes - 1}] + set pattern 0xAAAAAAAA + set antipattern 0x55555555 + + echo "Running memTestAddressBus" + + echo "addressMask: [convertToHex $addressMask]" + + echo "memTestAddressBus: Writing the default pattern at each of the power-of-two offsets..." + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}] } { + set addr [expr {$baseAddress + $offset}] + memwrite32 $addr $pattern + } + + echo "memTestAddressBus: Checking for address bits stuck high..." + memwrite32 $baseAddress $antipattern + + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + + if {$data != $pattern} { + echo "FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]" + return $pattern + } + } + + echo "memTestAddressBus: Checking for address bits stuck low or shorted..." + memwrite32 $baseAddress $pattern + for {set testOffset 32} {[expr {$testOffset & $addressMask}] != 0} {set testOffset [expr {$testOffset << 1}] } { + set addr [expr {$baseAddress + $testOffset}] + memwrite32 $addr $antipattern + + set data [memread32 $baseAddress] + if {$data != $pattern} { + echo "FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]" + return $pattern + } + + for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $baseAddress] + + if {(($data != $pattern) && ($offset != $testOffset))} { + echo "FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]" + return $pattern + } + } + set addr [expr {$baseAddress + $testOffset}] + memwrite32 $addr $pattern + } +} + +#*********************************************************************************** +# * +# * Function: memTestDevice() +# * +# * Description: Test the integrity of a physical memory device by +# * performing an increment/decrement test over the +# * entire region. In the process every storage bit +# * in the device is tested as zero and as one. The +# * base address and the size of the region are +# * selected by the caller. +# * Ported from: +# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C +# * Notes: +# * +# * Returns: Empty string if the test succeeds. +# * A non-zero result is the first address at which an +# * incorrect value was read back. By examining the +# * contents of memory, it may be possible to gather +# * additional information about the problem. +# * +#*********************************************************************************** +proc memTestDevice { baseAddress nBytes } { + echo "Running memTestDevice" + + echo "memTestDevice: Filling memory with a known pattern..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + memwrite32 [expr {$baseAddress + $offset}] $pattern + } + + echo "memTestDevice: Checking each location and inverting it for the second pass..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + + if {$data != $pattern} { + echo "FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]" + return $pattern + } + + set antiPattern [expr {~$pattern}] + memwrite32 [expr {$baseAddress + $offset}] $antiPattern + } + + echo "memTestDevice: Checking each location for the inverted pattern and zeroing it..." + for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} { + set antiPattern [expr {~$pattern & ((1<<32) - 1)}] + set addr [expr {$baseAddress + $offset}] + set data [memread32 $addr] + set dataHex [convertToHex $data] + set antiPatternHex [convertToHex $antiPattern] + if {$dataHex != $antiPatternHex} { + echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset" + return $pattern + } + } +} + +proc convertToHex { value } { + format 0x%08x $value +} diff --git a/unbrick-toolkit/OpenOCD/tools/test_cpu_speed.tcl b/unbrick-toolkit/OpenOCD/tools/test_cpu_speed.tcl new file mode 100644 index 0000000..f1a3fb3 --- /dev/null +++ b/unbrick-toolkit/OpenOCD/tools/test_cpu_speed.tcl @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Description: +# Measure the CPU clock frequency of an ARM Cortex-M based device. +# +# Return: +# The CPU clock frequency in Hz. A negative value indicates that the loop +# counter was saturated. +# +# Note: +# You may need to adapt the number of cycles for your device. +# +add_help_text cortex_m_test_cpu_speed "Measure the CPU clock frequency of an ARM Cortex-M based device" +add_usage_text cortex_m_test_cpu_speed {address [timeout [cycles_per_loop]]} +proc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } { + set loop_counter_start 0xffffffff + + halt + + # Backup registers and memory. + set backup_regs [get_reg -force {pc r0 xpsr}] + set backup_mem [read_memory $address 16 3] + + # We place the following code at the given address to measure the + # CPU clock frequency: + # + # 3801: subs r0, #1 + # d1fd: bne #-2 + # e7fe: b #-4 + write_memory $address 16 {0x3801 0xd1fd 0xe7fe} + + set_reg "pc $address r0 $loop_counter_start" + resume + sleep $timeout + halt + + # Get the loop counter value from register r0. + set loop_counter_end [dict values [get_reg r0]] + set loop_counter_diff [expr {$loop_counter_start - $loop_counter_end}] + + # Restore registers and memory. + set_reg $backup_regs + write_memory $address 16 $backup_mem + + if { [expr {$loop_counter_end == 0}] } { + return -1 + } + + return [expr {double($loop_counter_diff) * $cycles_per_loop / $timeout * 1000}] +} diff --git a/unbrick-toolkit/OpenOCD_recovery_Normal-log.txt b/unbrick-toolkit/OpenOCD_recovery_Normal-log.txt new file mode 100644 index 0000000..36dc4c3 --- /dev/null +++ b/unbrick-toolkit/OpenOCD_recovery_Normal-log.txt @@ -0,0 +1,74 @@ +UNBRICK SESSION: +--------------- + +> openocd -f interface/stlink.cfg -f target/dp32g030.cfg -c "reset halt" -c "uv_flash_bl boot3.bin" -c "uv_flash_fw TEST.bin" -c "shutdown" + +Open On-Chip Debugger 0.12.0 (2023-10-02) [https://github.com/sysprogs/openocd] +Licensed under GNU GPL v2 +libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'. +Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD +Info : clock speed 960 kHz +Info : STLINK V2J32S1 (API v2) VID:PID 0483:3748 +Info : Target voltage: 3.262151 +Info : [DP32G0xx.cpu] Cortex-M0 r0p0 processor detected +Info : [DP32G0xx.cpu] target has 4 breakpoints, 2 watchpoints +Info : starting gdb server for DP32G0xx.cpu on 3333 +Info : Listening on port 3333 for gdb connections +[DP32G0xx.cpu] halted due to debug-request, current mode: Thread +xPSR: 0xc1000000 pc: 0x000000d4 msp: 0x200015d8 + +Checking ROM masking +Erasing sector 0x0f = offset 0x0f00 +Region cleared OK +Erasing sector 0x1f = offset 0x1f00R=0xc3ff), Remaining 00 % +Region cleared OK +Writing at offset 0x1ffc (FLASH_ADDR=0xc7ff), Remaining 00 % +Checking ROM masking + +ROM masking is set to 0b100. Setting ON... +shutdown command invoked + +CPU reset: Transceiver should boot now. + +> + +___________________ +DUMP SESSION: +------------ + +>openocd -f interface/stlink.cfg -f target/dp32g030.cfg -c "reset halt" -c "uv_unmask_rom" -c "dump_image testFFFF.bin 0 0x10000" -c "shutdown" + +Open On-Chip Debugger 0.12.0 (2023-10-02) [https://github.com/sysprogs/openocd] +Licensed under GNU GPL v2 +libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'. +Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD +Info : clock speed 960 kHz +Info : STLINK V2J32S1 (API v2) VID:PID 0483:3748 +Info : Target voltage: 3.263745 +Info : [DP32G0xx.cpu] Cortex-M0 r0p0 processor detected +Info : [DP32G0xx.cpu] target has 4 breakpoints, 2 watchpoints +Info : starting gdb server for DP32G0xx.cpu on 3333 +Info : Listening on port 3333 for gdb connections +[DP32G0xx.cpu] halted due to debug-request, current mode: Thread +xPSR: 0xc0000000 pc: 0xaaaaaaaa msp: 0xaaaaaaa8 + +Checking ROM masking + +ROM masking is set to 0b110. Unsetting... +0x4 +dumped 65536 bytes in 1.074061s (59.587 KiB/s) +shutdown command invoked + +> + +_________________ +FIRMWARE ONLY: +------------- + +>openocd -f interface/stlink.cfg -f target/dp32g030.cfg -c "reset halt" -c "rom_mask_off" -c "reset halt" -c "uv_flash_fw fw.dec.bin" -c "shutdown" \ No newline at end of file diff --git a/unbrick-toolkit/UVK5_SWD_pinout.jpg b/unbrick-toolkit/UVK5_SWD_pinout.jpg new file mode 100644 index 0000000..fb8ff98 Binary files /dev/null and b/unbrick-toolkit/UVK5_SWD_pinout.jpg differ diff --git a/unbrick-toolkit/Unbrick-it.cmd b/unbrick-toolkit/Unbrick-it.cmd new file mode 100644 index 0000000..80b6d15 --- /dev/null +++ b/unbrick-toolkit/Unbrick-it.cmd @@ -0,0 +1,9 @@ +@REM Fires 1-handed unbricking command using cheap ST-Link v2 "baite" debug probe +@REM No need to solder. Just press the right wires on the right pads with your fingers. +@REM Restores bootloader 2.00.06 with factory firmware 2.01.27 +@ECHO ******** Launching 1 shot unbricking process with OpenOCD (STLink v2)... +@ECHO . +@CD OpenOCD +@openocd -f interface/stlink.cfg -f target/dp32g030.cfg -c "reset halt" -c "uv_flash_bl bootloader.bin" -c "uv_flash_fw k5_v2.01.27_fw.bin" -c "shutdown" +@PAUSE +