<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;"># Copyright 2023 Dual Tachyon
# https://github.com/DualTachyon
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

[PORTCON]
@ = 0x400B0000, 0x800

PORTA_SEL0 = 0x0000
&gt; A0, 0, 4
= GPIOA0, 0
= PWMP1_PLUS0, 1
= PWMP0_PLUS1, 2
= TM, 3
= WAKEUP0, 4

&gt; A1, 4, 4
= GPIOA1, 0
= XTAL_XI, 1

&gt; A2, 8, 4
= GPIOA2, 0
= XTAL_XO, 1

&gt; A3, 12, 4
= GPIOA3, 0
= CMP0_VN, 1
= XTAH_XI, 2

&gt; A4, 16, 4
= GPIOA4, 0
= CMP0_VP, 1
= XTAH_XO, 2

&gt; A5, 20, 4
= GPIOA5, 0
= UART1_CTS, 1
= PWMP1_PLUS1, 2
= TIMERP1_IN0, 3
= TIMERP1_OUT_L, 4
= WAKEUP1, 5
= SARADC_CH1, 6

&gt; A6, 24, 4
= GPIOA6, 0
= UART1_RTS, 1
= TIMERP1_IN1, 2
= TIMERP1_OUT_H, 3
= SARADC_CH1, 4
= OPA0_OUT, 5

&gt; A7, 28, 4
= GPIOA7, 0
= UART1_TX, 1
= TIMERP0_IN0, 2
= TIMERP0_OUT_L, 3
= SARADC_CH2, 4
= OPA0_VP, 5

PORTA_SEL1  = 0x0004
&gt; A8, 0, 4
= GPIOA8, 0
= UART1_RX, 1
= TIMERP0_IN1, 2
= TIMERP0_OUT_H, 3
= SARADC_CH3, 4
= OPA0_VN, 5

&gt; A9, 4, 4
= GPIOA9, 0
= SPI0_SSN, 1
= TIMERP1_IN0, 2
= TIMERP1_OUT_L, 3
= TM, 4
= SARADC_CH4, 5
= CMP1_VN, 6

&gt; A10, 8, 4
= GPIOA10, 0
= SPI0_CLK, 1
= SARADC_CH5, 2
= CMP1_VP, 3

&gt; A11, 12, 4
= GPIOA11, 0
= SPI0_MISO, 1
= PWMB0_CH0, 2
= PWMP0_BRAKE0, 3
= TIMERP1_IN1, 4
= TIMERP1_OUT_H, 5
= SARADC_CH6, 6

&gt; A12, 16, 4
= GPIOA12, 0
= SPI0_MOSI, 1
= PWMB0_CH1, 2
= PWMP0_CH0N, 3
= TIMERP0_IN0, 4
= TIMERP0_OUT_L, 5
= SARADC_CH7, 6

&gt; A13, 20, 4
= GPIOA13, 0
= PWMB0_CH2, 1
= PWMP0_CH1N, 2
= TIMERP0_IN1, 3
= TIMERP0_OUT_H, 4
= SARADC_CH8, 5

&gt; A14, 24, 4
= GPIOA14, 0
= PWMB1_CH0, 1
= PWMP0_CH2N, 2
= TIMERP1_IN0, 3
= TIMERP1_OUT_L, 4
= SARADC_CH9, 5

&gt; A15, 28, 4
= GPIOA15, 0
= PWMB1_CH1, 1
= PWMP0_CH0, 2
= TIMERP1_IN1, 3
= TIMERP1_OUT_H, 4

PORTB_SEL0 = 0x0008
&gt; B0, 0, 4
= GPIOB0, 0
= UART2_TX, 1
= IIC0_SCL, 2
= PWMB1_CH2, 3
= PWMP0_CH1, 4

&gt; B1, 4, 4
= GPIOB1, 0
= UART2_RX, 1
= IIC0_SDA, 2
= PWMP0_CH2, 3

&gt; B2, 8, 4
= GPIOB2, 0
= SPI1_SSN, 1
= PWMP0_BRAKE1, 2
= TIMERP1_HALL0, 3

&gt; B3, 12, 4
= GPIOB3, 0
= SPI1_CLK, 1
= IIC1_SDA, 2
= PWMP0_CH0N, 3
= TIMERP1_HALL1, 4

&gt; B4, 16, 4
= GPIOB4, 0
= SPI1_MISO, 1
= IIC1_SCL, 2
= PWMP1_CH0, 3
= PWMP0_CH1N, 4
= TIMERP1_HALL2, 5

&gt; B5, 20, 4
= GPIOB5, 0
= SPI1_MOSI, 1
= PWMP1_CH0N, 2
= PWMP0_CH2N, 3
= TIMERP0_IN0, 4
= TIMERP0_OUT_L, 5

&gt; B6, 24, 4
= GPIOB6, 0
= PWMP0_CH0, 1
= TIMERP0_IN1, 2
= TIMERP0_OUT_H, 3

&gt; B7, 28, 4
= GPIOB7, 0
= SPI0_SSN, 1
= UART0_TX, 2
= IIC0_SCL, 3
= PWMP1_BRAKE0, 4
= PWMP0_CH1, 5

PORTB_SEL1 = 0x000C
&gt; B8, 0, 4
= GPIOB8, 0
= SPI0_CLK, 1
= UART0_RX, 2
= IIC0_SDA, 3
= PWMB0_CH0, 4
= PWMP1_BRAKE1, 5
= PWMP0_CH2, 6

&gt; B9, 4, 4
= GPIOB9, 0
= SPI0_MISO, 1
= UART0_CTS, 2
= PWMB0_CH1, 3
= PWMP1_CH0, 4
= TIMERP1_IN1, 5
= TIMERP1_OUT_H, 6

&gt; B10, 8, 4
= GPIOB10, 0
= SPI0_MOSI, 1
= UART0_RTS, 2
= PWMB0_CH2, 3
= PWMP1_CH1, 4
= PWMP0_PLUS0, 5
= TIMERP1_IN0, 6
= TIMERP1_OUT_L, 7

&gt; B11, 12, 4
= GPIOB11, 0
= SWDIO, 1
= PWMP1_CH2, 2
= PWMP0_BRAKE2, 3

&gt; B12, 16, 4
= GPIOB12, 0
= UART1_TX, 1
= IIC1_SCL, 2
= PWMP1_CH0N, 3

&gt; B13, 20, 4
= GPIOB13, 0
= UART1_RX, 1
= IIC1_SDA, 2
= PWMP1_CH1N, 3

&gt; B14, 24, 4
= GPIOB14, 0
= SWCLK, 1
= UART2_TX, 2
= PWMP1_CH2N, 3

&gt; B15, 28, 4
= GPIOB15, 0
= SPI1_SSN, 1
= UART2_RX, 2

PORTC_SEL0 = 0x0010
&gt; C0, 0, 4
= GPIOC0, 0
= SPI1_CLK, 1
= UART2_CTS, 2
= PWMB1_CH0, 3

&gt; C1, 4, 4
= GPIOC1, 0
= SPI1_MISO, 1
= UART2_RTS, 2
= PWMB1_CH1, 3
= TIMERP0_IN0, 4
= TIMERP0_OUT_L, 5

&gt; C2, 8, 4
= GPIOC2, 0
= SPI1_MOSI, 1
= PWMB1_CH2, 2
= PWMP1_BRAKE2, 3
= TIMERP0_IN1, 4
= TIMERP0_OUT_H, 5

&gt; C3, 12, 4
= GPIOC3, 0
= UART0_TX, 1
= IIC0_SCL, 2
= PWMP1_CH1N, 3
= TIMERP0_HALL0, 4
= CMP2_VN, 5

&gt; C4, 16, 4
= GPIOC4, 0
= UART0_RX, 1
= IIC0_SDA, 2
= PWMP1_CH2N, 3
= TIMERP0_HALL1, 4
= CMP2_VP, 5

&gt; C5, 20, 4
= GPIOC5, 0
= TIMERP0_HALL2, 1
= TM, 2
= OPA1_VP, 3

&gt; C6, 24, 4
= GPIOC6, 0
= IIC1_SCL, 1
= PWMP1_CH1, 2
= TIMERP1_IN1, 3
= TIMERP1_OUT_H, 4
= OPA1_VN, 5

&gt; C7, 28, 4
= GPIOC7, 0
= IIC1_SDA, 1
= PWMP1_CH2, 2
= TIMERP1_IN0, 3
= TIMERP1_OUT_L, 4
= OPA1_OUT, 5

PORTA_IE = 0x0100
&gt; A0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; A1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; A2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; A3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; A4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; A5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; A6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; A7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; A8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; A9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; A10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; A11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; A12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; A13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; A14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; A15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTB_IE = 0x0104
&gt; B0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; B1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; B2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; B3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; B4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; B5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; B6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; B7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; B8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; B9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; B10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; B11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; B12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; B13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; B14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; B15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTC_IE = 0x0108
&gt; C0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; C1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; C2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; C3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; C4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; C5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; C6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; C7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; C8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; C9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; C10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; C11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; C12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; C13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; C14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; C15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTA_PU = 0x0200
&gt; A0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; A1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; A2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; A3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; A4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; A5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; A6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; A7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; A8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; A9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; A10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; A11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; A12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; A13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; A14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; A15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTB_PU = 0x0204
&gt; B0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; B1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; B2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; B3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; B4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; B5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; B6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; B7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; B8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; B9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; B10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; B11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; B12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; B13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; B14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; B15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTC_PU = 0x0208
&gt; C0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; C1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; C2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; C3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; C4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; C5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; C6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; C7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; C8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; C9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; C10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; C11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; C12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; C13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; C14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; C15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTA_PD = 0x0300
&gt; A0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; A1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; A2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; A3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; A4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; A5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; A6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; A7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; A8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; A9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; A10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; A11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; A12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; A13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; A14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; A15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTB_PD = 0x0304
&gt; B0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; B1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; B2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; B3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; B4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; B5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; B6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; B7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; B8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; B9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; B10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; B11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; B12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; B13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; B14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; B15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTC_PD = 0x0308
&gt; C0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; C1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; C2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; C3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; C4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; C5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; C6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; C7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; C8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; C9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; C10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; C11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; C12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; C13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; C14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; C15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTA_OD = 0x0400
&gt; A0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; A1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; A2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; A3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; A4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; A5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; A6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; A7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; A8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; A9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; A10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; A11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; A12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; A13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; A14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; A15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTB_OD = 0x0404
&gt; B0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; B1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; B2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; B3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; B4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; B5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; B6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; B7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; B8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; B9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; B10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; B11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; B12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; B13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; B14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; B15, 15, 1
= DISABLE, 0
= ENABLE, 1

PORTC_OD = 0x0408
&gt; C0, 0, 1
= DISABLE, 0
= ENABLE, 1

&gt; C1, 1, 1
= DISABLE, 0
= ENABLE, 1

&gt; C2, 2, 1
= DISABLE, 0
= ENABLE, 1

&gt; C3, 3, 1
= DISABLE, 0
= ENABLE, 1

&gt; C4, 4, 1
= DISABLE, 0
= ENABLE, 1

&gt; C5, 5, 1
= DISABLE, 0
= ENABLE, 1

&gt; C6, 6, 1
= DISABLE, 0
= ENABLE, 1

&gt; C7, 7, 1
= DISABLE, 0
= ENABLE, 1

&gt; C8, 8, 1
= DISABLE, 0
= ENABLE, 1

&gt; C9, 9, 1
= DISABLE, 0
= ENABLE, 1

&gt; C10, 10, 1
= DISABLE, 0
= ENABLE, 1

&gt; C11, 11, 1
= DISABLE, 0
= ENABLE, 1

&gt; C12, 12, 1
= DISABLE, 0
= ENABLE, 1

&gt; C13, 13, 1
= DISABLE, 0
= ENABLE, 1

&gt; C14, 14, 1
= DISABLE, 0
= ENABLE, 1

&gt; C15, 15, 1
= DISABLE, 0
= ENABLE, 1

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