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https://github.com/silenty4ng/uv-k5-firmware-chinese-lts
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93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/******************************************************************************
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* @file system_ARMCA9.c
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* @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series
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* @version V1.0.1
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* @date 13. February 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#include "irq_ctrl.h"
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#define SYSTEM_CLOCK 12000000U
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/*----------------------------------------------------------------------------
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System Core Clock Variable
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = SYSTEM_CLOCK;
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/*----------------------------------------------------------------------------
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System Core Clock update function
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void)
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{
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SystemCoreClock = SYSTEM_CLOCK;
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}
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/*----------------------------------------------------------------------------
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System Initialization
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*----------------------------------------------------------------------------*/
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void SystemInit (void)
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{
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/* do not use global variables because this function is called before
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reaching pre-main. RW section may be overwritten afterwards. */
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// Invalidate entire Unified TLB
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__set_TLBIALL(0);
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// Invalidate entire branch predictor array
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__set_BPIALL(0);
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__DSB();
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__ISB();
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// Invalidate instruction cache and flush branch target cache
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__set_ICIALLU(0);
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__DSB();
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__ISB();
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// Invalidate data cache
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L1C_InvalidateDCacheAll();
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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// Enable FPU
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__FPU_Enable();
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#endif
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// Create Translation Table
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MMU_CreateTranslationTable();
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// Enable MMU
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MMU_Enable();
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// Enable Caches
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L1C_EnableCaches();
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L1C_EnableBTAC();
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#if (__L2C_PRESENT == 1)
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// Enable GIC
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L2C_Enable();
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#endif
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// IRQ Initialize
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IRQ_Initialize();
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}
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