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uv-k5-firmware-chinese-lts/external/CMSIS_5/ARM.CMSIS.pdsc
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<?xml version="1.0" encoding="UTF-8"?>
<package schemaVersion="1.7.7" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.7/schema/PACK.xsd">
<name>CMSIS</name>
<description>CMSIS (Common Microcontroller Software Interface Standard)</description>
<vendor>ARM</vendor>
<!-- <license>license.txt</license> -->
<url>https://www.keil.com/pack/</url>
<releases>
<release version="5.9.1">
Active development ...
CMSIS-Core(M): 5.7.0
- Added new compiler macros.
CMSIS-DSP: Moved into separate pack!
CMSIS-NN: Moved into separate pack!
CMSIS-RTOS2: 2.2.0 (see revision history for details)
- RTX 5.7.0 (see revision history for details)
CMSIS-DAP: 2.1.2 (see revision history for details)
- Fix DAP_Transfer handling when transfer fails
</release>
<release version="5.9.0" date="2022-05-02">
CMSIS-Core(M): 5.6.0
- Arm Cortex-M85 cpu support
- Arm China STAR-MC1 cpu support
- Updated system_ARMCM55.c
CMSIS-DSP: 1.10.0 (see revision history for details)
CMSIS-NN: 3.1.0 (see revision history for details)
- Support for int16 convolution and fully connected for reference implementation
- Support for DSP extension optimization for int16 convolution and fully connected
- Support dilation for int8 convolution
- Support dilation for int8 depthwise convolution
- Support for int16 depthwise conv for reference implementation including dilation
- Support for int16 average and max pooling for reference implementation
- Support for elementwise add and mul int16 scalar version
- Support for softmax int16 scalar version
- Support for SVDF with 8 bit state tensor
CMSIS-RTOS2: 2.1.3 (unchanged)
- RTX 5.5.4 (see revision history for details)
CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack)
CMSIS-SVD: 1.3.9 (see revision history for details)
CMSIS-DAP: 2.1.1 (see revision history for details)
- Allow default clock frequency to use fast clock mode
Devices
- Support for Cortex-M85
Utilities
- SVDConv 3.3.42
- PackChk 1.3.95
</release>
<release version="5.8.0" date="2021-06-24">
CMSIS-Core(M): 5.5.0 (see revision history for details)
- Updated GCC LinkerDescription, GCC Assembler startup
- Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC
- Changed C-Startup to default Startup.
- Updated Armv8-M Assembler startup to use GAS syntax
Note: Updating existing projects may need manual user interaction!
CMSIS-Core(A): 1.2.1 (see revision history for details)
- Bugfixes for Cortex-A32
CMSIS-DAP: 2.1.0 (see revision history for details)
- Enhanced DAP_Info
- Added extra UART support
CMSIS-DSP: 1.9.0 (see revision history for details)
- Purged pre-built libs from Git
- Enhanced support for f16 datatype
- Fixed couple of GCC issues
CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0)
- Major interface change for functions compatible with TensorFlow Lite for Microcontroller
- Added optimization for SVDF kernel
- Improved MVE performance for fully Connected and max pool operator
- NULL bias support for fully connected operator in non-MVE case(Can affect performance)
- Expanded existing unit test suite along with support for FVP
- Removed Examples folder
CMSIS-RTOS2:
- RTX 5.5.3 (see revision history for details)
- CVE-2021-27431 vulnerability mitigation.
- Enhanced stack overrun checking.
- Various bug fixes and improvements.
CMSIS-Pack: 1.7.2 (see revision history for details)
- Support for Microchip XC32 compiler
- Support for Custom Datapath Extension
</release>
<release version="5.7.0" date="2020-04-09">
CMSIS-Build: 0.9.0 (beta)
- Draft for CMSIS Project description (CPRJ)
CMSIS-Core(M): 5.4.0 (see revision history for details)
- Cortex-M55 cpu support
- Enhanced MVE support for Armv8.1-MML
- Fixed device config define checks.
- L1 Cache functions for Armv7-M and later
CMSIS-Core(A): 1.2.0 (see revision history for details)
- Fixed GIC_SetPendingIRQ to use GICD_SGIR
- Added missing DSP intrinsics
- Reworked assembly intrinsics: volatile, barriers and clobber
CMSIS-DSP: 1.8.0 (see revision history for details)
- Added new functions and function groups
- Added MVE support
CMSIS-NN: 1.3.0 (see revision history for details)
- Added MVE support
- Further optimizations for kernels using DSP extension
CMSIS-RTOS2:
- RTX 5.5.2 (see revision history for details)
CMSIS-Driver: 2.8.0
- Added VIO API 0.1.0 (Preview)
- removed volatile from status related typedefs in APIs
- enhanced WiFi Interface API with support for polling Socket Receive/Send
CMSIS-Pack: 1.6.3 (see revision history for details)
- deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema.
Devices:
- ARMCM55 device
- ARMv81MML startup code recognizing __MVE_USED macro
- Refactored vector table references for all Cortex-M devices
- Reworked ARMCM* C-StartUp files.
- Include L1 Cache functions in ARMv8MML/ARMv81MML devices
Utilities:
Attention: Linux binaries moved to Linux64 folder!
- SVDConv 3.3.35
- PackChk 1.3.89
</release>
<release version="5.6.0" date="2019-07-10">
CMSIS-Core(M): 5.3.0 (see revision history for details)
- Added provisions for compiler-independent C startup code.
CMSIS-Core(A): 1.1.4 (see revision history for details)
- Fixed __FPU_Enable.
CMSIS-DSP: 1.7.0 (see revision history for details)
- New Neon versions of f32 functions
- Python wrapper
- Preliminary cmake build
- Compilation flags for FFTs
- Changes to arm_math.h
CMSIS-NN: 1.2.0 (see revision history for details)
- New function for depthwise convolution with asymmetric quantization.
- New support functions for requantization.
CMSIS-RTOS:
- RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+)
CMSIS-RTOS2:
- RTX 5.5.1 (see revision history for details)
CMSIS-Driver: 2.7.1
- WiFi Interface API 1.0.0
Devices:
- Generalized C startup code for all Cortex-M family devices.
- Updated Cortex-A default memory regions and MMU configurations
- Moved Cortex-A memory and system config files to avoid include path issues
</release>
<release version="5.5.1" date="2019-03-20">
The following folders are deprecated
- CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)
CMSIS-Core(M): 5.2.1 (see revision history for details)
- Fixed compilation issue in cmsis_armclang_ltm.h
</release>
<release version="5.5.0" date="2019-03-18">
The following folders have been removed:
- CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/)
- CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/)
The following folders are deprecated
- CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)
CMSIS-Core(M): 5.2.0 (see revision history for details)
- Reworked Stack/Heap configuration for ARM startup files.
- Added Cortex-M35P device support.
- Added generic Armv8.1-M Mainline device support.
CMSIS-Core(A): 1.1.3 (see revision history for details)
CMSIS-DSP: 1.6.0 (see revision history for details)
- reworked DSP library source files
- reworked DSP library documentation
- Changed DSP folder structure
- moved DSP libraries to folder ./DSP/Lib
- ARM DSP Libraries are built with ARMCLANG
- Added DSP Libraries Source variant
CMSIS-RTOS2:
- RTX 5.5.0 (see revision history for details)
CMSIS-Driver: 2.7.0
- Added WiFi Interface API 1.0.0-beta
- Added components for project specific driver implementations
CMSIS-Pack: 1.6.0 (see revision history for details)
Devices:
- Added Cortex-M35P and ARMv81MML device templates.
- Fixed C-Startup Code for GCC (aligned with other compilers)
Utilities:
- SVDConv 3.3.25
- PackChk 1.3.82
</release>
<release version="5.4.0" date="2018-08-01">
Aligned pack structure with repository.
The following folders are deprecated:
- CMSIS/Include/
- CMSIS/DSP_Lib/
CMSIS-Core(M): 5.1.2 (see revision history for details)
- Added Cortex-M1 support (beta).
CMSIS-Core(A): 1.1.2 (see revision history for details)
CMSIS-NN: 1.1.0
- Added new math functions.
CMSIS-RTOS2:
- API 2.1.3 (see revision history for details)
- RTX 5.4.0 (see revision history for details)
* Updated exception handling on Cortex-A
CMSIS-Driver:
- Flash Driver API V2.2.0
Utilities:
- SVDConv 3.3.21
- PackChk 1.3.71
</release>
<release version="5.3.0" date="2018-02-22">
Updated Arm company brand.
CMSIS-Core(M): 5.1.1 (see revision history for details)
CMSIS-Core(A): 1.1.1 (see revision history for details)
CMSIS-DAP: 2.0.0 (see revision history for details)
CMSIS-NN: 1.0.0
- Initial contribution of the bare metal Neural Network Library.
CMSIS-RTOS2:
- RTX 5.3.0 (see revision history for details)
- OS Tick API 1.0.1
</release>
<release version="5.2.0" date="2017-11-16">
CMSIS-Core(M): 5.1.0 (see revision history for details)
- Added MPU Functions for ARMv8-M for Cortex-M23/M33.
- Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
CMSIS-Core(A): 1.1.0 (see revision history for details)
- Added compiler_iccarm.h.
- Added additional access functions for physical timer.
CMSIS-DAP: 1.2.0 (see revision history for details)
CMSIS-DSP: 1.5.2 (see revision history for details)
CMSIS-Driver: 2.6.0 (see revision history for details)
- CAN Driver API V1.2.0
- NAND Driver API V2.3.0
CMSIS-RTOS:
- RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
CMSIS-RTOS2:
- API 2.1.2 (see revision history for details)
- RTX 5.2.3 (see revision history for details)
Devices:
- Added GCC startup and linker script for Cortex-A9.
- Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
- Added IAR startup code for Cortex-A9
</release>
<release version="5.1.1" date="2017-09-19">
CMSIS-RTOS2:
- RTX 5.2.1 (see revision history for details)
</release>
<release version="5.1.0" date="2017-08-04">
CMSIS-Core(M): 5.0.2 (see revision history for details)
- Changed Version Control macros to be core agnostic.
- Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
CMSIS-Core(A): 1.0.0 (see revision history for details)
- Initial release
- IRQ Controller API 1.0.0
CMSIS-Driver: 2.05 (see revision history for details)
- All typedefs related to status have been made volatile.
CMSIS-RTOS2:
- API 2.1.1 (see revision history for details)
- RTX 5.2.0 (see revision history for details)
- OS Tick API 1.0.0
CMSIS-DSP: 1.5.2 (see revision history for details)
- Fixed GNU Compiler specific diagnostics.
CMSIS-Pack: 1.5.0 (see revision history for details)
- added System Description File (*.SDF) Format
CMSIS-Zone: 0.0.1 (Preview)
- Initial specification draft
</release>
<release version="5.0.1" date="2017-02-03">
Package Description:
- added taxonomy for Cclass RTOS
CMSIS-RTOS2:
- API 2.1 (see revision history for details)
- RTX 5.1.0 (see revision history for details)
CMSIS-Core: 5.0.1 (see revision history for details)
- Added __PACKED_STRUCT macro
- Added uVisior support
- Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
- Updated template for secure main function (main_s.c)
- Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
CMSIS-DSP: 1.5.1 (see revision history for details)
- added ARMv8M DSP libraries.
CMSIS-Pack:1.4.9 (see revision history for details)
- added Pack Index File specification and schema file
</release>
<release version="5.0.0" date="2016-11-11">
Changed open source license to Apache 2.0
CMSIS_Core:
- Added support for Cortex-M23 and Cortex-M33.
- Added ARMv8-M device configurations for mainline and baseline.
- Added CMSE support and thread context management for TrustZone for ARMv8-M
- Added cmsis_compiler.h to unify compiler behaviour.
- Updated function SCB_EnableICache (for Cortex-M7).
- Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
CMSIS-RTOS:
- bug fix in RTX 4.82 (see revision history for details)
CMSIS-RTOS2:
- new API including compatibility layer to CMSIS-RTOS
- reference implementation based on RTX5
- supports all Cortex-M variants including TrustZone for ARMv8-M
CMSIS-SVD:
- reworked SVD format documentation
- removed SVD file database documentation as SVD files are distributed in packs
- updated SVDConv for Win32 and Linux
CMSIS-DSP:
- Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
- Added DSP libraries build projects to CMSIS pack.
</release>
<release version="4.5.0" date="2015-10-28">
- CMSIS-Core 4.30.0 (see revision history for details)
- CMSIS-DAP 1.1.0 (unchanged)
- CMSIS-Driver 2.04.0 (see revision history for details)
- CMSIS-DSP 1.4.7 (no source code change [still labeled 1.4.5], see revision history for details)
- CMSIS-Pack 1.4.1 (see revision history for details)
- CMSIS-RTOS 4.80.0 Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
- CMSIS-SVD 1.3.1 (see revision history for details)
</release>
<release version="4.4.0" date="2015-09-11">
- CMSIS-Core 4.20 (see revision history for details)
- CMSIS-DSP 1.4.6 (no source code change [still labeled 1.4.5], see revision history for details)
- CMSIS-Pack 1.4.0 (adding memory attributes, algorithm style)
- CMSIS-Driver 2.03.0 (adding CAN [Controller Area Network] API)
- CMSIS-RTOS
-- API 1.02 (unchanged)
-- RTX 4.79 (see revision history for details)
- CMSIS-SVD 1.3.0 (see revision history for details)
- CMSIS-DAP 1.1.0 (extended with SWO support)
</release>
<release version="4.3.0" date="2015-03-20">
- CMSIS-Core 4.10 (Cortex-M7 extended Cache Maintenance functions)
- CMSIS-DSP 1.4.5 (see revision history for details)
- CMSIS-Driver 2.02 (adding SAI (Serial Audio Interface) API)
- CMSIS-Pack 1.3.3 (Semantic Versioning, Generator extensions)
- CMSIS-RTOS
-- API 1.02 (unchanged)
-- RTX 4.78 (see revision history for details)
- CMSIS-SVD 1.2 (unchanged)
</release>
<release version="4.2.0" date="2014-09-24">
Adding Cortex-M7 support
- CMSIS-Core 4.00 (Cortex-M7 support, corrected C++ include guards in core header files)
- CMSIS-DSP 1.4.4 (Cortex-M7 support and corrected out of bound issues)
- CMSIS-Pack 1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
- CMSIS-SVD 1.2 (Cortex-M7 extensions)
- CMSIS-RTOS RTX 4.75 (see revision history for details)
</release>
<release version="4.1.1" date="2014-06-30">
- fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
</release>
<release version="4.1.0" date="2014-06-12">
- CMSIS-Driver 2.02 (incompatible update)
- CMSIS-Pack 1.3 (see revision history for details)
- CMSIS-DSP 1.4.2 (unchanged)
- CMSIS-Core 3.30 (unchanged)
- CMSIS-RTOS RTX 4.74 (unchanged)
- CMSIS-RTOS API 1.02 (unchanged)
- CMSIS-SVD 1.10 (unchanged)
PACK:
- removed G++ specific files from PACK
- added Component Startup variant "C Startup"
- added Pack Checking Utility
- updated conditions to reflect tool-chain dependency
- added Taxonomy for Graphics
- updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
</release>
<!-- release version="4.0.0">
- CMSIS-Driver 2.00 Preliminary (incompatible update)
- CMSIS-Pack 1.1 Preliminary
- CMSIS-DSP 1.4.2 (see revision history for details)
- CMSIS-Core 3.30 (see revision history for details)
- CMSIS-RTOS RTX 4.74 (see revision history for details)
- CMSIS-RTOS API 1.02 (unchanged)
- CMSIS-SVD 1.10 (unchanged)
</release -->
<release version="3.20.4" date="2014-02-20">
- CMSIS-RTOS 4.74 (see revision history for details)
- PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
</release>
<!-- release version="3.20.3">
- CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
- CMSIS-RTOS 4.73 (see revision history for details)
</release -->
<!-- release version="3.20.2">
- CMSIS-Pack documentation has been added
- CMSIS-Drivers header and documentation have been added to PACK
- CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
</release -->
<!-- release version="3.20.1">
- CMSIS-RTOS Keil RTX V4.72 has been added to PACK
- CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
</release -->
<!-- release version="3.20.0">
The software portions that are deployed in the application program are now under a BSD license which allows usage
of CMSIS components in any commercial or open source projects. The Pack Description file Arm.CMSIS.pdsc describes the use cases
The individual components have been update as listed below:
- CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
- CMSIS-DSP library is optimized for more performance and contains several bug fixes.
- CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
- CMSIS-SVD is unchanged.
</release -->
</releases>
<taxonomy>
<description Cclass="Audio">Software components for audio processing</description>
<description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
<description Cclass="Board Part">Drivers that support an external component available on an evaluation board</description>
<description Cclass="Compiler">Compiler Software Extensions</description>
<description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
<description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
<description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
<description Cclass="Data Exchange">Data exchange or data formatter</description>
<description Cclass="Extension Board">Drivers that support an extension board or shield</description>
<description Cclass="File System">File Drive Support and File System</description>
<description Cclass="IoT Client">IoT cloud client connector</description>
<description Cclass="IoT Service">IoT specific services</description>
<description Cclass="IoT Utility">IoT specific software utility</description>
<description Cclass="Graphics">Graphical User Interface</description>
<description Cclass="Network">Network Stack using Internet Protocols</description>
<description Cclass="RTOS">Real-time Operating System</description>
<description Cclass="Security">Encryption for secure communication or storage</description>
<description Cclass="USB">Universal Serial Bus Stack</description>
<description Cclass="Utility">Generic software utility components</description>
</taxonomy>
<devices>
<!-- ****************************** Cortex-M0 ****************************** -->
<family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui0497" title="Cortex-M0 Processor Devices Generic Users Guide"/>
<description>
The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM0">
<processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
</device>
</family>
<!-- ****************************** Cortex-M0P ****************************** -->
<family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui0662" title="Cortex-M0+ Processor Devices Generic Users Guide"/>
<description>
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM0P">
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
</device>
<device Dname="ARMCM0P_MPU">
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
</device>
</family>
<!-- ****************************** Cortex-M1 ****************************** -->
<family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
<!--book name="https://developer.arm.com/documentation/dui0497" title="Cortex-M0 Processor Devices Generic Users Guide"/-->
<description>
The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM1">
<processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
</device>
</family>
<!-- ****************************** Cortex-M3 ****************************** -->
<family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui0552" title="Cortex-M3 Processor Devices Generic Users Guide"/>
<description>
The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM3">
<processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
</device>
</family>
<!-- ****************************** Cortex-M4 ****************************** -->
<family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui0553" title="Cortex-M4 Processor Devices Generic Users Guide"/>
<description>
The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM4">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM4/Include/ARMCM4.h" define="ARMCM4"/>
</device>
<device Dname="ARMCM4_FP">
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
</device>
</family>
<!-- ****************************** Cortex-M7 ****************************** -->
<family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui0646" title="Cortex-M7 Processor Devices Generic Users Guide"/>
<description>
The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
- upward compatibility with the rest of the Cortex-M processor family.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM7">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
</device>
<device Dname="ARMCM7_SP">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
</device>
<device Dname="ARMCM7_DP">
<processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
</device>
</family>
<!-- ****************************** Cortex-M23 ********************** -->
<family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/dui1095" title="Cortex-M23 Processor Devices Generic Users Guide"/>
<description>
The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM23">
<processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
</device>
<device Dname="ARMCM23_TZ">
<processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
</device>
</family>
<!-- ****************************** Cortex-M33 ****************************** -->
<family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/100235" title="Cortex-M33 Processor Devices Generic Users Guide"/>
<description>
The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM33">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
</device>
<device Dname="ARMCM33_TZ">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
</device>
<device Dname="ARMCM33_DSP_FP">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
</device>
<device Dname="ARMCM33_DSP_FP_TZ">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
</device>
</family>
<!-- ****************************** Cortex-M35P ****************************** -->
<family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
<!--book name="Device/ARM/Documents/??_dgug.pdf" title="?? Device Generic Users Guide"/-->
<description>
The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM35P">
<processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
</device>
<device Dname="ARMCM35P_TZ">
<processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
</device>
<device Dname="ARMCM35P_DSP_FP">
<processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, no TrustZone
</description>
<compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
</device>
<device Dname="ARMCM35P_DSP_FP_TZ">
<processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
</device>
</family>
<!-- ****************************** Cortex-M55 ****************************** -->
<family Dfamily="ARM Cortex M55" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/101273" title="Cortex-M55 Processor Devices Generic Users Guide"/>
<description>
The Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology.
It is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance.
The Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM55.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x10000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00000000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x30000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20000000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM55">
<processor Dcore="Cortex-M55" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMCM55/Include/ARMCM55.h" define="ARMCM55"/>
</device>
</family>
<!-- ****************************** Cortex-M85 ****************************** -->
<family Dfamily="ARM Cortex M85" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/1019283" title="Cortex-M85 Processor Devices Generic Users Guide"/>
<description>
The Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE).
The processor also supports previous Armv8-M architectural features.
The design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning.
The Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption.
</description>
<!-- debug svd="Device/ARM/SVD/ARMCM85.svd"/ SVD files do not contain any peripheral -->
<memory name="ROM_NS" access="rxn" start="0x00000000" size="0x00200000" startup="1" default="1" alias="ROM_S"/>
<memory name="RAM_NS" access="rwxn" start="0x20000000" size="0x00020000" init ="0" default="1" alias="RAM_S"/>
<memory name="ROM_S" access="rxn" start="0x10000000" size="0x00200000" startup="1" default="1"/>
<memory name="RAM_S" access="rwxn" start="0x30000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMCM85">
<processor Dcore="Cortex-M85" DcoreVersion="r0p0" Dpacbti="PACBTI" Dmpu="MPU" Dfpu="DP_FPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI
</description>
<compile header="Device/ARM/ARMCM85/Include/ARMCM85.h" define="ARMCM85"/>
</device>
</family>
<!-- ****************************** ARMSC000 ****************************** -->
<family Dfamily="ARM SC000" Dvendor="ARM:82">
<description>
The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMSC000">
<processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
</device>
</family>
<!-- ****************************** ARMSC300 ****************************** -->
<family Dfamily="ARM SC300" Dvendor="ARM:82">
<description>
The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
- simple, easy-to-use programmers model
- highly efficient ultra-low power operation
- excellent code density
- deterministic, high-performance interrupt handling
</description>
<!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMSC300">
<processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
</device>
</family>
<!-- ****************************** ARMv8-M Baseline ********************** -->
<family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/ddi0553" title="Armv8-M Architecture Reference Manual"/>
<description>
Armv8-M Baseline based device with TrustZone
</description>
<!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMv8MBL">
<processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
</device>
</family>
<!-- ****************************** ARMv8-M Mainline ****************************** -->
<family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/ddi0553" title="Armv8-M Architecture Reference Manual"/>
<description>
Armv8-M Mainline based device with TrustZone
</description>
<!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
<memory id="IROM1" start="0x00000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00200000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x20000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20200000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMv8MML">
<processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
</device>
<device Dname="ARMv8MML_DSP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, no Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
</device>
<device Dname="ARMv8MML_SP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
</device>
<device Dname="ARMv8MML_DSP_SP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Single Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
</device>
<device Dname="ARMv8MML_DP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
no DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
</device>
<device Dname="ARMv8MML_DSP_DP">
<processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
</device>
</family>
<!-- ****************************** ARMv8.1-M Mainline ****************************** -->
<family Dfamily="ARMv8.1-M Mainline" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/ddi0553" title="Armv8-M Architecture Reference Manual"/>
<description>
Armv8.1-M Mainline based device with TrustZone and MVE
</description>
<!-- <debug svd="Device/ARM/SVD/ARMv8MML.svd"/> -->
<memory id="IROM1" start="0x10000000" size="0x00200000" startup="1" default="1"/>
<memory id="IROM2" start="0x00000000" size="0x00200000" startup="0" default="0"/>
<memory id="IRAM1" start="0x30000000" size="0x00020000" init ="0" default="1"/>
<memory id="IRAM2" start="0x20000000" size="0x00020000" init ="0" default="0"/>
<!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000" default="1"/-->
<device Dname="ARMv81MML_DSP_DP_MVE_FP">
<processor Dcore="ARMV81MML" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
<description>
Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone
</description>
<compile header="Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h" define="ARMv81MML_DSP_DP_MVE_FP"/>
</device>
</family>
<!-- ****************************** Cortex-A5 ****************************** -->
<family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/ddi0433" title="Cortex-A5 Technical Reference Manual"/>
<description>
The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
</description>
<memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR -->
<memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR -->
<memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM -->
<memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM -->
<device Dname="ARMCA5">
<processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
</device>
</family>
<!-- ****************************** Cortex-A7 ****************************** -->
<family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/ddi0464" title="Cortex-A7 MPCore Technical Reference Manual"/>
<description>
The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
an optional integrated GIC, and an optional L2 cache controller.
</description>
<memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR -->
<memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR -->
<memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM -->
<memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM -->
<device Dname="ARMCA7">
<processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
</device>
</family>
<!-- ****************************** Cortex-A9 ****************************** -->
<family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
<book name="https://developer.arm.com/documentation/100511" title="Cortex-A9 Technical Reference Manual"/>
<description>
The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
and 8-bit Java bytecodes in Jazelle state.
</description>
<memory id="IROM1" start="0x00000000" size="0x04000000" startup="1" default="1"/> <!-- 64MB NOR -->
<memory id="IROM2" start="0x0C000000" size="0x04000000" startup="0" default="0"/> <!-- 64MB NOR -->
<memory id="IRAM1" start="0x14000000" size="0x02000000" init ="0" default="1"/> <!-- 32MB SRAM -->
<memory id="IRAM2" start="0x80000000" size="0x40000000" init ="0" default="0"/> <!-- 1GB DRAM -->
<device Dname="ARMCA9">
<processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="12000000"/>
<compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
</device>
</family>
</devices>
<apis>
<!-- CMSIS Device API -->
<api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
<description>Device interrupt controller interface</description>
<files>
<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
</files>
</api>
<api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
<description>RTOS Kernel system tick timer interface</description>
<files>
<file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
</files>
</api>
<!-- CMSIS-RTOS API -->
<api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
<description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
<files>
<file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
</files>
</api>
<api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.2.0" exclusive="1">
<description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
<files>
<file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
<file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
</files>
</api>
<!-- CMSIS Driver API -->
<api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.4.0" exclusive="0">
<description>USART Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.3.0" exclusive="0">
<description>SPI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.2.0" exclusive="0">
<description>SAI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.4.0" exclusive="0">
<description>I2C Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.3.0" exclusive="0">
<description>CAN Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
<file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.3.0" exclusive="0">
<description>Flash Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.4.0" exclusive="0">
<description>MCI Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.4.0" exclusive="0">
<description>NAND Flash Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.2.0" exclusive="0">
<description>Ethernet MAC and PHY Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.2.0" exclusive="0">
<description>Ethernet MAC Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.2.0" exclusive="0">
<description>Ethernet PHY Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.3.0" exclusive="0">
<description>USB Device Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.3.0" exclusive="0">
<description>USB Host Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="WiFi" Capiversion="1.1.0" exclusive="0">
<description>WiFi driver</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__wifi__interface__gr.html" />
<file category="header" name="CMSIS/Driver/Include/Driver_WiFi.h" />
</files>
</api>
<api Cclass="CMSIS Driver" Cgroup="VIO" Capiversion="0.1.0" exclusive="1">
<description>Virtual I/O</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__vio__interface__gr.html" />
<file category="header" name="CMSIS/Driver/VIO/Include/cmsis_vio.h" />
<file category="other" name="CMSIS/Driver/VIO/cmsis_vio.scvd" />
</files>
</api>
</apis>
<!-- conditions are dependency rules that can apply to a component or an individual file -->
<conditions>
<!-- compiler -->
<condition id="ARMCC6">
<accept Tcompiler="ARMCC" Toptions="AC6"/>
<accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
</condition>
<condition id="ARMCC5">
<require Tcompiler="ARMCC" Toptions="AC5"/>
</condition>
<condition id="ARMCC">
<require Tcompiler="ARMCC"/>
</condition>
<condition id="GCC">
<require Tcompiler="GCC"/>
</condition>
<condition id="IAR">
<require Tcompiler="IAR"/>
</condition>
<condition id="ARMCC GCC">
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
</condition>
<condition id="ARMCC GCC IAR">
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<!-- Arm architecture -->
<condition id="ARMv6-M Device">
<description>Armv6-M architecture based device</description>
<accept Dcore="Cortex-M0"/>
<accept Dcore="Cortex-M1"/>
<accept Dcore="Cortex-M0+"/>
<accept Dcore="SC000"/>
</condition>
<condition id="ARMv7-M Device">
<description>Armv7-M architecture based device</description>
<accept Dcore="Cortex-M3"/>
<accept Dcore="Cortex-M4"/>
<accept Dcore="Cortex-M7"/>
<accept Dcore="SC300"/>
</condition>
<condition id="ARMv8-MBL Device">
<description>Armv8-M base line architecture based device</description>
<accept Dcore="ARMV8MBL"/>
<accept Dcore="Cortex-M23"/>
</condition>
<condition id="ARMv8-MML Device">
<description>Armv8-M main line architecture based device</description>
<accept Dcore="ARMV8MML"/>
<accept Dcore="Cortex-M33"/>
<accept Dcore="Cortex-M35P"/>
<accept Dcore="Star-MC1"/>
</condition>
<condition id="ARMv81-MML Device">
<description>Armv8.1-M main line architecture based device</description>
<accept Dcore="ARMV81MML"/>
<accept Dcore="Cortex-M55"/>
<accept Dcore="Cortex-M85"/>
</condition>
<condition id="ARMv8x-MML Device">
<description>Armv8-M/Armv8.1-M architecture based device</description>
<accept condition="ARMv8-MML Device"/>
<accept condition="ARMv81-MML Device"/>
</condition>
<condition id="ARMv8-M Device">
<description>Armv8-M architecture based device</description>
<accept condition="ARMv8-MBL Device"/>
<accept condition="ARMv8-MML Device"/>
<accept condition="ARMv81-MML Device"/>
</condition>
<condition id="ARMv6_7-M Device">
<description>Armv6_7-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
</condition>
<condition id="ARMv6_7_8-M Device">
<description>Armv6_7_8-M architecture based device</description>
<accept condition="ARMv6-M Device"/>
<accept condition="ARMv7-M Device"/>
<accept condition="ARMv8-M Device"/>
</condition>
<condition id="ARMv7-A Device">
<description>Armv7-A architecture based device</description>
<accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A7"/>
<accept Dcore="Cortex-A9"/>
</condition>
<condition id="No TrustZone">
<description>No TrustZone</description>
<require Dtz="NO_TZ"/>
</condition>
<condition id="TrustZone">
<description>TrustZone</description>
<require Dtz="TZ"/>
</condition>
<condition id="TZ Disabled">
<description>TrustZone (Disabled)</description>
<require Dtz="TZ"/>
<require Dsecure="TZ-disabled"/>
</condition>
<condition id="TZ Secure">
<description>TrustZone (Secure)</description>
<require Dtz="TZ"/>
<require Dsecure="Secure"/>
</condition>
<condition id="TZ Non-secure">
<description>TrustZone (Non-secure)</description>
<require Dtz="TZ"/>
<require Dsecure="Non-secure"/>
</condition>
<condition id="ARMv8-M Device without TrustZone">
<description>Armv8-M architecture based device without TrustZone</description>
<require condition="ARMv8-M Device"/>
<require condition="No TrustZone"/>
</condition>
<condition id="ARMv8-M Device with TZ Disabled">
<description>Armv8-M architecture based device with TrustZone (Disabled)</description>
<require condition="ARMv8-M Device"/>
<require condition="TZ Disabled"/>
</condition>
<condition id="ARMv8-M Device with TZ Secure">
<description>Armv8-M architecture based device with TrustZone (Secure)</description>
<require condition="ARMv8-M Device"/>
<require condition="TZ Secure"/>
</condition>
<condition id="ARMv8-M Device with TZ Non-secure">
<description>Armv8-M architecture based device with TrustZone (Non-secure)</description>
<require condition="ARMv8-M Device"/>
<require condition="TZ Non-secure"/>
</condition>
<!-- Startup -->
<condition id="Startup ARMCC6 Secure">
<description>Startup files for Arm Compiler 6 targeting TrustZone secure mode</description>
<require condition="ARMCC6"/>
<require condition="TZ Secure"/>
</condition>
<condition id="Startup ARMCC6 Unsecure">
<description>Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode</description>
<require condition="ARMCC6"/>
<deny condition="TZ Secure"/>
</condition>
<!-- CMSIS-Core -->
<condition id="ARMCM0 CMSIS">
<description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM0+ CMSIS">
<description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM0P*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM1 CMSIS">
<description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM1"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM3 CMSIS">
<description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM3"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM4 CMSIS">
<description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM4*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM7 CMSIS">
<description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM7*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM23 CMSIS">
<description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM23*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM33 CMSIS">
<description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM33*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM35P CMSIS">
<description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM35P*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM55 CMSIS">
<description>Generic Arm Cortex-M55 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM55*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCM85 CMSIS">
<description>Generic Arm Cortex-M85 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCM85*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC000 CMSIS">
<description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC000"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMSC300 CMSIS">
<description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMSC300"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMv8MBL CMSIS">
<description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMv8MBL"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMv8MML CMSIS">
<description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMv8MML*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMv81MML CMSIS">
<description>Generic Armv8.1-M Mainline device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMv81MML*"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA5 CMSIS">
<description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA5"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA7 CMSIS">
<description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA7"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<condition id="ARMCA9 CMSIS">
<description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA9"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
</condition>
<!-- RTOS RTX -->
<condition id="RTOS RTX">
<description>Components required for RTOS RTX</description>
<require condition="ARMv6_7-M Device"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="Device" Cgroup="Startup"/>
<deny Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/>
</condition>
<condition id="RTOS RTX IFX">
<description>Components required for RTOS RTX IFX</description>
<require condition="ARMv6_7-M Device"/>
<require condition="ARMCC GCC IAR"/>
<require Dvendor="Infineon:7" Dname="XMC4*"/>
<require Cclass="Device" Cgroup="Startup"/>
<deny Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/>
</condition>
<condition id="RTOS RTX5">
<description>Components required for RTOS RTX5</description>
<require condition="ARMv6_7_8-M Device"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5"/>
</condition>
<condition id="RTOS2 RTX5">
<description>Components required for RTOS2 RTX5</description>
<accept condition="ARMv6_7-M Device"/>
<accept condition="ARMv8-M Device without TrustZone"/>
<accept condition="ARMv8-M Device with TZ Disabled"/>
<accept condition="ARMv8-M Device with TZ Secure"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
<require Cclass="Device" Cgroup="Startup"/>
</condition>
<condition id="RTOS2 RTX5 v7-A">
<description>Components required for RTOS2 RTX5 on Armv7-A</description>
<require condition="ARMv7-A Device"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
<require Cclass="Device" Cgroup="Startup"/>
<require Cclass="Device" Cgroup="OS Tick"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
<condition id="RTOS2 RTX5 NS">
<description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
<require condition="ARMv8-M Device with TZ Non-secure"/>
<require condition="ARMCC GCC IAR"/>
<require Cclass="CMSIS" Cgroup="CORE"/>
<require Cclass="Device" Cgroup="Startup"/>
</condition>
<condition id="ARMCC ARMv6-M LE">
<description>Arm Compiler for Armv6-M architecture (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMCC ARMv6-M BE">
<description>Arm Compiler for Armv6-M architecture (big endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="ARMCC ARMv7-M NOFP LE">
<description>Arm Compiler for Armv7-M architecture without FPU (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="ARMCC ARMv7-M NOFP BE">
<description>Arm Compiler for Armv7-M architecture without FPU (big endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="ARMCC ARMv7-M FP LE">
<description>Arm Compiler for Armv7-M architecture with FPU (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="ARMCC ARMv7-M FP BE">
<description>Arm Compiler for Armv7-M architecture with FPU (big endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="ARMCC ARMv8-MBL LE">
<description>Arm Compiler for Armv8-M base line architecture (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv8-MBL Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="ARMCC ARMv8-MML NOFP LE">
<description>Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv8x-MML Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
<require Dmve="NO_MVE"/>
</condition>
<condition id="ARMCC ARMv8-MML FP LE">
<description>Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian)</description>
<require condition="ARMCC"/>
<require condition="ARMv8x-MML Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
<accept Dmve="MVE"/>
<accept Dmve="FP_MVE"/>
</condition>
<condition id="GCC ARMv6-M LE">
<description>GNU Compiler for Armv6-M architecture (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="GCC ARMv6-M BE">
<description>GNU Compiler for Armv6-M architecture (big endian)</description>
<require condition="GCC"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="GCC ARMv7-M NOFP LE">
<description>GNU Compiler for Armv7-M architecture without FPU (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="GCC ARMv7-M NOFP BE">
<description>GNU Compiler for Armv7-M architecture without FPU (big endian)</description>
<require condition="GCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="GCC ARMv7-M FP LE">
<description>GNU Compiler for Armv7-M architecture with FPU (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="GCC ARMv7-M FP BE">
<description>GNU Compiler for Armv7-M architecture with FPU (big endian)</description>
<require condition="GCC"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="GCC ARMv8-MBL LE">
<description>GNU Compiler for Armv8-M base line architecture (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv8-MBL Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="GCC ARMv8-MML NOFP LE">
<description>GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv8x-MML Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
<require Dmve="NO_MVE"/>
</condition>
<condition id="GCC ARMv8-MML FP LE">
<description>GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian)</description>
<require condition="GCC"/>
<require condition="ARMv8x-MML Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
<accept Dmve="MVE"/>
<accept Dmve="FP_MVE"/>
</condition>
<condition id="IARCC ARMv6-M LE">
<description>IAR Compiler for Armv6-M architecture (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="IARCC ARMv6-M BE">
<description>IAR Compiler for Armv6-M architecture (big endian)</description>
<require condition="IAR"/>
<require condition="ARMv6-M Device"/>
<require Dendian="Big-endian"/>
</condition>
<condition id="IARCC ARMv7-M NOFP LE">
<description>IAR Compiler for Armv7-M architecture without FPU (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="IARCC ARMv7-M NOFP BE">
<description>IAR Compiler for Armv7-M architecture without FPU (big endian)</description>
<require condition="IAR"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="IARCC ARMv7-M FP LE">
<description>IAR Compiler for Armv7-M architecture with FPU (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="IARCC ARMv7-M FP BE">
<description>IAR Compiler for Armv7-M architecture with FPU (big endian)</description>
<require condition="IAR"/>
<require condition="ARMv7-M Device"/>
<require Dendian="Big-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="IARCC ARMv8-MBL LE">
<description>IAR Compiler for Armv8-M base line architecture (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv8-MBL Device"/>
<require Dendian="Little-endian"/>
</condition>
<condition id="IARCC ARMv8-MML NOFP LE">
<description>IAR Compiler for Armv8-M main line architecture without FPU (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv8-MML Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
</condition>
<condition id="IARCC ARMv8-MML FP LE">
<description>IAR Compiler for Armv8-M main line architecture with FPU (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv8-MML Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
</condition>
<condition id="IARCC ARMv81-MML NOFP LE">
<description>IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv81-MML Device"/>
<require Dendian="Little-endian"/>
<require Dfpu="NO_FPU"/>
<require Dmve="NO_MVE"/>
</condition>
<condition id="IARCC ARMv81-MML FP LE">
<description>IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian)</description>
<require condition="IAR"/>
<require condition="ARMv81-MML Device"/>
<require Dendian="Little-endian"/>
<accept Dfpu="SP_FPU"/>
<accept Dfpu="DP_FPU"/>
<accept Dmve="MVE"/>
<accept Dmve="FP_MVE"/>
</condition>
<condition id="ARMASM ARMv6-M">
<description>Arm Assembler for Armv6-M architecture</description>
<require condition="ARMCC5"/>
<require condition="ARMv6-M Device"/>
</condition>
<condition id="GNUASM ARMv6-M">
<description>GNU Assembler for Armv6-M architecture</description>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
<require condition="ARMv6-M Device"/>
</condition>
<condition id="IARASM ARMv6-M">
<description>IAR Assembler for Armv6-M architecture</description>
<require condition="IAR"/>
<require condition="ARMv6-M Device"/>
</condition>
<condition id="ARMASM ARMv7-M">
<description>Arm Assembler for Armv7-M architecture</description>
<require condition="ARMCC5"/>
<require condition="ARMv7-M Device"/>
</condition>
<condition id="GNUASM ARMv7-M">
<description>GNU Assembler for Armv7-M architecture</description>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
<require condition="ARMv7-M Device"/>
</condition>
<condition id="IARASM ARMv7-M">
<description>IAR Assembler for Armv7-M architecture</description>
<require condition="IAR"/>
<require condition="ARMv7-M Device"/>
</condition>
<condition id="GNUASM ARMv8-MBL">
<description>GNU Assembler for Armv8-M base line architecture</description>
<require condition="ARMCC GCC"/>
<require condition="ARMv8-MBL Device"/>
</condition>
<condition id="GNUASM ARMv8-MML">
<description>GNU Assembler for Armv8-M/Armv8.1-M main line architecture</description>
<require condition="ARMCC GCC"/>
<require condition="ARMv8x-MML Device"/>
</condition>
<condition id="IARASM ARMv8-MBL">
<description>IAR Assembler for Armv8-M base line architecture</description>
<require condition="IAR"/>
<require condition="ARMv8-MBL Device"/>
</condition>
<condition id="IARASM ARMv8-MML">
<description>IAR Assembler for Armv8-M main line architecture</description>
<require condition="IAR"/>
<require condition="ARMv8x-MML Device"/>
</condition>
<condition id="ARMASM ARMv7-A">
<description>Arm Assembler for Armv7-A architecture</description>
<require condition="ARMCC5"/>
<require condition="ARMv7-A Device"/>
</condition>
<condition id="GNUASM ARMv7-A">
<description>GNU Assembler for Armv7-A architecture</description>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
<require condition="ARMv7-A Device"/>
</condition>
<condition id="IARASM ARMv7-A">
<description>IAR Assembler for Armv7-A architecture</description>
<require condition="IAR"/>
<require condition="ARMv7-A Device"/>
</condition>
<!-- OS Tick -->
<condition id="OS Tick PTIM">
<description>Components required for OS Tick Private Timer</description>
<accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A9"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
<condition id="OS Tick GTIM">
<description>Components required for OS Tick Generic Physical Timer</description>
<accept Dcore="Cortex-A7"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
</condition>
</conditions>
<components>
<!-- CMSIS-Core component -->
<component Cclass="CMSIS" Cgroup="CORE" Cversion="5.7.0" condition="ARMv6_7_8-M Device" >
<description>CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M</description>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/Core/html/index.html"/>
<file category="include" name="CMSIS/Core/Include/"/>
<file category="header" name="CMSIS/Core/Include/tz_context.h" condition="TrustZone"/>
<!-- Code template -->
<file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core/Template/ARMv8-M/main_s.c" version="1.1.1" select="Secure mode 'main' module for ARMv8-M"/>
<file category="sourceC" attr="template" condition="TZ Secure" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.1" select="RTOS Context Management (TrustZone for ARMv8-M)" />
</files>
</component>
<component Cclass="CMSIS" Cgroup="CORE" Cversion="1.2.1" condition="ARMv7-A Device" >
<description>CMSIS-CORE for Cortex-A</description>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
<file category="include" name="CMSIS/Core_A/Include/"/>
</files>
</component>
<!-- CMSIS-Startup components -->
<!-- Cortex-M0 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM0 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M0 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM0/Source/startup_ARMCM0.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM0/Source/system_ARMCM0.c" version="1.0.0" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.2" condition="ARMCM0 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M0 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM0/Source/system_ARMCM0.c" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-M0+ -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM0+ CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M0+ device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c" version="1.0.0" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.3.0" condition="ARMCM0+ CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-M1 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM1 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M1 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM1/Source/startup_ARMCM1.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM1/Source/system_ARMCM1.c" version="1.0.0" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.2" condition="ARMCM1 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M1 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM1/Source/system_ARMCM1.c" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-M3 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM3 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M3 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM3/Source/startup_ARMCM3.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM3/Source/system_ARMCM3.c" version="1.0.1" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.2" condition="ARMCM3 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M3 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM3/Source/system_ARMCM3.c" version="1.0.1" attr="config"/>
</files>
</component>
<!-- Cortex-M4 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM4 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M4 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM4/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM4/Source/startup_ARMCM4.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM4/Source/system_ARMCM4.c" version="1.0.1" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.2" condition="ARMCM4 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M4 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM4/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM4/Source/system_ARMCM4.c" version="1.0.1" attr="config"/>
</files>
</component>
<!-- Cortex-M7 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMCM7 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM7/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM7/Source/startup_ARMCM7.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM7/Source/system_ARMCM7.c" version="1.0.1" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.2" condition="ARMCM7 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM7/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM7/Source/system_ARMCM7.c" version="1.0.1" attr="config"/>
</files>
</component>
<!-- Cortex-M23 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.1.0" condition="ARMCM23 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M23 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM23/Source/startup_ARMCM23.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM23/Source/system_ARMCM23.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM23 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M23 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM23/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S" version="2.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.1.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM23/Source/system_ARMCM23.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M33 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.1.0" condition="ARMCM33 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M33 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM33/Source/startup_ARMCM33.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM33/Source/system_ARMCM33.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.3.0" condition="ARMCM33 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M33 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM33/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S" version="2.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S" version="2.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s" version="1.1.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM33/Source/system_ARMCM33.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M35P -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.1.0" condition="ARMCM35P CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm Cortex-M35P device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM35P/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMCM35P CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm Cortex-M35P device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM35P/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S" version="2.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S" version="1.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s" version="2.1.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M55 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM55 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Cortex-M55 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM55/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM55/Source/startup_ARMCM55.c" version="1.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM55/Source/system_ARMCM55.c" version="1.1.0" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-M85 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM85 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Cortex-M85 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCM85/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMCM85/Source/startup_ARMCM85.c" version="1.0.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct" version="1.0.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct" version="1.0.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMCM85/Source/system_ARMCM85.c" version="1.0.0" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-SC000 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMSC000 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm SC000 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMSC000/Source/startup_ARMSC000.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMSC000/Source/system_ARMSC000.c" version="1.0.0" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.3" condition="ARMSC000 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm SC000 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMSC000/Source/system_ARMSC000.c" version="1.0.0" attr="config"/>
</files>
</component>
<!-- Cortex-SC300 -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.0.3" condition="ARMSC300 CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Arm SC300 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMSC300/Source/startup_ARMSC300.c" version="2.0.3" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMSC300/Source/system_ARMSC300.c" version="1.0.1" attr="config"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.3" condition="ARMSC300 CMSIS">
<description>DEPRECATED: System and Startup for Generic Arm SC300 device</description>
<files>
<!-- include folder / device header file -->
<file category="header" name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.1" attr="config" condition="ARMCC"/>
<file category="sourceAsm" name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld" version="2.1.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMSC300/Source/system_ARMSC300.c" version="1.0.1" attr="config"/>
</files>
</component>
<!-- ARMv8MBL -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.1.0" condition="ARMv8MBL CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Armv8-M Baseline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="TZ Secure"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.2.0" condition="ARMv8MBL CMSIS">
<description>DEPRECATED: System and Startup for Generic Armv8-M Baseline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MBL/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S" version="2.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="2.2.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c" version="1.0.1" attr="config" condition="ARMCC GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
</files>
</component>
<!-- ARMv8MML -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.1.0" condition="ARMv8MML CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Armv8-M Mainline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c" version="1.0.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<component Cclass="Device" Cgroup="Startup" Cversion="1.3.0" condition="ARMv8MML CMSIS">
<description>DEPRECATED: System and Startup for Generic Armv8-M Mainline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv8MML/Include/"/>
<!-- startup / system file -->
<file category="sourceAsm" name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S" version="2.0.0" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="sourceAsm" name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S" version="2.3.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c" version="1.0.1" attr="config" condition="ARMCC GCC"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- ARMv81MML -->
<component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="2.2.0" condition="ARMv81MML CMSIS" isDefaultVariant="true">
<description>System and Startup for Generic Armv8.1-M Mainline device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMv81MML/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c" version="2.1.0" attr="config"/>
<file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Secure"/>
<file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct" version="1.1.0" attr="config" condition="Startup ARMCC6 Unsecure"/>
<file category="linkerScript" name="Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld" version="2.2.0" attr="config" condition="GCC"/>
<file category="sourceC" name="Device/ARM/ARMv81MML/Source/system_ARMv81MML.c" version="1.2.1" attr="config"/>
<!-- SAU configuration -->
<file category="header" name="Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h" version="1.0.1" attr="config" condition="TZ Secure"/>
</files>
</component>
<!-- Cortex-A5 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCA5 CMSIS">
<description>System and Startup for Generic Arm Cortex-A5 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA5/Include/"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.1" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.1" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA5/Config/system_ARMCA5.h" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA5/Config/mem_ARMCA5.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- Cortex-A7 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.1" condition="ARMCA7 CMSIS">
<description>System and Startup for Generic Arm Cortex-A7 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA7/Include/"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.1" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.1" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA7/Config/system_ARMCA7.h" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA7/Config/mem_ARMCA7.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- Cortex-A9 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.2" condition="ARMCA9 CMSIS">
<description>System and Startup for Generic Arm Cortex-A9 device</description>
<files>
<!-- include folder / device header file -->
<file category="include" name="Device/ARM/ARMCA9/Include/"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct" version="1.0.0" attr="config" condition="ARMCC5"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.1" attr="config" condition="ARMCC6"/>
<file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct" version="1.0.0" attr="config" condition="ARMCC6"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.1" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld" version="1.0.0" attr="config" condition="GCC"/>
<file category="sourceAsm" name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
<file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf" version="1.0.0" attr="config" condition="IAR"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/system_ARMCA9.c" version="1.0.1" attr="config"/>
<file category="sourceC" name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c" version="1.2.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA9/Config/system_ARMCA9.h" version="1.0.0" attr="config"/>
<file category="header" name="Device/ARM/ARMCA9/Config/mem_ARMCA9.h" version="1.1.0" attr="config"/>
</files>
</component>
<!-- IRQ Controller -->
<component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.2.0" condition="ARMv7-A Device">
<description>IRQ Controller implementation using GIC</description>
<files>
<file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
</files>
</component>
<!-- OS Tick -->
<component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
<description>OS Tick implementation using Private Timer</description>
<files>
<file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
</files>
</component>
<component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
<description>OS Tick implementation using Generic Physical Timer</description>
<files>
<file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
</files>
</component>
<!-- CMSIS-RTOS Keil RTX component -->
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.82.0" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
<description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
</RTE_Components_h>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
<file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
<file category="source" attr="config" name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
<!-- RTX templates -->
<file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c" select="CMSIS-RTOS 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c" select="CMSIS-RTOS Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c" select="CMSIS-RTOS Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c" select="CMSIS-RTOS Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c" select="CMSIS-RTOS Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c" select="CMSIS-RTOS Timer"/>
<!-- tool-chain specific template file -->
<file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
<file category="source" attr="template" condition="GCC" name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
<file category="source" attr="template" condition="IAR" name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
<!-- CPU and Compiler dependent -->
<!-- ARMCC -->
<file category="library" condition="ARMCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<!-- GCC -->
<file category="library" condition="GCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<!-- IAR -->
<file category="library" condition="IARCC ARMv6-M LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
<file category="library" condition="IARCC ARMv6-M BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
<file category="library" condition="IARCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
<file category="library" condition="IARCC ARMv7-M NOFP BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
<file category="library" condition="IARCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
<file category="library" condition="IARCC ARMv7-M FP BE" name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/IAR"/>
</files>
</component>
<!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.82.0" Capiversion="1.0.0" condition="RTOS RTX IFX">
<description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
</RTE_Components_h>
<files>
<!-- CPU independent -->
<file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
<file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
<file category="source" attr="config" name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
<!-- RTX templates -->
<file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c" select="CMSIS-RTOS 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c" select="CMSIS-RTOS Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c" select="CMSIS-RTOS Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c" select="CMSIS-RTOS Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c" select="CMSIS-RTOS Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c" select="CMSIS-RTOS Timer"/>
<!-- tool-chain specific template file -->
<file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
<file category="source" attr="template" condition="GCC" name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
<file category="source" attr="template" condition="IAR" name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
<!-- CPU and Compiler dependent -->
<!-- ARMCC -->
<file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib" src="CMSIS/RTOS/RTX/SRC/ARM"/>
<!-- GCC -->
<file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
<!-- IAR -->
</files>
</component>
<!-- CMSIS-RTOS Keil RTX5 component -->
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.7.0" Capiversion="1.0.0" condition="RTOS RTX5">
<description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
#define RTE_CMSIS_RTOS_RTX5 /* CMSIS-RTOS Keil RTX5 */
</RTE_Components_h>
<files>
<!-- RTX header file -->
<file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
<!-- RTX compatibility module for API V1 -->
<file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
</files>
</component>
<!-- CMSIS-RTOS2 Keil RTX5 component -->
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.7.0" Capiversion="2.2.0" condition="RTOS2 RTX5">
<description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<!-- RTX header files -->
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<!-- RTX configuration -->
<file category="header" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.6.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.2.0"/>
<!-- RTX templates -->
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c" version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c" version="2.0.0" select="CMSIS-RTOS2 Events"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c" version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c" version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c" version="2.0.0" select="CMSIS-RTOS2 Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c" version="2.0.1" select="CMSIS-RTOS2 Timer"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c" version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<!-- RTX library configuration -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
<file category="library" condition="ARMCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
<file category="library" condition="GCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
<file category="library" condition="IARCC ARMv6-M LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv7-M NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv7-M FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv81-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MM.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv81-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.7.0" Capiversion="2.2.0" condition="RTOS2 RTX5 NS">
<description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<!-- RTX header files -->
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<!-- RTX configuration -->
<file category="header" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.6.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.2.0"/>
<!-- RTX templates -->
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c" version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c" version="2.0.0" select="CMSIS-RTOS2 Events"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c" version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c" version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c" version="2.0.0" select="CMSIS-RTOS2 Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c" version="2.0.1" select="CMSIS-RTOS2 Timer"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c" version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<!-- RTX library configuration -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX libraries (CPU and Compiler dependent) -->
<!-- ARMCC -->
<file category="library" condition="ARMCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="ARMCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib" src="CMSIS/RTOS2/RTX/Source"/>
<!-- GCC -->
<file category="library" condition="GCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="GCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
<!-- IAR -->
<file category="library" condition="IARCC ARMv8-MBL LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv8-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv8-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv81-MML NOFP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMN.a" src="CMSIS/RTOS2/RTX/Source"/>
<file category="library" condition="IARCC ARMv81-MML FP LE" name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.7.0" Capiversion="2.2.0" condition="RTOS2 RTX5">
<description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<!-- RTX header files -->
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<!-- RTX configuration -->
<file category="header" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.6.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.2.0"/>
<!-- RTX templates -->
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c" version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c" version="2.0.0" select="CMSIS-RTOS2 Events"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c" version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c" version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c" version="2.0.0" select="CMSIS-RTOS2 Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c" version="2.0.1" select="CMSIS-RTOS2 Timer"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c" version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<!-- RTX sources (core) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX sources (handlers ARMASM) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s" condition="ARMASM ARMv6-M"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s" condition="ARMASM ARMv7-M"/>
<!-- RTX sources (handlers GAS) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S" condition="GNUASM ARMv6-M"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S" condition="GNUASM ARMv7-M"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="GNUASM ARMv8-MBL"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="GNUASM ARMv8-MML"/>
<!-- RTX sources (handlers IAR) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s" condition="IARASM ARMv6-M"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s" condition="IARASM ARMv7-M"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="IARASM ARMv8-MBL"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="IARASM ARMv8-MML"/>
<!-- OS Tick (SysTick) -->
<file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.7.0" Capiversion="2.2.0" condition="RTOS2 RTX5 v7-A">
<description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<!-- RTX header files -->
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<!-- RTX configuration -->
<file category="header" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.6.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.2.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/handlers.c" version="5.1.0"/>
<!-- RTX templates -->
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c" version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c" version="2.0.0" select="CMSIS-RTOS2 Events"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c" version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c" version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c" version="2.0.0" select="CMSIS-RTOS2 Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c" version="2.0.1" select="CMSIS-RTOS2 Timer"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c" version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<!-- RTX sources (core) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX sources (handlers ARMASM) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s" condition="ARMASM ARMv7-A"/>
<!-- RTX sources (handlers GAS) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S" condition="GNUASM ARMv7-A"/>
<!-- RTX sources (handlers IAR) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s" condition="IARASM ARMv7-A"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.7.0" Capiversion="2.2.0" condition="RTOS2 RTX5 NS">
<description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source)</description>
<RTE_Components_h>
<!-- the following content goes into file 'RTE_Components.h' -->
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
#define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
</RTE_Components_h>
<files>
<!-- RTX documentation -->
<file category="doc" name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
<!-- RTX header files -->
<file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
<!-- RTX configuration -->
<file category="header" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.h" version="5.6.0"/>
<file category="source" attr="config" name="CMSIS/RTOS2/RTX/Config/RTX_Config.c" version="5.2.0"/>
<!-- RTX templates -->
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c" version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c" version="2.0.0" select="CMSIS-RTOS2 Events"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c" version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c" version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c" version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c" version="2.0.0" select="CMSIS-RTOS2 Thread"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c" version="2.0.1" select="CMSIS-RTOS2 Timer"/>
<file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c" version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
<file category="other" name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
<!-- RTX sources (core) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
<!-- RTX sources (library configuration) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
<!-- RTX sources (GAS handlers) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S" condition="GNUASM ARMv8-MBL"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S" condition="GNUASM ARMv8-MML"/>
<!-- RTX sources (IAR handlers) -->
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s" condition="IARASM ARMv8-MBL"/>
<file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s" condition="IARASM ARMv8-MML"/>
<!-- OS Tick (SysTick) -->
<file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
</files>
</component>
<!-- CMSIS-Driver Custom components -->
<component Cclass="CMSIS Driver" Cgroup="USART" Csub="Custom" Cversion="1.0.0" Capiversion="2.4.0" custom="1">
<description>Access to #include Driver_USART.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_USART.c" select="USART Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="SPI" Csub="Custom" Cversion="1.0.0" Capiversion="2.3.0" custom="1">
<description>Access to #include Driver_SPI.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_SPI.c" select="SPI Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="SAI" Csub="Custom" Cversion="1.0.0" Capiversion="1.2.0" custom="1">
<description>Access to #include Driver_SAI.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_SAI.c" select="SAI Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="I2C" Csub="Custom" Cversion="1.0.0" Capiversion="2.4.0" custom="1">
<description>Access to #include Driver_I2C.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_I2C.c" select="I2C Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="CAN" Csub="Custom" Cversion="1.0.0" Capiversion="1.3.0" custom="1">
<description>Access to #include Driver_CAN.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_CAN.c" select="CAN Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="Flash" Csub="Custom" Cversion="1.0.0" Capiversion="2.3.0" custom="1">
<description>Access to #include Driver_Flash.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_Flash.c" select="Flash Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="MCI" Csub="Custom" Cversion="1.0.0" Capiversion="2.4.0" custom="1">
<description>Access to #include Driver_MCI.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_MCI.c" select="MCI Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="NAND" Csub="Custom" Cversion="1.0.0" Capiversion="2.4.0" custom="1">
<description>Access to #include Driver_NAND.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_NAND.c" select="NAND Flash Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="Ethernet" Csub="Custom" Cversion="1.0.0" Capiversion="2.2.0" custom="1">
<description>Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c" select="Ethernet PHY and MAC Driver"/>
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c" select="Ethernet PHY and MAC Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Csub="Custom" Cversion="1.0.0" Capiversion="2.2.0" custom="1">
<description>Access to #include Driver_ETH_MAC.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c" select="Ethernet MAC Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Csub="Custom" Cversion="1.0.0" Capiversion="2.2.0" custom="1">
<description>Access to #include Driver_ETH_PHY.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c" select="Ethernet PHY Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="USB Device" Csub="Custom" Cversion="1.0.0" Capiversion="2.3.0" custom="1">
<description>Access to #include Driver_USBD.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_USBD.c" select="USB Device Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="USB Host" Csub="Custom" Cversion="1.0.0" Capiversion="2.3.0" custom="1">
<description>Access to #include Driver_USBH.h file and code template for custom implementation</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_USBH.c" select="USB Host Driver"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="WiFi" Csub="Custom" Cversion="1.0.0" Capiversion="1.1.0" custom="1">
<description>Access to #include Driver_WiFi.h file</description>
<files>
<file category="header" name="CMSIS/Driver/Include/Driver_WiFi.h"/>
<file category="sourceC" attr="template" name="CMSIS/Driver/DriverTemplates/Driver_WiFi.c" select="WiFi Driver"/>
</files>
</component>
<!-- VIO components -->
<component Cclass="CMSIS Driver" Cgroup="VIO" Csub="Custom" Cversion="1.0.0" Capiversion="0.1.0" custom="1">
<description>Virtual I/O custom implementation template</description>
<files>
<file category="sourceC" name="CMSIS/Driver/VIO/Source/vio.c" attr="template" select="Virtual I/O"/>
</files>
</component>
<component Cclass="CMSIS Driver" Cgroup="VIO" Csub="Virtual" Cversion="1.0.0" Capiversion="0.1.0">
<description>Virtual I/O implementation using memory only</description>
<files>
<file category="sourceC" name="CMSIS/Driver/VIO/Source/vio_memory.c"/>
</files>
</component>
</components>
<boards>
<board name="uVision Simulator" vendor="Keil">
<description>uVision Simulator</description>
<mountedDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv81MML_DSP_DP_MVE_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM55"/>
</board>
<board name="EWARM Simulator" vendor="IAR">
<description>EWARM Simulator</description>
<mountedDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv81MML_DSP_DP_MVE_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM55"/>
</board>
</boards>
<examples>
<example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
<description>CMSIS-RTOS2 Blinky example</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="Blinky.uvprojx"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
<description>CMSIS-RTOS2 mixed API v1 and v2</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="Blinky.uvprojx"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
<description>CMSIS-RTOS2 Message Queue Example</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="MsqQueue.uvprojx"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Compiler" Cgroup="EventRecorder"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
<description>CMSIS-RTOS2 Memory Pool Example</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="MemPool.uvprojx"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Compiler" Cgroup="EventRecorder"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
<description>Bare-metal secure/non-secure example without RTOS</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="NoRTOS.uvmpw"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="TrustZone for ARMv8-M RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
<description>Secure/non-secure RTOS example with thread context management</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="RTOS.uvmpw"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="TrustZone for ARMv8-M RTOS Security Tests" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
<description>Secure/non-secure RTOS example with security test cases and system recovery</description>
<board name="uVision Simulator" vendor="Keil"/>
<project>
<environment name="uv" load="RTOS_Faults.uvmpw"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples_IAR/Blinky">
<description>CMSIS-RTOS2 Blinky example</description>
<board name="EWARM Simulator" vendor="IAR"/>
<project>
<environment name="iar" load="Blinky/Blinky.ewp"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
<example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue">
<description>CMSIS-RTOS2 Message Queue Example</description>
<board name="EWARM Simulator" vendor="IAR"/>
<project>
<environment name="iar" load="MsgQueue/MsgQueue.ewp"/>
</project>
<attributes>
<component Cclass="CMSIS" Cgroup="CORE"/>
<component Cclass="CMSIS" Cgroup="RTOS2"/>
<component Cclass="Device" Cgroup="Startup"/>
<category>Getting Started</category>
</attributes>
</example>
</examples>
</package>
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