mirror of
https://github.com/silenty4ng/uv-k5-firmware-chinese-lts
synced 2025-01-29 21:53:31 +00:00
190 lines
6.4 KiB
C
190 lines
6.4 KiB
C
/*
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* Copyright (c) 2013-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "Driver_NAND.h"
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#define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
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/* Driver Version */
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static const ARM_DRIVER_VERSION DriverVersion = {
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ARM_NAND_API_VERSION,
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ARM_NAND_DRV_VERSION
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};
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/* Driver Capabilities */
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static const ARM_NAND_CAPABILITIES DriverCapabilities = {
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0, /* Signal Device Ready event (R/Bn rising edge) */
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0, /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */
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0, /* Supports Sequence operation (ExecuteSequence, AbortSequence) */
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0, /* Supports VCC Power Supply Control */
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0, /* Supports 1.8 VCC Power Supply */
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0, /* Supports VCCQ I/O Power Supply Control */
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0, /* Supports 1.8 VCCQ I/O Power Supply */
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0, /* Supports VPP High Voltage Power Supply Control */
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0, /* Supports WPn (Write Protect) Control */
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0, /* Number of CEn (Chip Enable) lines: ce_lines + 1 */
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0, /* Supports manual CEn (Chip Enable) Control */
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0, /* Supports R/Bn (Ready/Busy) Monitoring */
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0, /* Supports 16-bit data */
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0, /* Supports NV-DDR Data Interface (ONFI) */
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0, /* Supports NV-DDR2 Data Interface (ONFI) */
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0, /* Fastest (highest) SDR Timing Mode supported (ONFI) */
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0, /* Fastest (highest) NV_DDR Timing Mode supported (ONFI) */
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0, /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) */
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0, /* Supports Driver Strength 2.0x = 18 Ohms */
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0, /* Supports Driver Strength 1.4x = 25 Ohms */
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0, /* Supports Driver Strength 0.7x = 50 Ohms */
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#if (ARM_NAND_API_VERSION > 0x201U)
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0 /* Reserved (must be zero) */
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#endif
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};
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/* Exported functions */
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static ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) {
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return DriverVersion;
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}
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static ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) {
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return DriverCapabilities;
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}
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static int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_Uninitialize (void) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) {
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switch ((int32_t)state) {
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case ARM_POWER_OFF:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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case ARM_POWER_LOW:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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case ARM_POWER_FULL:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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default:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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return ARM_DRIVER_OK;
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}
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static int32_t ARM_NAND_DevicePower (uint32_t voltage) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
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uint32_t addr_col, uint32_t addr_row,
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void *data, uint32_t data_cnt,
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uint8_t *status, uint32_t *count) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_AbortSequence (uint32_t dev_num) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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static int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) {
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switch (control) {
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case ARM_NAND_BUS_MODE:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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case ARM_NAND_BUS_DATA_WIDTH:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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case ARM_NAND_DEVICE_READY_EVENT:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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default:
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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return ARM_DRIVER_ERROR;
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}
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static ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) {
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ARM_NAND_STATUS stat;
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stat.busy = 0U;
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stat.ecc_error = 0U;
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return stat;
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}
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static int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) {
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return ARM_DRIVER_ERROR_UNSUPPORTED;
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}
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/* NAND Driver Control Block */
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extern \
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ARM_DRIVER_NAND Driver_NAND0;
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ARM_DRIVER_NAND Driver_NAND0 = {
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ARM_NAND_GetVersion,
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ARM_NAND_GetCapabilities,
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ARM_NAND_Initialize,
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ARM_NAND_Uninitialize,
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ARM_NAND_PowerControl,
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ARM_NAND_DevicePower,
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ARM_NAND_WriteProtect,
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ARM_NAND_ChipEnable,
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ARM_NAND_GetDeviceBusy,
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ARM_NAND_SendCommand,
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ARM_NAND_SendAddress,
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ARM_NAND_ReadData,
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ARM_NAND_WriteData,
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ARM_NAND_ExecuteSequence,
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ARM_NAND_AbortSequence,
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ARM_NAND_Control,
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ARM_NAND_GetStatus,
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ARM_NAND_InquireECC
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};
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