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https://github.com/silenty4ng/uv-k5-firmware-chinese-lts
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127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/**************************************************************************//**
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* @file ARMv8MBL.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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* ARMv8MBL Device
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* @version V5.3.1
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* @date 09. July 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ARMv8MBL_H
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#define ARMv8MBL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Processor Exceptions Numbers ----------------------------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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SVCall_IRQn = -5, /* 11 SVC Interrupt */
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PendSV_IRQn = -2, /* 14 PendSV Interrupt */
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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/* ------------------- Processor Interrupt Numbers ------------------------------ */
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Interrupt0_IRQn = 0,
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Interrupt1_IRQn = 1,
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Interrupt2_IRQn = 2,
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Interrupt3_IRQn = 3,
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Interrupt4_IRQn = 4,
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Interrupt5_IRQn = 5,
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Interrupt6_IRQn = 6,
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Interrupt7_IRQn = 7,
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Interrupt8_IRQn = 8,
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Interrupt9_IRQn = 9
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/* Interrupts 10 .. 480 are left out */
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* -------- Configuration of Core Peripherals ----------------------------------- */
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#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
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#define __SAUREGION_PRESENT 1U /* SAU regions are present */
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#define __MPU_PRESENT 0U /* no MPU present */
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#define __VTOR_PRESENT 0U /* no VTOR present */
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#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
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#include "core_armv8mbl.h" /* Processor and core peripherals */
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#include "system_ARMv8MBL.h" /* System Header */
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARMv8MBL_H */
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