mirror of
https://github.com/silenty4ng/uv-k5-firmware-chinese-lts
synced 2025-01-15 14:54:40 +00:00
48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
//
|
|
// Created by RUPC on 2024/1/8.
|
|
//
|
|
|
|
#ifndef HARDWARE_DP32G030_TIMER_H
|
|
#define HARDWARE_DP32G030_TIMER_H
|
|
#include <stdint.h>
|
|
|
|
#define TIMERBASE0_ADD 0x40064000
|
|
#define TIMERBASE1_ADD 0x40064800
|
|
//TIMER0
|
|
#define TIMERBASE0_EN_ADD (0X00+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_DIV_ADD (0X04+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_IE_ADD (0X10+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_IF_ADD (0X14+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_HIGH_LOAD_ADD (0X20+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_HIGH_CNT_ADD (0X24+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_LOW_LOAD_ADD (0X30+TIMERBASE0_ADD)
|
|
#define TIMERBASE0_LOW_CNT_ADD (0X34+TIMERBASE0_ADD)
|
|
|
|
#define TIMERBASE0_EN (*(volatile uint32_t *)TIMERBASE0_EN_ADD)
|
|
#define TIMERBASE0_DIV (*(volatile uint32_t *)TIMERBASE0_DIV_ADD)
|
|
#define TIMERBASE0_IE (*(volatile uint32_t *)TIMERBASE0_IE_ADD)
|
|
#define TIMERBASE0_IF (*(volatile uint32_t *)TIMERBASE0_IF_ADD)
|
|
#define TIMERBASE0_HIGH_LOAD (*(volatile uint32_t *)TIMERBASE0_HIGH_LOAD_ADD)
|
|
#define TIMERBASE0_HIGH_CNT (*(volatile uint32_t *)TIMERBASE0_HIGH_CNT_ADD)
|
|
#define TIMERBASE0_LOW_LOAD (*(volatile uint32_t *)TIMERBASE0_LOW_LOAD_ADD)
|
|
#define TIMERBASE0_LOW_CNT (*(volatile uint32_t *)TIMERBASE0_LOW_CNT_ADD)
|
|
|
|
|
|
//TIMER1
|
|
#define TIMERBASE1_EN_ADD 0X00+TIMERBASE1_ADD
|
|
#define TIMERBASE1_DIV_ADD 0X04+TIMERBASE1_ADD
|
|
#define TIMERBASE1_IE_ADD 0X10+TIMERBASE1_ADD
|
|
#define TIMERBASE1_IF_ADD 0X14+TIMERBASE1_ADD
|
|
#define TIMERBASE1_HIGH_LOAD_ADD 0X20+TIMERBASE1_ADD
|
|
#define TIMERBASE1_HIGH_CNT_ADD 0X24+TIMERBASE1_ADD
|
|
#define TIMERBASE1_LOW_LOAD_ADD 0X30+TIMERBASE1_ADD
|
|
#define TIMERBASE1_LOW_CNT_ADD 0X34+TIMERBASE1_ADD
|
|
|
|
|
|
|
|
extern uint8_t TIM0_CNT;
|
|
void TIM0_INIT();
|
|
void TIM0_SET_ARR(uint16_t Arr) ;
|
|
|
|
void TIM0_SET_PSC(uint16_t prescaler) ;
|
|
#endif //UV_K5_FIRMWARE_CUSTOM_0_17_TIMER_H
|